Semiconductor device

Abstract

This semiconductor device includes: a semiconductor substrate having a main region and a sense region; a gate insulating film; and a gate electrode. The main region includes: a diode region; a first IGBT region; and a second IGBT region. Each of the first IGBT region, the second IGBT region, and the sense region includes: an n-type emitter region exposed at an upper surface of the semiconductor substrate; a p-type contact region exposed at the upper surface of the semiconductor substrate; a p-type body region; an n-type drift region; and a p-type collector region. The area ratio of the contact region in the second IGBT region is smaller than the area ratio of the contact region in the first IGBT region. R1 > R3 > R2, when R1 is the area ratio of the emitter region in the first IGBT region, R2 is the area ratio of the emitter region in the second IGBT region, and R3 is the area ratio of the emitter region in the sense region.

Description

Semiconductor equipment 【0001】 (Cross-reference of related applications) This application is a related application to Japanese Patent Application No. 2024-214638, filed on 9 December 2024, and claims priority based on the said Japanese Patent Application. All contents of the said Japanese Patent Application are incorporated herein by reference as constituting this specification. 【0002】 The technology disclosed herein relates to semiconductor devices. 【0003】Japanese Patent Publication No. 2020-74371 discloses a semiconductor device having a semiconductor substrate with a plurality of trenches on its upper surface, a gate insulating film covering the inner surface of the trenches, and a gate electrode disposed within the trenches. The semiconductor substrate has an IGBT (Insulated-Gate Bipolar Transistor) region, a diode region, and a boundary region disposed between the IGBT region and the diode region. Inside the semiconductor substrate, there is a p-type base region and an n-type drift region that is in contact with the base region from below. The base region and the drift region are distributed across the IGBT region, the boundary region, and the diode region. The IGBT region further has an n-type emitter region, a p-type first contact region, and a p-type collector region. The emitter region is exposed on the upper surface of the semiconductor substrate, is in contact with the base region from above, and is in contact with the gate insulating film. The first contact region is exposed on the upper surface of the semiconductor substrate, is in contact with the base region from above, and has a higher p-type impurity concentration than the base region. The collector region is exposed on the underside of the semiconductor substrate and is in contact with the drift region from below. The diode region further comprises a second contact region and a cathode region. The second contact region is exposed on the upper surface of the semiconductor substrate and is in contact with the base region from above, and has a higher p-type impurity concentration than the base region. The cathode region is exposed on the underside of the semiconductor substrate and is in contact with the drift region from below, and has a higher n-type impurity concentration than the drift region. The boundary region further comprises a p-type third contact region and a p-type collector region. The third contact region is exposed on the upper surface of the semiconductor substrate and is in contact with the base region from above, and has a higher p-type impurity concentration than the base region. The collector region is exposed on the underside of the semiconductor substrate and is in contact with the drift region from below. 【0004】In the semiconductor device disclosed in Japanese Patent Application Laid-Open No. 2020-74371, the area ratio of the third contact region in the boundary region is smaller than the area ratio of the first contact region in the IGBT region. Since the ratio of the third contact region (i.e., the region with a high p-type impurity concentration) provided in the boundary region adjacent to the diode region is low, the amount of holes flowing from the boundary region (i.e., the third contact region) into the diode region is suppressed in the mode in which the diode operates. As a result, the recovery current during the recovery operation of the diode is suppressed, and the switching loss can be reduced. 【0005】 In the semiconductor device disclosed in Japanese Patent Application Laid-Open No. 2020-74371, in order to secure a region that functions as an IGBT, it is conceivable to arrange an emitter region in the boundary region as well. In this case, since the area ratio of the third contact region in the boundary region is smaller than the area ratio of the first contact region in the IGBT region, the area ratio of the emitter region in the boundary region becomes smaller than the area ratio of the emitter region in the IGBT region. 【0006】 Here, in order to monitor the current flowing through the IGBT in the IGBT region, boundary region, and diode region (hereinafter referred to as the main region) described above, a technique of providing a sense region in the semiconductor substrate is known. The sense region is a region where an IGBT is provided that is separated from the main region and has a smaller area than the main region. In a semiconductor device having a sense region, the current flowing through the sense region is detected, and the current flowing through the main region is calculated by converting the detected current based on the area ratio of the main region and the sense region. Therefore, in order to calculate the current flowing through the main region, it is desirable to make the current density of the main region and the current density of the sense region coincide. However, since the area of the sense region is small, it is difficult to apply a complex structure common to the main region (i.e., the IGBT region and the boundary region having emitter regions with different area ratios) to the sense region. In this specification, a technique capable of realizing a suitable current sensing function in a semiconductor device having a plurality of regions with different current densities in the main region is proposed. 【0007】The semiconductor device disclosed herein comprises a semiconductor substrate having a main region and a sense region separated from the main region and having a smaller area than the main region, with a plurality of trenches provided on the upper surface of the main region and the upper surface of the sense region, a gate insulating film covering the inner surface of each trench, and a gate electrode disposed in each trench and insulated from the semiconductor substrate by the gate insulating film. The main region has a diode region, a first IGBT region, and a second IGBT region disposed between the diode region and the first IGBT region. An inter-trench semiconductor layer sandwiched by the plurality of trenches is disposed in each of the first IGBT region, the second IGBT region, and the sense region. Each of the first IGBT region, the second IGBT region, and the sense region is provided within the inter-trench semiconductor layer and has an n-type emitter region exposed on the upper surface of the semiconductor substrate and in contact with the gate insulating film; a p-type contact region provided within the inter-trench semiconductor layer and exposed on the upper surface of the semiconductor substrate; a p-type body region provided within the inter-trench semiconductor layer, located below the emitter region and the contact region, in contact with the gate insulating film, and having a lower p-type impurity concentration than the contact region; an n-type drift region located below the body region, separated from the emitter region by the body region, and in contact with the gate insulating film; and a p-type collector region located below the drift region, separated from the body region by the drift region, and exposed on the lower surface of the semiconductor substrate. Within the main region, the drift region is distributed across the first IGBT region, the second IGBT region, and the diode region. The diode region includes a p-type anode region exposed on the upper surface of the semiconductor substrate and located above the drift region, and an n-type cathode region exposed on the lower surface of the semiconductor substrate and located below the drift region, having a higher n-type impurity concentration than the drift region.When the semiconductor substrate is viewed from above, the area ratio of the contact region in the second IGBT region is smaller than the area ratio of the contact region in the first IGBT region. When the semiconductor substrate is viewed from above, if R1 is the area ratio of the emitter region in the first IGBT region, R2 is the area ratio of the emitter region in the second IGBT region, and R3 is the area ratio of the emitter region in the sense region, then R1 > R3 > R2. 【0008】 In the semiconductor device described above, the area ratio of the contact region within the second IGBT region is smaller than the area ratio of the contact region within the first IGBT region. Because the area ratio of the contact region provided within the second IGBT region adjacent to the diode region is small, the amount of holes flowing from the second IGBT region into the diode region is suppressed in the operating mode in which freewheeling current flows. Therefore, the recovery current during recovery operation can be suppressed. 【0009】 Furthermore, in the semiconductor device described above, the area ratio R1 of the emitter region in the first IGBT region, the area ratio R2 of the emitter region in the second IGBT region, and the area ratio R3 of the emitter region in the sense region have the relationship R1 > R3 > R2. The area ratio of the emitter region in each region correlates with the current density of each region. Therefore, by setting the area ratio R3 of the emitter region in the sense region to a value between the area ratio R1 of the emitter region in the first IGBT region and the area ratio R2 of the emitter region in the second IGBT region, the current density of the sense region can be brought closer to the current density of the main region. In this way, by setting the area ratio R3 to satisfy the above relationship, this semiconductor device can realize a suitable current sensing function without applying a complex structure common to the main region to the sense region. 【0010】Plan view of the semiconductor device according to Example 1. Enlarged plan view of the main region. Cross-sectional view along line III-III in Figure 2. Cross-sectional view along line IV-IV in Figure 2. Cross-sectional view along line V-V in Figure 2. Enlarged plan view of the sense region. Cross-sectional view along line VII-VII in Figure 6. Cross-sectional view along line VIII-VIII in Figure 6. Enlarged plan view showing a modified example of the sense region. Enlarged plan view showing another modified example of the sense region. Enlarged plan view showing another modified example of the sense region. Enlarged plan view showing a modified example of the second IGBT region. 【0011】 In one example of a semiconductor device disclosed herein, a plurality of emitter regions may be arranged in the first IGBT region, the second IGBT region, and the sense region, respectively, at intervals along the longitudinal direction of the trench. In the first IGBT region, the spacing between the emitter regions may be narrower than in the second IGBT region. In the sense region, the spacing between the emitter regions may be constant. 【0012】 With this configuration, since the emitter regions are arranged at regular intervals within the sense region, it is possible to suppress the reduction in short-circuit withstand capability caused by localized current concentration within the sense region. 【0013】 In one example of a semiconductor device disclosed herein, a plurality of emitter regions may be arranged in the first IGBT region, the second IGBT region, and the sense region, respectively, at intervals in the longitudinal direction of the trench. When the spacing of the emitter regions in the first IGBT region is W1, the spacing of the emitter regions in the second IGBT region is W2, and the spacing of the emitter regions in the sense region is W3, W1 < W3 < W2. 【0014】 With this configuration, a simple design can be used to ensure that the area ratios R1, R2, and R3 satisfy R1 > R3 > R2. 【0015】 In one example semiconductor device disclosed herein, the contact region may be in contact with the emitter region. 【0016】When a semiconductor device is in the ON state, holes exist within the drift region. These holes are discharged through the contact region. With the above configuration, since the contact region is positioned in contact with the emitter region, the inflow of holes into the emitter region is suppressed, and the durability of the semiconductor device can be ensured. 【0017】 In one example semiconductor device disclosed herein, a plurality of the inter-trench semiconductor layers may be arranged within the second IGBT region. Within the second IGBT region, the area ratio of the contact region within the inter-trench semiconductor layer may be smaller for inter-trench semiconductor layers closer to the diode region. 【0018】 With this configuration, in the operating mode where freewheeling current flows, the amount of holes flowing from the second IGBT region to the diode region is further suppressed. As a result, the recovery current during recovery operation is suppressed, and switching losses can be reduced. 【0019】 An example semiconductor device disclosed herein may further include a main emitter electrode in contact with the upper surface of the semiconductor substrate within the main region, and a sense emitter electrode in contact with the upper surface of the semiconductor substrate within the sense region. The emitter regions in the first IGBT region and the second IGBT region may be in ohmic contact with the main emitter electrode. The contact regions in the first IGBT region and the second IGBT region may be in ohmic contact with the main emitter electrode. The emitter region in the sense region may be in ohmic contact with the sense emitter electrode. The contact regions in the sense region may be in ohmic contact with the sense emitter electrode. 【0020】(Example 1) The semiconductor device 10 of Example 1 will be described with reference to the drawings. The semiconductor device 10 is composed of a semiconductor substrate 12 and electrodes, insulating films, etc., provided on the upper surface 12a and lower surface 12b of the semiconductor substrate 12. The semiconductor substrate 12 is not particularly limited, but is composed of semiconductor materials such as Si and SiC. Hereinafter, the direction parallel to the upper surface 12a of the semiconductor substrate 12 will be called the x-direction, the direction parallel to the upper surface 12a of the semiconductor substrate 12 and perpendicular to the x-direction will be called the y-direction, and the thickness direction of the semiconductor substrate 12 will be called the z-direction. 【0021】 As shown in Figure 1, the semiconductor substrate 12 has a main region 14 and a sense region 16. The main region 14 is divided into a first IGBT region 14A, a second IGBT region 14B, and a diode region 14C. IGBT structures are provided in the first IGBT region 14A and the second IGBT region 14B, and a diode structure is provided in the diode region 14C. The first IGBT region 14A and the diode region 14C are arranged alternately and repeatedly along the y-direction when the semiconductor substrate 12 is viewed from above. The second IGBT region 14B is located between the first IGBT region 14A and the diode region 14C. 【0022】 Multiple small signal pads 18 are provided on the upper surface 12a of the semiconductor substrate 12. The sense region 16 is located in the area between two of the multiple small signal pads 18. The sense region 16 is located separately from the main region 14. The area of ​​the sense region 16 is smaller than the area of ​​the main region 14. An IGBT structure is provided in the sense region 16. The sense region 16 is provided to calculate the current flowing through the main region 14. By detecting the current flowing through the sense region 16 and converting the detected current based on the area ratio of the main region 14 and the sense region 16, the current flowing through the main region 14 can be calculated. 【0023】First, the configuration of the main region 14 will be described. As shown in Figures 2 to 5, a plurality of trenches 22 are provided on the upper surface 12a of the semiconductor substrate 12. Each trench 22 extends linearly in the x direction. Each trench 22 is arranged with spacing in the y direction. A plurality of trenches 22 are provided in each of the first IGBT region 14A, the second IGBT region 14B, and the diode region 14C. Hereinafter, each semiconductor region sandwiched between two adjacent trenches 22 will be referred to as the inter-trench semiconductor layer 23. Each inter-trench semiconductor layer 23 extends linearly in the x direction when the semiconductor substrate 12 is viewed from above. In this embodiment, a plurality of inter-trench semiconductor layers 23 exist in each of the first IGBT region 14A, the second IGBT region 14B, and the diode region 14C. However, it is sufficient that at least one inter-trench semiconductor layer 23 exists in each of the regions 14A, 14B, and 14C. 【0024】 The inner surface of each trench 22 is covered with a gate insulating film 24. A gate electrode 26 is placed inside each trench 22. Each gate electrode 26 is insulated from the semiconductor substrate 12 by the gate insulating film 24. As shown in Figures 3 to 5, in the first IGBT region 14A and the second IGBT region 14B, the upper surface of each gate electrode 26 is covered with an interlayer insulating film 28. In the diode region 14C, the upper surface of each gate electrode 26 is not covered with an interlayer insulating film. 【0025】 An upper electrode 70 is positioned on the upper surface 12a of the semiconductor substrate 12. Within the first IGBT region 14A and the second IGBT region 14B, the upper electrode 70 is in contact with the upper surface 12a of the semiconductor substrate 12 and the upper surface of the interlayer insulating film 28. Within the first IGBT region 14A and the second IGBT region 14B, the upper electrode 70 is insulated from the gate electrode 26 by the interlayer insulating film 28. Within the diode region 14C, the upper electrode 70 is in contact with the upper surface 12a of the semiconductor substrate 12 and the gate electrode 26. That is, in the diode region 14C, the gate electrode 26 is fixed at the same potential as the upper electrode 70. A lower electrode 72 is positioned on the lower surface 12b of the semiconductor substrate 12. The lower electrode 72 covers substantially the entire area of ​​the lower surface 12b of the semiconductor substrate 12. 【0026】 Inside the first IGBT region 14A and the second IGBT region 14B, there are multiple emitter regions 30, multiple contact regions 31, a body region 32, a drift region 34, and a collector region 36. 【0027】 The emitter region 30 is an n-type region. As shown in Figures 2, 3, and 5, the emitter region 30 is exposed on the upper surface 12a of the semiconductor substrate 12. The emitter region 30 is in contact with the gate insulating film 24 at the upper end of the trench 22. The emitter region 30 is in ohmic contact with the upper electrode 70. As shown in Figure 2, the multiple emitter regions 30 are arranged within each inter-trench semiconductor layer 23, spaced apart in the longitudinal direction (i.e., x-direction) of the trench 22. The width of each emitter region 30 in the x-direction is approximately equal to that of the first IGBT region 14A and the second IGBT region 14B. 【0028】 The contact region 31 is a p-type region. As shown in Figures 2 and 4, the contact region 31 is exposed on the upper surface 12a of the semiconductor substrate 12. The contact region 31 is in contact with the gate insulating film 24 at the upper end of the trench 22. The contact region 31 is in ohmic contact with the upper electrode 70. As shown in Figure 2, the contact region 31 is in contact with the emitter region 30 in the x-direction within each inter-trench semiconductor layer 23. In the first IGBT region 14A, both ends of the contact region 31 in the x-direction are in contact with the emitter region 30. In the first IGBT region 14A, the contact region 31 and the emitter region 30 are arranged alternately and repeatedly along the x-direction. In the second IGBT region 14B, one end of the contact region 31 in the x-direction is in contact with the emitter region 30, and the other end in the x-direction is in contact with a low-concentration n-type region 38, which will be described later. 【0029】The body region 32 is a p-type region. The body region 32 has a lower p-type impurity concentration than the contact region 31. As shown in Figures 3 to 5, the body region 32 is located below the emitter region 30 and the contact region 31 within each inter-trench semiconductor layer 23. The body region 32 is in contact with the emitter region 30 and the contact region 31 from below. The body region 32 is in contact with the gate insulating film 24 below the emitter region 30 and the contact region 31. 【0030】 The drift region 34 is an n-type region. The drift region 34 is arranged across the first IGBT region 14A and the second IGBT region 14B. The drift region 34 has a low-concentration drift region 34a and a buffer region 34b. 【0031】 The low-concentration drift region 34a has a lower n-type impurity concentration than the emitter region 30 and the buffer region 34b. As shown in Figures 3 to 5, the low-concentration drift region 34a is located below the body region 32. The low-concentration drift region 34a is in contact with the body region 32 from below. The low-concentration drift region 34a is separated from the emitter region 30 by the body region 32. The low-concentration drift region 34a is in contact with the gate insulating film 24 below the body region 32. The low-concentration drift region 34a is in contact with the gate insulating film 24 at the lower end of the trench 22. 【0032】 The buffer region 34b has a higher n-type impurity concentration than the low-concentration drift region 34a. The buffer region 34b is in contact with the low-concentration drift region 34a from below. 【0033】 The collector region 36 is a p-type region. The collector region 36 is positioned across the first IGBT region 14A and the second IGBT region 14B. The collector region 36 is positioned below the drift region 34. The collector region 36 is in contact with the drift region 34 from below. The collector region 36 is separated from the body region 32 by the drift region 34. The collector region 36 is exposed on the lower surface 12b of the semiconductor substrate 12. The collector region 36 is in ohmic contact with the lower electrode 72. 【0034】 A low-concentration n-type region 38 is further provided inside the second IGBT region 14B. The low-concentration n-type region 38 has a lower n-type impurity concentration than the emitter region 30. As shown in Figures 2 and 5, the low-concentration n-type region 38 is exposed on the upper surface 12a of the semiconductor substrate 12. The low-concentration n-type region 38 is in contact with the gate insulating film 24 at the upper end of the trench 22. As shown in Figure 2, the low-concentration n-type region 38 is located in the inter-trench semiconductor layer 23, in the x-direction, within the area sandwiched between two contact regions 31. Comparing the first IGBT region 14A and the second IGBT region 14B, the second IGBT region 14B has a configuration in which a portion of the emitter region 30 and contact region 31 in the first IGBT region 14A is replaced by the low-concentration n-type region 38. The low-concentration n-type region 38 is in non-ohmic contact with the upper electrode 70. 【0035】 The spacing W1 shown in Figure 2 is the spacing between two adjacent emitter regions 30 in the x-direction within each inter-trench semiconductor layer 23 of the first IGBT region 14A. Similarly, the spacing W2 shown in Figure 2 is the spacing between two adjacent emitter regions 30 in the x-direction within each inter-trench semiconductor layer 23 of the second IGBT region 14B. Spacing W2 is wider than spacing W1. Therefore, when viewing the semiconductor substrate 12 from above, if we let R1 be the area ratio of the emitter regions 30 in the first IGBT region 14A and R2 be the area ratio of the emitter regions 30 in the second IGBT region 14B, then area ratio R2 is smaller than area ratio R1. 【0036】 Furthermore, as described above, the second IGBT region 14B has a configuration in which a portion of the contact region 31 in the first IGBT region 14A is replaced by a low-concentration n-type region 38. That is, when the semiconductor substrate 12 is viewed from above, the area ratio of the contact region 31 in the second IGBT region 14B is smaller than the area ratio of the contact region 31 in the first IGBT region 14A. 【0037】 Inside the diode region 14C, there is an anode region 40, a drift region 44, and a cathode region 46. 【0038】The anode region 40 is a p-type region. The anode region 40 has an anode contact region 40a and a main anode region 40b. The anode contact region 40a has a higher n-type impurity concentration than the main anode region 40b. As shown in Figures 2 and 4, the anode contact region 40a is exposed on the upper surface 12a of the semiconductor substrate 12. The anode contact region 40a is in contact with the gate insulating film 24 at the upper end of the trench 22. The anode contact region 40a is in ohmic contact with the upper electrode 70. As shown in Figures 2, 3, and 5, the main anode region 40b is exposed on the upper surface 12a of the semiconductor substrate 12. As shown in Figure 4, the main anode region 40b extends below the anode contact region 40a and is in contact with the anode contact region 40a from below. As shown in Figure 2, when the semiconductor substrate 12 is viewed from above, the anode contact region 40a and the main anode region 40b are arranged alternately and repeatedly along the x-direction. 【0039】 The drift region 44 is an n-type region. The drift region 44 has a low-concentration drift region 44a and a buffer region 44b. 【0040】 The low-concentration drift region 44a has a lower n-type impurity concentration than the buffer region 44b. The low-concentration drift region 44a is located below the main anode region 40b. The low-concentration drift region 44a is in contact with the main anode region 40b from below. The low-concentration drift region 44a has approximately the same n-type impurity concentration as the low-concentration drift region 34a in the first IGBT region 14A and the second IGBT region 14B. The low-concentration drift region 44a is connected to the low-concentration drift region 34a in the first IGBT region 14A and the second IGBT region 14B. 【0041】The buffer region 44b has an n-type impurity concentration higher than that of the low-concentration drift region 44a. The buffer region 44b is in contact with the low-concentration drift region 34a from below. The buffer region 44b has substantially the same n-type impurity concentration as the buffer region 34b in the first IGBT region 14A and the second IGBT region 14B. The buffer region 44b is connected to the buffer region 34b in the first IGBT region 14A and the second IGBT region 14B. 【0042】 The cathode region 46 is an n-type region. The cathode region 46 has an n-type impurity concentration higher than that of the drift region 34. The cathode region 46 is disposed below the drift region 34. The cathode region 46 is in contact with the drift region 34 from below. The cathode region 46 is adjacent to the collector region 36. The cathode region 46 is exposed on the lower surface 12b of the semiconductor substrate 12. The cathode region 46 is in ohmic contact with the lower electrode 72. 【0043】 As described above, in the main region 14, an IGBT connected between the upper electrode 70 and the lower electrode 72 is formed in the first IGBT region 14A and the second IGBT region 14B by the emitter region 30, the body region 32, the drift region 34, the collector region 36, the gate electrode 26, etc. When the semiconductor device 10 operates as an IGBT, the upper electrode 70 functions as a main emitter electrode, and the lower electrode 72 functions as a collector electrode. 【0044】 Also, in the diode region 14C, a diode connected between the upper electrode 70 and the lower electrode 72 is formed by the anode region 40, the cathode region 46, etc. When the semiconductor device 10 operates as a diode, the upper electrode 70 functions as an anode electrode, and the lower electrode 72 functions as a cathode electrode. That is, the diode is connected in anti-parallel to the IGBT. 【0045】When the main region 14 operates as an IGBT, a higher potential is applied to the lower electrode 72 than to the upper electrode 70. When a potential above the gate threshold is applied to the gate electrode 26, a channel is formed in the body region 32 in the area in contact with the gate insulating film 24, and the emitter region 30 and the drift region 34 are connected by this channel. As a result, electrons flow from the emitter region 30 to the drift region 34 through the channel. Also, holes flow from the collector region 36 to the drift region 34. This turns the IGBT on. When the potential of the gate electrode 26 is lowered to below the gate threshold, the channel disappears and the IGBT turns off. Note that the low-concentration n-type region 38 has such a low n-type impurity concentration that it does not make ohmic contact with the upper electrode 70. Therefore, in the second IGBT region 14B, even if a channel is formed below the low-concentration n-type region 38, electrons do not flow from the low-concentration n-type region 38 to the drift region 34. In other words, the region where the low-concentration n-type region 38 is formed does not function as an IGBT. 【0046】 When the main region 14 operates as a diode, a higher potential is applied to the upper electrode 70 than to the lower electrode 72. In this state, electrons flow from the cathode region 46 to the drift region 44. Also, holes flow from the anode region 40 to the drift region 44. As a result, the pn diode composed of the anode region 40, the drift region 44, and the cathode region 46 turns on, and a freewheeling current flows. 【0047】 Here, in the second IGBT region 14B adjacent to the diode region 14C, a parasitic diode is formed by the contact region 31, the body region 32, the drift region 34, and the cathode region 46 within the diode region 14C. Therefore, in the mode in which the diode operates, this parasitic diode also turns on, and holes flow from the body region 32 in the second IGBT region 14B to the drift region 44 in the diode region 14C. If the amount of such hole inflow is large, a large recovery current flows during the diode's recovery operation, increasing switching losses. 【0048】In the semiconductor device 10 of this embodiment, when viewing the semiconductor substrate 12 from above, the area ratio of the contact region 31 in the second IGBT region 14B is smaller than the area ratio of the contact region 31 in the first IGBT region 14A. For this reason, the amount of holes flowing from the second IGBT region 14B into the diode region 14C is suppressed. As a result, the recovery current during the recovery operation of the diode is suppressed. 【0049】 Next, the configuration of the sense region 16 will be described. The sense region 16 has the same configuration as the first IGBT region 14A except for the configuration of the emitter region 50 and the contact region 51. As shown in FIGS. 6 to 8, in the sense region 16, a plurality of trenches 22, a gate insulating film 24, a gate electrode 26, and an interlayer insulating film 28 are provided, similar to the first IGBT region 14A. As shown in FIGS. 7 and 8, a sense emitter electrode 80 is disposed on the upper surface 12a of the semiconductor substrate 12. The sense emitter electrode 80 is separated from the upper electrode 70 in the main region 14. A lower electrode 72 is disposed on the lower surface 12b of the semiconductor substrate 12. The lower electrode 72 is disposed across the main region 14 and the sense region 16. 【0050】 Inside the sense region 16, an emitter region 50, a contact region 51, a body region 52, a drift region 54, and a collector region 56 are provided. As described above, since the configurations other than the emitter region 50 and the contact region 51 are the same as those of the first IGBT region 14A, the description of the body region 52, the drift region 54, and the collector region 56 will be omitted. 【0051】The emitter region 50 is exposed on the upper surface 12a of the semiconductor substrate 12. As shown in Figures 6 and 7, the emitter region 50 is in contact with the gate insulating film 24 at the upper end of the trench 22. The emitter region 50 is in ohmic contact with the sense emitter electrode 80. As shown in Figure 6, the multiple emitter regions 50 are arranged within each inter-trench semiconductor layer 23 with spacing in the longitudinal direction (i.e., the y-direction) of the trench 22. The width of each emitter region 50 in the y-direction in the longitudinal direction of the trench 22 is approximately equal to the width of each emitter region 30 in the first IGBT region 14A and the second IGBT region 14B. The spacing W3 in Figure 6 is the spacing between two adjacent emitter regions 50 in the y-direction within each inter-trench semiconductor layer 23. Each spacing W3 is approximately constant, wider than the spacing W1 shown in Figure 2 and narrower than the spacing W2. In other words, when the semiconductor substrate 12 is viewed from above, if the area ratio of the emitter region 50 within the sense region 16 is R3, then the relationship R1 > R3 > R2 holds between the area ratios R1 and R2 mentioned above. More specifically, in this embodiment, when the area of ​​the first IGBT region 14A is S1 and the area of ​​the second IGBT region 14B is S2, the area ratios R1, R2, and R3 are set such that the equation R3 = (S1・R1 + S2・R2) / S1 + S2 holds. 【0052】 The contact region 51 is exposed on the upper surface 12a of the semiconductor substrate 12. As shown in Figures 6 and 8, the contact region 51 is in contact with the gate insulating film 24 at the upper end of the trench 22. The contact region 51 is in ohmic contact with the sense emitter electrode 80. As shown in Figure 6, the contact region 51 is in contact with the emitter region 50 in the y direction within each inter-trench semiconductor layer 23. The contact region 51 and the emitter region 50 are arranged alternately and repeatedly along the y direction. 【0053】 Within the sense region 16, an IGBT is formed by the emitter region 50, body region 52, drift region 54, collector region 56, and gate electrode 26, etc., and is connected between the sense emitter electrode 80 and the lower electrode 72. The operation of the sense region 16 is the same as when the main region 14 operates as an IGBT. 【0054】In a semiconductor device 10 having a sense region 16, the current flowing through the sense region 16 is detected, and the current flowing through the main region is calculated by converting the detected current based on the area ratio of the main region 14 and the sense region 16. Therefore, in order to calculate the current flowing through the main region 14, it is desirable to match the current density of the main region 14 with the current density of the sense region 16. However, because the area of ​​the sense region 16 is small, it is difficult to apply a complex structure common to the main region 14 (i.e., the first IGBT region 14A and the second IGBT region 14B) to the sense region 16. 【0055】 However, in the semiconductor device 10 of this embodiment, the area ratio R1 of the emitter region 30 in the first IGBT region 14A, the area ratio R2 of the emitter region 30 in the second IGBT region 14B, and the area ratio R3 of the emitter region 50 in the sense region 16 have the relationship R1 > R3 > R2. The area ratio of the emitter region in each region correlates with the current density of each region. Therefore, by setting the area ratio R3 of the emitter region 50 in the sense region 16 to a value between the area ratio R1 of the emitter region 30 in the first IGBT region 14A and the area ratio R2 of the emitter region 30 in the second IGBT region 14B, the current density of the sense region 16 can be brought closer to the current density of the main region 14. In particular, in this embodiment, the area ratios R1, R2, and R3 are set such that R3 = (S1・R1 + S2・R2) / S1 + S2, so that the current density of the main region 14 and the current density of the sense region 16 are approximately the same. In this way, by setting the area ratio R3 to satisfy the above relationship, this semiconductor device 10 can realize a suitable current sensing function without applying a complex structure common to the main region 14 within the sense region 16. 【0056】Furthermore, in this embodiment, since the emitter regions 50 are arranged at a constant interval W3 in the sense region 16, a decrease in short-circuit withstand capability due to local current concentration within the sense region 16 can be suppressed. Moreover, since the emitter regions 30 are arranged at a constant interval W1 and W2 in the first IGBT region 14A and the second IGBT region 14B, respectively, a simple configuration can be used to design the area ratios R1, R2, and R3 to satisfy R1 > R3 > R2. 【0057】 (Example 2) In Example 2, the arrangement of the emitter region 130, contact region 131, and low-density n-type region 138 within the second IGBT region 14B differs from that of Example 1. In Example 2, as shown in Figure 9, within the second IGBT region 14B, the width of the low-density n-type region 138 in the x-direction differs for each inter-trench semiconductor layer 23. Specifically, within the second IGBT region 14B, the closer the inter-trench semiconductor layer 23 is to the diode region 14C, the wider the width of the low-density n-type region 138. In other words, within the second IGBT region 14B, the closer the inter-trench semiconductor layer 23 is to the diode region 14C, the smaller the area ratio of the contact region 131. In this configuration, in the operating mode in which freewheeling current flows, the amount of holes flowing from the second IGBT region 14B to the diode region 14C is further suppressed. As a result, the recovery current during recovery operation is suppressed, and switching losses can be reduced. 【0058】Furthermore, when viewing the semiconductor substrate 12 from above, there are various possible arrangements of the emitter region 50 and contact region 51 in the sense region 16. For example, as shown in Figure 10, the positions of the emitter region 150 and contact region 151 in the y-direction may be offset in adjacent inter-trench semiconductor layers 23. Also, as shown in Figure 11, a low-density n-type region 258 similar to the low-density n-type region 38 of the second IGBT region 14B may be provided in the area sandwiched between two contact regions 250. Also, as shown in Figure 12, the contact region 351 in each inter-trench semiconductor layer 23 may be arranged to extend long in the y-direction. Multiple emitter regions 350 may be provided in each inter-trench semiconductor layer 23 so as to be in contact with only one of the trenches 22. 【0059】 Furthermore, in the above-described embodiment, as shown in Figure 1, the sense region 16 was arranged in the area sandwiched between the two small signal pads 18, but the layout of the main region 14 and the sense region 16 is not particularly limited. For example, the sense region 16 may be placed in the center of the semiconductor substrate 12, and the main region 14 may be arranged to surround the sense region 16. 【0060】 Furthermore, in the above-described embodiment, a low-concentration p-type region having a lower p-type impurity concentration than the contact region 31 and the body region 32 may be provided instead of the low-concentration n-type region 38. 【0061】The configurations of the semiconductor device disclosed herein are listed below. (Configuration 1) A semiconductor substrate having a main region and a sense region separated from the main region and having a smaller area than the main region, wherein a plurality of trenches are provided on the upper surface of the main region and the upper surface of the sense region, respectively, a gate insulating film covering the inner surface of each trench, and a gate electrode disposed in each trench and insulated from the semiconductor substrate by the gate insulating film, wherein the main region has a diode region, a first IGBT region, and a second IGBT region disposed between the diode region and the first IGBT region, an inter-trench semiconductor layer sandwiched by the plurality of trenches is disposed in each of the first IGBT region, the second IGBT region, and the sense region, an n-type emitter region provided in the inter-trench semiconductor layer, exposed on the upper surface of the semiconductor substrate and in contact with the gate insulating film, The main region comprises: a p-type contact region provided within the inter-trench semiconductor layer and exposed on the upper surface of the semiconductor substrate; a p-type body region provided within the inter-trench semiconductor layer, located below the emitter region and the contact region, in contact with the gate insulating film, and having a lower p-type impurity concentration than the contact region; an n-type drift region located below the body region, separated from the emitter region by the body region, and in contact with the gate insulating film; and a p-type collector region located below the drift region, separated from the body region by the drift region, and exposed on the lower surface of the semiconductor substrate, wherein the main region is distributed across the first IGBT region, the second IGBT region, and the diode region, and the diode region comprises: a p-type anode region exposed on the upper surface of the semiconductor substrate and located above the drift region; and an n-type cathode region exposed on the lower surface of the semiconductor substrate and located below the drift region, having a higher n-type impurity concentration than the drift region.A semiconductor device having the following characteristics: When the semiconductor substrate is viewed from above, the area ratio of the contact region in the second IGBT region is smaller than the area ratio of the contact region in the first IGBT region; When the semiconductor substrate is viewed from above, when the area ratio of the emitter region in the first IGBT region is R1, the area ratio of the emitter region in the second IGBT region is R2, and the area ratio of the emitter region in the sense region is R3, R1 > R3 > R2. (Configuration 2) A semiconductor device according to Configuration 1, wherein a plurality of emitter regions are arranged in the first IGBT region, the second IGBT region, and the sense region, respectively, at intervals in the longitudinal direction of the trench, the spacing between the emitter regions is narrower in the first IGBT region than in the second IGBT region, and the spacing between the emitter regions is constant in the sense region. (Configuration 3) A semiconductor device according to Configuration 1 or 2, wherein a plurality of emitter regions are arranged in each of the first IGBT region, the second IGBT region, and the sense region at intervals in the longitudinal direction of the trench, and when the interval of the emitter regions in the first IGBT region is W1, the interval of the emitter regions in the second IGBT region is W2, and the interval of the emitter regions in the sense region is W3, W1 < W3 < W2. (Configuration 4) A semiconductor device according to any one of Configurations 1 to 3, wherein the contact region is in contact with the emitter region. (Configuration 5) A semiconductor device according to any one of Configurations 1 to 4, wherein a plurality of inter-trench semiconductor layers are arranged in the second IGBT region, and within the second IGBT region, the inter-trench semiconductor layer closer to the diode region has a smaller area ratio of the contact region within the inter-trench semiconductor layer. (Configuration 6) The configuration further comprises a main emitter electrode in contact with the upper surface of the semiconductor substrate within the main region, and a sense emitter electrode in contact with the upper surface of the semiconductor substrate within the sense region, wherein the emitter region in the first IGBT region and the second IGBT region is in ohmic contact with the main emitter electrode, and the contact region in the first IGBT region and the second IGBT region is in ohmic contact with the main emitter electrode.A semiconductor device according to any one of configurations 1 to 5, wherein the emitter region within the sense region is in ohmic contact with the sense emitter electrode, and the contact region within the sense region is in ohmic contact with the sense emitter electrode. 【0062】 Although specific examples of the present invention have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness.

Claims

1. A semiconductor substrate (12) having a main region (14) and a sense region (16) separated from the main region and having a smaller area than the main region, with a plurality of trenches (22) provided on the upper surface of the main region and the upper surface of the sense region, a gate insulating film (24) covering the inner surface of each trench, and a gate electrode (26) disposed in each trench and insulated from the semiconductor substrate by the gate insulating film, wherein the main region has a diode region (14C), a first IGBT region (14A), and a second IGBT region (14B) disposed between the diode region and the first IGBT region, an inter-trench semiconductor layer (23) sandwiched by the plurality of trenches is disposed in each of the first IGBT region, the second IGBT region, and the sense region, The main region comprises: an n-type emitter region (30, 50) provided within the inter-trench semiconductor layer, exposed on the upper surface of the semiconductor substrate, and in contact with the gate insulating film; a p-type contact region (31, 51) provided within the inter-trench semiconductor layer and exposed on the upper surface of the semiconductor substrate; a p-type body region (32, 52) provided within the inter-trench semiconductor layer, located below the emitter region and the contact region, in contact with the gate insulating film, and having a lower p-type impurity concentration than the contact region; an n-type drift region (34, 54) located below the body region, separated from the emitter region by the body region, and in contact with the gate insulating film; and a p-type collector region (36, 56) located below the drift region, separated from the body region by the drift region, and exposed on the lower surface of the semiconductor substrate, wherein within the main region, the drift region is distributed across the first IGBT region, the second IGBT region, and the diode region. The diode region is exposed on the upper surface of the semiconductor substrate and is located above the drift region, and comprises a p-type anode region (40),A semiconductor device (10) having an n-type cathode region (46) exposed on the lower surface of the semiconductor substrate, located below the drift region, and having a higher n-type impurity concentration than the drift region, wherein when the semiconductor substrate is viewed from above, the area ratio of the contact region in the second IGBT region is smaller than the area ratio of the contact region in the first IGBT region, and when the semiconductor substrate is viewed from above, R1 is the area ratio of the emitter region in the first IGBT region, R2 is the area ratio of the emitter region in the second IGBT region, and R3 is the area ratio of the emitter region in the sense region, such that R1 > R3 > R2.

2. The semiconductor device according to claim 1, wherein a plurality of emitter regions are arranged in each of the first IGBT region, the second IGBT region, and the sense region at intervals in the longitudinal direction of the trench, wherein the spacing between the emitter regions is narrower in the first IGBT region than in the second IGBT region, and the spacing between the emitter regions is constant in the sense region.

3. The semiconductor device according to claim 1, wherein a plurality of emitter regions are arranged in each of the first IGBT region, the second IGBT region, and the sense region at intervals in the longitudinal direction of the trench, and when the interval of the emitter regions in the first IGBT region is W1, the interval of the emitter regions in the second IGBT region is W2, and the interval of the emitter regions in the sense region is W3, W1 < W3 < W2.

4. The semiconductor device according to claim 1, wherein the contact region is in contact with the emitter region.

5. The semiconductor device according to claim 1, wherein a plurality of inter-trench semiconductor layers are arranged within the second IGBT region, and within the second IGBT region, the inter-trench semiconductor layer closer to the diode region has a smaller area ratio of the contact region within the inter-trench semiconductor layer.

6. The semiconductor device according to claim 1, further comprising: a main emitter electrode (70) in contact with the upper surface of the semiconductor substrate within the main region; and a sense emitter electrode (80) in contact with the upper surface of the semiconductor substrate within the sense region, wherein the emitter regions in the first IGBT region and the second IGBT region are in ohmic contact with the main emitter electrode; the contact regions in the first IGBT region and the second IGBT region are in ohmic contact with the main emitter electrode; the emitter region in the sense region is in ohmic contact with the sense emitter electrode; and the contact regions in the sense region are in ohmic contact with the sense emitter electrode.

Images