Electro-optical device

Abstract

An electro-optical device according to an embodiment of the present disclosure is provided with a plurality of switching elements provided one by one to two first pixels provided corresponding to a common signal line. The switching element is provided between: first wiring located between an electro-optical element and a holding circuit, in one first pixel of the two first pixels; and second wiring located between an electro-optical element and a holding circuit in the other first pixel of the two first pixels.

Description

Electro-optical device 【0001】 This disclosure relates to an electro-optical device. 【0002】 In the driving method of an electro-optical device, for example, there are a line sequential driving method in which each pixel is driven for each pixel row and a surface simultaneous driving method in which all pixels are driven collectively. An example of the line sequential driving method is disclosed in, for example, Patent Document 1. 【0003】 Japanese Patent Application Laid-Open No. 2008-224798 【0004】 By the way, the driving method is selected according to the use of the electro-optical device. Since the circuit designs are different between the line sequential driving method and the surface simultaneous driving method, it is necessary to perform circuit design for each use of the electro-optical device. Therefore, it is difficult to reduce the time and cost required for device development. It is desirable to provide an electro-optical device capable of reducing the time and cost required for device development. 【0005】 The electro-optical device according to the first embodiment of this disclosure includes a plurality of signal lines, a plurality of scanning lines, a plurality of first control lines, a plurality of second control lines, and a plurality of pixels provided corresponding to the locations where the plurality of signal lines and the plurality of scanning lines intersect each other. This electro-optical device further includes, among the plurality of pixels, a plurality of switch elements provided one by one for every two of the plurality of pixels when the plurality of pixels provided corresponding to a common signal line are regarded as a plurality of first pixels. This electro-optical device further includes a driving circuit capable of driving the plurality of pixels via the plurality of signal lines, the plurality of scanning lines, and the plurality of first control lines and controlling the plurality of switch elements via the plurality of second control lines. 【0006】Each pixel comprises an electro-optic element and a pixel circuit connected to the electro-optic element. The pixel circuit comprises a holding circuit, a first switch element provided between the signal line and the holding circuit, and a second switch element provided between the electro-optic element and the holding circuit. The scan line is connected to the on / off control terminal of the first switch element. The first control line is connected to the on / off control terminal of the second switch element. The second control line is connected to the on / off control terminal of the switch element. The switch element is provided between the first wiring and the second wiring, and is capable of connecting and disconnecting the first wiring and the second wiring. The first wiring is provided between the electro-optic element and the holding circuit in the second pixel, which is one of the two first pixels. The second wiring is provided between the electro-optic element and the holding circuit in the third pixel, which is the other of the two first pixels. 【0007】 In the electro-optical apparatus according to the first embodiment of this disclosure, a plurality of switch elements are provided, one for each of two first pixels provided corresponding to a common signal line. The switch element is provided between the first wiring between the electro-optical element and the holding circuit in the second pixel, which is one of the two first pixels, and between the second wiring between the electro-optical element and the holding circuit in the third pixel, which is the other of the two first pixels. As a result, when the switch element is off, sequential driving is possible, driving the second and third pixels in order. By performing this sequential driving for all first pixels provided corresponding to a common signal line, line sequential driving is possible. Furthermore, when the switch element is on, simultaneous driving is possible in the second and third pixels, alternately switching between holding a voltage to the holding circuit and outputting the voltage held by the holding circuit to the electro-optical element. By performing this simultaneous driving for all first pixels provided corresponding to a common signal line, surface simultaneous driving is possible. Thus, in the electro-optical apparatus according to the first embodiment of this disclosure, sequential line driving and simultaneous surface driving can be switched by setting a switch element to either on or off. In other words, a common pixel circuit can be used for both sequential line driving and simultaneous surface driving. 【0008】An electro-optical apparatus according to a second embodiment of the present disclosure comprises a plurality of signal lines, a plurality of scan lines, a plurality of control lines, and a plurality of pixels provided corresponding to the points where the plurality of signal lines and the plurality of scan lines intersect each other. The electro-optical apparatus further comprises a drive circuit capable of driving the plurality of pixels via the plurality of signal lines, the plurality of scan lines, and the plurality of control lines. A pixel comprises an electro-optical element and a pixel circuit connected to the electro-optical element. The pixel circuit comprises a holding circuit and a first switch element provided between the signal line and the holding circuit. The scan lines are connected to the on / off control terminals of the first switch element. The plurality of pixels includes a plurality of first pixels and a plurality of second pixels. The plurality of signal lines includes a plurality of first signal lines electrically connected to the plurality of first pixels and a plurality of second signal lines electrically connected to the plurality of second pixels. The plurality of scan lines includes a plurality of first scan lines electrically connected to the plurality of first pixels and a plurality of second scan lines electrically connected to the plurality of second pixels. The multiple control lines include multiple first control lines electrically connected to multiple first pixels and multiple second control lines electrically connected to multiple second pixels. 【0009】 An electro-optical apparatus according to a second embodiment of the present disclosure further comprises a first laminate and a second laminate. The first laminate includes a plurality of first pixels, a plurality of first signal lines, a plurality of first scan lines, a plurality of first control lines, and a plurality of first connection parts, one for each first pixel. The second laminate includes a plurality of second pixels, a plurality of second signal lines, a plurality of second scan lines, a plurality of second control lines, and a plurality of second connection parts, one for each second pixel. The pixel circuit included in the first laminate has a holding circuit, a first switch element, and a second switch element provided between the first connection part and the holding circuit. The first control line is connected to the on / off control terminal of the second switch element. The pixel circuit included in the second laminate has a holding circuit, a first switch element, and a third switch element provided between the second connection part and the holding circuit. The second control line is connected to the on / off control terminal of the third switch element. The first connection is electrically connected to the wiring between the second switch element and the electro-optic element. The second connection is electrically connected to the third switch element and the first connection. 【0010】In the electro-optical device according to the second embodiment of this disclosure, a first laminate is provided which includes a plurality of first signal lines, a plurality of first scan lines, a plurality of first control lines, and a plurality of first pixels, and a second laminate is provided which includes a plurality of second signal lines, a plurality of second scan lines, a plurality of second control lines, and a plurality of second pixels. The first pixel is provided which includes an electro-optical element and a first pixel circuit in which a second switch element is provided between a holding circuit and an electro-optical element. The second pixel is provided which includes a second pixel circuit in which a second switch element is provided between a holding circuit and an electro-optical element. As a result, in the first and second pixels, surface-to-surface drive is possible, which allows simultaneous writing to a plurality of electro-optical elements by alternately switching between holding a voltage to the holding circuit and outputting the voltage held in the holding circuit to the electro-optical element. Here, the first laminate itself has a circuit configuration that allows sequential writing to a plurality of electro-optical elements via a plurality of first signal lines, a plurality of first scan lines, and a plurality of first control lines. Thus, in the electro-optical apparatus according to the second embodiment of this disclosure, the first laminate that enables linear sequential driving can be reused. 【0011】 Figure 1 is a diagram showing an example of the schematic configuration of a display device according to the first embodiment of this disclosure. Figure 2 is a diagram showing an example of the circuit configuration of two pixels connected to an arbitrary signal line DTL in the display device of Figure 1. Figure 3 shows an example of the time variation of various control signals and various voltages in line sequential drive mode. Figure 4 shows an example of the time variation of various control signals and various voltages in surface-to-surface drive mode. Figure 5 is a diagram showing a modified example of the circuit configuration of two pixels connected to an arbitrary signal line DTL in the display device of Figure 1. Figure 6 is a diagram showing an example of the schematic configuration of a display device according to the second embodiment of this disclosure. Figure 7 is a diagram showing an example of the circuit configuration of two pixels connected to an arbitrary signal line DTL in the display device of Figure 6. Figure 8 is a diagram showing a modified example of the circuit configuration of two pixels connected to an arbitrary signal line DTL in the display device of Figure 6. Figure 9 is a diagram showing an example of the schematic configuration of a display device according to the third embodiment of this disclosure. Figure 10 is a diagram showing an example of the circuit configuration of pixels provided on the display panel and additional panel of Figure 9, respectively. 【0012】 The embodiments of this disclosure will be described in detail below with reference to the drawings. 【0013】 <1. Background> In electro-optical devices, there are two main driving methods: a linear sequential driving method that drives each pixel row by row, and a plane-wide simultaneous driving method that drives all pixels at once. The driving method is selected according to the application of the electro-optical device. Since the circuit design differs between the linear sequential driving method and the plane-wide simultaneous driving method, it is necessary to design the circuit for each application of the electro-optical device. Therefore, it is difficult to reduce the time and cost required for device development. In light of these problems, the applicant has conceived of an electro-optical device that can reduce the time and cost required for device development. The following describes such an electro-optical device in detail. 【0014】 <2. First Embodiment> [Configuration] The display device 1 according to the first embodiment of the present disclosure will now be described. Figure 1 shows an example of the schematic configuration of the display device 1. The display device 1 includes, for example, a display panel 10, a backlight 20, and a logic circuit (Integrated Circuit) 30, as shown in Figure 1. The display device 1 corresponds to one specific example of the "electro-optical device" of one embodiment of the present disclosure. The logic circuit 30 corresponds to one specific example of the "drive circuit" of one embodiment of the present disclosure. The logic circuit 30 may be provided separately from the display panel 10, or it may be provided within the display panel 10. 【0015】 The display panel 10 has, for example, a plurality of pixels 11 arranged two-dimensionally in the row and column directions. The pixels 11 correspond to a specific example of the "pixel" in one embodiment of the present disclosure. The display panel 10 is capable of displaying an image based on an image signal input from outside the display device 1, for example, by having the plurality of pixels 11 driven by a logic circuit 30. 【0016】The display panel 10 includes, for example, a plurality of scan lines WSL and a plurality of control lines CTL extending in the row direction, and a plurality of signal lines DTL extending in the column direction. The scan lines WSL correspond to a specific example of the "scan lines" in one embodiment of the present disclosure. The plurality of control lines CTL include a plurality of control lines CTL1 and a plurality of control lines CTL2. Control line CTL1 corresponds to a specific example of the "first control line" in one embodiment of the present disclosure. Control line CTL2 corresponds to a specific example of the "second control line" in one embodiment of the present disclosure. The signal lines DTL correspond to a specific example of the "signal lines" in one embodiment of the present disclosure. In the display panel 10, pixels 11 are provided corresponding to the locations where the signal lines DTL and the scan lines WSL intersect. Each scan line WSL is connected to the on / off control terminal of the switch element SW1 described later. Each control line CTL1 is connected to the on / off control terminal of the switch element SW2 described later. Each control line CTL2 is connected to the on / off control terminal of the switch element 12, which will be described later. Each signal line DTL is connected to the input terminal of the switch element SW1, which will be described later. 【0017】 Figure 2 shows an example of the circuit configuration of two pixels 11 connected to an arbitrary signal line DTL in the display device 1. Each pixel 11 includes, for example, an electro-optic element 111 and a pixel circuit 112 connected to the electro-optic element 111. The electro-optic element 111 is composed of, for example, a liquid crystal cell. The liquid crystal cell is capable of modulating the light incident on the liquid crystal according to the direction and magnitude of the applied voltage. The electro-optic element 111 is not limited to, for example, a liquid crystal cell, but can be any type of optical modulation element capable of modulating incident light. 【0018】The pixel circuit 112 includes a holding circuit MEM, a switch element SW1 provided between the signal line DTL and the holding circuit MEM, and a switch element SW2 provided between the electro-optic element 111 and the holding circuit MEM. The holding circuit MEM corresponds to one specific example of the "holding circuit" in one embodiment of the present disclosure. The switch element SW1 corresponds to one specific example of the "first switch element" in one embodiment of the present disclosure. The switch element SW2 corresponds to one specific example of the "second switch element" in one embodiment of the present disclosure. The switch elements SW1 and SW2 are composed of transistors, for example, with gate electrodes provided as on / off control terminals. 【0019】 The input terminal of switch element SW1 is connected to the signal line DTL, and the output terminal of switch element SW1 is connected to the input terminal of the holding circuit MEM. The input terminal of switch element SW2 is connected to the output terminal of the holding circuit MEM, and the output terminal of switch element SW2 is connected to one end of the electro-optic element 111 via wiring ptn1. Wiring ptn1 is provided between switch element SW2 and the electro-optic element 111 and is connected to the output terminal of switch element SW2 and one end of the electro-optic element 111. The holding circuit MEM is composed of SRAM (Static Random Access Memory). 【0020】 The display panel 10 further includes a plurality of switch elements 12, one for every two pixels 11a, where a plurality of pixels 11a corresponding to a common signal line DTL are referred to as a plurality of pixels 11a. A common switch element 12 is connected to two pixels 11a. A pixel 11a corresponds to a specific example of the "first pixel" in one embodiment of the present disclosure. A switch element 12 corresponds to a specific example of the "switch element" in one embodiment of the present disclosure. Hereinafter, one of the two pixels 11a to which the common switch element 12 is connected will be referred to as pixel 13, and the other of the two pixels 11a to which the common switch element 12 is connected will be referred to as pixel 14. The plurality of pixels 11 included in the display panel 10 are composed of a plurality of pairs of pixels 13, 14. 【0021】The switch element 12 is provided between the wiring ptn1 of pixel 13 and the wiring ptn1 of pixel 14. The switch element 12 is capable of connecting and disconnecting the wiring ptn1 of pixel 13 and the wiring ptn1 of pixel 14. Pixel 13 corresponds to a specific example of the "second pixel" in one embodiment of the present disclosure. Pixel 14 corresponds to a specific example of the "third pixel" in one embodiment of the present disclosure. The wiring ptn1 of pixel 13 corresponds to a specific example of the "first wiring" in one embodiment of the present disclosure. The wiring ptn1 of pixel 14 corresponds to a specific example of the "second wiring" in one embodiment of the present disclosure. 【0022】 The backlight 20 is capable of emitting light that illuminates the back of the display panel 10. The backlight 20 is composed of, for example, a plurality of LEDs arranged in the row and column directions. The light emitted from the backlight 20 is incident on the electro-optic elements 111 of each pixel 11. The logic circuit 30 is capable of driving the plurality of pixels 11 via a plurality of signal lines DTL, a plurality of scan lines WSL, and a plurality of control lines CTL1, and of controlling a plurality of switch elements 12 via a plurality of control lines CLT2. 【0023】When the logic circuit 30 is in line-sequential drive mode, for example, it is possible to turn off each switch element 12 via a plurality of control lines CTL2, and then write to a plurality of electro-optic elements 111 line-sequentially for each frame period via a plurality of signal lines DTL, a plurality of scan lines WSL, and a plurality of control lines CTL1. Here, writing to the electro-optic elements 111 refers to applying a voltage or current to the electro-optic elements 111 according to the video signal. In the plane-wide drive mode, the logic circuit 30, for example, turns on each switch element 12 via multiple control lines CTL2, then alternately turns on and off the two switch elements SW2 included in each pair of pixels 13 and 14 via multiple control lines CTL1, and sequentially turns on and off the switch elements SW1 included in the pixels in each pair of pixels 13 and 14 where the switch element SW2 is off via multiple scan lines WSL, and turns off the switch elements SW1 included in the pixels in each pair of pixels 13 and 14 where the switch element SW2 is on, thereby enabling simultaneous writing to multiple electro-optic elements 111 for each frame period. 【0024】 The logic circuit 30 includes, for example, a scan line drive circuit 31, a signal line drive circuit 32, a control line drive circuit 33, and a display control circuit 34, as shown in Figure 1. The signal line drive circuit 32 is capable of supplying, for example, a video signal for a unit pixel row supplied from the display control circuit 34 as a signal voltage to each pixel 11. Specifically, the signal line drive circuit 32 is capable of supplying, for example, a signal voltage corresponding to a video signal for a unit pixel row to each pixel 11 of the unit pixel row selected by the scan line drive circuit 31, via a plurality of signal lines DTLs. 【0025】The scan line drive circuit 31 is capable of sequentially selecting multiple pixels 11 for each unit pixel row based on, for example, a scan timing control signal (e.g., a vertical synchronization signal VSYNC and a clock signal) supplied from the display control circuit 34. Specifically, the scan line drive circuit 31 is capable of selecting each pixel 11 in a unit pixel row of multiple pixels 11 arranged in two dimensions by, for example, applying a selection pulse to the scan line WSL and applying the selection pulse to the switch element SW1 of each pixel 11 in a unit pixel row of multiple pixels 11 arranged in two dimensions. At each pixel 11 selected by the scan line drive circuit 31, the signal voltage supplied from the signal line drive circuit 32 is stored in the holding circuit MEM. 【0026】 The control line drive circuit 33 can, for example, select the pixel 11 to which the signal voltage stored in the holding circuit MEM will be output to the electro-optical element 111, based on the scanning timing control signal (e.g., the vertical synchronization signal VSYNC and the clock signal) supplied from the display control circuit 34. 【0027】 In sequential line drive mode, the control line drive circuit 33 can select all pixels 11 as output targets by applying a selection pulse to the switch element SW2 of each pixel 11 via each control line CTL1. In other words, in sequential line drive mode, the switch element SW2 of each pixel 11 is in the ON state. Therefore, in sequential line drive mode, in the unit pixel row selected by the scan line drive circuit 31, the signal voltage stored in the holding circuit MEM of each pixel 11 is output to each electro-optic element 111 via the ON state switch element SW2. 【0028】In the area-wide drive mode, the control line drive circuit 33, for example, alternately applies selection pulses to two switch elements SW2 included in each pair of pixels 13 and 14 via multiple control lines CTL1 at each frame period. This makes it possible to alternately repeat, at each frame period, a first write period in which the signal voltage stored in the holding circuit MEM of each pixel 13 is output to the respective electro-optic elements 111 of pixels 13 and 14, and a second write period in which the signal voltage stored in the holding circuit MEM of each pixel 14 is output to the respective electro-optic elements 111 of pixels 13 and 14. In other words, in area-wide drive mode, the display panel 10 displays across the entire display area (area-wide display) at each frame period. 【0029】 The display control circuit 34 can, for example, store and hold the input video signal in frame memory for each screen (each frame displayed). The display control circuit 34 can also, for example, control the scan line drive circuit 31, signal line drive circuit 32, and control line drive circuit 33 that drive the display panel 10 so that they operate in conjunction. Specifically, the display control circuit 34 can, for example, supply scan timing control signals (for example, the vertical synchronization signal VSYNC and the clock signal) to the scan line drive circuit 31 and the control line drive circuit 33, and supply the signal line drive circuit 32 with a video signal for a unit pixel row based on the video signal held in frame memory, and an output timing control signal. 【0030】 [Operation] Next, the operation of the display device 1 will be described. 【0031】(Line-sequential drive mode) Figure 3 shows an example of the time variation of various control signals and voltages in line-sequential drive mode. Figure 3 shows an example of the time variation of the following various control signals and voltages. VSYNC: Vertical synchronization signal CNCT: Control signal applied to control line CTL2 connected to switch element 12 DT: Signal voltage applied to signal line DTL GT1: Selection signal applied to scan line WSL connected to switch element SW1 included in pixel 13 MM1: Voltage held in hold circuit MEM included in pixel 13 TGT1: Selection signal applied to control line CTL1 connected to switch element SW2 included in pixel 13 PIX1: Voltage applied to electro-optic element 111 included in pixel 13 GT2: Selection signal applied to scan line WSL connected to switch element SW1 included in pixel 14 MM2: Voltage held in hold circuit MEM included in pixel 14 TGT2: Selection signal applied to control line CTL1 connected to switch element SW2 included in pixel 14 PIX2: Voltage applied to electro-optic element 111 included in pixel 14 【0032】In line sequential drive mode, the logic circuit 30 always turns off the control signal CNCT and turns on the selection signals TGT1 and TGT2. Then, at time t1, the logic circuit 30 turns on the selection signal GT1 of a certain pixel row (first pixel row). As a result, the voltage MM1 of the holding circuit MEM in each pixel 13 of the pixel row where the selection signal GT1 is turned on changes to a voltage corresponding to the signal voltage, and accordingly, the voltage PIX1 of the electro-optic element 111 in each pixel 13 of the pixel row where the selection signal GT1 is turned on also changes to a voltage corresponding to the signal voltage. Subsequently, at time t2, the logic circuit 30 turns off the selection signal GT1 of the first pixel row and turns on the selection signal GT2 of the pixel row adjacent to the first pixel row (second pixel row). Then, in each pixel 14 of the pixel row where the selection signal GT2 is turned on, the voltage MM2 of the holding circuit MEM changes to a voltage corresponding to the signal voltage, and accordingly, the voltage PIX2 of the electro-optic element 111 in each pixel 14 of the pixel row where the selection signal GT2 is turned on also changes to a voltage corresponding to the signal voltage. The logic circuit 30 performs this control sequentially for each pixel row across all pixel rows. As a result, the display device 1 performs image display by line sequential drive. 【0033】 (Surface-wide drive mode) Figure 4 shows an example of the time variation of various control signals and voltages in surface-wide drive mode. Figure 4 shows an example of the time variation of various control signals and voltages similar to that in Figure 3. 【0034】In the plane-wide drive mode, the logic circuit 30 always turns on the control signal CNCT. This connects the two electro-optic elements 111 in parallel to each other in each pair of pixels 13 and 14. Then, at time t1 immediately before the frame period F1, the logic circuit 30 turns off the control signal TGT1 of one of the pixels 13 in each pair of pixels 13 and 14, disconnecting the holding circuit MEM of one of the pixels 13 from the two electro-optic elements 111. Subsequently, at time t2 of the frame period F1, the logic circuit 30 turns on the control signal TGT2 of the other pixel 14 in each pair of pixels 13 and 14, connecting the holding circuit MEM of the other pixel 14 to the two electro-optic elements 111. Then, the voltage MM2 of the holding circuit MEM is applied to both electro-optic elements 111 of each pair of pixels 13 and 14, and the voltages PIX1 and PIX2 of both electro-optic elements 111 of each pair of pixels 13 and 14 change to voltages corresponding to the signal voltage. In this way, the entire surface is displayed at once during the frame period F1. 【0035】 The logic circuit 30 then, at time t3 in frame period F1, turns on the selection signal GT1 of each pixel 13, 14 in a given pair of pixels (the first pair of pixels) whose switch element SW2 is off, and connects the holding circuit MEM of each pixel 13 to the signal line DTL. As a result, the voltage MM1 of the holding circuit MEM in each pixel 13 where the selection signal GT1 is turned on changes to a voltage corresponding to the signal voltage. The logic circuit 30 then turns off the selection signal GT1 of each pixel 13 in a given pair of pixels (the first pair of pixels), and disconnects the holding circuit MEM of each pixel 13 in a given pair of pixels (the first pair of pixels) from the signal line DTL. During frame period F1, the logic circuit 30 sequentially controls the selection signal GT1 of each pixel 13 in a pair of pixels for each pair of pixels in all pairs of pixels. As a result, during frame period F1, the holding circuit MEM holds a voltage corresponding to the signal voltage for each pixel 13 of the two pixel rows where the selection signal GT1 is switched on or off. In this way, during frame period F1, the entire surface is displayed simultaneously, and a new voltage is held that will be used for the entire surface display in the next frame period F2. 【0036】At time t4 in frame period F1, logic circuit 30 turns off the control signal TGT2 of the other pixel 14 of each pair of pixels 13, 14, disconnecting the holding circuit MEM of the other pixel 14 from the two electro-optic elements 111. At time t5 in frame period F2, logic circuit 30 turns on the control signal TGT1 of one of the pixels 13 of each pair of pixels 13, 14, connecting the holding circuit MEM of one of the pixels 13 of each pair to the two electro-optic elements 111. As a result, the voltage MM1 of the holding circuit MEM is applied to both electro-optic elements 111 of each pair of pixels 13, 14, and the voltages PIX1 and PIX2 of both electro-optic elements 111 of each pair of pixels 13, 14 change to voltages corresponding to the signal voltage. In this way, the entire surface is displayed at once during frame period F2. 【0037】 The logic circuit 30 then, at time t6 in frame period F2, turns on the selection signal GT2 of each pixel 14 in a given two-pixel row (first two-pixel row) whose switch element SW2 is off, and connects the holding circuit MEM of each pixel 14 to the signal line DTL. As a result, the voltage MM2 of the holding circuit MEM in each pixel 14 where the selection signal GT2 is turned on changes to a voltage corresponding to the signal voltage. The logic circuit 30 then turns off the selection signal GT2 of each pixel 14 in a given two-pixel row (first two-pixel row), and disconnects the holding circuit MEM of each pixel 14 in a given two-pixel row (first two-pixel row) from the signal line DTL. During frame period F2, the logic circuit 30 sequentially controls the on / off switching of the selection signal GT2 of each pixel 14 in a two-pixel row for all two-pixel rows. As a result, during frame period F2, the holding circuit MEM holds a voltage corresponding to the signal voltage for each pixel 14 of the two pixel rows where the selection signal GT1 is turned on or off. In this way, during frame period F2, a whole-screen display is performed, and at the same time, a new voltage is held that will be used for the whole-screen display in the next frame period. The logic circuit 30 repeatedly performs the above-described series of controls, thereby performing a whole-screen display for each frame period and holding the voltage to be used for the whole-screen display of the next frame. 【0038】[Effects] Next, the effects of the display device 1 will be explained. 【0039】 In this embodiment, one switch element 12 is provided for each of the pixels 13 and 14, which are provided corresponding to a common signal line DTL. The switch element 12 is provided between the wiring ptn1 between the electro-optic element 111 and the holding circuit MEM in pixel 13, and between the wiring ptn1 between the electro-optic element 111 and the holding circuit MEM in pixel 14. As a result, when the switch element 12 is off, sequential driving is possible, driving the pixels 13 and 14 in order. By performing this sequential driving for each pair of pixels 13 and 14 included in the display panel 10, line sequential driving is possible. Furthermore, when the switch element 12 is on, simultaneous driving is possible in pixels 13 and 14, alternately switching between holding the voltage to the holding circuit MEM and outputting the voltage held by the holding circuit MEM to the electro-optic element 111. By performing this simultaneous driving for each pair of pixels 13 and 14 included in the display panel 10, surface simultaneous driving is possible. In this manner, by setting the switch element 12 of this embodiment to either on or off, it is possible to switch between sequential line driving and unified surface driving. In other words, a common pixel circuit 112 can be used for both sequential line driving and unified surface driving. Therefore, compared to designing separate circuits for a display device that can only perform sequential line driving and a display device that can only perform unified surface driving, the time and cost required for device development of the display device 1 can be reduced. 【0040】In this embodiment, for example, after turning off each switch element 12 via a plurality of control lines CTL2, writing is performed in line sequential manner to a plurality of electro-optical elements 111 via a plurality of signal lines DTL, a plurality of scanning lines WSL, and a plurality of control lines CTL1, so that line sequential driving is possible. On the other hand, for example, after turning on each switch element 12 via a plurality of control lines CTL2, two switch elements SW2 included in each set of pixels 13, 14 are alternately turned on and off via a plurality of control lines CTL1, and, via a plurality of scanning lines WSL, switch elements SW1 included in pixels in which the switch element SW2 is off among each set of pixels 13, 14 are turned on and off in line sequential manner, and switch elements SW1 included in pixels in which the switch element SW2 is on among each set of pixels 13, 14 are turned off, so that batch writing is performed to a plurality of electro-optical elements 111 for each frame period, enabling surface batch driving. That is, in both line sequential driving and surface batch driving, a common pixel circuit 112 can be used. Therefore, compared with the case where circuit designs for a display device capable of only line sequential driving and a display device capable of only surface batch driving are separately performed, the time and cost required for device development of the display device 1 can be reduced. 【0041】 In this embodiment, the holding circuit MEM is configured to include an SRAM. Thereby, both line sequential driving and surface batch driving can be performed in a frame period. 【0042】 In this embodiment, the electro-optical element 111 is configured to include a light modulation element such as liquid crystal. Thereby, video display using a light modulation element such as liquid crystal can be performed in line sequential driving and surface batch driving. 【0043】 In this embodiment, a plurality of pixels 11 are provided on a common panel (display panel 10). Thereby, line sequential driving and surface batch driving can be realized on a common panel (display panel 10). 【0044】 <3. Modification Example of the First Embodiment> Next, a modification example of the display device 1 according to the first embodiment will be described. 【0045】In the first embodiment, the holding circuit MEM may be configured to include a capacitive element, for example, as shown in FIG. 5. Even in such a case, as in the first embodiment, the time and cost required for device development of the display device 1 can be reduced. 【0046】 In the first embodiment and its modification, the logic circuit 30 may be capable of alternately performing line sequential driving and surface batch driving every predetermined frame period (for example, every one frame period). Even in such a case, as in the first embodiment, the time and cost required for device development of the display device 1 can be reduced. 【0047】 In the first embodiment and its modification, instead of the backlight 20, a light source capable of emitting light for irradiating the front surface of the display panel 10 may be provided. Even in such a case, as in the first embodiment, the time and cost required for device development of the display device 1 can be reduced. 【0048】 <4. Second Embodiment> [Configuration] The display device 2 according to the second embodiment of the present disclosure will be described. FIG. 6 shows an example of the schematic configuration of the display device 2. The display device 2 includes, for example, a display panel 40 and a logic circuit 30 as shown in FIG. 6. The display device 2 corresponds to a specific example of the "electro-optical device" of an embodiment of the present disclosure. The logic circuit 30 may be provided separately from the display panel 40 or may be provided within the display panel 40. 【0049】 The display panel 40 has, for example, a plurality of pixels 41 two-dimensionally arranged in the row direction and the column direction. The pixel 41 corresponds to a specific example of the "pixel" of an embodiment of the present disclosure. The display panel 40 can display an image based on a video signal input from the outside of the display device 2 when a plurality of pixels 41 are driven by the logic circuit 30. 【0050】The display panel 40 has, for example, a plurality of scan lines WSL and a plurality of control lines CTL extending in the row direction, and a plurality of signal lines DTL extending in the column direction. The plurality of control lines CTL include a plurality of control lines CTL1 and a plurality of control lines CTL2. In the display panel 40, pixels 41 are provided corresponding to the locations where the signal lines DTL and the scan lines WSL intersect. Each scan line WSL is connected to the on / off control terminal of the switch element SW1. Each control line CTL1 is connected to the on / off control terminal of the switch element SW2. Each control line CTL2 is connected to the on / off control terminal of the switch element 12. Each signal line DTL is connected to the input terminal of the switch element SW1. 【0051】 Figure 7 shows an example of the circuit configuration of two pixels 41 connected to an arbitrary signal line DTL in the display device 2. Each pixel 41 includes, for example, an electro-optic element 411, a transistor Tr connected in series with the electro-optic element 411, and a pixel circuit 112 connected to the gate of the transistor Tr. The electro-optic element 411 is composed of, for example, an organic EL (Electro-Luminescence) cell. The organic EL cell is capable of modulating the light emission intensity according to the magnitude of the applied current. The electro-optic element 411 is not limited to, for example, an organic EL cell, but can be any type of self-luminescent element capable of modulating the emitted light. 【0052】The display panel 40 further includes a plurality of switch elements 12, one for every two pixels 41a, where a plurality of pixels 41a are provided corresponding to a common signal line DTL among the plurality of pixels 41a. The common switch element 12 is connected to two pixels 41a. Pixel 41a corresponds to a specific example of the "first pixel" in one embodiment of the present disclosure. The switch element 12 corresponds to a specific example of the "switch element" in one embodiment of the present disclosure. Hereinafter, one of the two pixels 41a to which the common switch element 12 is connected will be referred to as pixel 42, and the other of the two pixels 41a to which the common switch element 12 is connected will be referred to as pixel 43. The plurality of pixels 41 included in the display panel 40 are composed of multiple sets of pixels 42, 43. 【0053】 The switch element 12 is provided between the wiring ptn1 of pixel 42 and the wiring ptn1 of pixel 43. The switch element 12 is capable of connecting and disconnecting the wiring ptn1 of pixel 42 and the wiring ptn1 of pixel 43. Pixel 42 corresponds to a specific example of the "second pixel" in one embodiment of the present disclosure. Pixel 43 corresponds to a specific example of the "third pixel" in one embodiment of the present disclosure. The wiring ptn1 of pixel 42 corresponds to a specific example of the "first wiring" in one embodiment of the present disclosure. The wiring ptn1 of pixel 43 corresponds to a specific example of the "second wiring" in one embodiment of the present disclosure. 【0054】 The logic circuit 30 is capable of performing the same control as the logic circuit 30 of the first embodiment described above. In the description of the logic circuit 30 in the first embodiment described above, pixel 11a will be read as pixel 41a, pixel 13 as pixel 42, pixel 14 as pixel 43, and electro-optic element 111 as electro-optic element 411. 【0055】(Line-sequential drive mode) In line-sequential drive mode, the logic circuit 30 always turns off the control signal CNCT and turns on the selection signals TGT1 and TGT2. Then, at time t1, the logic circuit 30 turns on the selection signal GT1 of a certain pixel row (first pixel row). As a result, the voltage MM1 of the holding circuit MEM in each pixel 42 of the pixel row where the selection signal GT1 is turned on changes to a voltage corresponding to the signal voltage, and accordingly, the current of the electro-optic element 411 in each pixel 42 of the pixel row where the selection signal GT1 is turned on also changes to a current value corresponding to the signal voltage. Subsequently, at time t2, the logic circuit 30 turns off the selection signal GT1 of the first pixel row and turns on the selection signal GT2 of the pixel row adjacent to the first pixel row (second pixel row). Then, in each pixel 43 of the pixel row where the selection signal GT2 is turned on, the voltage MM2 of the holding circuit MEM changes to a voltage corresponding to the signal voltage, and accordingly, the current of the electro-optic element 411 in each pixel 43 of the pixel row where the selection signal GT2 is turned on also changes to a current value corresponding to the signal voltage. The logic circuit 30 performs this control sequentially for each pixel row across all pixel rows. As a result, the display device 2 performs image display by line sequential drive. 【0056】 (Simultaneous Surface Drive Mode) In simultaneous surface drive mode, the logic circuit 30 always turns on the control signal CNCT. As a result, the two transistors Tr1 are connected in parallel to each other in each pair of pixels 42 and 43. The logic circuit 30 then turns off the control signal TGT1 of one of the pixels 42 in each pair of pixels 42 and 43 at time t1 immediately before the frame period F1, thereby disconnecting the holding circuit MEM of one of the pixels 42 in each pair from the two transistors Tr1. Subsequently, at time t2 of the frame period F1, the logic circuit 30 turns on the control signal TGT2 of the other pixel 43 in each pair of pixels 42 and 43, thereby connecting the holding circuit MEM of the other pixel 43 in each pair of pixels 42 and 43 to the two transistors Tr1. Then, the voltage MM2 of the holding circuit MEM is applied to both transistors Tr1 of each pair of pixels 42 and 43, and the current in both electro-optic elements 411 of each pair of pixels 42 and 43 changes to a current value corresponding to the signal voltage. In this way, the entire surface is displayed together during the frame period F1. 【0057】 The logic circuit 30 then, at time t3 in frame period F1, turns on the selection signal GT1 of each pixel 42, 43 in a given pair of pixels (the first pair of pixels) whose switch element SW2 is off, and connects the holding circuit MEM of each pixel 42 to the signal line DTL. As a result, the voltage MM1 of the holding circuit MEM in each pixel 42 for which the selection signal GT1 is turned on changes to a voltage corresponding to the signal voltage. The logic circuit 30 then turns off the selection signal GT1 of each pixel 42 in a given pair of pixels (the first pair of pixels), and disconnects the holding circuit MEM of each pixel 42 in a given pair of pixels (the first pair of pixels) from the signal line DTL. During frame period F1, the logic circuit 30 sequentially controls the selection signal GT1 of each pixel 42 in a pair of pixels for each pair of pixels in all pairs of pixels. As a result, during frame period F1, the holding circuit MEM holds a voltage corresponding to the signal voltage for each pixel 42 of the two pixel rows where the selection signal GT1 is switched on or off. In this way, during frame period F1, the entire surface is displayed simultaneously, and a new voltage is held that will be used for the entire surface display in the next frame period F2. 【0058】 At time t4 in frame period F1, logic circuit 30 turns off the control signal TGT2 of the other pixel 43 of each pair of pixels 42, 43, disconnecting the holding circuit MEM of the other pixel 43 from the two transistors Tr1. At time t5 in frame period F2, logic circuit 30 turns on the control signal TGT1 of one of the pixels 42 of each pair of pixels 42, 43, connecting the holding circuit MEM of one of the pixels 42 of each pair of pixels 42, 43 to the two electro-optic elements 411. As a result, the voltage MM1 of the holding circuit MEM is applied to both transistors Tr1 of each pair of pixels 42, 43, and the current in both electro-optic elements 411 of each pair of pixels 42, 43 changes to a current value corresponding to the signal voltage. In this way, the entire surface is displayed at once during frame period F2. 【0059】The logic circuit 30 then, at time t6 in frame period F2, turns on the selection signal GT2 of each pixel 43 in a given pair of pixel rows (the first pair of pixel rows) whose switch element SW2 is off, and connects the holding circuit MEM of each pixel 43 to the signal line DTL. As a result, the voltage MM2 of the holding circuit MEM in each pixel 43 where the selection signal GT2 is turned on changes to a voltage corresponding to the signal voltage. The logic circuit 30 then turns off the selection signal GT2 of each pixel 43 in a given pair of pixel rows (the first pair of pixel rows), and disconnects the holding circuit MEM of each pixel 43 in a given pair of pixel rows (the first pair of pixel rows) from the signal line DTL. In frame period F2, the logic circuit 30 sequentially controls the selection signal GT2 of each pixel 43 in a pair of pixel rows for each pair of pixel rows in all pixel rows. As a result, during frame period F2, the holding circuit MEM holds a voltage corresponding to the signal voltage for each pixel 43 of the two pixel rows where the selection signal GT1 is switched on or off. In this way, during frame period F2, a whole-screen display is performed, and at the same time, a new voltage is held that will be used for the whole-screen display in the next frame period. The logic circuit 30 repeatedly performs the above-described series of controls, thereby performing a whole-screen display for each frame period and holding the voltage to be used for the whole-screen display of the next frame. 【0060】 [Effects] Next, we will explain the effects of the display device 2. 【0061】In this embodiment, one switch element 12 is provided for each pixel 42, 43, which are provided corresponding to a common signal line DTL. The switch element 12 is provided between the wiring ptn1 between the electro-optic element 411 and the holding circuit MEM in pixel 42, and between the wiring ptn1 between the electro-optic element 411 and the holding circuit MEM in pixel 43. As a result, when the switch element 12 is off, sequential driving is possible, driving pixels 42, 43 in order. By performing this sequential driving for each pair of pixels 42, 43 included in the display panel 40, line sequential driving is possible. Furthermore, when the switch element 12 is on, simultaneous driving is possible for pixels 42, 43, which alternately switches between holding a voltage to the holding circuit MEM and outputting the voltage held by the holding circuit MEM to the electro-optic element 411. By performing this simultaneous driving for each pair of pixels 42, 43 included in the display panel 40, surface simultaneous driving is possible. In this manner, by setting the switch element 12 of this embodiment to either on or off, line-sequential driving and area-wide simultaneous driving can be switched. In other words, a common pixel circuit 112 can be used for both line-sequential driving and area-wide simultaneous driving. Therefore, compared to designing separate circuits for a display device that can only perform line-sequential driving and a display device that can only perform area-wide simultaneous driving, the time and cost required for device development of the display device 2 can be reduced. 【0062】In this embodiment, for example, sequential line driving is possible by turning off each switch element 12 via multiple control lines CTL2, and then sequentially writing to multiple electro-optic elements 411 via multiple signal lines DTL, multiple scan lines WSL, and multiple control lines CTL1. On the other hand, for example, by turning on each switch element 12 via multiple control lines CTL2, and then sequentially turning on and off two switch elements SW2 included in each pair of pixels 42, 43 via multiple control lines CTL1, and sequentially turning on and off the switch elements SW1 included in the pixels where the switch element SW2 is off, and then turning off the switch elements SW1 included in the pixels where the switch element SW2 is on, all at once for each frame period, all at once is possible for multiple electro-optic elements 411. In other words, a common pixel circuit 112 can be used for both sequential line driving and all-at-a-times-a-frame driving. Therefore, compared to designing separate circuits for a display device capable of sequential line drive only and a display device capable of simultaneous surface drive only, the time and cost required for device development of display device 2 can be reduced. 【0063】 In this embodiment, the holding circuit MEM is configured to include SRAM. This allows both sequential line driving and simultaneous area driving to be performed during the frame period. 【0064】 In this embodiment, the electro-optic element 411 is configured to include self-emissive elements such as organic EL. This enables image display using self-emissive elements such as organic EL in both line-sequential driving and area-synchronized driving modes. 【0065】 In this embodiment, multiple pixels 41 are provided on a common panel (display panel 40). This makes it possible to achieve both sequential line driving and simultaneous surface driving on the common panel (display panel 40). 【0066】 <5. Modifications of the Second Embodiment> Next, a modification of the display device 2 according to the second embodiment will be described. 【0067】In the second embodiment, the holding circuit MEM may be configured to include a capacitive element, for example, as shown in Figure 8. Even in this case, the time and cost required for device development of the display device 2 can be reduced, similar to the second embodiment. 【0068】 In the second embodiment and its modifications, the logic circuit 30 may be capable of alternately performing line sequential driving and area simultaneous driving at predetermined frame intervals (for example, every 1 frame interval). Even in this case, as in the second embodiment, the time and cost required for device development of the display device 2 can be reduced. 【0069】 <6. Third Embodiment> [Configuration] A display device 3 according to the third embodiment of the present disclosure will now be described. Figure 9 shows an example of the schematic configuration of the display device 3. The display device 3 includes, for example, a display panel 50, an additional panel 60, a backlight 20, and a logic circuit 70, as shown in Figure 9. The display device 3 corresponds to one specific example of the "electro-optical device" of one embodiment of the present disclosure. The display panel 50 corresponds to one specific example of the "first laminate" of one embodiment of the present disclosure. The additional panel 60 corresponds to one specific example of the "second laminate" of one embodiment of the present disclosure. The logic circuit 70 may be provided separately from the display panel 50 and the additional panel 60, or it may be provided within the display panel 50 or the additional panel 60. 【0070】 The display panel 50 has a plurality of pixels 11 arranged two-dimensionally in the row and column directions, for example, as shown in Figures 9 and 10. The pixels 11 correspond to a specific example of the "first pixel" in one embodiment of the present disclosure. The additional panel 60 has a plurality of pixels 61 arranged two-dimensionally in the row and column directions, for example, as shown in Figure 10. The pixels 61 correspond to a specific example of the "second pixel" in one embodiment of the present disclosure. The display panel 50 and the additional panel 60 are capable of displaying images based on video signals input from outside the display device 3, for example, by having the plurality of pixels 11 and 61 driven by a logic circuit 70. 【0071】The display panel 50 has, for example, a plurality of scan lines WSLx and a plurality of control lines CTLx extending in the row direction, and a plurality of signal lines DTLx extending in the column direction. The scan lines WSLx correspond to a specific example of the "first scan line" in one embodiment of the present disclosure. The plurality of control lines CTLx correspond to a specific example of the "first control line" in one embodiment of the present disclosure. The signal lines DTLx correspond to a specific example of the "first signal line" in one embodiment of the present disclosure. In the display panel 50, pixels 11 are provided corresponding to the locations where the signal lines DTLx and scan lines WSLx intersect. Each scan line WSLx is connected to the on / off control terminal of the switch element SW1. Each control line CTLx is connected to the on / off control terminal of the switch element SW2. Each signal line DTLx is connected to the input terminal of the switch element SW1. 【0072】 The additional panel 60 has, for example, a plurality of scan lines WSLy and a plurality of control lines CTLy extending in the row direction, and a plurality of signal lines DTLy extending in the column direction. The scan lines WSLy correspond to a specific example of the "second scan line" in one embodiment of the present disclosure. The control lines CTLy correspond to a specific example of the "second control line" in one embodiment of the present disclosure. The signal lines DTLy correspond to a specific example of the "second signal line" in one embodiment of the present disclosure. In the additional panel 60, pixels 61 are provided corresponding to the locations where the signal lines DTLy and the scan lines WSLy intersect. Each scan line WSLy is connected to the on / off control terminal of the switch element SW1. Each control line CTLy is connected to the on / off control terminal of the switch element SW2. Each signal line DTLy is connected to the input terminal of the switch element SW1. 【0073】Pixel 11 includes, for example, an electro-optic element 111 and a pixel circuit 112 connected to the electro-optic element 111. In the display panel 50, a switch element SW2 is provided between the holding circuit 112 and the electro-optic element 111 in the pixel circuit 112. The pixel circuit 112 in the display panel 50 corresponds to a specific example of the "first pixel circuit" in one embodiment of the present disclosure. The electro-optic element 111 is composed of, for example, a liquid crystal cell. The liquid crystal cell is capable of modulating the light incident on the liquid crystal according to the direction and magnitude of the applied voltage. The electro-optic element 111 is not limited to, for example, a liquid crystal cell, but can be any type of optical modulation element capable of modulating incident light. 【0074】 Pixel 61 has a pixel circuit 112 in which, for example, a switch element SW2 is provided between a holding circuit 112 and an electro-optic element 111. The pixel circuit 112 in the additional panel 60 corresponds to a specific example of the "second pixel circuit" in one embodiment of the present disclosure. 【0075】 In the display panel 50, the pixel circuit 112 includes a holding circuit MEM, a switch element SW1 provided between the signal line DTLx and the holding circuit MEM, and a switch element SW2 provided between the electro-optic element 111 and the holding circuit MEM. The holding circuit MEM in the display panel 50 corresponds to a specific example of the "holding circuit" in one embodiment of the present disclosure. The switch element SW1 in the display panel 50 corresponds to a specific example of the "first switch element" in one embodiment of the present disclosure. The switch element SW2 in the display panel 50 corresponds to a specific example of the "second switch element" in one embodiment of the present disclosure. The switch elements SW1 and SW2 are composed of transistors, for example, with gate electrodes provided as on / off control terminals. 【0076】In the display panel 50, the input terminal of switch element SW1 is connected to the signal line DTLx, and the output terminal of switch element SW1 is connected to the input terminal of the holding circuit MEM. In the display panel 50, the input terminal of switch element SW2 is connected to the output terminal of the holding circuit MEM, and the output terminal of switch element SW2 is connected to one end of the electro-optic element 111 via wiring ptn1. In the display panel 50, wiring ptn1 is provided between switch element SW2 and the electro-optic element 111 and is connected to the output terminal of switch element SW2 and one end of the electro-optic element 111. In the display panel 50, the holding circuit MEM is composed of SRAM. The display panel 50 has a connection pad P1 electrically connected to wiring ptn1. The connection pad P1 corresponds to one specific example of the "first connection part" in one embodiment of the present disclosure. 【0077】 In the additional panel 60, the pixel circuit 112 includes a holding circuit MEM, a switch element SW1 provided between the signal line DTly and the holding circuit MEM, and a switch element SW2 provided between the electro-optic element 111 (connection pad P2 described later) and the holding circuit MEM. The holding circuit MEM in the additional panel 60 corresponds to one specific example of the "holding circuit" in one embodiment of the present disclosure. The switch element SW1 in the additional panel 60 corresponds to one specific example of the "first switch element" in one embodiment of the present disclosure. The switch element SW2 in the additional panel 60 corresponds to one specific example of the "second switch element" in one embodiment of the present disclosure. The switch elements SW1 and SW2 are composed of transistors, for example, with gate electrodes provided as on / off control terminals. 【0078】In the additional panel 60, the input terminal of switch element SW1 is connected to the signal line DTly, and the output terminal of switch element SW1 is connected to the input terminal of the holding circuit MEM. In the additional panel 60, the input terminal of switch element SW2 is connected to the output terminal of the holding circuit MEM, and the output terminal of switch element SW2 is connected to one end of the electro-optic element 111 via wiring ptn2, connection pads P1 and P2, and wiring ptn1. In the additional panel 60, wiring ptn2 is provided between switch element SW2 and connection pad P2, and is connected to the output terminal of switch element SW2 and connection pad P2. In the additional panel 60, the holding circuit MEM is composed of SRAM. The additional panel 60 has a connection pad P2 that is electrically connected to wiring ptn2. Connection pads P1 and P2 are connected to each other, and the display panel 50 and the additional panel 60 are stacked on top of each other. Connection pad P2 corresponds to one specific example of the "second connection part" in one embodiment of the present disclosure. 【0079】 The backlight 20 is capable of emitting light that illuminates the back of the display panel 50. The backlight 20 is composed of, for example, a plurality of LEDs arranged in the row and column directions. The light emitted from the backlight 20 is incident on the electro-optic elements 111 of each pixel 11. 【0080】 In the plane-wide drive mode, the logic circuit 70 alternately turns on and off two switch elements SW2 included in each pair of pixels 11, 61 connected by connection pads P1, P2 via multiple control lines CTLx and multiple control lines CTLy, and sequentially turns on and off the switch elements SW1 included in pixels where the switch element SW2 is off among the pairs of pixels 11, 61 connected by connection pads P1, P2 via multiple scan lines WSLx and multiple scan lines WSLy, and turns off the switch elements SW1 included in pixels where the switch element SW2 is on among the pairs of pixels 11, 61 connected by connection pads P1, P2, thereby enabling simultaneous writing to multiple electro-optic elements 111 for each frame period. 【0081】The logic circuit 70 includes, for example, a scan line drive circuit 71, a signal line drive circuit 72, a control line drive circuit 73, and a display control circuit 74, as shown in Figure 9. The signal line drive circuit 72 is capable of supplying, for example, a video signal for a unit pixel row supplied from the display control circuit 74 as a signal voltage to each pixel 11 or each pixel 61. Specifically, the signal line drive circuit 72 is capable of supplying, for example, a signal voltage corresponding to a unit pixel row of video signal to each pixel 11 of the unit pixel row selected by the scan line drive circuit 71 via the signal line DTLx. The signal line drive circuit 72 is capable of supplying, for example, a signal voltage corresponding to a unit pixel row of video signal to each pixel 61 of the unit pixel row selected by the scan line drive circuit 71 via the signal line DTLy. 【0082】 The scan line drive circuit 71 can sequentially select multiple pixels 11 for each unit pixel row based on, for example, a scan timing control signal (e.g., a vertical synchronization signal VSYNC and a clock signal) supplied from the display control circuit 74. Specifically, the scan line drive circuit 71 can select each pixel 11 in a unit pixel row of the multiple pixels 11 arranged in two dimensions as a voltage holding target by, for example, applying a selection pulse to the scan line WSLx and applying the selection pulse to the on / off control terminal of the switch element SW1 of each pixel 11 in a unit pixel row of the multiple pixels 11 arranged in two dimensions. Then, for each pixel 11 selected by the scan line drive circuit 71, the signal voltage supplied from the signal line drive circuit 72 is stored in the holding circuit MEM. 【0083】The scan line drive circuit 71 can sequentially select multiple pixels 61 for each unit pixel row based on, for example, a scan timing control signal (e.g., a vertical synchronization signal VSYNC and a clock signal) supplied from the display control circuit 74. Specifically, the scan line drive circuit 71 can select each pixel 61 in a unit pixel row of the multiple pixels 61 arranged in two dimensions as a voltage holding target by, for example, applying a selection pulse to the scan line WSLy and applying the selection pulse to the on / off control terminal of the switch element SW1 of each pixel 61 in a unit pixel row of the multiple pixels 61 arranged in two dimensions. Then, for each pixel 61 selected by the scan line drive circuit 71, the signal voltage supplied from the signal line drive circuit 72 is stored in the holding circuit MEM. 【0084】 The control line drive circuit 73 can, for example, select a pixel 11 or pixel 61 to output a signal voltage stored in the holding circuit MEM to the electro-optical element 111, based on a scanning timing control signal (e.g., a vertical synchronization signal VSYNC and a clock signal) supplied from the display control circuit 74. 【0085】 In the area-wide drive mode, the control line drive circuit 73 can select all two-dimensionally arranged pixels 11 as display targets by, for example, applying a selection pulse to the on / off control terminal of the switch element SW2 of the pixel 11 via the control line CTLx. In the area-wide drive mode, the control line drive circuit 73 can further decouple all two-dimensionally arranged pixels 61 from all pixels 11 by, for example, applying a non-selection signal to the on / off control terminal of the switch element SW2 of the pixel 61 via the control line CTLi. Then, for all pixels 11 selected by the control line drive circuit 73, a display is made according to the signal voltage supplied from the holding circuit MEM. In the area-wide drive mode, the control line drive circuit 73 can, for example, select all pixel rows and cause the display panel 50 to display across the entire display area. 【0086】In the surface-wide drive mode, the control line drive circuit 73 can select all two-dimensionally arranged pixels 61 as display targets by, for example, applying a selection pulse to the on / off control terminal of the switch element SW2 of the pixel 61 via the control line CTly. In the surface-wide drive mode, the control line drive circuit 73 can further decouple all two-dimensionally arranged pixel circuits 112 in the display panel 50 from all pixels 61 and all electro-optic elements 111 by, for example, applying a non-selection signal to the on / off control terminal of the switch element SW2 of the pixel 11 via the control line CTLx. Then, all pixels 61 and all electro-optic elements 111 selected by the control line drive circuit 73 display according to the signal voltage supplied from the holding circuit MEM. In the surface-wide drive mode, the control line drive circuit 73 can, for example, select all pixel rows and cause all electro-optic elements 111 of the display panel 50 and the additional panel 60 to display across the entire display area. 【0087】 The display control circuit 74 can, for example, store and hold the input video signal in frame memory for each screen (each frame displayed). The display control circuit 74 can also, for example, control the scan line drive circuit 71, signal line drive circuit 72, and control line drive circuit 73 that drive the display panel 50 and the additional panel 60 so that they operate in conjunction. Specifically, the display control circuit 74 can, for example, supply scan timing control signals (for example, the vertical synchronization signal VSYNC and the clock signal) to the scan line drive circuit 71 and the control line drive circuit 73, and supply the signal line drive circuit 72 with a video signal for a unit pixel row based on the video signal held in frame memory, and an output timing control signal. 【0088】(Simultaneous surface drive mode) At time t1 immediately before the frame period F1, the logic circuit 70 turns off the control signal TGT1 of one of the two pixels 11, 61 connected by connection pads P1, P2, thereby disconnecting the holding circuit MEM of one of the two pixels 11, 61 connected by connection pads P1, P2 from the electro-optical element 111. Then, at time t2 of the frame period F1, the logic circuit 70 turns on the control signal TGT2 of the other pixel 61 connected by connection pads P1, P2, thereby connecting the holding circuit MEM of the other pixel 61 connected by connection pads P1, P2 to the electro-optical element 111. As a result, the voltage MM2 of the holding circuit MEM is applied to the electro-optical elements 111 of all pixels 11, and the voltage of the electro-optical elements 111 changes to a voltage corresponding to the signal voltage. In this way, the entire surface is displayed during frame period F1. 【0089】 The logic circuit 70 then turns on the selection signal GT1 of one of the two pixels 11 and 61 connected by connection pads P1 and P2 at time t3 in the frame period F1, and connects the holding circuit MEM of one of the two pixels 11 and 61 connected by connection pads P1 and P2 to the signal line DTLx. As a result, the voltage MM1 of the holding circuit MEM changes to a voltage corresponding to the signal voltage in each pixel 11 for which the selection signal GT1 has been turned on. The logic circuit 70 then turns off the selection signal GT1 of one of the two pixels 11 and 61 connected by connection pads P1 and P2, and disconnects the holding circuit MEM of one of the two pixels 11 and 61 connected by connection pads P1 and P2 from the signal line DTLx. During the frame period F1, the logic circuit 70 sequentially controls the selection signal GT1 to be turned on and off in multiple target pixel rows out of all pixel rows. As a result, during the frame period F1, the holding circuit MEM holds a voltage corresponding to the signal voltage in multiple target pixel rows out of all pixel rows. In this way, during the frame period F1, the entire surface is displayed simultaneously, and a new voltage holding is performed using one of the two pixels 11, 61 connected by connection pads P1, P2. 【0090】At time t4 in frame period F1, the logic circuit 70 turns off the control signal TGT2 of the other pixel 61 of the two pixels 11, 61 connected by connection pads P1, P2, thereby disconnecting the holding circuit MEM of the other pixel 61 from the electro-optic element 111. As a result, the voltage MM1 of the holding circuit MEM is applied to the electro-optic elements 111 of all pixels 11, and the voltage of the electro-optic elements 111 changes to a voltage corresponding to the signal voltage. In this way, the entire surface is displayed at once during frame period F2. 【0091】 The logic circuit 70 then turns on the selection signal GT2 of the other pixel 61 of the two pixels 11, 61 connected by connection pads P1, P2 at time t6 in the frame period F2, and connects the holding circuit MEM of the other pixel 61 of the two pixels 11, 61 connected by connection pads P1, P2 to the signal line DTly. As a result, the voltage MM2 of the holding circuit MEM changes to a voltage corresponding to the signal voltage in each pixel 61 for which the selection signal GT2 has been turned on. The logic circuit 70 then turns off the selection signal GT2 of the other pixel 61 of the two pixels 11, 61 connected by connection pads P1, P2, and disconnects the holding circuit MEM of the other pixel 61 of the two pixels 11, 61 connected by connection pads P1, P2 from the signal line DTly. During the frame period F2, the logic circuit 70 sequentially controls the selection signal GT2 to be turned on and off in multiple target pixel rows out of all pixel rows. As a result, during the frame period F2, the holding circuit MEM holds a voltage corresponding to the signal voltage in multiple target pixel rows out of all pixel rows. In this way, during the frame period F2, the entire surface is displayed simultaneously, and a new voltage is held using the other pixel 61 of the two pixels 11 and 61 connected by connection pads P1 and P2. The logic circuit 70 repeatedly performs the above series of controls to display the entire surface for each frame period and to hold the voltage to be used for the entire surface display of the next frame. 【0092】 [Effects] Next, we will explain the effects of the display device 3. 【0093】In this embodiment, a display panel 50 is provided that includes a plurality of signal lines DTLx, a plurality of scan lines WSLx, a plurality of control lines CTLx, and a plurality of pixels 11, and an additional panel 60 is provided that includes a plurality of signal lines DTLy, a plurality of scan lines WSLy, a plurality of control lines CTLY, and a plurality of pixels 61. Each pixel 11 is provided with an electro-optical element 111 and a pixel circuit 112 in which a switch element SW2 is provided between a holding circuit MEM and an electro-optical element 111. Each pixel 61 is provided with a pixel circuit 112 in which a switch element SW2 is provided between a holding circuit MEM and an electro-optical element 111 (connection pad P2). This enables a surface-wide drive that allows writing to multiple electro-optic elements 111 in a single frame period by alternately turning on and off the switch element SW2 of the display panel 50 and the switch element SW2 of the additional panel 60, which are provided corresponding to the common electro-optic element 111, and sequentially turning on and off the switch element SW1 included in the pixels in each set of pixels 11, 61 where the switch element SW2 is off, via multiple scan lines WSLx and multiple control lines CTLx, and turning off the switch element SW1 included in the pixels in each set of pixels 11, 61 where the switch element SW2 is on. Here, the display panel 50 itself has a circuit configuration that allows sequential writing to multiple electro-optic elements 111 via multiple signal lines DTLx, multiple scan lines WSLx and multiple control lines CTLx. Thus, in the display device 3 according to this embodiment, a display panel 50 that enables sequential driving can be reused. Therefore, compared to designing separate circuits for display devices capable of sequential line drive only and display devices capable of simultaneous surface drive only, the time and cost required for device development of the display device 3 can be reduced. 【0094】In this embodiment, for example, two switch elements SW2 included in two pixels 11 and 61 connected by connection pads P1 and P2 are alternately turned on and off via multiple control lines CTLx and multiple control lines CTLy, and the switch elements SW1 included in pixels where switch element SW2 is off in each pair of pixels 11 and 61 are turned on and off via multiple scan lines WSLx and multiple control lines CTLx, and the switch elements SW1 included in pixels where switch element SW2 is on in each pair of pixels 11 and 61 are turned off, thereby enabling surface-wide simultaneous writing to multiple electro-optic elements 111 for each frame period. In other words, a display panel 50 that enables line-sequential driving can be reused. Therefore, compared to designing separate circuits for a display device that can only perform line-sequential driving and a display device that can only perform surface-wide simultaneous driving, the time and cost required for device development of the display device 3 can be reduced. 【0095】 In this embodiment, connection pads P1 and P2 are connected to each other, and the display panel 50 and the additional panel 60 are stacked on top of each other. In other words, the display panel 50 that enables sequential line driving can be reused. Therefore, compared to designing separate circuits for a display device that can only perform sequential line driving and a display device that can only perform simultaneous surface driving, the time and cost required for device development of the display device 3 can be reduced. 【0096】 In this embodiment, the holding circuit MEM is configured to include SRAM. This allows both sequential line driving and simultaneous area driving to be performed during the frame period. 【0097】 In this embodiment, the electro-optic element 111 is configured to include an optical modulation element such as a liquid crystal. This enables image display using an optical modulation element such as a liquid crystal in both line-sequential and surface-synchronized driving modes. 【0098】 <7. Modifications of the Third Embodiment> Next, a modification of the display device 3 according to the third embodiment will be described. 【0099】In the third embodiment, the holding circuit MEM may include a capacitive element. Even in this case, the time and cost required for device development of the display device 3 can be reduced, similar to the third embodiment. 【0100】 In the third embodiment and its modified form, the display panel 50 and the additional panel 60 may be composed of a laminate formed on a common substrate. In this case, the portion of the laminate formed on the common substrate corresponding to the display panel 50 and the portion of the laminate formed on the common substrate corresponding to the additional panel 60 are electrically connected, for example, by wiring layers or through vias. Even in this case, as in the third embodiment, the time and cost required for device development of the display device 3 can be reduced. 【0101】 In the third embodiment and its modifications, a light source capable of emitting light to illuminate the front surface of the display panel 50 may be provided instead of the backlight 20. Even in this case, as in the third embodiment, the time and cost required for device development of the display device 3 can be reduced. 【0102】 In the third embodiment and its modifications, the electro-optic element 111 may be composed of, for example, an organic EL cell or other self-emissive element. In this case, a transistor Tr is connected in series with the electro-optic element 111, and the gate of the transistor Tr is connected to the output terminal of the switch element SW1. Furthermore, the backlight 20 is omitted. Even in this case, as in the third embodiment, the time and cost required for device development of the display device 3 can be reduced. 【0103】 The present disclosure has been described above with reference to embodiments and their modifications, but the present disclosure is not limited to the above embodiments, and various modifications are possible. The effects described herein are merely illustrative. The effects of the present disclosure are not limited to those described herein. The present disclosure may have effects other than those described herein. 【0104】Furthermore, for example, this disclosure can take the following configuration. (1) A plurality of signal lines, a plurality of scan lines, a plurality of first control lines, a plurality of second control lines, a plurality of pixels provided corresponding to the intersections of the plurality of signal lines and the plurality of scan lines, a plurality of switch elements provided one for every two first pixels among the plurality of first pixels, when a plurality of pixels provided corresponding to a common signal line among the plurality of pixels are designated as a plurality of first pixels, a drive circuit capable of driving the plurality of pixels via the plurality of signal lines, the plurality of scan lines and the plurality of first control lines, and controlling the plurality of switch elements via the plurality of second control lines, the pixel having an electro-optic element and a pixel circuit connected to the electro-optic element, the pixel circuit having a holding circuit, a first switch element provided between the signal line and the holding circuit, and a second switch element provided between the electro-optic element and the holding circuit, the scan lines being connected to the on / off control terminals of the first switch elements, the first control lines being connected to the on / off control terminals of the second switch elements, (2) The electro-optic device wherein the second control line is connected to the on / off control terminal of the switch element, and the switch element is provided between a first wiring between the electro-optic element and the holding circuit in a second pixel which is one of the two first pixels, and between the second wiring between the electro-optic element and the holding circuit in a third pixel which is the other of the two first pixels, and the first wiring and the second wiring can be switched off. (2) The electro-optic device according to (1), wherein the drive circuit can turn off each of the switch elements via the plurality of second control lines, and then write to the plurality of electro-optic elements in line sequentially via the plurality of signal lines, the plurality of scan lines and the plurality of first control lines.(3) The electro-optical apparatus according to (1), wherein the drive circuit turns on each of the switch elements via the plurality of second control lines, alternately turns on and off the two second switch elements included in the two first pixels via the plurality of first control lines, turns on and off sequentially via the plurality of scan lines for the first switch elements included in the first pixel of the two first pixels in which the second switch elements are off, and writes to the first pixel of the two first pixels in which the second switch elements are on in a batch for each frame period.(4) An electro-optical device comprising: a plurality of signal lines; a plurality of scan lines; a plurality of control lines; a plurality of pixels provided corresponding to the points where the plurality of signal lines and the plurality of scan lines intersect each other; and a drive circuit capable of driving the plurality of pixels via the plurality of signal lines, the plurality of scan lines and the plurality of control lines, wherein each pixel has a pixel circuit, the pixel circuit has a holding circuit, a first switch element provided between the signal line and the holding circuit, and a second switch element, the scan line is connected to the on / off control terminal of the first switch element, the control line is connected to the on / off control terminal of the second switch element, and the electro-optical device further comprises a first laminate and a second laminate. The first laminate includes a plurality of first signal lines which are part of the plurality of signal lines, a plurality of first scan lines which are part of the plurality of scan lines, a plurality of first control lines which are part of the plurality of control lines, and a plurality of first pixels which are provided among the plurality of pixels corresponding to the locations where the plurality of first signal lines and the plurality of first scan lines intersect each other; the second laminate includes a plurality of second signal lines which are part of the plurality of signal lines, a plurality of second scan lines which are part of the plurality of scan lines, a plurality of second control lines which are part of the plurality of control lines, and a plurality of second pixels which are provided among the plurality of pixels corresponding to the locations where the plurality of second signal lines and the plurality of second scan lines intersect each other; the first pixel has an electro-optic element and a first pixel circuit which is provided as the pixel circuit, the second switch element between the holding circuit and the electro-optic element; and the second pixel has a second pixel circuit which is provided as the pixel circuit, the second switch element between the holding circuit and the electro-optic element.(5) The electro-optical apparatus according to (4), wherein the drive circuit alternately turns on and off the second switch of the first laminate and the second switch of the second laminate, which are provided corresponding to a common electro-optic element, via the plurality of control lines, and sequentially turns on and off the first switch element included in the pixels of the first and second pixels in which the second switch element is off, via the plurality of scan lines, and turns off the first switch element included in the pixels of the first and second pixels in which the second switch element is on, thereby enabling writing to the plurality of electro-optic elements in a batch for each frame period. (6) The electro-optical apparatus according to (4), wherein the first laminate further has a first connection portion for each first pixel that is electrically connected to a first wiring between the second switch element and the electro-optic element, and the second laminate further has a second connection portion for each second pixel that is electrically connected to a second wiring that is electrically connected to the second switch element, and the first connection portion and the second connection portion are connected to each other, and the first laminate and the second laminate are stacked on top of each other. (7) The holding circuit includes SRAM (Static Random Access Memory) in the electro-optical apparatus according to any one of (1) to (6). (8) The holding circuit includes a capacitive element in the electro-optical apparatus according to any one of (1) to (6). (9) The electro-optical element includes a light modulation element in the electro-optical apparatus according to any one of (1) to (8). (10) The electro-optical element includes a self-luminous element in the electro-optical apparatus according to any one of (1) to (8). (11) The plurality of pixels are provided on a common panel in the electro-optical apparatus according to any one of (1) to (3). 【0105】 This application claims priority based on Japanese Patent Application No. 2024-217739, filed with the Japan Patent Office on 12 December 2024, and all contents of that application are incorporated herein by reference. 【0106】Those skilled in the art will understand that various modifications, combinations, subcombinations, and changes can be conceived depending on design requirements and other factors, and that these fall within the scope of the attached claims and their equivalents.

Claims

1. A plurality of signal lines, a plurality of scan lines, a plurality of first control lines, a plurality of second control lines, a plurality of pixels provided corresponding to the intersections of the plurality of signal lines and the plurality of scan lines, a plurality of switch elements provided one for every two second pixels among the plurality of first pixels, where a plurality of pixels provided corresponding to a common signal line are designated as a plurality of first pixels, and a drive circuit capable of driving the plurality of pixels via the plurality of signal lines, the plurality of scan lines and the plurality of first control lines, and controlling the plurality of switch elements via the plurality of second control lines, wherein each pixel has an electro-optic element and a pixel circuit connected to the electro-optic element, the pixel circuit has a holding circuit, a first switch element provided between the signal line and the holding circuit, and a second switch element provided between the electro-optic element and the holding circuit, the scan lines are connected to the on / off control terminals of the first switch elements, and the first control lines are connected to the on / off control terminals of the second switch elements. The second control line is connected to the on / off control terminal of the switch element, and the switch element is provided between a first wiring in a third pixel, which is one of the two second pixels, and the holding circuit, and between a second wiring in a fourth pixel, which is the other of the two second pixels, and the holding circuit, thereby enabling the connection between the first wiring and the second wiring in the electro-optic device.

2. The electro-optic apparatus according to claim 1, wherein the drive circuit is capable of sequentially writing to the plurality of electro-optic elements via the plurality of signal lines, the plurality of scan lines, and the plurality of first control lines, after turning off each of the switch elements via the plurality of second control lines.

3. The electro-optical apparatus according to claim 1, wherein the drive circuit turns on each of the switch elements via the plurality of second control lines, alternately turns on and off the two second switch elements included in the two first pixels via the plurality of first control lines, turns on and off sequentially via the plurality of scan lines for the first switch elements included in the first pixel of the two first pixels in which the second switch elements are off, and enables writing to the first pixel of the two first pixels in which the second switch elements are on, all at once for each frame period.

4. An electro-optical device comprising: a plurality of signal lines; a plurality of scan lines; a plurality of control lines; a plurality of pixels provided corresponding to the intersections of the plurality of signal lines and the plurality of scan lines; and a drive circuit capable of driving the plurality of pixels via the plurality of signal lines, the plurality of scan lines and the plurality of control lines, wherein each pixel has a pixel circuit, the pixel circuit has a holding circuit, a first switch element provided between the signal line and the holding circuit, and a second switch element, the scan lines are connected to the on / off control terminals of the first switch elements, the control lines are connected to the on / off control terminals of the second switch elements, and the electro-optical device further comprises a first laminate and a second laminate. The first laminate includes a plurality of first signal lines which are part of the plurality of signal lines, a plurality of first scan lines which are part of the plurality of scan lines, a plurality of first control lines which are part of the plurality of control lines, and a plurality of first pixels which are provided among the plurality of pixels corresponding to the locations where the plurality of first signal lines and the plurality of first scan lines intersect each other; the second laminate includes a plurality of second signal lines which are part of the plurality of signal lines, a plurality of second scan lines which are part of the plurality of scan lines, a plurality of second control lines which are part of the plurality of control lines, and a plurality of second pixels which are provided among the plurality of pixels corresponding to the locations where the plurality of second signal lines and the plurality of second scan lines intersect each other; the first pixel has an electro-optic element and a first pixel circuit which is provided as the pixel circuit, the second switch element between the holding circuit and the electro-optic element; and the second pixel has a second pixel circuit which is provided as the pixel circuit, the second switch element between the holding circuit and the electro-optic element.

5. The electro-optical apparatus according to claim 4, wherein the drive circuit alternately turns on and off the second switch of the first laminate and the second switch of the second laminate, which are provided corresponding to a common electro-optic element, via the plurality of control lines, and sequentially turns on and off the first switch element included in the pixels of the first and second pixels in which the second switch element is off, via the plurality of scan lines, and turns off the first switch element included in the pixels of the first and second pixels in which the second switch element is on, thereby enabling writing to the plurality of electro-optic elements in a batch for each frame period.

6. The electro-optical apparatus according to claim 4, wherein the first laminate further has a first connection portion for each first pixel that is electrically connected to a first wiring between the second switch element and the electro-optic element, and the second laminate further has a second connection portion for each second pixel that is electrically connected to a second wiring that is electrically connected to the second switch element, and the first connection portion and the second connection portion are connected to each other, and the first laminate and the second laminate are stacked on top of each other.

7. The electro-optical apparatus according to claim 1 or 4, wherein the holding circuit includes SRAM (Static Random Access Memory).

8. The electro-optical apparatus according to claim 1 or claim 4, wherein the holding circuit includes a capacitive element.

9. The electro-optic device according to claim 1 or claim 4, wherein the electro-optic element includes a light modulation element.

10. The electro-optic device according to claim 1 or claim 4, wherein the electro-optic element includes a self-luminous element.

11. The electro-optical apparatus according to claim 1, wherein the plurality of pixels are provided on a common panel.

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