Detection device

Abstract

This detection device comprises: a substrate; a plurality of photodiodes disposed on the substrate; and an element insulating film provided between the plurality of photodiodes. In the plurality of photodiodes, a lower electrode, a lower buffer layer, an active layer, an upper buffer layer, and a first upper electrode are laminated in this order. The element insulating film covers at least side surfaces of the lower buffer layer, the active layer, and the upper buffer layer, is disposed between the upper buffer layer and the first upper electrode, and has a plurality of openings provided in a region overlapping the first upper electrode. The first upper electrode is electrically connected to the upper buffer layer through the plurality of openings of the element insulating film.

Description

Detection device

[0001] The present invention relates to a detection device.

[0002] Optical sensors capable of detecting fingerprint patterns and vein patterns are known (for example, Patent Document 1). Such an optical sensor has a plurality of photodiodes (OPD: Organic Photodiode) using an organic semiconductor material as an active layer. As described in Patent Document 2, the photodiode is laminated, for example, in the order of a lower electrode, an electron transport layer, an active layer, a hole transport layer, and an upper electrode. The electron transport layer or the hole transport layer is also called a buffer layer.

[0003] Japanese Patent Application Laid-Open No. 2009-32005 International Publication No. 2020 / 188959

[0004] When patterning an active layer, an insulating film, etc. of such an OPD by etching, pinholes may be formed. Therefore, a short circuit may occur between the upper electrode and the lower electrode through the pinholes.

[0005] An object of the present invention is to provide a detection device capable of suppressing the occurrence of a short circuit between an upper electrode and a lower electrode.

[0006] The detection device according to one aspect of the present disclosure includes a substrate, a plurality of photodiodes disposed on the substrate, and an element insulating film provided between the plurality of photodiodes. The plurality of photodiodes are laminated in the order of a lower electrode, a lower buffer layer, an active layer, an upper buffer layer, and a first upper electrode. The element insulating film covers at least the side surfaces of the lower buffer layer, the active layer, and the upper buffer layer, and is disposed between the upper buffer layer and the first upper electrode, and has a plurality of openings provided in a region overlapping the first upper electrode. The first upper electrode is electrically connected to the upper buffer layer through the plurality of openings of the element insulating film.

[0007] Figure 1 is a schematic plan view showing a detection device according to an embodiment. Figure 2 is a block diagram showing an example of the configuration of the detection device according to an embodiment. Figure 3 is a circuit diagram showing the detection device according to an embodiment. Figure 4 is a schematic plan view showing the arrangement relationship of a plurality of photodiodes in the detection region and the contact and mounting parts in the surrounding region. Figure 5 is a cross-sectional view taken along line V-V' in Figure 4. Figure 6 is a plan view showing a photodiode according to an embodiment. Figure 7 is an explanatory diagram for explaining the manufacturing method of the detection device according to an embodiment. Figure 8 is an explanatory diagram for explaining the manufacturing method of the detection device according to an embodiment. Figure 9 is an explanatory diagram for explaining another example of the manufacturing method of the detection device according to an embodiment. Figure 10 is a plan view showing a photodiode according to a first modified example. Figure 11 is a cross-sectional view showing a photodiode according to a second modified example.

[0008] The embodiments for implementing this disclosure will be described in detail with reference to the drawings. This disclosure is not limited to the embodiments described below. Furthermore, the components described below include those that can be easily conceived by a person skilled in the art, and those that are substantially the same. In addition, the components described below can be combined as appropriate. The disclosure is merely an example, and any modifications that a person skilled in the art can easily conceive while maintaining the spirit of this disclosure are naturally included within the scope of this disclosure. Furthermore, in order to make the explanation clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual embodiment, but these are merely examples and do not limit the interpretation of this disclosure. Furthermore, in this disclosure and in each drawing, elements similar to those described above with respect to previously shown drawings are denoted by the same reference numerals, and detailed explanations may be omitted as appropriate.

[0009] In this disclosure, when describing a manner in which one structure is placed on top of another structure, unless otherwise specified, the term "on top of" includes both cases: when one structure is placed directly on top of another structure so as to be in contact with it, and when another structure is placed above another structure via yet another structure.

[0010] (Embodiment) Figure 1 is a schematic plan view showing a detection device according to an embodiment. As shown in Figure 1, the detection device 1 includes a substrate 21, a sensor unit 10, a gate line drive circuit 15, a signal line selection circuit 16, a detection circuit 48, a control circuit 122, a power supply circuit 123, a first light source substrate 51, a second light source substrate 52, and light sources 53 and 54. The first light source substrate 51 is provided with a plurality of light sources 53. The second light source substrate 52 is provided with a plurality of light sources 54.

[0011] The control board 121 is electrically connected to the substrate 21 via the wiring board 71. The wiring board 71 is, for example, a flexible printed circuit board or a rigid circuit board. The wiring board 71 is provided with a detection circuit 48. The control board 121 is provided with a control circuit 122 and a power supply circuit 123. The control circuit 122 is, for example, an FPGA (Field Programmable Gate Array). The control circuit 122 supplies control signals to the sensor unit 10, the gate line drive circuit 15, and the signal line selection circuit 16 to control the detection operation of the sensor unit 10. The control circuit 122 also supplies control signals to the light sources 53 and 54 to control whether the light sources 53 and 54 are lit or not. The power supply circuit 123 supplies voltage signals such as the sensor power supply signal VDDSNS (see Figure 3) to the sensor unit 10, the gate line drive circuit 15, and the signal line selection circuit 16. Furthermore, the power supply circuit 123 supplies power supply voltage to the light sources 53 and 54.

[0012] The substrate 21 has a detection region AA and a peripheral region GA. The detection region AA is the region where the multiple photodiodes PD (see Figure 4) of the sensor unit 10 are provided. The peripheral region GA is the region between the outer periphery of the detection region AA and the outer edge of the substrate 21, and is a region where the multiple photodiodes PD are not provided.

[0013] The gate line drive circuit 15 and the signal line selection circuit 16 are provided in the peripheral region GA. Specifically, the gate line drive circuit 15 is provided in the region of the peripheral region GA that extends along the second direction Dy. The signal line selection circuit 16 is provided in the region of the peripheral region GA that extends along the first direction Dx, and is provided between the sensor unit 10 and the detection circuit 48.

[0014] In the following explanation, the first direction Dx is one direction in a plane parallel to the substrate 21. The second direction Dy is one direction in a plane parallel to the substrate 21 and is perpendicular to the first direction Dx. Note that the second direction Dy may intersect the first direction Dx without being perpendicular to it. The third direction Dz is perpendicular to the first direction Dx and the second direction Dy and is the normal direction to the main surface of the substrate 21. Furthermore, "plan view" refers to the positional relationship when viewed from a direction perpendicular to the substrate 21 (third direction Dz).

[0015] Multiple light sources 53 are provided on the first light source substrate 51 and are arranged along the second direction Dy. Multiple light sources 54 are provided on the second light source substrate 52 and are arranged along the second direction Dy. The first light source substrate 51 and the second light source substrate 52 are electrically connected to the control circuit 122 and the power supply circuit 123, respectively, via terminals 124 and 125 provided on the control board 121.

[0016] The multiple light sources 53 and 54 can be, for example, inorganic LEDs (Light Emitting Diodes) or organic EL (OLEDs: Organic Light Emitting Diodes). Each of the multiple light sources 53 and 54 emits light of a different wavelength.

[0017] The first light emitted from the light source 53 is mainly reflected by the surface of the object to be detected, such as a finger, and enters the sensor unit 10. As a result, the sensor unit 10 can detect fingerprints by detecting the shape of the irregularities on the surface of the finger, etc. The second light emitted from the light source 54 is mainly reflected inside the finger, etc., or passes through the finger, etc., and enters the sensor unit 10. As a result, the sensor unit 10 can detect biological information inside the finger, etc. Biological information includes, for example, pulse waves, pulse rate, and vascular images of the finger or palm. In other words, the detection device 1 may be configured as a fingerprint detection device for detecting fingerprints, or as a vein detection device for detecting vascular patterns such as veins.

[0018] Note that the arrangement of light sources 53 and 54 shown in Figure 1 is merely an example and can be changed as appropriate. The detection device 1 is provided with multiple types of light sources 53 and 54. However, it is not limited to this, and there may be only one type of light source. For example, multiple light sources 53 and multiple light sources 54 may be arranged on the first light source substrate 51 and the second light source substrate 52, respectively. Also, there may be one or more light source substrates on which light sources 53 and light sources 54 are provided. Alternatively, it is sufficient to have at least one light source.

[0019] Figure 2 is a block diagram showing an example configuration of a detection device according to an embodiment. As shown in Figure 2, the detection device 1 further includes a detection control circuit 11 and a detection unit 40. Some or all of the functions of the detection control circuit 11 are included in the control circuit 122. Also, some or all of the functions of the detection unit 40 other than the detection circuit 48 are included in the control circuit 122.

[0020] The sensor unit 10 has multiple photodiodes PD. The photodiodes PD of the sensor unit 10 output an electrical signal corresponding to the irradiated light as a detection signal Vdet to the signal line selection circuit 16. The sensor unit 10 also performs detection according to the gate drive signal VGL supplied from the gate line drive circuit 15.

[0021] The detection control circuit 11 is a circuit that supplies control signals to the gate line drive circuit 15, the signal line selection circuit 16, and the detection unit 40, respectively, and controls their operation. The detection control circuit 11 supplies various control signals such as the start signal STV and the clock signal CK to the gate line drive circuit 15. The detection control circuit 11 also supplies various control signals such as the selection signal ASW to the signal line selection circuit 16. Furthermore, the detection control circuit 11 supplies various control signals to the light sources 53 and 54 to control their illumination and de-illumination.

[0022] The gate line drive circuit 15 is a circuit that drives multiple gate lines GL (see Figure 3) based on various control signals. The gate line drive circuit 15 sequentially or simultaneously selects multiple gate lines GL and supplies a gate drive signal VGL to the selected gate lines GL. As a result, the gate line drive circuit 15 selects multiple photodiodes PD connected to the gate lines GL.

[0023] The signal line selection circuit 16 is a switch circuit that sequentially or simultaneously selects a plurality of signal lines SL (see Figure 3). The signal line selection circuit 16 is, for example, a multiplexer. Based on the selection signal ASW supplied from the detection control circuit 11, the signal line selection circuit 16 connects the selected signal line SL to the detection circuit 48. As a result, the signal line selection circuit 16 outputs the detection signal Vdet of the photodiode PD to the detection unit 40.

[0024] The detection unit 40 includes a detection circuit 48, a signal processing circuit 44, a coordinate extraction circuit 45, a storage circuit 46, and a detection timing control circuit 47. The detection timing control circuit 47 controls the detection circuit 48, the signal processing circuit 44, and the coordinate extraction circuit 45 to operate synchronously based on a control signal supplied from the detection control circuit 11.

[0025] The detection circuit 48 is, for example, an analog front-end circuit (AFE). The detection circuit 48 is a signal processing circuit that has at least the functions of a detection signal amplification circuit 42 and an A / D conversion circuit 43. The detection signal amplification circuit 42 amplifies the detection signal Vdet. The A / D conversion circuit 43 converts the analog signal output from the detection signal amplification circuit 42 into a digital signal.

[0026] The signal processing circuit 44 is a logic circuit that detects a predetermined physical quantity input to the sensor unit 10 based on the output signal of the detection circuit 48. The signal processing circuit 44 can detect the surface irregularities of the finger or palm based on the signal from the detection circuit 48 when the finger is in contact with or close to the detection surface. The signal processing circuit 44 can also detect information related to the living body based on the signal from the detection circuit 48. This information related to the living body includes, for example, the vascular image of the finger or palm, pulse wave, pulse rate, blood oxygen concentration, etc.

[0027] The memory circuit 46 temporarily stores the signals calculated by the signal processing circuit 44. The memory circuit 46 may be, for example, RAM (Random Access Memory), a register circuit, or the like.

[0028] The coordinate extraction circuit 45 is a logic circuit that determines the detection coordinates of surface irregularities of fingers, etc., when finger contact or proximity is detected in the signal processing circuit 44. The coordinate extraction circuit 45 is also a logic circuit that determines the detection coordinates of blood vessels in fingers and palms. The coordinate extraction circuit 45 combines the detection signals Vdet output from each photodiode PD of the sensor unit 10 to generate two-dimensional information indicating the shape of surface irregularities of fingers, etc., and two-dimensional information indicating the shape of blood vessels in fingers and palms. The coordinate extraction circuit 45 may output the detection signal Vdet as the sensor output voltage Vo without calculating the detection coordinates.

[0029] Figure 3 is a circuit diagram showing a detection device according to an embodiment. Figure 3 also shows the circuit configuration of the detection circuit 48. As shown in Figure 3, the sensor pixel PX includes a photodiode PD, a capacitive element Ca, and a drive transistor Tr. The capacitive element Ca is the capacitance (sensor capacitance) formed on the photodiode PD and is equivalently connected in parallel with the photodiode PD.

[0030] Multiple gate lines GL (scan lines) extend in the first direction Dx and are arranged in the second direction Dy. Multiple signal lines SL extend in the second direction Dy and are arranged in the first direction Dx. A drive transistor Tr (transistor) is connected to the gate lines GL and signal lines SL. Figure 3 shows two gate lines GL(m) and GL(m+1) aligned in the second direction Dy from among the multiple gate lines GL. Also, it shows two signal lines SL(n) and SL(n+1) aligned in the first direction Dx from among the multiple signal lines SL. The sensor pixel PX is the region enclosed by the gate lines GL and signal lines SL. The photodiode PD is placed in the region enclosed by adjacent gate lines GL and adjacent signal lines SL.

[0031] A drive transistor Tr is provided corresponding to each of the multiple photodiodes PD. The drive transistor Tr is composed of a thin-film transistor, and in this example, it is composed of an n-channel MOS (Metal Oxide Semiconductor) type TFT (Thin Film Transistor).

[0032] Each of the multiple gate lines GL is connected to the gate of a plurality of drive transistors Tr arranged in a first direction Dx. Each of the multiple signal lines SL is connected to either the source or the drain of a plurality of drive transistors Tr arranged in a second direction Dy. The other source or drain of the plurality of drive transistors Tr is connected to the cathode and capacitive element Ca of the photodiode PD. In other words, the photodiode PD is connected to the signal lines SL via the drive transistors Tr.

[0033] The anode of the photodiode PD is supplied with the sensor power supply signal VDDSNS from the power supply circuit 123 (see Figure 1). In addition, the signal line SL and the capacitive element Ca are supplied with the sensor reference voltage COM, which is the initial potential of the signal line SL and the capacitive element Ca, from the power supply circuit 123 via the reset transistor TrR.

[0034] During the exposure period, when light is shone onto the sensor pixel PX, a current flows through the photodiode PD in proportion to the amount of light, causing charge to accumulate in the capacitive element Ca. During the readout period, when the drive transistor Tr is turned on, a current flows through the signal line SL in proportion to the charge accumulated in the capacitive element Ca. The signal line SL is connected to the detection circuit 48 via the output transistor TrS of the signal line selection circuit 16. As a result, the detection device 1 can detect a signal corresponding to the amount of light shone onto the photodiode PD for each sensor pixel PX.

[0035] The detection circuit 48 is connected to the signal line SL when the switch SSW is turned on during the readout period. The detection signal amplification circuit 42 of the detection circuit 48 converts the current or charge supplied from the signal line SL into a voltage. A reference potential (Vref) with a fixed potential is input to the non-inverting input (+) of the detection signal amplification circuit 42, and the signal line SL is connected to the inverting input (-). In this embodiment, the same signal as the sensor reference voltage COM is input as the reference potential (Vref) voltage. The control circuit 122 (see Figure 1) calculates the difference between the detection signal Vdet when light is irradiated and the detection signal Vdet when light is not irradiated as the sensor output voltage Vo. The detection signal amplification circuit 42 also has a capacitive element Cb and a reset switch RSW. During the reset period, the reset switch RSW is turned on, and the charge of the capacitive element Cb is reset.

[0036] Furthermore, the driving transistor Tr is not limited to an n-type TFT, but may be composed of a p-type TFT. Also, the pixel circuit of the sensor pixel PX shown in Figure 3 is merely an example, and the sensor pixel PX may be provided with multiple transistors corresponding to one photodiode PD.

[0037] Next, the detailed configuration of the photodiode PD will be described with reference to Figures 4 to 6. Figure 4 is a schematic plan view showing the arrangement of multiple photodiodes in the detection region and the contact and mounting parts in the surrounding region.

[0038] As shown in Figure 4, multiple photodiodes PD are arranged in a matrix in the detection region AA. The photodiodes PD in this embodiment are organic photodiodes (OPDs) in which an organic semiconductor is used as the active layer 33 (see Figure 5).

[0039] The lower electrodes 31 of the plurality of photodiodes PD are provided separately for each of the plurality of photodiodes PD and are arranged in a matrix in the detection region AA. Further, the first upper electrodes 35 of the plurality of photodiodes PD are provided continuously across the plurality of photodiodes PD and are provided over the entire detection region AA. A part of the first upper electrode 35 extends into the peripheral region GA and is connected to the contact portion CN, and is electrically connected to an external circuit (for example, the control circuit 122 and the power supply circuit 123 (see FIG. 1)) through the wiring of the substrate 21.

[0040] The detection device 1 has a sealing film 90 that covers the plurality of photodiodes PD. The sealing film 90 is provided across the detection region AA and the peripheral region GA and is provided up to the outer edge side of the substrate 21. The sealing film 90 extends up to the outer edge side of the substrate 21 beyond the plurality of insulating films (for example, the organic insulating film 26, the barrier film 27, etc.) provided on the substrate 21. The sealing film 90 can suppress the intrusion of moisture from the outer edge side of the substrate 21 toward the detection region AA side. The detailed configurations of the photodiode PD, each insulating film, and the sealing film 90 will be described later with reference to FIG. 5.

[0041] The mounting portion 95 is provided on the substrate 21 outside the outer periphery of the sealing film 90. The mounting portion 95 includes, for example, connection terminals for connecting to the wiring substrate 71 (see FIG. 1). Alternatively, the mounting portion 95 may include mounting terminals for mounting an IC (Integrated Circuit) that constitutes the detection circuit 48 or the like.

[0042] Next, the stacked structure of the plurality of photodiodes PD and the sealing film 90 of the detection device 1 will be described. FIG. 5 is a cross-sectional view taken along the line V-V' of FIG. 4. FIG. 6 is a plan view showing the photodiode according to the embodiment. In FIG. 5, two photodiodes PD (sensor pixels PX) adjacent to each other in the first direction Dx are shown.

[0043] In the following description, in the direction perpendicular to the surface of the substrate 21, the direction from the substrate 21 toward the sealing film 90 is referred to as "upper side" or simply "up". Also, the direction from the sealing film 90 toward the substrate 21 is referred to as "lower side" or simply "down".

[0044] As shown in FIG. 5, the detection device 1 includes a substrate 21, a driving transistor Tr, a plurality of inorganic insulating films (an undercoat film 22, a gate insulating film 23, an interlayer insulating film 24, and a stacked insulating film 25), an organic insulating film 26, a barrier film 27, a photodiode PD, an element insulating film 39, and a sealing film 90. In the detection region AA, a plurality of inorganic insulating films (an undercoat film 22, a gate insulating film 23, an interlayer insulating film 24, and a stacked insulating film 25), an organic insulating film 26, a barrier film 27, a photodiode PD, an element insulating film 39, and a sealing film 90 are stacked in this order on the substrate 21.

[0045] The substrate 21 is an insulating substrate formed of a film-shaped resin. The driving transistor Tr is provided in a region overlapping with the lower electrode 31 of the photodiode PD. Specifically, the driving transistor Tr includes a semiconductor layer 61, a source electrode 62, a drain electrode 63, and a gate electrode 64.

[0046] A light shielding film 65 is provided on the substrate 21. The light shielding film 65 is provided between the semiconductor layer 61 and the substrate 21. The light shielding film 65 suppresses the intrusion of light from the substrate 21 side into the channel region of the semiconductor layer 61.

[0047] The undercoat film 22 is provided on the substrate 21 so as to cover the light shielding film 65. The undercoat film 22 is formed of an inorganic insulating film such as a silicon nitride film or a silicon oxide film. Note that the configuration of the undercoat film 22 is not limited to a single layer, and may be a stacked film formed by stacking, for example, two or three or more layers.

[0048] The driving transistor Tr is provided on the substrate 21. The semiconductor layer 61 is provided on the undercoat film 22. The gate insulating film 23 is provided on the undercoat film 22 so as to cover the semiconductor layer 61. The gate insulating film 23 is an inorganic insulating film such as a silicon oxide film. The gate electrode 64 is provided on the gate insulating film 23.

[0049] In the example shown in FIG. 5, the driving transistor Tr has a top gate structure. However, the present invention is not limited to this, and the driving transistor Tr may have a bottom gate structure or a dual gate structure in which gate electrodes 64 are provided on both the upper and lower sides of the semiconductor layer 61.

[0050] The interlayer insulating film 24 is provided on the gate insulating film 23, covering the gate electrode 64. The interlayer insulating film 24 has, for example, a laminated structure of a silicon nitride film and a silicon oxide film. The source electrode 62 and the drain electrode 63 are provided on the interlayer insulating film 24. The source electrode 62 is connected to the source region of the semiconductor layer 61 via a contact hole CH2 provided through the gate insulating film 23 and the interlayer insulating film 24. The drain electrode 63 is connected to the drain region of the semiconductor layer 61 via a contact hole CH3 provided through the gate insulating film 23 and the interlayer insulating film 24. The superimposed insulating film 25 is provided on the interlayer insulating film 24, covering the source electrode 62 and the drain electrode 63.

[0051] Furthermore, a connecting wire 64a is provided in the same layer as the gate electrode 64. The connecting wire 64a is electrically connected to the gate electrode 64. In addition, a connecting wire 65a is provided in the same layer as the light-shielding film 65. The connecting wire 65a is electrically connected to the light-shielding film 65. The connecting wires 64a and 65a are connected via a contact hole CH4 that penetrates the undercoat film 22 and the gate insulating film 23. As a result, the light-shielding film 65 is electrically connected to the gate electrode 64 via the connecting wires 64a and 65a, and is supplied with the same potential as the gate electrode 64.

[0052] The organic insulating film 26 is provided on top of the superimposed insulating film 25, covering the source electrode 62 and drain electrode 63 of the drive transistor Tr. The organic insulating film 26 is a planarized film formed of an organic insulating material. In this embodiment, the contact hole CH1 of the organic insulating film 26 is provided in a region that overlaps with the source electrode 62. The lower electrode 31 of the photodiode PD is electrically connected to the source electrode 62 at the bottom of the contact hole CH1.

[0053] In addition, the detection device 1 may be configured such that the superimposed insulating film 25 is not provided among the inorganic insulating films (undercoat film 22, gate insulating film 23, interlayer insulating film 24, and superimposed insulating film 25). In this case, the organic insulating film 26 is provided on top of the interlayer insulating film 24, covering the source electrode 62 and the drain electrode 63.

[0054] The barrier film 27 is provided on the organic insulating film 26. The barrier film 27 is formed of an inorganic insulating material such as a silicon nitride film (SiN).

[0055] The photodiode PD is provided on the barrier film 27. The photodiode PD has a lower electrode 31, a lower buffer layer 32, an active layer 33, an upper buffer layer 34, a second upper electrode 36, and a first upper electrode 35. The photodiode PD is stacked in the order of lower electrode 31, lower buffer layer 32, active layer 33, upper buffer layer 34, second upper electrode 36, and first upper electrode 35 in a direction perpendicular to the substrate 21.

[0056] The lower electrode 31 is formed of a light-transmitting conductive material such as ITO (Indium Tin Oxide). As described above, the lower electrode 31 is provided for each photodiode PD. In adjacent photodiodes PD, the lower electrodes 31 are arranged spaced apart from each other.

[0057] The insulating film 38 is provided to cover the peripheral edge of the lower electrode 31. The insulating film 38 insulates the lower electrodes 31 of adjacent photodiodes PD. The insulating film 38 is also provided to cover the contact hole CH1, and covers the lower electrode 31 in the region overlapping with the contact hole CH1. Even if a step break occurs in the lower buffer layer 32 in the region overlapping with the contact hole CH1, the insulating film 38 is provided, so a short circuit between the active layer 33 and the lower electrode 31 can be suppressed. In this embodiment, the insulating film 38 is a silicon nitride film (SiN) or a silicon oxide film (SiO ２ It is formed from inorganic insulating materials such as ).

[0058] The lower electrode 31, lower buffer layer 32, active layer 33, upper buffer layer 34, and second upper electrode 36 are provided spaced apart for each of the multiple photodiodes PD. Specifically, the lower buffer layer 32, active layer 33, upper buffer layer 34, and second upper electrode 36 are provided overlapping the lower electrode 31 in this order.

[0059] The active layer 33 changes its properties (e.g., voltage-current characteristics and resistance) depending on the light it is irradiated with. Organic materials are used as the material for the active layer 33. Specifically, the active layer 33 is a bulk heterostructure in which a p-type organic semiconductor and an n-type organic semiconductor, an n-type fullerene derivative (PCBM), are mixed. For example, C13 is a low-molecular-weight organic material used for the active layer 33. ６０ (Fullerene), PCBM (Phenyl C ６１ Methyl butyrate: Phenyl C 61 -butyric acid methyl ester), CuPc (copper phthalocyanine), F １６ CuPc (fluorinated copper phthalocyanine), rubrene (5,6,11,12-tetraphenyltetracene), PDI (perylene derivative), etc. can be used.

[0060] The active layer 33 can be formed by vapor deposition (Dry Process) using these low-molecular-weight organic materials. In this case, the active layer 33 can be, for example, CuPc and F １６ A multilayer film with CuPc, or rubrene and C ６０ It may be a laminated film. The active layer 33 can also be formed by a wet process. In this case, the active layer 33 is made of a material that combines the low molecular weight organic material and the polymer organic material described above. As the polymer organic material, for example, P3HT (poly(3-hexylthiophene)), F8BT (F8-alt-benzothiadiazole), etc. can be used. The active layer 33 can be a film in which P3HT and PCBM are mixed, or a film in which F8BT and PDI are mixed. Note that the active layer 33 is not limited to a bulk heterostructure and may be of the PIN type.

[0061] The lower buffer layer 32 and the upper buffer layer 34 are provided to facilitate the arrival of holes and electrons generated in the active layer 33 at the lower electrode 31 or the second upper electrode 36. The lower buffer layer 32 is provided between the lower electrode 31 and the active layer 33 and is in direct contact with both the lower electrode 31 and the active layer 33. The upper buffer layer 34 is provided between the active layer 33 and the second upper electrode 36 and is in direct contact with both the active layer 33 and the second upper electrode 36.

[0062] In this embodiment, the lower electrode 31 is the cathode electrode of the photodiode PD, and the upper electrodes (first upper electrode 35 and second upper electrode 36) are the anode electrodes of the photodiode PD. In this case, the lower buffer layer 32 is an electron transport layer, and the upper buffer layer 34 is a hole transport layer. The material used for the electron transport layer is ethoxylated polyethyleneimine (PEIE). The material used for the hole transport layer is a metal oxide layer. As the metal oxide layer, tungsten oxide (WO) ３ ), molybdenum oxide, etc. are used.

[0063] The lower electrode 31 may be the anode electrode of the photodiode PD, and the upper electrodes (first upper electrode 35 and second upper electrode 36) may be the cathode electrode of the photodiode PD. In this case, the lower buffer layer 32 may be a hole transport layer, and the upper buffer layer 34 may be an electron transport layer.

[0064] The second upper electrode 36 is provided on the upper buffer layer 34. The second upper electrode 36 is formed of a translucent conductive material such as ITO or IZO (Indium Zinc Oxide). However, it is not limited to this, and the second upper electrode 36 may be formed of an opaque conductive material such as silver (Ag).

[0065] The element insulating film 39 is provided between adjacent photodiodes PD. Specifically, the element insulating film 39 is provided on top of the insulating film 38 between adjacent photodiodes PD, covering at least the lower buffer layer 32, active layer 33, upper buffer layer 34, and the side surface of the second upper electrode 36. This provides insulation between the lower buffer layer 32, active layer 33, upper buffer layer 34, and second upper electrode 36 of adjacent photodiodes PD. Furthermore, the element insulating film 39 is positioned between the second upper electrode 36 and the first upper electrode 35, and a plurality of openings OP are provided in the region overlapping with the first upper electrode 35. The element insulating film 39 is formed of an organic insulating material such as acrylic resin. Alternatively, the element insulating film 39 may be an inorganic insulating material such as silicon nitride (SiN).

[0066] As shown in Figure 6, the multiple apertures OP provided in the element insulating film 39 are arranged in a matrix in a plan view. That is, the multiple apertures OP are arranged in the first direction Dx and the second direction Dy. In Figure 6, for the sake of clarity, the first upper electrode 35 is shown by a dashed line, and the second upper electrode 36 and the lower electrode 31 are shown by dashed lines.

[0067] Each of the multiple openings OP is, for example, rectangular. The width Wx of each of the multiple openings OP in the first direction Dx is smaller than the distance Lx between two adjacent openings OP in the first direction Dx. Also, the width Wy of each of the multiple openings OP in the second direction Dy is smaller than the distance Ly between two adjacent openings OP in the second direction Dy. More preferably, the width Wx of each of the multiple openings OP in the first direction Dx is 1 / 2 or less of the distance Lx between two adjacent openings OP in the first direction Dx. Also, the width Wy of each of the multiple openings OP in the second direction Dy is 1 / 2 or less of the distance Ly between two adjacent openings OP in the second direction Dy.

[0068] The widths Wx and Wy of each of the multiple apertures OP are, for example, about 10 μm each. The distances Lx and Ly between two adjacent apertures OP are, for example, about 30 μm each.

[0069] The first upper electrode 35 is provided continuously across multiple photodiodes PD, covering the second upper electrode 36 and the element insulating film 39. In the region where the element insulating film 39 is provided, the upper buffer layer 34, the second upper electrode 36, the element insulating film 39, and the first upper electrode 35 are stacked in that order. Furthermore, the first upper electrode 35 is electrically connected to the second upper electrode 36 and the upper buffer layer 34 through multiple openings OP in the element insulating film 39 at each of the multiple photodiodes PD. A sensor power supply signal VDDSNS (see Figure 3) having a predetermined potential is supplied to each of the multiple photodiodes PD through the first upper electrode 35.

[0070] The sealing film 90 is provided on the first upper electrode 35. The sealing film 90 is formed of an inorganic insulating material such as a silicon nitride film (SiN). The photodiode PD is well sealed by the sealing film 90, and the intrusion of moisture from the upper side can be suppressed. Note that the sealing film 90 is not limited to a single layer film but may be a multilayer film. Furthermore, the sealing film 90 may be a multilayer film in which an inorganic sealing film formed of an inorganic insulating material and an organic sealing film formed of an organic insulating material are laminated.

[0071] With the above configuration, in the detection device 1 of this embodiment, an element insulating film 39 is placed between the upper buffer layer 34 and the second upper electrode 36 of the photodiode PD and the first upper electrode 35. The first upper electrode 35 is electrically connected to the upper buffer layer 34 and the second upper electrode 36 through a plurality of openings OP in the element insulating film 39. As a result, even if through holes 102 are formed that penetrate the lower buffer layer 32, the active layer 33 and the upper buffer layer 34 when the photodiode PD is patterned by etching, the element insulating film 39 is provided to cover the through holes 102. Therefore, in this embodiment, it is possible to ensure conductivity between the first upper electrode 35 and the upper buffer layer 34 and the second upper electrode 36 while suppressing the occurrence of a short circuit between the first upper electrode 35 and the lower electrode 31.

[0072] Furthermore, the widths Wx and Wy of each of the multiple openings OP are smaller than the distances Lx and Ly between two adjacent openings OP. For this reason, compared to a configuration in which, for example, openings OP of the element insulating film 39 are formed over almost the entire area overlapping with the upper buffer layer 34 and the first upper electrode 35, the element insulating film 39 can be well provided covering the through holes 102 even when through holes 102 are formed in the lower buffer layer 32, the active layer 33, and the upper buffer layer 34. In other words, the probability that openings OP of the element insulating film 39 are not formed in the area overlapping with the through holes 102, or at least that openings OP are formed in the area overlapping with the through holes 102, can be reduced. Therefore, in this embodiment, it is possible to suppress the occurrence of a short circuit between the first upper electrode 35 and the lower electrode 31.

[0073] Note that the shape, arrangement, and number of the multiple apertures OP of the element insulating film 39 shown in Figure 6 are merely examples and can be changed as appropriate. For example, the multiple apertures OP are not limited to a square shape, but may be rectangular, polygonal, circular, elliptical, or other shapes. For example, if the multiple apertures OP are circular, the widths Wx and Wy can be rephrased as diameter or diameter.

[0074] Furthermore, in this embodiment, since the active layer 33 (including the lower buffer layer 32 and the upper buffer layer 34) is patterned separately for each photodiode PD, it is possible to suppress delays in the arrival time of carriers (holes and electrons) generated in the active layer 33 compared to a configuration in which the active layer 33 is continuously provided across multiple photodiodes PD.

[0075] More specifically, if the active layer 33 is provided across the entire detection area AA, then the active layer 33 also exists in the area between adjacent lower electrodes 31. Carriers generated in the area of ​​the active layer 33 that does not overlap with the lower electrodes 31 may experience a delay in response before reaching the lower electrodes 31 compared to carriers generated in the area of ​​the active layer 33 that overlaps with the lower electrodes 31. This delay in carriers generated in the active layer 33 may lead to detection errors or a decrease in the resolution between sensor pixels PX.

[0076] In this embodiment, the active layer 33 is patterned with separation between each photodiode PD (each lower electrode 31), and an insulating film 38 and an element insulating film 39 are provided in the region between adjacent lower electrodes 31. Therefore, compared to the case where the active layer 33 is provided across the entire detection region AA, the generation of carriers in the region between adjacent lower electrodes 31 is suppressed. Consequently, it is possible to suppress the delay in the arrival time of carriers (holes and electrons) generated in the active layer 33 in each photodiode PD.

[0077] Furthermore, in this embodiment, an insulating film 38 is provided between adjacent lower electrodes 31, and an element insulating film 39 is provided between adjacent active layers 33. This makes it possible to suppress leakage current between adjacent photodiodes PD.

[0078] (Method of Manufacturing the Detection Device) Figure 7 is an explanatory diagram illustrating the method of manufacturing the detection device according to the embodiment. Figure 8 is an explanatory diagram illustrating the method of manufacturing the detection device according to the embodiment. Figure 7 shows the process up to the patterning of the active layer 33 and the second upper electrode 36, and Figure 8 shows the process from the formation of the element insulating film 39 to the formation of the sealing film 90. Note that in Figures 7 and 8, the driving transistor Tr, various wirings, and insulating films formed between the substrate 21 and the photodiode PD are not shown.

[0079] As shown in Figure 7, an organic layer that will become the active layer 33 is coated and formed on the substrate 21, covering the plurality of lower electrodes 31, insulating film 38, and connection terminals 81 formed on the substrate 21 (step ST1). The active layer 33 is formed by coating, for example, spin coating or slit coating. The connection terminals 81 are electrodes that constitute the contact portion CN (see Figure 4) and are electrically connected to the plurality of photodiodes PD via the first upper electrode 35. Prior to step ST1, there is a step of forming a plurality of lower electrodes 31 in the detection region AA of the substrate 21, and forming connection terminals 81 in a peripheral region GA different from the detection region AA to supply a predetermined potential to the plurality of photodiodes PD.

[0080] Next, a second upper electrode 36 is deposited on the active layer 33 (step ST2). For example, IZO is used as the material for the second upper electrode 36. The second upper electrode 36 is formed over the entire surface of the active layer 33, for example, by sputtering.

[0081] A resist 92 is formed on the second upper electrode 36 by photolithography and etching (step ST3). The resist 92 is provided in the region overlapping with the lower electrode 31 (the region where the photodiode PD is to be formed), and removed in the region not overlapping with the lower electrode 31. The resist 92 is also removed in the region overlapping with the connection terminal 81 of the peripheral region GA.

[0082] The second upper electrode 36 is patterned, separating it from each of the multiple lower electrodes 31 (step ST4). In step ST4, the second upper electrode 36 in areas where the resist 92 is not provided is removed by dry etching. The second upper electrode 36 in areas where the resist 92 is provided (areas where the photodiode PD is to be formed) remains.

[0083] Next, using the multiple second upper electrodes 36 patterned in step ST4 as a mask, the active layer 33 is patterned, separating it from each of the multiple lower electrodes 31 (step ST5). In step ST5, the active layer 33 in areas where the second upper electrodes 36 are not provided is removed by dry etching. The active layer 33 in the areas where the second upper electrodes 36 are provided (the areas where the photodiode PD is to be formed) remains. Also in step ST5, the resist 92 on the second upper electrodes 36 is removed. Furthermore, in steps ST4 and ST5, the active layer 33 and the second upper electrodes 36 are also removed in areas overlapping with the connection terminals 81 of the peripheral region GA.

[0084] Next, as shown in Figure 8, an element insulating film 39 is formed to cover the multiple second upper electrodes 36 and between adjacent multiple active layers 33 and multiple second upper electrodes 36 (step ST6). The element insulating film 39 covers the sides of the active layer 33 and the second upper electrodes 36 and is provided on top of the insulating film 38 between adjacent active layers 33 and second upper electrodes 36.

[0085] A resist 93 is formed on the element insulating film 39 by photolithography and etching (step ST7). The resist 93 is provided in the region overlapping with the second upper electrode 36, and is removed in the region overlapping with the second upper electrode 36 where multiple openings OP of the element insulating film 39 are to be formed.

[0086] By dry etching, multiple openings OP are formed in the region of the element insulating film 39 that overlaps with the second upper electrode 36 (step ST8). In step ST8, the portion of the element insulating film 39 that overlaps with the connection terminal 81 of the peripheral region GA is also removed, exposing the connection terminal 81.

[0087] The first upper electrode 35 is formed by covering multiple second upper electrodes 36 and the element insulating film 39 (step ST9). In step ST9, the first upper electrode 35 is in contact with the second upper electrode 36 through multiple openings OP in the element insulating film 39. The first upper electrode 35 is also provided to extend to a region that overlaps with the connection terminal 81 of the peripheral region GA and is connected to the connection terminal 81.

[0088] A resist 94 is patterned on the first upper electrode 35 by photolithography and etching (step ST10). The resist 94 is formed on the entire detection area AA and the area overlapping with the connection terminal 81 of the first upper electrode 35. In addition, the resist 94 is removed from the area of ​​the peripheral region GA that does not overlap with the connection terminal 81.

[0089] Dry etching removes the portion of the first upper electrode 35 that is not covered with resist 94, that is, the portion that does not overlap with the connection terminal 81 of the peripheral region GA (step ST11).

[0090] Next, a sealing film 90 is formed on the first upper electrode 35 (step ST12). Note that the sealing film 90 is not limited to a single layer film, but may be a laminated film formed by stacking multiple insulating films.

[0091] The detection device 1 can be manufactured through the process described above. According to the manufacturing method of the detection device 1 of this embodiment, the second upper electrode 36 is used as a mask to pattern the active layer 33, so the variation in the shape of the active layer 33 can be suppressed compared to a method in which the second upper electrode 36 and the active layer 33 are patterned using masks individually. Therefore, the detection device 1 has reduced detection errors caused by variations in the shape of the multiple photodiodes PD. Consequently, the detection device 1 can improve its detection accuracy.

[0092] Figure 9 is an explanatory diagram illustrating another example of the manufacturing method of the detection device according to the embodiment. Steps ST11 to ST15 shown in Figure 9 are the same as steps ST1 to ST5 shown in Figure 7 described above, and a repeated explanation will be omitted.

[0093] As shown in Figure 9, after the active layer 33 is coated and formed, foreign matter 101 may adhere to it (step ST11). The second upper electrode 36 is formed on the active layer 33, covering the foreign matter 101 (step ST12).

[0094] The resist 92 formed on the second upper electrode 36 becomes thinner in the region overlapping with the foreign matter 101 (step ST13). Alternatively, the resist 92 may not be formed in the region overlapping with the foreign matter 101. As a result, in the process of patterning the second upper electrode 36 (step ST14), the second upper electrode 36 and resist 92 in the region overlapping with the foreign matter 101 may also be removed, forming through holes in the second upper electrode 36. In the process of patterning the active layer 33 using multiple second upper electrodes 36 as a mask, through holes 102 may also be formed in the active layer 33 (step ST15).

[0095] Through the process described above, even if a through-hole 102 is formed due to the adhesion of foreign matter 101, the element insulating film 39 is provided to cover the through-hole 102 as shown in Figure 5. Therefore, in this embodiment, it is possible to ensure conductivity between the first upper electrode 35 and the upper buffer layer 34 and the second upper electrode 36 while suppressing the occurrence of a short circuit between the first upper electrode 35 and the lower electrode 31.

[0096] Note that the manufacturing method of the detection device 1 shown in Figures 7 to 9 is merely an example and can be modified as appropriate. The foreign object 101 and through hole 102 shown in Figure 9 are shown with their sizes exaggerated for illustrative purposes.

[0097] (First Modified Example) Figure 10 is a plan view showing a photodiode according to the first modified example. In the following description, the same reference numerals are used for components that are the same as those described in the embodiments described above, and redundant explanations are omitted.

[0098] As shown in Figure 10, in the detection device 1A according to the first modified example, the multiple openings OP formed in the element insulating film 39 are arranged in a staggered pattern in a plan view. Specifically, the multiple openings OP in the nth row arranged in the first direction Dx and the multiple openings OP in the adjacent (n+1)th row are arranged with a shift in position in the first direction Dx. The multiple openings OP are arranged in a triangular shape with the multiple openings OP in two adjacent rows.

[0099] The width Wx of each of the multiple openings OP in the first direction Dx is smaller than the distance Lx between two adjacent openings OP in the first direction Dx. Also, the width Wx of each of the multiple openings OP in the first direction Dx is smaller than the distance Cx between the centers of two adjacent openings OP in the first direction Dx. The width Wx of each of the multiple openings OP in the first direction Dx and the width Wy in the second direction Dy are smaller than the distance Cxy between the centers of two adjacent openings OP in an oblique direction. The distances Cx and Cxy are the distances between the geometric centers of adjacent openings OP.

[0100] The widths Wx and Wy of each of the multiple apertures OP are, for example, about 10 μm each. The distance Lx between two adjacent apertures OP is, for example, about 30 μm. The distances Cx and Cxy between the centers of two adjacent apertures OP are, for example, both about 40 μm each.

[0101] Note that the shape, arrangement, and number of the multiple openings OP shown in Figure 10 are merely examples and can be modified as appropriate.

[0102] (Second Modification) Figure 11 is a cross-sectional view showing a photodiode according to the second modification. As shown in Figure 11, the detection device 1B according to the second modification differs from the embodiment described above in that it does not have a second upper electrode 36.

[0103] In the second modified example, the element insulating film 39 is positioned between the upper buffer layer 34 and the first upper electrode 35, and a plurality of openings OP are provided in the region overlapping with the first upper electrode 35. The first upper electrode 35 is electrically connected to the upper buffer layer 34 in each of the plurality of photodiodes PD through the plurality of openings OP of the element insulating film 39.

[0104] In the second modified example, since an element insulating film 39 having multiple apertures OP is provided, it is possible to suppress the occurrence of a short circuit between the first upper electrode 35 and the lower electrode 31. However, in the second modified example, since there is no second upper electrode 36, in the process of patterning the lower buffer layer 32, active layer 33, and upper buffer layer 34 of the photodiode PD by etching (see Figure 7), a different mask is provided in place of the second upper electrode 36.

[0105] While preferred embodiments of this disclosure have been described above, this disclosure is not limited to such embodiments. The contents disclosed in the embodiments are merely examples, and various modifications are possible without departing from the spirit of this disclosure. Any modifications made without departing from the spirit of this disclosure will naturally fall within the technical scope of this disclosure. At least one of various omissions, substitutions, and modifications of components can be made without departing from the gist of each embodiment and each modification described above.

[0106] 1 Detection device 10 Sensor section 21 Substrate 26 Organic insulating film 27 Barrier film 31 Lower electrode 32 Lower buffer layer 33 Active layer 34 Upper buffer layer 35 First upper electrode 36 Second upper electrode 38 Insulating film 39 Element insulating film 81 Connection terminal 90 Encapsulation film 95 Mounting section OP Aperture PD Photodiode PX Sensor pixel Tr Driving transistor

Claims

1. A detection device comprising: a substrate; a plurality of photodiodes arranged on the substrate; and an element insulating film provided between the plurality of photodiodes, wherein the plurality of photodiodes are stacked in the order of a lower electrode, a lower buffer layer, an active layer, an upper buffer layer, and a first upper electrode; the element insulating film covers at least the sides of the lower buffer layer, the active layer, and the upper buffer layer, and is provided between the upper buffer layer and the first upper electrode, and has a plurality of openings provided in a region overlapping with the first upper electrode; and the first upper electrode is electrically connected to the upper buffer layer through the plurality of openings in the element insulating film.

2. The detection device according to claim 1, wherein the plurality of photodiodes each have a second upper electrode disposed between the upper buffer layer and the first upper electrode, and the upper buffer layer, the second upper electrode, the element insulating film, and the first upper electrode are stacked in that order, and the first upper electrode is electrically connected to the upper buffer layer via the plurality of apertures in the element insulating film and the second upper electrode.

3. The detection device according to claim 1, wherein the width of the plurality of openings is smaller than the distance between adjacent openings.

4. The detection device according to claim 1, wherein the width of the plurality of openings is 1 / 2 or less of the distance between adjacent openings.

5. The detection device according to claim 1, wherein the plurality of openings are arranged in a matrix in a plan view.

6. The detection device according to claim 1, wherein the plurality of openings are arranged in a staggered pattern in a plan view.

7. The detection device according to claim 1, comprising: a plurality of scan lines extending in a first direction and arranged in a second direction intersecting the first direction; a plurality of signal lines extending in the second direction and arranged in the first direction; and transistors connected to the scan lines and the signal lines, wherein the photodiode is arranged in a region enclosed by adjacent scan lines and adjacent signal lines and is connected to the signal lines via the transistors.

8. The detection device according to claim 7, wherein the plurality of signal lines are connected to a detection circuit.

9. The detection device according to claim 2, wherein the lower electrode, the active layer, and the second upper electrode are arranged at intervals from each of the plurality of photodiodes, and the first upper electrode is provided continuously across the plurality of photodiodes, covering the second upper electrode and the element insulating film.

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