Semiconductor device and method for producing semiconductor device

Abstract

Provided is a semiconductor device (1) comprising: a semiconductor laminate (20) having an electron transit layer (22) being a first nitride semiconductor layer and an electron supply layer (23) being a second nitride semiconductor layer located above the electron transit layer (22); a gate layer (40) being a p-type third nitride semiconductor layer located above a first region (20a) of the semiconductor laminate (20); a source electrode (70S) and a drain electrode (70D) located above a second region (20b) of the semiconductor laminate (20); and a gate electrode (70G) being a Schottky electrode located above the gate layer (40). The source electrode (70S), the drain electrode (70D), and the gate electrode (70G) include a TiAl alloy layer.

Description

Semiconductor device and method for manufacturing a semiconductor device 【0001】 This disclosure relates to semiconductor devices and methods for manufacturing semiconductor devices, and more particularly to semiconductor devices using Group III nitride semiconductors and methods for manufacturing semiconductor devices. 【0002】 Semiconductor devices using Group III nitride semiconductors such as gallium nitride (GaN) or aluminum gallium nitride (AlGaN) exhibit high dielectric breakdown voltage characteristics due to the wide band gap of the material. Furthermore, heterostructures such as AlGaN and GaN can be easily formed in semiconductor devices using Group III nitride semiconductors. 【0003】 In semiconductor devices having a heterostructure of AlGaN and GaN layers, the difference between the piezoelectric polarization generated from the lattice constant difference between AlGaN and GaN and the spontaneous polarization of AlGaN and GaN causes a high concentration of electrons called two-dimensional electron gas (2DEG) to be generated on the GaN layer side of the interface between the AlGaN and GaN layers, forming a two-dimensional electron gas channel. Semiconductor devices utilizing this two-dimensional electron gas channel have relatively high electron saturation rates, relatively high insulation resistance, and relatively high thermal conductivity, and are therefore applied to high-frequency power devices and the like. For example, semiconductor devices with a two-dimensional electron gas channel are used as switching power devices. Specifically, semiconductor devices with a two-dimensional electron gas channel are used as field-effect transistors (GaN-FETs) using GaN. Examples of this type of semiconductor device include heterojunction field-effect transistors such as high electron mobility transistors (HEMTs). 【0004】 A GaN-FET, for example, comprises an electron transport layer which is a GaN layer, an electron supply layer which is an AlGaN layer provided on the electron transport layer, a gate electrode provided on the electron supply layer, and a source electrode and a drain electrode provided on the electron supply layer in a portion of the electron supply layer different from the portion where the gate electrode is formed. 【0005】In recent years, research and development of semiconductor devices such as GaN-FETs has been rapidly progressing, primarily for use in fast chargers. Fast chargers require miniaturization and lower costs, and consequently, there is a demand for miniaturization and lower costs for the semiconductor devices used in them. 【0006】 Therefore, it is conceivable to form the gate electrode, source electrode, and drain electrode of a semiconductor device simultaneously. This can reduce manufacturing costs (labor costs, material costs, etc.). Furthermore, by forming the gate electrode, source electrode, and drain electrode simultaneously, variations in the formation of the gate electrode, source electrode, and drain electrode can be suppressed, thereby suppressing changes in the inter-electrode distance between the gate electrode and the source electrode or drain electrode. As a result, it becomes possible to shrink the inter-electrode distance and increase integration, making it possible to miniaturize the semiconductor device. 【0007】 However, generally, gate electrodes, source electrodes, and drain electrodes are often formed using different metallic materials because they require different characteristics. Therefore, it is difficult to form the gate electrode, source electrode, and drain electrode simultaneously. Specifically, the source and drain electrodes should ideally be ohmic electrodes with low contact resistance on an n-type semiconductor layer; therefore, metallic materials with a small work function are suitable for the source and drain electrodes. On the other hand, the gate electrode should ideally be a Schottky electrode with good Schottky properties; therefore, metallic materials with a large work function are suitable for the gate electrode. 【0008】 For these reasons, it has been common practice in conventional semiconductor devices to form the gate electrode, source electrode, and drain electrode using different metallic materials. Consequently, it has been impossible to form the gate electrode, source electrode, and drain electrode simultaneously in conventional semiconductor devices, making the process of forming the gate electrode, source electrode, and drain electrode complex. 【0009】Furthermore, in order to reduce the contact resistance of the source and drain electrodes, which are made of a Ti and Al laminate, it is necessary to perform heat treatment after forming the source and drain electrodes. This also made it difficult to form the source and drain electrodes and the gate electrode simultaneously. 【0010】 Therefore, a semiconductor device that is a GaN-FET capable of simultaneously forming the gate electrode, source electrode, and drain electrode has been proposed (Patent Document 1). The semiconductor device disclosed in Patent Document 1 comprises an AlN buffer layer made of AlN, a GaN buffer layer made of GaN, an electron supply layer made of AlGaN provided on the GaN buffer layer, and an InAlGaN layer (n ＋ The device comprises a cap layer, a gate electrode made of Pd formed in the recess of the cap layer, and a source electrode and drain electrode made of non-alloy Pd provided on the cap layer. This configuration allows the source electrode and drain electrode to be made of non-alloy electrodes that have not undergone heat treatment, and enables the use of metal materials with a large work function for the source electrode and drain electrode, so that the gate electrode, source electrode, and drain electrode can be formed from the same metal material. This makes it possible to form the gate electrode, source electrode, and drain electrode simultaneously. 【0011】 Japanese Patent Publication No. 2007-324263 【0012】 However, if an InAlGaN layer with a high dopant carrier density is formed on the electron supply layer, as in the semiconductor device disclosed in Patent Document 1, the dopants of the InAlGaN layer penetrate into the electron supply layer. As a result, the electron supply in the electron supply layer increases, the threshold voltage of the gate electrode decreases, and there is a risk of leakage current occurring between the source electrode and the drain electrode. 【0013】Therefore, one could consider lowering the carrier concentration of the InAlGaN layer formed on the electron supply layer or undoping the InAlGaN layer. However, doing so would increase the contact resistance of the source and drain electrodes. Heat treatment can be used to reduce the contact resistance. 【0014】 However, in semiconductor devices having a structure in which a p-type nitride semiconductor layer is provided between the gate electrode and the electron supply layer, even if the gate electrode, source electrode, and drain electrode can be formed simultaneously, if heat treatment is performed after the gate electrode is formed, current will flow more easily into the p-type nitride semiconductor layer located beneath the gate electrode, causing the gate current to increase. 【0015】 This disclosure has been made in view of the above issues, and aims to provide a semiconductor device and a method for manufacturing a semiconductor device that can suppress gate current even when a p-type nitride semiconductor layer is provided below the gate electrode, and can also achieve miniaturization and cost reduction. 【0016】 To achieve the above objective, one embodiment of a semiconductor device according to the present disclosure includes a semiconductor laminate having a first nitride semiconductor layer and a second nitride semiconductor layer located above the first nitride semiconductor layer, wherein a two-dimensional electron gas channel is formed; a p-type third nitride semiconductor layer located above a first region in the semiconductor laminate; a source electrode and a drain electrode located above a second region in the semiconductor laminate; and a gate electrode located above the third nitride semiconductor layer, which is a Schottky electrode, wherein the source electrode, the drain electrode and the gate electrode include a TiAl alloy layer. 【0017】Furthermore, one embodiment of a method for manufacturing a semiconductor device according to the present disclosure includes the steps of: forming a semiconductor stack having a second nitride semiconductor layer located above a first nitride semiconductor layer; forming a p-type third nitride semiconductor layer above the semiconductor stack; patterning the third nitride semiconductor layer to form a third nitride semiconductor layer of a predetermined shape above a first region in the semiconductor stack; forming a metal layer containing Ti and Al so as to cover the third nitride semiconductor layer; patterning the metal layer to form a source electrode and a drain electrode of a predetermined shape above a second region in the semiconductor stack, and forming a gate electrode of a predetermined shape above the third nitride semiconductor layer; and alloying the source electrode, the drain electrode and the gate electrode by heat treatment. 【0018】 According to this disclosure, even if the structure has a p-type nitride semiconductor layer provided below the gate electrode, the gate current can be suppressed, and miniaturization and cost reduction can be achieved. 【0019】Figure 1 is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 1. Figure 2A is a cross-sectional view showing the process of forming a semiconductor laminate in the semiconductor device manufacturing method according to Embodiment 1. Figure 2B is a cross-sectional view showing the process of forming a recess in the semiconductor laminate in the semiconductor device manufacturing method according to Embodiment 1. Figure 2C is a cross-sectional view showing the process of forming a regrowth layer, a gate layer, and a gate contact layer in the semiconductor device manufacturing method according to Embodiment 1. Figure 2D is a cross-sectional view showing the process of patterning the gate layer and the gate contact layer in the semiconductor device manufacturing method according to Embodiment 1. Figure 2E is a cross-sectional view showing the process of forming an insulating layer in the semiconductor device manufacturing method according to Embodiment 1. Figure 2F is a cross-sectional view showing the process of forming a metal layer in the semiconductor device manufacturing method according to Embodiment 1. Figure 2G is a cross-sectional view showing the process of patterning the metal layer in the semiconductor device manufacturing method according to Embodiment 1. Figure 2H is a cross-sectional view showing the heat treatment process in the semiconductor device manufacturing method according to Embodiment 1. Figure 3 is a cross-sectional view of a semiconductor device of Comparative Example 1. Figure 4 is a cross-sectional view of a semiconductor device of Comparative Example 2. Figure 5 is a diagram showing the relationship between the average carrier concentration of the gate layer and the gate current in the semiconductor device of Embodiment 1 and the semiconductor device of Comparative Example 1. Figure 6 is an enlarged view of the peripheral portion of the gate electrode in the semiconductor device according to Embodiment 1. Figure 7 is a diagram showing the Al content and Ti content at seven measurement points in the first gate electrode region of the gate electrode. Figure 8 is a diagram showing the Al content and Ti content at seven measurement points in the second gate electrode region of the gate electrode. Figure 9 is a cross-sectional view showing the configuration of the semiconductor device according to Embodiment 2. Figure 10A is a cross-sectional view showing the process of forming a buffer layer, electron transport layer, electron supply layer, gate layer and gate contact layer in the method for manufacturing the semiconductor device according to Embodiment 2. Figure 10B is a cross-sectional view showing the process of patterning the gate layer and gate contact layer in the method for manufacturing the semiconductor device according to Embodiment 2. Figure 10C is a cross-sectional view showing the process of forming an insulating layer in the method for manufacturing the semiconductor device according to Embodiment 2. Figure 10D is a cross-sectional view showing the process of forming a metal layer in the method for manufacturing the semiconductor device according to Embodiment 2.Figure 10E is a cross-sectional view showing the process of patterning a metal layer in the semiconductor device manufacturing method according to Embodiment 2. Figure 10F is a cross-sectional view showing the heat treatment process in the semiconductor device manufacturing method according to Embodiment 2. 【0020】 The embodiments of this disclosure will be described below with reference to the drawings. The embodiments described below are all specific examples of this disclosure. Therefore, the numerical values, shapes, materials, components, arrangement positions and connection forms of the components, as well as the steps (processes) and the order of the steps shown in the following embodiments are examples and are not intended to limit this disclosure. Accordingly, among the components in the following embodiments, those components that are not described in the independent claims representing the highest-level concepts of this disclosure will be described as optional components. 【0021】 Please note that each figure is a schematic diagram and not necessarily a strictly accurate representation. Therefore, the scale and other aspects may not necessarily be consistent across all figures. In addition, the same reference numerals are used for substantially identical components in each figure, and redundant explanations are omitted or simplified. 【0022】 Furthermore, in this specification, the terms "up" and "above" and "down" and "below" in the configuration of semiconductor devices do not refer to the upward (vertically upward) and downward (vertically downward) directions in absolute spatial perception, but rather are terms defined by the relative positional relationship based on the stacking order in a stacked structure. Moreover, the terms "up" and "down" apply not only when two components are spaced apart and another component exists between them, but also when two components are placed in close proximity and touching each other. 【0023】 (Embodiment 1) First, the semiconductor device 1 according to Embodiment 1 will be described using Figure 1. Figure 1 is a cross-sectional view showing the configuration of the semiconductor device 1 according to Embodiment 1. 【0024】 The semiconductor device 1 in this embodiment is a heterojunction field-effect transistor. Specifically, the semiconductor device 1 is a high electron-mobility transistor (HEMT) having a Schottky junction gate structure. 【0025】 As shown in Figure 1, the semiconductor device 1 comprises a substrate 10, a semiconductor laminate 20, a regrowth layer 30, a gate layer 40, a gate contact layer 50, an insulating layer 60, a gate electrode 70G, a source electrode 70S, and a drain electrode 70D. 【0026】 The substrate 10 is, for example, a substrate containing silicon (Si). Specifically, the substrate 10 is a silicon substrate. In this embodiment, the substrate 10 is a silicon substrate made of a Si single crystal. 【0027】 The substrate 10 is not limited to a silicon substrate; any substrate that serves as a base for forming a nitride semiconductor layer is acceptable. For example, the substrate 10 may be made of sapphire, SiC, GaN, or AlN. 【0028】 The semiconductor stack 20 is located above the substrate 10. The semiconductor stack 20 has a structure in which multiple semiconductor layers are stacked. In this embodiment, the semiconductor stack 20 comprises a buffer layer 21, an electron transport layer 22, and an electron supply layer 23. 【0029】 The buffer layer 21, electron transport layer 22, electron supply layer 23, regrowth layer 30, gate layer 40, and gate contact layer 50 are composed of semiconductor material. Specifically, the buffer layer 21, electron transport layer 22, electron supply layer 23, regrowth layer 30, gate layer 40, and gate contact layer 50 are nitride semiconductor layers composed of group III nitride semiconductors. Therefore, semiconductor device 1 is a nitride semiconductor device. 【0030】 The buffer layer 21 is a nitride semiconductor layer located on the substrate 10. In this embodiment, the buffer layer 21 is provided directly above the substrate 10. The buffer layer 21 has a structure in which multiple layers of AlN and AlGaN are stacked, for example. As an example, the buffer layer 21 has a structure in which 20 to 100 pairs of AlN and AlGaN are stacked, with each pair being one. The thickness of the buffer layer 21 is, for example, 2 μm. 【0031】Note that the buffer layer 21 may be composed of a single layer or a plurality of layers of group III nitride semiconductors such as GaN, AlGaN, AlN, InGaN, or AlInGaN. For example, the buffer layer 21 may have a structure in which a plurality of Al １－α Ga α N (0 ≤ α < 0.8) layers are stacked. 【0032】 The electron transport layer 22 is a nitride semiconductor layer located above the substrate 10. In the present embodiment, the electron transport layer 22 is a GaN layer composed of undoped (i-type) GaN and is provided immediately above the buffer layer 21. The thickness of the electron transport layer 22 is, for example, 200 nm. 【0033】 Note that the group III nitride semiconductor constituting the electron transport layer 22 is not limited to GaN. The electron transport layer 22 may be composed of a group III nitride semiconductor such as AlGaN, InGaN, or AlInGaN. Further, the electron transport layer 22 is not limited to being undoped, and the electron transport layer 22 may contain an n-type impurity such as Si. 【0034】 The electron supply layer 23 is a nitride semiconductor layer located above the electron transport layer 22. In the present embodiment, the electron supply layer 23 is the uppermost layer of the semiconductor laminate 20. The electron supply layer 23 is, for example, an AlGaN layer composed of undoped (i-type) AlGaN with an Al composition ratio of 25% and is provided immediately above the electron transport layer 22. The electron supply layer 23 has a larger bandgap than the electron transport layer 22. The thickness of the electron supply layer 23 is, for example, 20 nm. 【0035】On the side of the electron transport layer 22 at the heterointerface between the electron supply layer 23 and the electron transport layer 22, a high-concentration two-dimensional electron gas is generated, and a two-dimensional electron gas channel 20C is formed. That is, the electron transport layer 22 is a channel layer in which the two-dimensional electron gas channel 20C is formed. Specifically, the two-dimensional electron gas channel 20C is formed in a portion of the electron transport layer 22 on the side of the electron supply layer 23. Note that the electron transport layer 22 located under the electron supply layer 23 is a barrier layer. Thus, a two-dimensional electron gas channel 20C is formed in the semiconductor laminate 20. Therefore, the semiconductor device 1 is a GaN-FET having the two-dimensional electron gas channel 20C. 【0036】 Note that the composition ratio of Al in the electron supply layer 23 made of AlGaN is not limited to 25%. The composition ratio of Al in the electron supply layer 23 may be 10% to 100%. Further, the group III nitride semiconductor constituting the electron supply layer 23 is not limited to AlGaN. For example, the electron supply layer 23 may be constituted by a group III nitride semiconductor such as AlN, InGaN, AlInGaN, or the like. Further, the electron supply layer 23 is not limited to an undoped layer in which no impurities are doped, and may be an n-type impurity-doped layer doped with n-type impurities such as Si. 【0037】 Further, the electron supply layer 23 does not have to be provided directly above the electron transport layer 22. For example, a spacer layer may be provided between the electron transport layer 22 and the electron supply layer 23. As the spacer layer, for example, an AlN layer having a thickness of about 1 nm made of AlN can be used. 【0038】 A recess 20R is formed in the semiconductor laminate 20. The recess 20R is a recess formed in the electron supply layer 23. Specifically, the recess 20R is a through recess penetrating the electron supply layer 23 and reaching the electron transport layer 22. In the present embodiment, the recess 20R reaches inside the electron transport layer 22, and a recess is provided in the electron transport layer 22. The recess 20R is formed so as to penetrate the electron supply layer 23 and remove a part of the surface of the electron transport layer 22. As an example, the depth of the recess 20R is 80 nm, but it is not limited thereto. 【0039】The recess 20R is formed in the first region 20a of the semiconductor laminate 20. The first region 20a is the gate region corresponding to the gate electrode 70G. Therefore, the recess 20R is a gate recess formed at the position corresponding to the gate electrode 70G. 【0040】 The regrowth layer 30 is a nitride semiconductor layer located above the semiconductor stack 20. The regrowth layer 30 is located above the electron supply layer 23. Specifically, the regrowth layer 30 is provided directly above the electron supply layer 23. 【0041】 In this embodiment, since the electron supply layer 23 is provided with a recess 20R, the regrowth layer 30 is provided on the electron supply layer 23 so as to cover the recess 20R. The regrowth layer 30 is provided along the inner surface of the recess 20R without filling the recess 20R. 【0042】 The regrowth layer 30 is a layer grown by regrowing the same semiconductor material as the electron supply layer 23. Therefore, the regrowth layer 30 is composed of the same semiconductor material as the electron supply layer 23. In this embodiment, the regrowth layer 30 is an AlGaN layer composed of undoped (i-type) AlGaN with an Al composition ratio of 25%, similar to the electron supply layer 23. The thickness of the regrowth layer 30 is thinner than the thickness of the electron supply layer 23, but is not limited to this. As an example, the thickness of the regrowth layer 30 made of undoped AlGaN is 20 nm. 【0043】 Furthermore, the Al composition ratio of the regrowth layer 30 made of AlGaN is not limited to 25%. The Al composition ratio of the regrowth layer 30 may be 20% to 100%. Also, the group III nitride semiconductor constituting the regrowth layer 30 is not limited to AlGaN. For example, the regrowth layer 30 may be composed of a group III nitride semiconductor such as AlN, InGaN, or AlInGaN. Moreover, the regrowth layer 30 is not limited to an undoped layer without impurities, but may also be an n-type impurity-doped layer doped with n-type impurities such as Si. 【0044】The gate layer 40 is a nitride semiconductor layer located above the first region 20a (gate region) in the semiconductor stack 20. Therefore, the gate layer 40 is positioned below the gate electrode 70G. Specifically, the gate layer 40 is positioned between the gate electrode 70G and the electron supply layer 23. 【0045】 In this embodiment, a recess 20R is formed in the first region 20a of the semiconductor laminate 20, so the gate layer 40 is provided above the recess 20R. At least a portion of the gate layer 40 is embedded in the recess 20R. 【0046】 Furthermore, in this embodiment, since the regrowth layer 30 is provided along the inner surface of the recess 20R, the gate layer 40 is located above the regrowth layer 30. Specifically, the gate layer 40 is provided directly above the regrowth layer 30. 【0047】 The gate layer 40 is not provided across the entire surface of the regrowth layer 30, but rather in a predetermined shape on a portion of the regrowth layer 30. In other words, the gate layer 40 is partially provided on the semiconductor laminate 20. Specifically, the gate layer 40 is formed in an island shape and is provided only in the peripheral portion of the recess 20R of the semiconductor laminate 20. 【0048】 The gate layer 40 is a p-type nitride semiconductor layer containing p-type impurities. In other words, the gate layer 40 is positioned below the gate electrode 70G as a p-type nitride semiconductor layer. As a result, the gate layer 40, being a p-type nitride semiconductor layer, depletes the two-dimensional electron gas (2DEG) generated in the semiconductor stack 20, making the semiconductor device 1 a normally-off transistor. 【0049】 As an example, the gate layer 40 is a p-type GaN layer containing magnesium (Mg) as a p-type impurity dopant. The average carrier concentration of the p-type impurity in the gate layer 40 is 2.1 × 10⁻⁶. １７ cm －３ The above is preferable. Note that the gate layer 40 is not limited to a p-type GaN layer, but may also be a p-type AlGaN layer. The thickness of the gate layer 40 is, for example, 180 nm. 【0050】 The gate contact layer 50 is a nitride semiconductor layer located above the gate layer 40. Furthermore, the gate contact layer 50 is positioned below the gate electrode 70G. Therefore, the gate contact layer 50 is located between the gate layer 40 and the gate electrode 70G. 【0051】 The gate contact layer 50 is patterned simultaneously with the gate layer 40 to form a predetermined shape. Therefore, the side surface of the gate contact layer 50 and the side surface of the gate layer 40 are flush. 【0052】 The gate contact layer 50 is a GaN layer composed of undoped (i-type) GaN and is located directly above the gate layer 40. The thickness of the gate contact layer 50 is thinner than the thickness of the gate layer 40. For example, the thickness of the gate contact layer 50 is 2 nm. 【0053】 Furthermore, the Group III nitride semiconductor constituting the gate contact layer 50 is not limited to GaN. The gate contact layer 50 may be composed of undoped AlGaN. Alternatively, the gate contact layer 50 may have a structure in which GaN and AlGaN are stacked. Moreover, the gate contact layer 50 is not limited to an undoped layer that is not doped with impurities, but may also be a p-type impurity-doped layer doped with p-type impurities such as Mg. 【0054】 The insulating layer 60 is located above the semiconductor laminate 20. Specifically, the insulating layer 60 is located above the electron supply layer 23 in the semiconductor laminate 20. In this embodiment, since the regrowth layer 30 is provided on top of the electron supply layer 23, the insulating layer 60 is provided directly above the regrowth layer 30. 【0055】The insulating layer 60 is not provided above the first region 20a and the second region 20b of the semiconductor laminate 20. Therefore, the insulating layer 60 has a first opening 60a above the first region 20a and a second opening 60b above the second region 20b. The first region 20a is the gate region corresponding to the gate electrode 70G, and the second region 20b is the source-drain region corresponding to the source electrode 70S and the drain electrode 70D. The first opening 60a of the insulating layer 60 is a gate contact opening for connecting the gate electrode 70G and the semiconductor laminate 20, and the second opening 60b of the insulating layer 60 is a source-drain opening for connecting the source electrode 70S and the drain electrode 70D and the semiconductor laminate 20. 【0056】 The insulating layer 60 is formed above the recess 20R of the semiconductor laminate 20, and covers the gate layer 40 which is formed in a predetermined shape, except for the area above the first region 20a in the semiconductor laminate 20. Specifically, the insulating layer 60 is formed across the upper surface of the regrowth layer 30, the side surface of the gate layer 40, and the area above the gate layer 40. In other words, a portion of the insulating layer 60 having the first opening 60a is located above the gate layer 40. 【0057】 In this embodiment, since a gate contact layer 50 of a predetermined shape is formed on the gate layer 40, the insulating layer 60 is formed across the side surface and the upper surface of the gate contact layer 50. The insulating layer 60 is formed to cover the upper ends of the gate layer 40 and the gate contact layer 50, except for the area above the first region 20a. 【0058】 The insulating layer 60 is made of SiN and SiO ２ , SiON, AlN, Al ２ O ３ It is composed of at least one of SiC or C (diamond). The thickness of the insulating layer 60 is preferably 2 nm or more and 30 nm or less. In this embodiment, the insulating layer 60 is a SiN layer composed of SiN with a thickness of 140 nm. 【0059】The gate electrode 70G is located above the first region 20a (gate region) in the semiconductor stack 20. In this embodiment, a recess 20R is formed in the semiconductor stack 20, and the gate electrode 70G is located above the recess 20R. 【0060】 The gate electrode 70G is a Schottky electrode located above the gate layer 40, which is a p-type nitride semiconductor layer provided in a first region 20a of the semiconductor laminate 20. In this embodiment, since the gate contact layer 50 is provided on top of the gate layer 40, the gate electrode 70G is located above the gate contact layer 50. Specifically, the gate layer 40 is provided directly above the gate contact layer 50. The gate electrode 70G is provided at the first opening 60a of the insulating layer 60. Therefore, the gate electrode 70G is in contact with the gate contact layer 50 via the first opening 60a of the insulating layer 60. 【0061】 The source electrode 70S and the drain electrode 70D are located above the second region 20b (source-drain region) in the semiconductor laminate 20. The source electrode 70S and the drain electrode 70D are arranged to face each other with the gate electrode 70G in between. In this embodiment, the gate electrode 70G is located closer to the source electrode 70S. That is, the distance between the gate electrode 70G and the source electrode 70S (gate-source distance) is smaller than the distance between the gate electrode 70G and the drain electrode 70D (gate-drain distance). The gate electrode 70G may also be located closer to the drain electrode 70D, or it may be located at the midpoint between the source electrode 70S and the drain electrode 70D. 【0062】The source electrode 70S and the drain electrode 70D are each located above the electron supply layer 23. In this embodiment, since the regrowth layer 30 is provided above the electron supply layer 23, both the source electrode 70S and the drain electrode 70D are located above the regrowth layer 30. Specifically, the source electrode 70S and the drain electrode 70D are provided directly above the regrowth layer 30. The source electrode 70S and the drain electrode 70D are provided at the second opening 60b of the insulating layer 60. Therefore, the source electrode 70S and the drain electrode 70D are in contact with the regrowth layer 30 via the second opening 60b of the insulating layer 60. 【0063】 The source electrode 70S, drain electrode 70D, and gate electrode 70G are made of the same material. In this embodiment, the source electrode 70S, drain electrode 70D, and gate electrode 70G all include a TiAl alloy layer. Specifically, the source electrode 70S, drain electrode 70D, and gate electrode 70G are made solely of a TiAl alloy layer. 【0064】 The film thickness of the source electrode 70S, the drain electrode 70D, and the gate electrode 70G are all the same. For example, the film thickness of the source electrode 70S, the drain electrode 70D, and the gate electrode 70G is 240 nm, but is not limited to this. Also, for example, the width of the gate electrode 70G is 1.6 μm, and the widths of the drain electrode 70D and the gate electrode 70G are 5.1 μm. Furthermore, for example, the distance between the gate electrode 70G and the source electrode 70S (gate-source distance) is 0.85 μm, and for example, the distance between the gate electrode 70G and the drain electrode 70D (gate-drain distance) is 10 μm. 【0065】Next, the method for manufacturing the semiconductor device 1 in this embodiment will be described using Figures 2A to 2H. Figures 2A to 2H are cross-sectional views showing each step in the method for manufacturing the semiconductor device 1 according to Embodiment 1. Figure 2A shows the step of forming the semiconductor laminate 20. Figure 2B shows the step of forming a recess 20R in the semiconductor laminate 20. Figure 2C shows the step of forming the regrowth layer 30, the gate layer 40, and the gate contact layer 50. Figure 2D shows the step of patterning the gate layer 40 and the gate contact layer 50. Figure 2E shows the step of forming the insulating layer 60. Figure 2F shows the step of forming the metal layer 70m. Figure 2G shows the step of patterning the metal layer 70m. Figure 2H shows the heat treatment step. 【0066】 First, as shown in Figure 2A, a semiconductor laminate 20 consisting of a buffer layer 21, an electron transport layer 22, and an electron supply layer 23 is formed on the substrate 10 using metal-organic chemical vapor deposition (MOCVD) (semiconductor laminate formation process). 【0067】 In this embodiment, a semiconductor laminate 20 is formed by sequentially epitaxially growing a buffer layer 21 with a layer thickness of 2 μm and consisting of a stacked structure of AlN and AlGaN, an electron transport layer 22 with a layer thickness of 200 nm and consisting of GaN, and an electron supply layer 23 with a layer thickness of 20 nm and consisting of AlGaN with an Al composition ratio of 25% on a silicon substrate 10. In the semiconductor laminate 20 formed in this way, a high concentration of two-dimensional electron gas is generated in the portion of the electron supply layer 23 on the electron transport layer 22 side at the heterointerface between the electron transport layer 22 and the electron supply layer 23, and a two-dimensional electron gas channel 20C is formed. 【0068】 Next, as shown in Figure 2B, a portion of the semiconductor stack 20 is removed to form a recess 20R in the semiconductor stack 20 (recess formation step). Specifically, a recess 20R is formed in the electron supply layer 23 of the semiconductor stack 20. 【0069】In this case, for example, a resist is applied to the semiconductor laminate 20, and then the resist is patterned by lithography to form a resist mask, leaving the resist in areas other than those where the recess 20R is to be formed. In other words, a resist mask is formed that has openings in the areas corresponding to the recess 20R. Subsequently, dry etching is performed using the resist mask with openings as a mask to etch the semiconductor laminate 20 exposed at the openings in the resist mask, thereby forming a recess 20R in the semiconductor laminate 20. Specifically, a recess 20R is formed that penetrates the electron supply layer 23 and reaches the electron transport layer 22. After that, the resist mask and the polymer generated by dry etching are removed. 【0070】 In this embodiment, the recess 20R was formed by dry etching, but this is not limited to that. Specifically, the recess 20R may be formed by wet etching. 【0071】 Next, at least a gate layer 40 is formed on top of the semiconductor stack 20 (gate layer formation step). As shown in Figure 2C, in this embodiment, not only the gate layer 40 but also the regrowth layer 30 and the gate contact layer 50 are formed. Specifically, the regrowth layer 30, the gate layer 40, and the gate contact layer 50 are sequentially formed on top of the semiconductor stack 20 by MOCVD. 【0072】 In this case, for example, a regrowth layer 30 is epitaxially grown over the entire surface of the inner surface of the recess 20R formed in the semiconductor laminate 20 and the upper surface of the electron supply layer 23, then a gate layer 40 is epitaxially grown over the entire surface of the electron supply layer 23, and then a gate contact layer 50 is epitaxially grown over the entire surface of the gate layer 40. 【0073】The material of the regrowth layer 30 is the same as that of the electron supply layer 23. In this embodiment, a 20 nm thick AlGaN layer made of undoped AlGaN with an Al composition ratio of 25% was formed as the regrowth layer 30. The regrowth layer 30 is made of a semiconductor material that does not make ohmic contact with the source electrode 70S and the drain electrode 70D unless heat is treated. Furthermore, a 180 nm thick GaN layer made of GaN doped with magnesium as a p-type impurity was formed as the gate layer 40, and a 2 nm thick GaN layer made of undoped GaN was formed as the gate contact layer 50. 【0074】 Next, the gate layer 40 is patterned to form a gate layer 40 of a predetermined shape above the first region 20a in the semiconductor stack 20 (gate layer patterning step). As shown in Figure 2D, in this embodiment, the gate layer 40 and the gate contact layer 50 are patterned simultaneously to form the gate layer 40 and the gate contact layer 50 in an island shape. 【0075】 In this case, for example, a resist mask is formed by coating the gate contact layer 50 with resist and then patterning the resist using lithography, leaving resist in the areas where the gate layer 40 and gate contact layer 50 remain. Subsequently, the gate layer 40 and gate contact layer 50 are etched away using the resist mask as a mask until the regrowth layer 30 is exposed, thereby forming the gate layer 40 and gate contact layer 50 in an island-like manner. At this time, as shown in Figure 2D, the surface layer of the exposed regrowth layer 30 may also be removed by dry etching. After that, the resist mask and the polymer generated by dry etching are removed. 【0076】 In this embodiment, the gate layer 40 and the gate contact layer 50 were patterned into a predetermined shape by dry etching, but this is not limited to this method. Specifically, the gate layer 40 and the gate contact layer 50 may be patterned into a predetermined shape by wet etching. 【0077】Next, as shown in FIG. 2E, an insulating layer 60 having a predetermined shape is formed (insulating layer formation step). Specifically, as the insulating layer 60 having a predetermined shape, an insulating layer 60 having a first opening 60a located above the first region 20a of the semiconductor laminate 20 and a second opening 60b located above the second region 20b of the semiconductor laminate 20 is formed. In the present embodiment, a SiN layer was formed as the insulating layer 60 by MOCVD. 【0078】 In this case, after forming an insulating film on the semiconductor laminate 20 so as to cover at least the gate layer 40 formed in a predetermined shape, a part of the insulating film is removed by dry etching using a fluorine-based gas to form an opening in the insulating film. Thereby, an insulating layer 60 having a predetermined shape can be formed. 【0079】 In the present embodiment, first, as raw material gases, SiH ４ and NH ３ are used to form an insulating film made of a SiN film on the entire exposed regrowth layer 30 so as to cover the gate layer 40 and the gate contact layer 50 formed in a predetermined shape. Thereafter, after applying a resist on the insulating film, the resist is patterned by a lithography method to form a resist mask leaving the resist at locations excluding the first region 20a and the second region 20b. That is, a resist mask having openings at portions corresponding to the first region 20a and the second region 20b is formed. Thereafter, dry etching using a fluorine-based gas is performed with the resist mask having the openings as a mask until the underlying layer of the insulating film is exposed, thereby etching the insulating film exposed at the openings of the resist mask. Thereby, an insulating layer 60 having the first opening 60a and the second opening 60b can be formed. Also, at a portion corresponding to the first opening 60a, the gate contact layer 50 which is the underlying layer of the insulating film is exposed, and at a portion corresponding to the second opening 60b, the regrowth layer 30 which is the underlying layer of the insulating film is exposed. Thereafter, the resist mask and the polymer generated by dry etching are removed. The removal of this polymer may be performed by oxygen ashing (O ２ ashing). Also, the oxygen ashing may be performed separately after removing the polymer. 【0080】In this embodiment, the insulating layer 60 of a predetermined shape is formed by dry etching, but this is not limited to this. Specifically, the insulating layer 60 of a predetermined shape may be formed by wet etching. However, dry etching makes it easier to obtain Schottky contact of the gate electrode 70G. In particular, by forming the first opening 60a and the second opening 60b by dry etching using a fluorine-based gas, a Schottky junction layer can be easily formed on the first region 20a (gate region), and the gate current can be suppressed. Also, when forming the first opening 60a and the second opening 60b, the regrowth layer 30 and the electron supply layer 23 may be penetrated. 【0081】 Next, as shown in Figure 2F, a metal layer 70m is formed to cover at least the gate layer 40 which has been formed into a predetermined shape (metal layer formation step). In this embodiment, the metal layer 70m is formed to cover the gate layer 40 and the gate contact layer 50 which have been formed into a predetermined shape. Specifically, the metal layer 70m is formed over the entire upper surface of the semiconductor laminate 20 so as to cover the exposed gate contact layer 50, the exposed regrowth layer 30, and the insulating layer 60. Therefore, the first opening 60a and the second opening 60b of the insulating layer 60 are covered with the metal layer 70m. The metal layer 70m can be formed by sputtering or vapor deposition. 【0082】 The metal layer 70m contains Ti and Al. For example, the metal layer 70m is a laminate of a Ti film composed of Ti and an Al film composed of Al. In this embodiment, the metal layer 70m is a laminate with a three-layer structure of Ti film, Al film and Ti film. In this case, for example, a Ti film with a thickness of 20 nm, an Al film with a thickness of 200 nm, and a Ti film with a thickness of 20 nm were sequentially deposited by sputtering or vapor deposition to form a Ti (20 nm) / Al (200 nm) / Ti (20 nm) laminate. 【0083】 Furthermore, the material, layer structure, and film thickness of the metal layer 70m are not particularly limited, as long as it becomes the desired TiAl alloy layer after heat treatment. Also, the metal layer 70m is not limited to a laminated film of multiple metal films, but may be a single layer, as long as it becomes the desired TiAl alloy layer after heat treatment. 【0084】 Next, as shown in Figure 2G, the metal layer 70m is patterned to form a source electrode 70S and a drain electrode 70D of a predetermined shape on the second region 20b of the semiconductor laminate 20, and a gate electrode 70G of a predetermined shape is formed above the gate layer 40 (metal layer patterning step). 【0085】 For example, a resist is applied to a metal layer 70m, and then the resist is patterned by lithography to form a resist mask, leaving the resist in the first region 20a and the second region 20b of the semiconductor laminate 20. Subsequently, the metal layer 70m is etched by dry etching using the resist mask as a mask. As a result, the metal layer 70m remains in the first opening 60a and the second opening 60b, allowing the formation of a predetermined shape source electrode 70S and drain electrode 70D on the second region 20b, and a predetermined shape gate electrode 70G on the first region 20a (i.e., above the gate layer 40). After that, the resist mask and the polymer generated by dry etching are removed. 【0086】 In this way, the source electrode 70S, drain electrode 70D, and gate electrode 70G can be formed in the same process. Note that the patterning of the metal layer 70m may be performed by methods other than lithography and dry etching, such as the lift-off method. 【0087】 Next, as shown in Figure 2H, a heat treatment is performed at a predetermined temperature (heat treatment step). By performing the heat treatment, the source electrode 70S, drain electrode 70D, and gate electrode 70G can be alloyed. In other words, the source electrode 70S, drain electrode 70D, and gate electrode 70G will contain a TiAl alloy layer. Furthermore, by performing the heat treatment, ohmic contact between the source electrode 70S and the drain electrode 70D can be obtained. Therefore, the temperature during the heat treatment (heat treatment temperature) should be 450°C or higher. If the heat treatment temperature is 450°C or higher, the source electrode 70S, drain electrode 70D, and gate electrode 70G can be easily alloyed, and ohmic contact between the source electrode 70S and the drain electrode 70D can be obtained. 【0088】 In this embodiment, the heat treatment was performed by rapid thermal annealing (RTA) in a nitrogen gas atmosphere at a heat treatment temperature of 525°C for a heat treatment time of 60 seconds. The heat treatment conditions (heat treatment method, heat treatment temperature, heat treatment time, etc.) can be appropriately selected within a range where the leakage current does not increase due to Al diffusion into the insulating layer 60, as long as alloying and ohmic contact can be ensured. 【0089】 Thus, by going through the series of steps shown in Figures 2A to 2H, a semiconductor device 1 with the structure shown in Figure 1 can be obtained. 【0090】 Here, the features of the semiconductor device 1 according to this embodiment will be explained, including the process by which one aspect of this disclosure was obtained, while comparing it with the semiconductor devices 1X and 1Y of the comparative examples. Figure 3 is a cross-sectional view of the semiconductor device 1X of comparative example 1, and Figure 4 is a cross-sectional view of the semiconductor device 1Y of comparative example 2 disclosed in Patent Document 1. 【0091】 As shown in Figure 3, the semiconductor device 1X of Comparative Example 1 comprises a substrate 10, a semiconductor laminate 20 having a buffer layer 21, an electron transport layer 22, and an electron supply layer 23, a regrowth layer 30, a gate layer 40, a gate contact layer 50, an insulating layer 60, a gate electrode 100G, a source electrode 100S, and a drain electrode 100D. 【0092】 As shown in Figure 4, the semiconductor device 1Y of Comparative Example 2 comprises a substrate 201, an Al buffer layer 202, a GaN buffer layer 203, a spacer layer 204 made of AlN, an electron supply layer 205 made of AlGaN, and an InAlGaN layer (n ＋ The device comprises a cap layer 206, a gate electrode 200G provided in a recess of the cap layer 206, and a source electrode 200S and a drain electrode 200D made of non-alloy Pd provided on the cap layer 206. 【0093】In the semiconductor device 1X of Comparative Example 1 shown in Figure 3, the gate electrode 100G, source electrode 100S, and drain electrode 100D are formed using different metallic materials. For example, the gate electrode 100G is a metallic layer (non-alloy layer) made of nickel (Ni), and the source electrode 100S and drain electrode 100D are metallic layers (non-alloy layers) consisting of a laminate of Ti film and Al film. Alternatively, the gate electrode 100G is a metallic layer (non-alloy layer) consisting of a three-layer laminate of Ti film, Al film, and Ti film, and the source electrode 100S and drain electrode 100D are TiAl alloy layers. The source electrode 100S and drain electrode 100D can be formed by heat-treating a three-layer laminate of Ti film, Al film, and Ti film to alloy it. 【0094】 Thus, in the semiconductor device 1X of Comparative Example 1, the gate electrode 100G, the source electrode 100S, and the drain electrode 100D are made of different metallic materials, so it is not possible to form the gate electrode 100G, the source electrode 100S, and the drain electrode 100D simultaneously. 【0095】 Therefore, the process of forming the gate electrode 100G, source electrode 100S, and drain electrode 100D becomes complex, increasing manufacturing costs (labor costs, material costs, etc.). Furthermore, when the source electrode 100S and drain electrode 100D are composed of a laminate of Ti film and Al film, a heat treatment called alloy treatment is required after forming the source electrode 100S and drain electrode 100D in order to reduce contact resistance. This also made it difficult to form the source electrode 100S, drain electrode 100D, and gate electrode 100G simultaneously. 【0096】 Furthermore, if the gate electrode 100G, source electrode 100S, and drain electrode 100D are formed in separate processes, variations will occur in the patterns of the gate electrode, source electrode, and drain electrode, causing changes in the inter-electrode distance between the gate electrode and the source electrode or drain electrode. As a result, variations will occur in the characteristics of the semiconductor device. 【0097】In contrast, in the semiconductor device 1Y of Comparative Example 2, the source electrode 200S and drain electrode 200D can be made of non-alloy electrodes that have not undergone heat treatment, and a metal material with a large work function can be used for the source electrode 200S and drain electrode 200D. As a result, the gate electrode 200G, the source electrode 200S, and the drain electrode 200D can be formed from the same metal material. This makes it possible to form the gate electrode 200G, the source electrode 200S, and the drain electrode 200D simultaneously in the semiconductor device 1Y of Comparative Example 2. 【0098】 However, in the semiconductor device 1Y of Comparative Example 2, in order to make the source electrode 200S and drain electrode 200D ohmic electrodes without heat treatment (i.e., non-annealing), an InAlGaN layer (n) is used as a cap layer 206 on top of the electron supply layer 205. ＋ A layer needs to be provided. In other words, the carrier density of the dopant (Si, etc.) is high (for example, 1 × 10⁻¹⁶). １９ cm －３ ) InAlGaN layer (n ＋ A cap layer 206, which is a layer, needs to be provided on top of the electron supply layer 205. 【0099】 Therefore, if the structure of semiconductor device 1Y of Comparative Example 2 is applied to semiconductor device 1X of Comparative Example 1, and an InAlGaN layer with a high carrier density of dopant is formed on the electron supply layer 23 by epitaxial growth, the dopant of the InAlGaN layer will penetrate into the electron supply layer 23. As a result, the electron supply in the electron supply layer 23 will increase, the threshold of the gate electrode 100G will decrease, and there is a risk that a leakage current will be generated between the source electrode 100S and the drain electrode 100D. 【0100】Therefore, in order to suppress the generation of leakage current, it is conceivable to lower the carrier concentration of the InAlGaN layer or to undope the InAlGaN layer, but doing so would increase the contact resistance of the source electrode 100S and the drain electrode 100D. In this case, heat treatment could be considered to lower the contact resistance, but in the semiconductor device 1X of Comparative Example 1, a gate layer 40, which is a p-type nitride semiconductor layer, is provided between the gate electrode 100G and the electron supply layer 23. Therefore, if heat treatment is performed after the formation of the gate electrode 100G, current will flow more easily into the gate layer 40 (p-type nitride semiconductor layer) below the gate electrode 100G, and the gate current will increase. 【0101】 In response to these challenges, the inventors of the present invention have conducted diligent studies and have found a semiconductor device that can suppress gate current even if it has a structure in which the gate electrode, source electrode, and drain electrode can be formed simultaneously, and in which a p-type nitride semiconductor layer is provided beneath the gate electrode. 【0102】 Specifically, the semiconductor device 1 according to this embodiment includes a semiconductor laminate 20 having an electron transport layer 22 which is a first nitride semiconductor layer and an electron supply layer 23 which is a second nitride semiconductor layer located above the electron transport layer 22; a gate layer 40 which is a p-type third nitride semiconductor layer located above a first region 20a in the semiconductor laminate 20; a source electrode 70S and a drain electrode 70D located above a second region 20b in the semiconductor laminate 20; and a gate electrode 70G which is a Schottky electrode located above the gate layer 40 which is a third nitride semiconductor layer. The source electrode 70S, the drain electrode 70D, and the gate electrode 70G include a TiAl alloy layer. 【0103】This configuration allows the gate electrode 70G to be a Schottky electrode even after heat treatment is performed after its formation, thereby suppressing the gate current. Furthermore, since the source electrode 70S, drain electrode 70D, and gate electrode 70G are made of the same material, they can be formed in the same process. This reduces manufacturing costs (labor costs, material costs, etc.) and enables the semiconductor device 1 to be manufactured at a lower cost. Additionally, by forming the gate electrode 70G, source electrode 70S, and drain electrode 70D simultaneously, variations in the formation of the gate electrode 70G, source electrode 70S, and drain electrode 70D can be suppressed. In other words, variations in the position of each electrode of the gate electrode 70G, source electrode 70S, and drain electrode 70D are eliminated. As a result, in multiple semiconductor devices 1, changes in the inter-electrode distance between the gate electrode 70G and the source electrode 70S or drain electrode 70D can be suppressed (i.e., the inter-electrode distance can be kept constant), which enables shrinking and high integration of the inter-electrode distance, and thus allows for miniaturization of the semiconductor device 1. 【0104】 As described above, the semiconductor device 1 according to this embodiment has a structure in which a gate layer 40, which is a p-type nitride semiconductor layer, is provided below the gate electrode 70G. This structure allows for suppression of the gate current, as well as miniaturization and cost reduction. Moreover, the amount of gate current can be adjusted by adjusting the carrier concentration of the gate layer 40, which is a p-type nitride semiconductor layer. 【0105】Here, the relationship between the average carrier concentration C of the gate layer 40 and the gate current Ig will be explained using Figure 5. Figure 5 is a diagram showing the relationship between the average carrier concentration C of the gate layer 40 and the gate current Ig in the semiconductor device 1 in Embodiment 1 and the semiconductor device 1X of Comparative Example 1 shown in Figure 3. In Figure 5, the gate layer 40 is a p-type GaN layer containing Mg as a dopant. The gate current Ig is the value when a voltage of 6V is applied to the gate electrode 70G of the semiconductor device 1 and the gate electrode 100G of the semiconductor device 1X. In Figure 5, the characteristics indicated by black circles as "Embodiment 1" represent the characteristics of the semiconductor device 1 in Embodiment 1, and the characteristics indicated by black triangles as "Comparative Example 1" represent the characteristics of the semiconductor device 1X of Comparative Example 1. 【0106】 If the gate current Ig per unit gate length is less than 1 μA / mm, the gate electrode can be said to be in Schottky contact. In the semiconductor device 1 according to this embodiment, the average carrier concentration of the gate layer 40, which is a third nitride semiconductor layer, is 2.1 × 10⁻⁶. １７ cm －３ That concludes the explanation. Therefore, as shown in Figure 5, in the semiconductor device 1 according to this embodiment, the gate electrode 70G is in Schottky contact. In other words, the gate electrode 70G functions as a Schottky electrode. 【0107】 Furthermore, as shown in Figure 6, the gate electrode 70G has a first gate electrode region 71 and a second gate electrode region 72. Figure 6 is an enlarged view of the peripheral portion of the gate electrode 70G in the semiconductor device 1 shown in Figure 1. 【0108】 As shown in Figure 6, the first gate electrode region 71 is the portion of the gate electrode 70G located above the insulating layer 60. In other words, the first gate electrode region 71 is located above the portion of the insulating layer 60 that is located above the gate layer 40. 【0109】Furthermore, the second gate electrode region 72 is the portion of the gate electrode 70G that contacts the semiconductor laminate 20 through the first opening 60a of the insulating layer 60. The second gate electrode region 72 is located above the gate layer 40 at the first opening 60a of the insulating layer 60. In this embodiment, since the uppermost layer of the semiconductor laminate 20 in the recess 20R is the gate contact layer 50, the second gate electrode region 72 is in contact with the upper surface of the gate contact layer 50. 【0110】 Furthermore, in the gate electrode 70G, the uniformity of the average Ti content in the second gate electrode region 72 is worse than the uniformity of the average Ti content in the first gate electrode region 71. In other words, the variation in the average Ti content in the second gate electrode region 72 is greater than the variation in the average Ti content in the first gate electrode region 71. Specifically, the uniformity of the average Ti content in the first gate electrode region 71 is almost constant and good, while the uniformity of the average Ti content in the second gate electrode region 72 is poor. 【0111】 Here, we will explain the results of a compositional analysis performed on the gate electrode 70G, which is composed of a TiAl alloy layer. In this analysis, the Ti content (Ti composition) and Al content (Al composition) were measured quantitatively for each of the first gate electrode region 71 and the second gate electrode region 72 of the gate electrode 70G. As shown in Figure 6, the measurement points for the first gate electrode region 71 and the second gate electrode region 72 are seven points in the thickness direction (depth direction) of the gate electrode 70G. Specifically, the measurement points 20 nm inside from the upper and lower surfaces of the gate electrode 70G were designated as points 1 and 7, respectively, and points 2 to 6 were evenly divided (point interval approximately 32 nm). The interval between point 6 and point 7 was set to 40 nm. Points 1 and 7 are the positions of the interface between the Ti film and the Al film, and the interface between the Al film and the Ti film, respectively, in the laminated structure of the three-layer structure of the Ti film and Al film and Ti film that constitutes the gate electrode 70G before heat treatment. 【0112】Then, in each of the first gate electrode region 71 and the second gate electrode region 72, the Ti content (wt%) and Al content (wt%) at each of the seven points 1 to 7 were measured by EDX analysis. The measurement results are shown in Figures 7 and 8. Figure 7 shows the Al content and Ti content at seven measurement points in the first gate electrode region 71 (gate electrode 70G on the insulating layer 60) of the gate electrode 70G. Figure 8 shows the Al content and Ti content at seven measurement points in the second gate electrode region 72 (gate electrode 70G on the semiconductor laminate 20, which is the epitaxial layer) of the gate electrode 70G. 【0113】 As shown in Figure 7, in the first gate electrode region 71, the variation in the average content of Al and Ti in the thickness direction of the gate electrode 70G is small, and the uniformity of the average content of Al and Ti is good. Specifically, in the first gate electrode region 71, the average content of Al and Ti in the thickness direction of the gate electrode 70G is almost constant. 【0114】 Specifically, as shown in Figure 7, the average Al content at the seven measurement points in the first gate electrode region 71 is 71.0%, and the standard deviation (σ) is 2.0%. Furthermore, if R is the maximum-minimum difference between the maximum value (MAX) and the minimum value (MIN), and the uniformity U is defined as U = (MAX - MIN) / 2 * AVE, then R = 6.9% and U = 0.049. 【0115】 Similarly, for the Ti content at the seven measurement points in the first gate electrode region 71, the average (AVE) was 29.0%, and the standard deviation (σ) was 2.0%. The maximum-minimum difference R and uniformity U were R = 6.9% and U = 0.116. 【0116】 Furthermore, as shown in Figure 8, in the second gate electrode region 72, the average content of Al and Ti varies greatly in the thickness direction of the gate electrode 70G, indicating poor uniformity of the average content of Al and Ti. Specifically, in the second gate electrode region 72, the average content of Al is higher in the central part of the gate electrode 70G in the thickness direction. On the other hand, the average content of Ti is lower in the central part of the gate electrode 70G in the thickness direction. 【0117】 Specifically, as shown in Figure 8, the average Al content at the seven measurement points in the second gate electrode region 72 was 74.6%, and the standard deviation (σ) was 10.8%. The maximum-minimum difference R and uniformity U were R = 30.7% and U = 0.206. 【0118】 Similarly, for the Ti content at the seven measurement points in the second gate electrode region 72, the average (AVE) was 25.4%, and the standard deviation (σ) was 10.8%. The maximum-minimum difference R and uniformity U were R = 30.7% and U = 0.604. 【0119】 Furthermore, the gate electrode 70G has a composition region in the thickness direction of the gate electrode 70G in which the Ti content is 5% or less smaller than in other parts. Specifically, as shown in Figure 8, the second gate electrode region 72 of the gate electrode 70G includes a first composition region 70a, a second composition region 70b, and a third composition region 70c along the thickness direction of the gate electrode 70G, and the Ti content of the second composition region 70b is 5% or less smaller than the Ti content of the first composition region 70a and the third composition region 70c. It is also preferable that the Ti content of the second composition region 70b be 10% or more smaller than the Ti content of the first composition region 70a and the third composition region 70c. In this embodiment, the second composition region 70b is the central part in the thickness direction of the gate electrode 70G. Therefore, the Ti content in the central part in the thickness direction of the second gate electrode region 72 is smaller than the Ti content at each of the ends in the thickness direction of the second gate electrode region 72. Furthermore, a transition region exists at the boundary between the first composition region 70a and the second composition region 70b, in which the Ti content gradually increases. Also, a transition region exists at the boundary between the second composition region 70b and the third composition region 70c, in which the Ti content gradually decreases. 【0120】Furthermore, regarding the Al content in the second gate electrode region 72, the opposite can be said to apply to the Ti content. That is, the gate electrode 70G has a composition region in the thickness direction of the gate electrode 70G where the Al content is 5% or more greater than in other parts. Specifically, as shown in Figure 8, in the second gate electrode region 72, the Al content of the second composition region 70b is 5% or more greater than the Al content of the first composition region 70a and the third composition region 70c. In addition, it is preferable that the Al content of the second composition region 70b be 10% or more greater than the Al content of the first composition region 70a and the third composition region 70c. Specifically, the Al content in the central part of the second gate electrode region 72 in the thickness direction is greater than the Al content at each of the ends of the second gate electrode region 72 in the thickness direction. Also, there is a transition region at the boundary between the first composition region 70a and the second composition region 70b where the Al content gradually decreases. Furthermore, a transition region exists at the boundary between the second composition region 70b and the third composition region 70c, in which the Al content gradually changes significantly. 【0121】 In this way, the inventors of the present invention investigated the mechanism by which a first gate electrode region 71 and a second gate electrode region 72, having different Ti and Al composition distributions, are formed in the gate electrode 70G composed of a TiAl alloy layer, and it is presumed that this is because, in the heat treatment process shown in Figure 2H, the metal layer 70m, which consists of a laminate of a Ti film and an Al film, is alloyed by high-speed short-time annealing (RTA). 【0122】 Specifically, when a metal layer 70 m consisting of a Ti film and an Al film is rapidly heated and cooled by high-speed short-time annealing (RTA), the metal layer 70 m on the insulating layer 60 does not cool rapidly due to poor heat dissipation caused by the presence of the insulating layer 60, resulting in a locally longer heat treatment time. As a result, Ti is more easily diffused into the metal layer 70 m on the insulating layer 60. 【0123】 On the other hand, the metal layer 70m directly above the semiconductor laminate 20 (epitaxial layer) has improved heat dissipation and is rapidly cooled because there is no insulating layer 60, thus shortening the localized heat treatment time. As a result, Ti does not easily diffuse into the metal layer 70m directly above the semiconductor laminate 20. 【0124】 Thus, since Ti in the metal layer 70m does not diffuse easily directly above the semiconductor stack 20, the Ti content of the alloyed gate electrode 70G decreases in the second gate electrode region 72 on the semiconductor stack 20 where the Ti film of the metal layer 70m exists. 【0125】 In this embodiment, the metal layer 70m, which has a three-layer structure of Al film, Ti film, and Al film, is alloyed by high-speed short-time annealing (RTA). As a result, in the metal layer 70m directly above the semiconductor laminate 20, the Ti in the central part of the thickness direction where the Ti film exists is less likely to diffuse, and as shown in Figure 8, the Ti content in the central part, the second composition region 70b, is reduced. 【0126】 As described above, in the semiconductor device 1 according to this embodiment, the gate electrode 70G includes a first composition region 70a, a second composition region 70b, and a third composition region 70c along the thickness direction of the gate electrode 70G, and the Ti content of the second composition region 70b is 5% or more less than the Ti content of the first composition region 70a and the third composition region 70c. 【0127】 This results in a higher Al content in the second composition region 70b. In other words, a composition region with a high Al content remains partially in the gate electrode 70G. Therefore, the gate series resistance of the gate electrode 70G can be reduced. 【0128】 Furthermore, in the gate electrode 70G, the composition region with a partially high Al content (i.e., the composition region with a partially low Ti content) remains in the second gate electrode region 72, but does not remain in the first gate electrode region 71. 【0129】 Furthermore, as a result of forming a composition region with a partially low Ti content in the gate electrode 70G, the gate electrode 70G will have a first gate electrode region 71 with good uniformity of average Ti content and a second gate electrode region 72 with poor uniformity of average Ti content. 【0130】Thus, by forming a first gate electrode region 71 with good uniformity of average Ti content on the gate electrode 70G (i.e., uniform diffusion of Ti in the RTA), the corrosion resistance of the gate electrode 70G is improved, and corrosion during the process can be suppressed. Furthermore, high heat resistance and high reliability are also improved, so deterioration or damage of the gate electrode 70G under high voltage and high electric field conditions can be suppressed. 【0131】 Furthermore, in the semiconductor device 1 according to this embodiment, the source electrode 70S, the drain electrode 70D, and the gate electrode 70G are made of the same material and have the same film thickness. In other words, the source electrode 70S, the drain electrode 70D, and the gate electrode 70G have the same structure. 【0132】 As a result, the source electrode 70S, drain electrode 70D, and gate electrode 70G can be formed in the same process, simplifying the process of forming the source electrode 70S, drain electrode 70D, and gate electrode 70G, and enabling the manufacturing of the semiconductor device 1 at a low cost. 【0133】 Furthermore, the semiconductor device 1 according to this embodiment further includes a regrowth layer 30 as a fourth nitride semiconductor layer located above the electron supply layer 23 (second nitride semiconductor layer), and the gate layer 40, which is a third nitride semiconductor layer, is located above the regrowth layer 30. 【0134】 This configuration allows the threshold gate voltage to be adjusted by controlling the thickness of the regrowth layer 30 located below the gate electrode 70G. 【0135】 Furthermore, in the semiconductor device 1 according to this embodiment, the semiconductor laminate 20 has a recess 20R that penetrates the electron supply layer 23, which is a second nitride semiconductor layer, the regrowth layer 30, which is a fourth nitride semiconductor layer, is provided so as to cover the recess 20R, and at least a part of the gate layer 40, which is a third nitride semiconductor layer, is embedded in the recess 20R. 【0136】This configuration allows for increasing the thickness of the electron supply layer 23 in areas other than below the gate electrode 70G to lower the on-resistance, while eliminating the electron supply layer 23 in the area below the gate electrode 70G and controlling the gate voltage by the thickness of the regrowth layer 30. Specifically, the gate voltage can be lowered by reducing the thickness of the regrowth layer 30 in the area below the gate electrode 70G. 【0137】 Furthermore, the semiconductor device 1 according to this embodiment further includes a gate contact layer 50 as a fifth nitride semiconductor layer located between the gate layer 40, which is a third nitride semiconductor layer, and the gate electrode 70G. 【0138】 In this configuration, a gate contact layer 50 made of nitride semiconductor material exists on top of a gate layer 40 which is a p-type nitride semiconductor layer, thereby increasing the Schottky barrier. 【0139】 Furthermore, the method for manufacturing the semiconductor device 1 according to this embodiment includes the steps of: forming a semiconductor laminate 20 having an electron supply layer 23 (second nitride semiconductor layer) located above an electron transport layer 22 (first nitride semiconductor layer); forming a p-type gate layer 40 (third nitride semiconductor layer) above the semiconductor laminate 20; patterning the gate layer 40 to form a gate layer 40 of a predetermined shape above a first region 20a in the semiconductor laminate 20; forming a metal layer 70m containing Ti and Al so as to cover the gate layer 40; patterning the metal layer 70m to form a source electrode 70S and a drain electrode 70D of a predetermined shape on a second region 20b in the semiconductor laminate 20, and forming a gate electrode 70G of a predetermined shape above the gate layer 40; and alloying the source electrode 70S, drain electrode 70D and gate electrode 70G by heat treatment. 【0140】As a result, the source electrode 70S, drain electrode 70D, and gate electrode 70G are formed in the same process, which reduces manufacturing costs and enables a lower cost for the semiconductor device 1. Furthermore, by forming the gate electrode 70G, source electrode 70S, and drain electrode 70D simultaneously, variations in the formation of the gate electrode 70G, source electrode 70S, and drain electrode 70D can be suppressed. This suppresses changes in the distance between the gate electrode 70G and the source electrode 70S or drain electrode 70D, allowing for a smaller semiconductor device 1. 【0141】 Furthermore, the manufacturing method of the semiconductor device 1 according to this embodiment includes a step of forming an insulating layer 60 of a predetermined shape between the step of patterning the gate layer 40 (third nitride semiconductor layer) and the step of forming the metal layer 70m. In the step of forming the insulating layer 60 of a predetermined shape, an insulating film is formed on the semiconductor laminate 20 so as to cover the gate layer 40 formed in a predetermined shape, and then a part of the insulating film is removed by dry etching using a fluorine-based gas to form an opening in the insulating film. 【0142】 This allows for easy formation of a Schottky junction layer on the first region 20a (gate region) of the semiconductor laminate 20, thereby suppressing the gate current. 【0143】 Furthermore, in the manufacturing method of the semiconductor device 1 according to this embodiment, in the step of forming an insulating layer 60 of a predetermined shape, oxygen ashing is performed after forming an opening in the insulating film. 【0144】 This makes it even easier to form a Schottky junction layer on the first region 20a of the semiconductor laminate 20. Therefore, the gate current can be further suppressed. 【0145】 (Embodiment 2) Next, the semiconductor device 1A according to Embodiment 2 will be described with reference to Figure 9. Figure 9 is a cross-sectional view showing the configuration of the semiconductor device 1A according to Embodiment 2. In the following description, the differences from Embodiment 1 will be the main focus, and the explanation of the common points will be omitted or simplified. 【0146】As shown in Figure 9, the semiconductor device 1A according to this embodiment comprises a substrate 10, a semiconductor laminate 20A having a buffer layer 21, an electron transport layer 22, and an electron supply layer 23A, a gate layer 40, a gate contact layer 50, an insulating layer 60, a gate electrode 70G, a source electrode 70S, and a drain electrode 70D. 【0147】 The semiconductor device 1A according to this embodiment differs from the semiconductor device 1 according to Embodiment 1 in the configuration of the semiconductor stack 20A. Specifically, in the semiconductor device 1 according to Embodiment 1, a recess 20R was formed in the semiconductor stack 20, but in the semiconductor device 1A according to this embodiment, a recess 20R is not formed in the semiconductor stack 20A. More specifically, in Embodiment 1, a recess 20R was formed in the electron supply layer 23, but in this embodiment, a recess 20R is not formed in the electron supply layer 23A. 【0148】 Furthermore, the semiconductor device 1A according to this embodiment does not have a regrowth layer 30 formed on it compared to the semiconductor device 1 according to the first embodiment. Therefore, in this embodiment, the gate layer 40 is provided directly above the electron supply layer 23A. 【0149】 The semiconductor device 1A configured in this way can be manufactured by the method shown in Figures 10A to 10F. Figures 10A to 10F are cross-sectional views showing each step in the manufacturing method of the semiconductor device 1A according to Embodiment 2. Figure 10A shows the step of forming the buffer layer 21, electron transport layer 22, electron supply layer 23A, gate layer 40, and gate contact layer 50. Figure 10B shows the step of patterning the gate layer 40 and gate contact layer 50. Figure 10C shows the step of forming the insulating layer 60. Figure 10D shows the step of forming the metal layer 70m. Figure 10E shows the step of patterning the metal layer 70m. Figure 10F shows the heat treatment step. 【0150】First, as shown in Figure 10A, a semiconductor laminate 20A consisting of a buffer layer 21, an electron transport layer 22, and an electron supply layer 23A is formed on the substrate 10 (semiconductor laminate formation step), a gate layer 40 is formed above the semiconductor laminate 20A (gate layer formation step), and a gate contact layer 50 is formed above the gate layer 40 (gate contact layer formation step). 【0151】 In this embodiment, a buffer layer 21, an electron transport layer 22, an electron supply layer 23A, a gate layer 40, and a gate contact layer 50 are sequentially formed using MOCVD. Specifically, on a silicon substrate 10, a buffer layer 21 with a layer thickness of 2 μm and consisting of a laminated structure of AlN and AlGaN, an electron transport layer 22 with a layer thickness of 200 nm and consisting of GaN, an electron supply layer 23A with a layer thickness of 20 nm and consisting of AlGaN with an Al composition ratio of 25%, a gate layer 40 with a layer thickness of 180 nm and consisting of GaN doped with magnesium as a p-type impurity, and a gate contact layer 50 with a layer thickness of 2 nm and consisting of undoped GaN are sequentially formed by epitaxial growth. 【0152】 Next, as shown in Figure 10B, the gate layer 40 is patterned to form a gate layer 40 of a predetermined shape above the first region 20a in the semiconductor laminate 20A (gate layer patterning step). In this embodiment, the gate layer 40 and the gate contact layer 50 are patterned simultaneously using the same method as in Embodiment 1 above, thereby forming the gate layer 40 and the gate contact layer 50 in an island shape. Specifically, after applying a resist onto the gate contact layer 50, the resist is patterned by lithography, thereby forming a resist mask by leaving the resist in the areas where the gate layer 40 and the gate contact layer 50 remain. Then, using the resist mask as a mask, dry etching is performed to etch away the gate layer 40 and the gate contact layer 50 until the electron supply layer 23A is exposed, thereby forming the gate layer 40 and the gate contact layer 50 in an island shape. After that, the resist mask and the polymer generated by dry etching are removed. 【0153】Next, as shown in Figure 10C, an insulating layer 60 of a predetermined shape is formed (insulating layer formation step). Specifically, an insulating layer 60 of a predetermined shape is formed by the same method as in Embodiment 1 above, having a first opening 60a located above the first region 20a of the semiconductor laminate 20A and a second opening 60b located above the second region 20b of the semiconductor laminate 20A. 【0154】 Specifically, in this embodiment as well, first, SiH is used as the raw material gas. ４ and NH ３ Using this method, an insulating film made of SiN is formed over the entire surface of the exposed electron supply layer 23A so as to cover the gate layer 40 and gate contact layer 50 formed in a predetermined shape. Then, after coating the insulating film with a resist, the resist is patterned by lithography to form a resist mask, leaving the resist in the areas excluding the first region 20a and the second region 20b. In other words, a resist mask with openings in the areas corresponding to the first region 20a and the second region 20b is formed. Then, using the resist mask with openings as a mask, dry etching is performed using a fluorine-based gas until the underlying layer of the insulating film is exposed, thereby etching the insulating film exposed at the openings of the resist mask. This makes it possible to form an insulating layer 60 having a first opening 60a and a second opening 60b. In addition, the gate contact layer 50, which is the underlying layer of the insulating film, is exposed in the area corresponding to the first opening 60a, and the electron supply layer 23A, which is the underlying layer of the insulating film, is exposed in the area corresponding to the second opening 60b. After that, the resist mask and the polymer generated by dry etching are removed. In this embodiment as well, the removal of this polymer is performed by oxygen ashing (O ２ It is recommended to perform an ashing. 【0155】Next, as shown in Figure 10D, a metal layer 70m is formed to cover the gate layer 40 formed in a predetermined shape (metal layer formation step). In this embodiment as well, a metal layer 70m is formed to cover the gate layer 40 and gate contact layer 50 formed in a predetermined shape using the same method as in Embodiment 1 above. Specifically, a metal layer 70m is formed over the entire surface above the semiconductor laminate 20A so as to cover the exposed gate contact layer 50, the exposed electron supply layer 23A, and the insulating layer 60. In this embodiment as well, the metal layer 70m contains Ti and Al. Specifically, the metal layer 70m is a laminate with a three-layer structure of a Ti film, an Al film, and a Ti film. 【0156】 Next, as shown in Figure 10E, the metal layer 70m is patterned to form a source electrode 70S and a drain electrode 70D of a predetermined shape on the second region 20b of the semiconductor laminate 20A, and a gate electrode 70G of a predetermined shape is formed above the gate layer 40 (metal layer patterning step). 【0157】 Specifically, in this embodiment as well, after applying a resist onto the metal layer 70m, the resist is patterned by lithography to form a resist mask, leaving the resist in the first region 20a and the second region 20b of the semiconductor laminate 20A. Subsequently, the metal layer 70m is etched by dry etching using the resist mask as a mask. As a result, the metal layer 70m remains in the first opening 60a and the second opening 60b, allowing the formation of a predetermined shape source electrode 70S and drain electrode 70D on the second region 20b, and a predetermined shape gate electrode 70G on the first region 20a (i.e., above the gate layer 40). After that, the resist mask and the polymer generated by dry etching are removed. 【0158】Next, as shown in Figure 10F, a heat treatment is performed at a predetermined temperature (heat treatment step). By performing the heat treatment, the source electrode 70S, drain electrode 70D, and gate electrode 70G can be alloyed. In other words, the source electrode 70S, drain electrode 70D, and gate electrode 70G will contain a TiAl alloy layer. Furthermore, by performing the heat treatment, ohmic contact can be obtained between the source electrode 70S and the drain electrode 70D. Therefore, in this embodiment as well, the temperature during the heat treatment (heat treatment temperature) should preferably be 450°C or higher. 【0159】 Specifically, in this embodiment as well, the heat treatment temperature was set to 525°C, the heat treatment time to 60 seconds, and the heat treatment was performed by high-speed short-time annealing (RTA) in a nitrogen gas atmosphere. 【0160】 Therefore, although not shown in the figures, in this embodiment as well, similar to Embodiment 1, the gate electrode 70G has a first gate electrode region 71 located above the portion of the insulating layer 60 located above the gate layer 40, and a second gate electrode region 72 in contact with the semiconductor laminate 20 through a first opening 60a, and the uniformity of the average Ti content in the second gate electrode region 72 is worse than the uniformity of the average Ti content in the first gate electrode region 71. Furthermore, in the second gate electrode region 72, the gate electrode 70G includes a first composition region 70a, a second composition region 70b, and a third composition region 70c along the thickness direction of the gate electrode 70G, and the Ti content of the second composition region 70b is 5% or more smaller than the Ti content of the first composition region 70a and the third composition region 70c. 【0161】 Thus, by going through the series of steps shown in Figures 10A to 10F, a semiconductor device 1A with the structure shown in Figure 9 can be obtained. 【0162】The semiconductor device 1A according to this embodiment, configured in this manner, is similar to the semiconductor device 1 in Embodiment 1 above, and comprises a semiconductor laminate 20A having an electron transport layer 22 which is a first nitride semiconductor layer and an electron supply layer 23A which is a second nitride semiconductor layer located above the electron transport layer 22; a gate layer 40 which is a p-type third nitride semiconductor layer located above the first region 20a of the semiconductor laminate 20A; a source electrode 70S and a drain electrode 70D located above the second region 20b of the semiconductor laminate 20A; and a gate electrode 70G which is a Schottky electrode located above the gate layer 40 which is the third nitride semiconductor layer. The source electrode 70S, the drain electrode 70D, and the gate electrode 70G include a TiAl alloy layer. 【0163】 This configuration makes it possible to obtain the same effects as the semiconductor device 1 in the first embodiment described above. 【0164】 Specifically, even if heat treatment is performed after the gate electrode 70G is formed, the gate electrode 70G can be made into a Schottky electrode, thus suppressing the gate current. Furthermore, since the source electrode 70S, drain electrode 70D, and gate electrode 70G are made of the same material, it is possible to form the source electrode 70S, drain electrode 70D, and gate electrode 70G in the same process, thereby reducing the cost of the semiconductor device 1A. In addition, by forming the gate electrode 70G, source electrode 70S, and drain electrode 70D simultaneously, variations in the formation of the gate electrode 70G, source electrode 70S, and drain electrode 70D can be suppressed, thereby suppressing changes in the inter-electrode distance between the gate electrode 70G and the source electrode 70S or drain electrode 70D, and enabling miniaturization of the semiconductor device 1A. 【0165】 As described above, the semiconductor device 1A according to this embodiment also has a structure in which a gate layer 40, which is a p-type nitride semiconductor layer, is provided below the gate electrode 70G. This allows for suppression of the gate current, as well as miniaturization and cost reduction. Moreover, in this embodiment as well, the amount of gate current can be adjusted by adjusting the carrier concentration of the gate layer 40, which is a p-type nitride semiconductor layer. 【0166】 Furthermore, in the semiconductor device 1A according to this embodiment, the average carrier concentration of the gate layer 40, which is the third nitride semiconductor layer, is 2.1 × 10 １７ cm －３ That concludes the explanation. As a result, the gate electrode 70G makes Schottky contact, and the gate electrode 70G functions as a Schottky electrode. 【0167】 (Modification) The semiconductor device relating to the present disclosure has been described above based on Embodiments 1 and 2, but the present disclosure is not limited to Embodiments 1 and 2. 【0168】 For example, in embodiments 1 and 2 described above, a gate contact layer 50 was provided between the gate electrode 70G and the gate layer 40, but this is not limited to this. Specifically, a gate contact layer 50 may not be provided between the gate electrode 70G and the gate layer 40, and the gate electrode 70G may be provided directly above the gate layer 40. 【0169】 Furthermore, while embodiments 1 and 2 described above explain the formation of two regions with different Ti and Al composition distributions in the gate electrode 70G, the invention is not limited to this. For example, in the source electrode 70S and drain electrode 70D, similar to the gate electrode 70G, the metal layer consisting of a laminate of a Ti film and an Al film is alloyed by high-speed short-time annealing (RTA). As a result, in the source electrode 70S and drain electrode 70D, Ti diffuses easily in the portion on the insulating layer 60, while Ti diffuses less easily in the portion directly above the semiconductor laminate 20. Therefore, two regions with different Ti and Al composition distributions are also formed in the source electrode 70S and drain electrode 70D. Specifically, a composition region with a partially high Al content (i.e., a composition region with a partially low Ti content) is formed. In addition, as a result, in each of the source electrode 70S and drain electrode 70D, a first region with good uniformity of average Ti content and a second region with poor uniformity of average Ti content are formed. 【0170】Furthermore, this disclosure also includes forms obtained by applying various modifications to the above embodiments that a person skilled in the art could conceive, and forms realized by arbitrarily combining the components and functions of the embodiments without departing from the spirit of this disclosure. In addition, this disclosure also includes any combination of two or more claims from the multiple claims described in the claims of this application, provided that they are not technically contradictory. For example, if the cited claims described in the claims of this application are made into a multi-claim or multi-multi-claim so as to refer to all of the higher-level claims without technically contradictory, then all combinations of claims included in that multi-claim or multi-multi-claim are also included in this disclosure. 【0171】 The technology disclosed herein can be used as semiconductor devices such as switching transistors used in communication equipment, inverters, and power supply circuits that require high-speed operation. 【0172】 1, 1A Semiconductor device 10 Substrate 20, 20A Semiconductor laminate 20C Two-dimensional electron gas channel 20R Recess 20a First region 20b Second region 21 Buffer layer 22 Electron transport layer 23, 23A Electron supply layer 30 Re-growth layer 40 Gate layer 50 Gate contact layer 60 Insulating layer 60a First aperture 60b Second aperture 70G Gate electrode 70S Source electrode 70D Drain electrode 71 First gate electrode region 72 Second gate electrode region 70a First composition region 70b Second composition region 70c Third composition region

Claims

1. A semiconductor device comprising: a semiconductor laminate having a first nitride semiconductor layer and a second nitride semiconductor layer located above the first nitride semiconductor layer, wherein a two-dimensional electron gas channel is formed; a p-type third nitride semiconductor layer located above a first region in the semiconductor laminate; a source electrode and a drain electrode located above a second region in the semiconductor laminate; and a gate electrode located above the third nitride semiconductor layer, which is a Schottky electrode, wherein the source electrode, the drain electrode and the gate electrode include a TiAl alloy layer.

2. The average carrier concentration of the third nitride semiconductor layer is 2.1 × 10⁻⁶ １７ cm －３ The semiconductor device according to claim 1.

3. The semiconductor device according to claim 1, wherein the gate electrode includes a first composition region, a second composition region, and a third composition region along the thickness direction of the gate electrode, and the Ti content of the second composition region is 5% or more less than the Ti content of the first composition region and the third composition region.

4. The semiconductor device according to claim 3, further comprising an insulating layer having an opening above the second region, a portion of the insulating layer located above the third nitride semiconductor layer, the gate electrode having a first gate electrode region located above the portion of the insulating layer located above the third nitride semiconductor layer, and a second gate electrode region in contact with the semiconductor laminate through the opening, wherein the uniformity of the average Ti content in the second gate electrode region is worse than the uniformity of the average Ti content in the first gate electrode region.

5. The semiconductor device according to claim 1, wherein the film thickness of the source electrode, the drain electrode, and the gate electrode are all the same.

6. The semiconductor device according to claim 1, further comprising a fourth nitride semiconductor layer located above the second nitride semiconductor layer, wherein the third nitride semiconductor layer is located above the fourth nitride semiconductor layer.

7. The semiconductor device according to claim 6, wherein the semiconductor laminate has a recess penetrating the second nitride semiconductor layer, the fourth nitride semiconductor layer is provided so as to cover the recess, and at least a portion of the third nitride semiconductor layer is embedded in the recess.

8. The semiconductor device according to any one of claims 1 to 7, further comprising a fifth nitride semiconductor layer located between the third nitride semiconductor layer and the gate electrode.

9. A method for manufacturing a semiconductor device, comprising the steps of: forming a semiconductor laminate having a second nitride semiconductor layer located above a first nitride semiconductor layer; forming a p-type third nitride semiconductor layer above the semiconductor laminate; patterning the third nitride semiconductor layer to form a third nitride semiconductor layer of a predetermined shape above a first region in the semiconductor laminate; forming a metal layer containing Ti and Al so as to cover the third nitride semiconductor layer; patterning the metal layer to form a source electrode and a drain electrode of a predetermined shape above a second region in the semiconductor laminate, and a gate electrode of a predetermined shape above the third nitride semiconductor layer; and alloying the source electrode, the drain electrode and the gate electrode by heat treatment.

10. A method for manufacturing a semiconductor device according to claim 9, comprising the step of forming an insulating layer of a predetermined shape between the step of patterning the third nitride semiconductor layer and the step of forming the metal layer, wherein in the step of forming the insulating layer of the predetermined shape, an insulating film is formed above the semiconductor laminate so as to cover the third nitride semiconductor layer formed in the predetermined shape, and then a part of the insulating film is removed by dry etching using a fluorine-based gas to form an opening in the insulating film.

11. The method for manufacturing a semiconductor device according to claim 10, wherein, in the step of forming the insulating layer of a predetermined shape, oxygen ashing is performed after forming an opening in the insulating film.

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