Semiconductor device

Abstract

A semiconductor device (1) comprises: a semiconductor layer (40) that includes a first region (A1) and a second region (A2) and that has an area bisected by the first region (A1) and the second region (A2); a transistor (10); and a transistor (20), wherein first gate wiring (114) surrounding a first source electrode (11) and second gate wiring (124) surrounding a second source electrode (21) are formed, the first gate wiring (114) and the second gate wiring (124) are formed such that the boundary (90C) between the first region (A1) and the second region (A2) is interposed therebetween, drain wiring (140) surrounds the first gate wiring (114) and the second gate wiring (124), and the drain wiring (140) is not formed between the first gate wiring (114) and the second gate wiring (124).

Description

Semiconductor device 【0001】 The present disclosure relates to a semiconductor device. 【0002】 Conventionally, a semiconductor device including a vertical MOS transistor and an EQR (Equi Potential Ring) has been known (see, for example, Patent Document 1). 【0003】 International Publication No. 2024 / 018715 【0004】 By providing the semiconductor device with an EQR, it becomes possible to suppress leakage current. However, it becomes difficult to use the area directly under the EQR as the active region of the vertical MOS transistor. In such a semiconductor device, it has been difficult to sufficiently widen the active region and reduce the on-resistance. 【0005】 Therefore, an object of the present disclosure is to provide a semiconductor device that realizes reduction of on-resistance while suppressing leakage current. 【0006】A semiconductor device according to one aspect of the present disclosure comprises a semiconductor substrate on its back side, a semiconductor layer on its front side including a first region and a second region adjacent to the first region in a plan view of the semiconductor substrate, the area of ​​which is divided into two equal parts by the first region and the second region in a plan view, a first vertical MOS transistor formed in the first region of the semiconductor layer, a second vertical MOS transistor formed in the second region of the semiconductor layer, and a metal layer formed in contact with the back side of the semiconductor layer, wherein the semiconductor substrate is a common drain region of the first vertical MOS transistor and the second vertical MOS transistor, and in a plan view, the first region includes a first source electrode of the first vertical MOS transistor and a front A first gate wiring is formed in the semiconductor layer, connected to the first gate electrode of the first vertical MOS transistor and surrounding the first source electrode. In the second region, a second source electrode of the second vertical MOS transistor and a second gate wiring are formed, connected to the second gate electrode of the second vertical MOS transistor and surrounding the second source electrode. The first gate wiring and the second gate wiring are formed across the boundary between the first region and the second region. A drain wiring connected to the common drain region is formed on the outer periphery of the semiconductor layer. The drain wiring surrounds the first gate wiring and the second gate wiring, and no drain wiring is formed between the first gate wiring and the second gate wiring. 【0007】 According to this disclosure, it is possible to provide a semiconductor device that reduces on-resistance while suppressing leakage current. 【0008】Figure 1 is a cross-sectional view showing an example of the structure of a semiconductor device according to the embodiment. Figure 2 is a plan view showing an example of the arrangement of pads in a semiconductor device according to the embodiment. Figure 3 is a cross-sectional view showing the main current flowing through the semiconductor device according to the embodiment. Figure 4 is a plan view showing an example of the arrangement of electrodes in a semiconductor device according to the embodiment. Figure 5 is a circuit diagram showing an example of a semiconductor device according to the embodiment. Figure 6 is a cross-sectional view showing an example of the structure of a semiconductor device according to the embodiment. Figure 7 is a plan view showing an example of the arrangement of pads in a semiconductor device according to Comparative Example 2. Figure 8 is a plan view showing an example of the arrangement of electrodes in a semiconductor device according to Comparative Example 2. Figure 9 is a cross-sectional view showing an example of the structure of a semiconductor device according to Comparative Example 1 before BT testing. Figure 10 is a cross-sectional view showing an example of the structure of a semiconductor device according to Comparative Example 1 during BT testing. Figure 11 is a cross-sectional view showing an example of the structure of a semiconductor device according to Comparative Example 2 before BT testing. Figure 12 is a cross-sectional view showing an example of the structure of a semiconductor device according to Comparative Example 2 during BT testing. Figure 13 is a diagram showing the electrical characteristics of the semiconductor device according to Comparative Example 1 and the semiconductor device according to Comparative Example 2 after BT testing. Figure 14 is a cross-sectional view showing an example of the structure of a semiconductor device according to the embodiment during BT testing for the first vertical MOS transistor. Figure 15 is a cross-sectional view showing an example of the structure of a semiconductor device according to an embodiment during BT testing of a second vertical MOS transistor. Figure 16 is a cross-sectional view showing an example of the structure of a semiconductor device according to comparative example 2. Figure 17 is a plan view showing an example of the arrangement of electrodes of a semiconductor device according to an embodiment. Figure 18 is a cross-sectional view showing an example of the structure of a semiconductor device according to modification 1 of the embodiment. Figure 19 is a cross-sectional view showing an example of the structure of a semiconductor device according to modification 1 of the embodiment. Figure 20 is a cross-sectional view showing an example of the structure of a semiconductor device according to modification 2 of the embodiment. Figure 21 is a cross-sectional view showing an example of the structure of a semiconductor device according to modification 3 of the embodiment. Figure 22 is a cross-sectional view showing an example of the structure of a semiconductor device according to modification 4 of the embodiment. Figure 23 is a cross-sectional view showing an example of the structure of a semiconductor device according to modification 5 of the embodiment. 【0009】The embodiments described below are all specific examples of the present disclosure. The numerical values, shapes, materials, components, arrangement positions of components, and connection configurations shown in the following embodiments are examples only and are not intended to limit the present disclosure. 【0010】 In the following embodiments, the terms "up" and "down" do not refer to the upward (vertically upward) and downward (vertically downward) directions in absolute spatial perception. Furthermore, the terms "up" and "down" apply not only when two components are spaced apart and another component exists between them, but also when two components are placed in close proximity and touching each other. 【0011】 Furthermore, each figure is a schematic diagram and not necessarily a strictly accurate representation. Therefore, for example, the scale may not necessarily match in each figure. In each figure, substantially identical components are given the same reference numerals, and redundant explanations are omitted or simplified. 【0012】 Furthermore, in this specification, terms indicating relationships between elements such as parallel or orthogonal, terms indicating shapes of elements such as circular or rectangular, and numerical ranges do not represent only strict meanings, but also include substantially equivalent ranges, such as differences of a few percent. 【0013】 Furthermore, in this specification and the drawings, the x-axis, y-axis, and z-axis represent the three axes of a three-dimensional Cartesian coordinate system. In the embodiments, the two axes parallel to the semiconductor substrate are defined as the x-axis and y-axis, and the direction perpendicular to the x-axis and y-axis is defined as the z-axis direction. In the embodiments described below, the positive z-axis direction may be described as upward, and the negative z-axis direction may be described as downward. 【0014】 Furthermore, in this specification, "plan view" means viewing the semiconductor substrate from the positive z-axis direction, and the resulting diagram is called a plan view. 【0015】(Embodiment) [Structure of Semiconductor Device] The structure of the semiconductor device according to this embodiment will be described below. The semiconductor device according to this embodiment is a chip-size package (CSP) type semiconductor device that can be mounted face down, with two vertical MOS (Metal Oxide Semiconductor) transistors formed on a semiconductor substrate. The two vertical MOS transistors are power transistors, and are so-called trench MOS type FETs (Field Effect Transistors). 【0016】 Figure 1 is a cross-sectional view showing an example of the structure of a semiconductor device 1 according to this embodiment. Figure 2 is a plan view showing an example of the arrangement of pads in the semiconductor device 1 according to this embodiment. Figure 3 is a cross-sectional view showing the main current flowing through the semiconductor device 1 according to this embodiment. The main current is the main component of the current flowing through the circuit, and is the current that flows in the designed direction along the designed current path, excluding leakage current and surge current. When considered from within the semiconductor device 1, the main current refers to the current that flows along the path indicated by the bidirectional arrow in Figure 3, and when the semiconductor device 1 is viewed from above, it refers to the current that flows horizontally inside the semiconductor device 1 (i.e., the current that flows horizontally inside the metal layer 30 or semiconductor substrate 32 in Figure 3). Figures 1 and 3 show the cross-section along line I-I in Figure 2. 【0017】 As shown in Figures 1 and 2, the semiconductor device 1 comprises a semiconductor layer 40, a metal layer 30, a first vertical MOS transistor 10 (hereinafter also referred to as "transistor 10") formed in a first region A1 of the semiconductor layer 40, and a second vertical MOS transistor 20 (hereinafter also referred to as "transistor 20") formed in a second region A2 of the semiconductor layer 40. The semiconductor device 1 also comprises an interlayer insulating layer 34 and a passivation layer 35. 【0018】The semiconductor layer 40 includes a semiconductor substrate 32 on its back side (i.e., the negative z-axis side) and a first region A1 and a second region A2 on its front side (i.e., the positive z-axis side). As shown in Figure 2, the first region A1 and the second region A2 are adjacent to each other in a plan view of the semiconductor substrate 32. The semiconductor layer 40 is bisected in area by the first region A1 and the second region A2 in a plan view of the semiconductor substrate 32. That is, the first region A1 and the second region A2 are the two halves that divide the semiconductor layer 40 in area. The semiconductor layer 40 further includes a low-concentration impurity layer 33 on the positive z-axis side of the semiconductor substrate 32, and is constructed by stacking the semiconductor substrate 32 and the low-concentration impurity layer 33. 【0019】 The semiconductor substrate 32 is made of silicon containing impurities of a first conductivity type. 【0020】 The low-concentration impurity layer 33 is positioned on the surface side of the semiconductor layer 40, formed in contact with the semiconductor substrate 32, and is made of silicon containing a first conductivity type impurity at a concentration lower than the concentration of the first conductivity type impurity in the semiconductor substrate 32. The low-concentration impurity layer 33 may be formed on the semiconductor substrate 32, for example, by epitaxial growth. 【0021】 The metal layer 30 is formed in contact with the back side of the semiconductor layer 40, that is, in contact with the main surface of the semiconductor substrate 32 on the negative z-axis side of the semiconductor layer 40. The metal layer 30 may be a multilayer structure including a layer mainly composed of silver or copper. The metal layer 30 may also contain trace amounts of elements other than metal that are mixed in as impurities during the metal manufacturing process. Furthermore, the metal layer 30 may be formed over the entire back surface of the semiconductor layer 40. 【0022】Furthermore, as shown in Figures 1 and 2, the transistor 10 includes a first source electrode 11, a first source region 14, a first gate conductor 15, a first gate oxide film 16, a first body region 18, and a first gate wiring 114. The transistor 10 also has a plurality (in this case, seven) of first source pads 111 and first gate pads 119 on the surface of the semiconductor layer 40 (i.e., the surface of the low-concentration impurity layer 33), which are bonded to the mounting substrate via a bonding material during face-down mounting. In addition, as shown in Figure 4, which will be described later, the transistor 10 has a first gate electrode 19. 【0023】 The transistor 20 includes a second source electrode 21, a second source region 24, a second gate conductor 25, a second gate oxide film 26, a second body region 28, and a second gate wiring 124. The transistor 20 also has a plurality (in this case, seven) of second source pads 121 and second gate pads 129 on the surface of the semiconductor layer 40 (i.e., the surface of the low-concentration impurity layer 33), which are bonded to the mounting substrate via a bonding material during face-down mounting. Furthermore, as shown in Figure 4 described later, the transistor 20 has a second gate electrode 29. The first source pad 111, the first gate pad 119, the second source pad 121, and the second gate pad 129 are sometimes collectively referred to as "pads". 【0024】 As shown in Figure 2, in a plan view, the semiconductor layer 40 is rectangular in shape, with transistors 10 and 20 aligned in the first direction (x-axis direction), and the main current flows in the first direction. Here, the semiconductor layer 40 is assumed to be rectangular in shape in a plan view, having one long side 91 and the other long side 92 parallel to the first direction, and one short side 93 and the other short side 94 in a direction perpendicular to the first direction (y-axis direction). In other words, here, the semiconductor layer 40 is assumed to be rectangular with the first direction as its long side. 【0025】 In Figure 2, the center line 90 is a line that bisects the rectangular semiconductor layer 40 in the first direction in a plan view. Therefore, the center line 90 is a straight line perpendicular to the first direction in a plan view. 【0026】 The boundary 90C is the boundary between the first region A1 and the second region A2. In a plan view of the semiconductor substrate 32, the area of ​​the semiconductor layer 40 is divided equally by the first region A1 and the second region A2. In other words, the boundary 90C divides the area of ​​the semiconductor layer 40 equally in a plan view, but it does not necessarily have to be a straight line. In a plan view, the center line 90 and the boundary 90C may or may not coincide. 【0027】 As shown in Figure 2, the first gate pad 119 is positioned such that, in a plan view, none of the multiple first source pads 111 are sandwiched between it and one of its long sides 91, or between it and the boundary 90C in the first direction. 【0028】 The multiple first source pads 111, in a plan view, include multiple substantially rectangular shapes (in this case, all of the first source pads 111), and these multiple substantially rectangular first source pads 111 are arranged in a stripe pattern, with each of their longitudinal directions parallel to one short side 93 and the other short side 94. 【0029】 The second gate pad 129 is positioned such that, in a plan view, no part of the multiple second source pads 121 is sandwiched between it and the other long side 92, and between it and the boundary 90C in the first direction. 【0030】 The multiple second source pads 121, in a plan view, include multiple substantially rectangular shapes (in this case, all of the second source pads 121), and these multiple substantially rectangular second source pads 121 are arranged in a stripe pattern, with each of their longitudinal directions parallel to one short side 93 and the other short side 94. 【0031】 Furthermore, the number of first gate pads 119 and the number of second gate pads 129 are not necessarily limited to one as illustrated in Figure 2, but may be two or more. Also, the first gate pads 119 and the second gate pads 129 may be substantially circular in shape as illustrated in Figure 2, or they may not be substantially circular in shape. 【0032】Furthermore, the number of multiple first source pads 111 and the number of multiple second source pads 121 are not necessarily limited to the seven exemplified in Figure 2, and may be any number other than seven. Also, the multiple roughly rectangular first source pads 111 are not limited to the arrangement shown in Figure 2, but may be arranged in a stripe pattern parallel to one long side 91 and the other long side 92, and the multiple roughly rectangular second source pads 121 are not limited to the arrangement shown in Figure 2, but may be arranged in a stripe pattern parallel to one long side 91 and the other long side 92. 【0033】 As shown in Figures 1 and 2, a first body region 18 containing impurities of a second conductivity type different from a first conductivity type is formed in the first region A1 of the low-concentration impurity layer 33. The first body region 18 has a first source region 14 containing impurities of the first conductivity type, a first gate conductor 15, and a first gate oxide film 16 formed therein. 【0034】 The first source electrode 11 of the transistor 10 is formed in the first region A1. The first source electrode 11 is connected to the first source region 14 and the first body region 18. The first gate oxide film 16 is formed inside a plurality of first gate trenches 17 that extend from the upper surface of the semiconductor layer 40 through the first source region 14 and the first body region 18 to a depth of part of the low-concentration impurity layer 33. 【0035】 The first gate conductor 15 is formed on the first gate oxide film 16 inside the first gate trench 17. The first gate conductor 15 is an embedded gate electrode embedded within the semiconductor layer 40 and is electrically connected to the first gate pad 119. The first gate conductor 15 may be polysilicon containing impurities, as is not limited to this example. 【0036】 The first gate oxide film 16 may be, as an example, silicon oxide (SiO₂) ２ It would be preferable if it were composed of the following: 【0037】The first source electrode 11 may be made of a metal containing any one or more of aluminum, copper, gold, and silver as an example not limited thereto. 【0038】 In the second region A2 of the low-concentration impurity layer 33, a second body region 28 containing impurities of the second conductivity type is formed. In the second body region 28, a second source region 24 containing impurities of the first conductivity type, a second gate conductor 25, and a second gate oxide film 26 are formed. 【0039】 In the second region A2, a second source electrode 21 of the transistor 20 is formed. The second source electrode 21 is connected to the second source region 24 and the second body region 28. The second gate oxide film 26 is formed inside a plurality of second gate trenches 27 formed to a depth penetrating the second source region 24 and the second body region 28 from the upper surface of the semiconductor layer 40 to a part of the low-concentration impurity layer 33. 【0040】 The second gate conductor 25 is formed on the second gate oxide film 26 inside the second gate trench 27. The second gate conductor 25 is a buried gate electrode embedded in the semiconductor layer 40 and is electrically connected to the second gate pad 129. The second gate conductor 25 may be, as an example not limited thereto, polysilicon containing impurities. 【0041】 The second gate oxide film 26 may be, as an example not limited thereto, composed of silicon oxide (SiO ２ ). 【0042】 The second source electrode 21 may be made of a metal containing any one or more of aluminum, copper, gold, and silver as an example not limited thereto. 【0043】 With the above configuration of the transistor 10 and the transistor 20, the semiconductor substrate 32 functions as a common drain region in which the first drain region of the transistor 10 and the second drain region of the transistor 20 are shared. 【0044】Further, as shown in FIG. 3, the semiconductor device 1 has a bidirectional path from the first source electrode 11 to the second source electrode 21 via the first drain region, the metal layer 30, and the second drain region as the main current path. 【0045】 The interlayer insulating layer 34 is an insulating layer formed above the semiconductor layer 40 and has a plurality of openings. The passivation layer 35 is a layer formed above the semiconductor layer 40. A part of the passivation layer 35 is also formed above the interlayer insulating layer 34 and the first source electrode 11, and above the interlayer insulating layer 34 and the second source electrode 21. 【0046】 As shown in FIG. 1, the first source region 14 and the first body region 18 are covered with the interlayer insulating layer 34 having an opening, and are connected to the first source electrode 11 through the opening of the interlayer insulating layer 34. The first source electrode 11 is provided in the opening and is connected to the first source region 14 and the first body region 18. The interlayer insulating layer 34 and the first source electrode 11 are covered with the passivation layer 35 having an opening. 【0047】 The second source region 24 and the second body region 28 are covered with the interlayer insulating layer 34 having an opening, and are connected to the second source electrode 21 through the opening of the interlayer insulating layer 34. The second source electrode 21 is provided in the opening and is connected to the second source region 24 and the second body region 28. The interlayer insulating layer 34 and the second source electrode 21 are covered with the passivation layer 35 having an opening. 【0048】 The interlayer insulating layer 34 may be formed of silicon oxide (SiO ２ ) as a non-limiting example. 【0049】 The passivation layer 35 may be formed of polyimide as a non-limiting example. 【0050】Therefore, the multiple first source pads 111 and the multiple second source pads 121 each refer to regions where the first source electrode 11 and the second source electrode 21 are partially exposed on the surface of the semiconductor device 1 through the openings in the passivation layer 35, i.e., terminal portions. Similarly, the first gate pad 119 and the second gate pad 129 each refer to regions where the first gate electrode 19 and the second gate electrode 29 are partially exposed on the surface of the semiconductor device 1 through the openings in the passivation layer 35, i.e., terminal portions. 【0051】 In the semiconductor device 1, for example, the first conductivity type may be N-type and the second conductivity type may be P-type, and the first source region 14, the second source region 24, the semiconductor substrate 32, and the low-concentration impurity layer 33 may be N-type semiconductors, while the first body region 18 and the second body region 28 may be P-type semiconductors. 【0052】 Furthermore, in the semiconductor device 1, for example, the first conductivity type may be P-type and the second conductivity type may be N-type, and the first source region 14, the second source region 24, the semiconductor substrate 32, and the low-concentration impurity layer 33 may be P-type semiconductors, while the first body region 18 and the second body region 28 may be N-type semiconductors. 【0053】 Furthermore, the semiconductor device 1 is equipped with a drain wiring 140. The arrangement of electrodes including this drain wiring 140 will be explained with reference to Figure 4. 【0054】Figure 4 is a plan view showing an example of the arrangement of electrodes in a semiconductor device 1 according to this embodiment. More specifically, Figure 4 is a plan view showing a typical example of the shape in plan view of the components of the semiconductor device 1, namely the first source electrode 11, the first gate electrode 19, the first gate wiring 114, the second source electrode 21, the second gate electrode 29, the second gate wiring 124, and the drain wiring 140. In Figure 4, the interlayer insulating layer 34 and the passivation layer 35 of the semiconductor device 1 are omitted to show them as transparent. Also in Figure 4, the first source pad 111, the first gate pad 119, the second source pad 121, and the second gate pad 129 are indicated by dashed lines at their corresponding positions. In Figure 4, the drain wiring 140 is marked with a dot. 【0055】 The first gate electrode 19 may be made of a metal including, but not limited to, one or more of aluminum, copper, gold, and silver. 【0056】 A first gate wiring 114 of the transistor 10 is formed in the first region A1. The first gate wiring 114 is connected to the first gate electrode 19. In a plan view, the first gate wiring 114 is formed to surround the first source electrode 11. That is, the first gate wiring 114 is located outside the first source electrode 11 in the first region A1, i.e., on the long sides 91, 92, 93, and 94, which are the edges of the semiconductor layer 40, and has a frame shape. Also in a plan view, the first gate electrode 19 is located inside the frame-shaped first gate wiring 114. 【0057】 The first gate wiring 114 is composed of two layers: a first gate wiring metal 1141 and a first gate wiring conductor 1142, both formed above the semiconductor layer 40 (more specifically, the low-concentration impurity layer 33). The first gate wiring metal 1141 and the first gate wiring conductor 1142 each have a layered shape. The first gate wiring metal 1141 has a film-like portion on the positive z-axis side and a projection that protrudes from the film-like portion on the negative z-axis side and contacts the first gate wiring conductor 1142. 【0058】As shown in Figure 1, the first gate wiring 114 is provided above the low-concentration impurity layer 33 without being in contact with it. The protruding portions of the first gate wiring conductor 1142 and the first gate wiring metal 1141 of the first gate wiring 114 are embedded inside the interlayer insulating layer 34, and the film-like portion of the first gate wiring metal 1141 of the first gate wiring 114 is provided above the interlayer insulating layer 34 and is covered by the passivation layer 35. 【0059】 The width of the first gate wiring 114 is the length in the direction perpendicular to the direction in which the first gate wiring 114 extends. For example, in a cross-sectional view parallel to the zx plane as shown in Figure 1, it is the length of the first gate wiring 114 in the x-axis direction. 【0060】 In the first gate wiring 114, the width of the first gate wiring conductor 1142 is greater than the width of the first gate wiring metal 1141. More specifically, the width of the first gate wiring conductor 1142 is greater than the width of the film-like portion of the first gate wiring metal 1141. 【0061】 The first gate wiring metal 1141 is made of a metal, and may be made of a metal containing one or more of the following, not limited to aluminum, copper, gold, and silver. The first gate wiring metal 1141 according to this embodiment is made of a metal containing copper and mainly composed of aluminum. 【0062】 The first gate wiring conductor 1142 is made of a non-metallic conductor, in some but not limited examples, and more specifically, of polysilicon. 【0063】 The second gate electrode 29 may be made of a metal including, but not limited to, one or more of aluminum, copper, gold, and silver. 【0064】The second gate wiring 124 of the transistor 20 is formed in the second region A2. The second gate wiring 124 is connected to the second gate electrode 29. In a plan view, the second gate wiring 124 is formed to surround the second source electrode 21. In other words, the second gate wiring 124 is located outside the second source electrode 21 in the second region A2, that is, on the long sides 91, 92, 93, and 94, which are the edges of the semiconductor layer 40, and has a frame shape. Also in a plan view, the second gate electrode 29 is located inside the frame-shaped second gate wiring 124. 【0065】 The second gate wiring 124 is composed of two layers: a second gate wiring metal 1241 and a second gate wiring conductor 1242, both formed above the semiconductor layer 40 (more specifically, the low-concentration impurity layer 33). The second gate wiring metal 1241 and the second gate wiring conductor 1242 each have a layered shape. The second gate wiring metal 1241 has a film-like portion on the positive z-axis side and a projection that protrudes from the film-like portion on the negative z-axis side and contacts the second gate wiring conductor 1242. 【0066】 As shown in Figure 1, the second gate wiring 124 is provided above the low-concentration impurity layer 33 without being in contact with it. The protruding portions of the second gate wiring conductor 1242 and the second gate wiring metal 1241 of the second gate wiring 124 are embedded inside the interlayer insulating layer 34, and the film-like portion of the second gate wiring metal 1241 of the second gate wiring 124 is provided above the interlayer insulating layer 34 and is covered by the passivation layer 35. 【0067】 The width of the second gate wiring 124 is the length in the direction perpendicular to the direction in which the second gate wiring 124 extends. For example, in a cross-sectional view parallel to the zx plane as shown in Figure 1, it is the length of the second gate wiring 124 in the x-axis direction. 【0068】 In the second gate wiring 124, the width of the second gate wiring conductor 1242 is greater than the width of the second gate wiring metal 1241. More specifically, the width of the second gate wiring conductor 1242 is greater than the width of the film-like portion of the second gate wiring metal 1241. 【0069】 The second gate wiring metal 1241 is made of a metal, and may be made of a metal containing one or more of the following, not limited to aluminum, copper, gold, and silver. In this embodiment, the second gate wiring metal 1241 is made of a metal containing copper and mainly composed of aluminum. 【0070】 The second gate wiring conductor 1242 is made of a non-metallic conductor, in some but not limited examples, and more specifically, of polysilicon. 【0071】 The first active region 100 refers to the smallest region that encompasses all the areas where a conduction channel is formed when a voltage above a threshold is applied to the first gate electrode 19 (first gate conductor 15) of the transistor 10. The areas where a conduction channel is formed are the areas where each of the multiple first gate trenches 17 is adjacent to the first source region 14. The first active region 100 is contained within the first body region 18. 【0072】 The second active region 200 refers to the smallest region that encompasses all areas where a conduction channel is formed when a voltage above a threshold is applied to the second gate electrode 29 (second gate conductor 25) of the transistor 20. The areas where a conduction channel is formed are the areas where each of the multiple second gate trenches 27 is adjacent to the second source region 24. The second active region 200 is contained within the second body region 28. 【0073】 A PN junction exists at the contact surface between the first body region 18 and the low-concentration impurity layer 33, functioning as a body diode. A PN junction also exists at the contact surface between the second body region 28 and the low-concentration impurity layer 33, functioning as a body diode. These body diodes are hypothetically represented in Figure 1. 【0074】Figure 5 is a circuit diagram showing an example of a semiconductor device 1 according to this embodiment. In Figure 5, the first gate pad G1, the first source pad S1, the second gate pad G2, and the second source pad S2 are shown in the circuit diagram. The first gate pad G1 and the first source pad S1 correspond to the first gate pad 119 and the first source pad 111 in Figure 2 and so on. The second gate pad G2 and the second source pad S2 correspond to the second gate pad 129 and the second source pad 121 in Figure 2 and so on. 【0075】 Furthermore, the first gate wiring 114 and the second gate wiring 124 are formed with the boundary 90C between the first region A1 and the second region A2 in between. In other words, the boundary 90C is located between the first gate wiring 114 and the second gate wiring 124. It can also be said that the first gate wiring 114 and the second gate wiring 124 are formed facing each other with the boundary 90C in between. Note that the statement that the first gate wiring 114 and the second gate wiring 124 face each other means that, among the portions of the first gate wiring 114 and the second gate wiring 124 formed with the boundary 90C in between, when the semiconductor device 1 is folded along the center line 90, the first gate wiring 114 and the second gate wiring 124 overlap in at least a portion of the area. 【0076】 The drain wiring 140 is a component connected to the common drain region. The drain wiring 140 is not connected to the first gate electrode 19 and the second gate electrode 29, nor to the first source electrode 11 and the second source electrode 21, and is formed to be at the same potential as the common drain region. 【0077】The drain wiring 140 is formed on the outer periphery of the semiconductor layer 40, that is, it is located near the edges of the semiconductor layer 40, namely the long sides 91, 92, short sides 93, and short sides 94. In this embodiment, the drain wiring 140 is located closer to the edge of the semiconductor layer 40 than the first gate wiring 114 and the second gate wiring 124. In other words, the drain wiring 140 is located on the outermost periphery of the semiconductor layer 40, surrounding both the first gate wiring 114 and the second gate wiring 124. The drain wiring 140 is formed spanning the first region A1 and the second region A2. 【0078】 In this embodiment, the semiconductor layer 40 has a rectangular shape. Therefore, the drain wiring 140 also has a rectangular frame shape, and no branches or the like are provided in this frame shape. In other words, the drain wiring 140 is not formed between the first gate wiring 114 and the second gate wiring 124. 【0079】 Figure 6 is a cross-sectional view showing an example of the structure of the semiconductor device 1 according to this embodiment. Figure 6 shows a cross-section along VI-VI in Figure 2. The drain wiring 140 is formed above the semiconductor layer 40. The drain wiring 140 is composed of two layers: a drain wiring metal 141 and a drain wiring conductor 142. The drain wiring metal 141 and the drain wiring conductor 142 each have a layered shape. The drain wiring metal 141 has a film-like portion on the positive z-axis side and a projection that protrudes from the film-like portion on the negative z-axis side and contacts the drain wiring conductor 142. 【0080】 As shown in Figure 6, the drain wiring 140 is provided above the low-concentration impurity layer 33 without being in contact with it. The protruding portions of the drain wiring conductor 142 and the drain wiring metal 141 of the drain wiring 140 are embedded inside the interlayer insulating layer 34, and the film-like portion of the drain wiring metal 141 of the drain wiring 140 is provided above the interlayer insulating layer 34 and is covered by the passivation layer 35. 【0081】The width of the drain wiring 140 is the length in the direction perpendicular to the direction in which the drain wiring 140 extends. For example, in a cross-sectional view parallel to the zx plane as shown in Figure 6, it is the length of the drain wiring 140 in the x-axis direction. 【0082】 In the drain wiring 140, the width of the drain wiring metal 141 (more specifically, the width of the film-like portion of the drain wiring metal 141) and the width of the drain wiring conductor 142 are the same, but are not limited to this. 【0083】 The drain wiring metal 141 is made of a metal, and may be made of a metal containing one or more of the following, not limited to aluminum, copper, gold, and silver. In this embodiment, the drain wiring metal 141 is made of a metal containing copper and mainly composed of aluminum. 【0084】 The drain wiring conductor 142 is made of a non-metallic conductor, as is not limited to this example, and more specifically, of polysilicon. 【0085】 The drain wiring 140 functions as an EQR (EQUI Potential Ring). The drain wiring 140, being an EQR, is installed with the expectation that it will suppress the occurrence of leakage current in transistors 10 and 20. 【0086】 This function will be explained using Comparative Example 1 and Comparative Example 2. First, the semiconductor device 1y according to Comparative Example 1 and the semiconductor device 1z according to Comparative Example 2 will be described. 【0087】 The semiconductor device 1y according to Comparative Example 1 has the same configuration as the semiconductor device 1 according to this embodiment, except that it does not have a drain wiring 140. 【0088】 The semiconductor device 1z according to Comparative Example 2 has the same configuration as the semiconductor device 1 according to this embodiment, except that it is equipped with a first drain wiring 113 and a second drain wiring 123 instead of the drain wiring 140. 【0089】Figure 7 is a plan view showing an example of the arrangement of pads in a semiconductor device 1z according to Comparative Example 2. Figure 8 is a plan view showing an example of the arrangement of electrodes in a semiconductor device 1z according to Comparative Example 2. As with Figure 4, Figure 8 is a plan view showing a typical example of the shape in plan view of the components of the semiconductor device 1z, specifically the first source electrode 11, the first gate electrode 19, the first gate wiring 114, the second source electrode 21, the second gate electrode 29, the second gate wiring 124, the first drain wiring 113, and the second drain wiring 123. In Figure 8, the interlayer insulating layer 34 and the passivation layer 35 of the semiconductor device 1z are omitted to show them as transparent. Also in Figure 8, the first source pad 111, the first gate pad 119, the second source pad 121, and the second gate pad 129 are indicated by dashed lines at their corresponding positions. Furthermore, in Figure 8, the first drain wiring 113 and the second drain wiring 123 are marked with dots. 【0090】 The first drain wiring 113 is an electrode located in the first region A1. The first drain wiring 113 is located in the first region A1, on the outer periphery of the semiconductor layer 40, closer to the edges of the semiconductor layer 40, namely the long sides 91, 92, 93, and 94, than the first gate wiring 114. In other words, the first drain wiring 113 is located on the outermost periphery of the first region A1. 【0091】 The second drain wiring 123 is an electrode located in the second region A2. The second drain wiring 123 is located in the second region A2, on the outer periphery of the semiconductor layer 40, closer to the edges of the semiconductor layer 40, namely the long sides 91, 92, 93, and 94, than the second gate wiring 124. In other words, the second drain wiring 123 is located on the outermost periphery of the second region A2. 【0092】The first drain wiring 113 is not connected to the first gate electrode 19 and the second gate electrode 29, nor to the first source electrode 11 and the second source electrode 21. The second drain wiring 123 is not connected to the first gate electrode 19 and the second gate electrode 29, nor to the first source electrode 11 and the second source electrode 21. The first drain wiring 113 and the second drain wiring 123 are formed to be at the same potential as the common drain region. 【0093】 At the boundary 90C between the first region A1 and the second region A2, the first drain wiring 113 and the second drain wiring 123 are common. At this boundary 90C, the common first drain wiring 113 and the second drain wiring 123 may be referred to as the common drain wiring 130. The common drain wiring 130 is formed between the first gate wiring 114 and the second gate wiring 124. 【0094】 Next, the functions of the first drain wiring 113, the second drain wiring 123, and the common drain wiring 130 will be explained. 【0095】 In typical vertical MOS transistors, a BT test (Bias-Temperature Test) is performed as a reliability test. This BT test involves applying a reverse voltage up to the guaranteed upper limit to the body diode for an extended period of time under high-temperature conditions, and confirming whether or not any abnormalities occur in the electrical characteristics due to the application of this reverse voltage. 【0096】 Figure 9 is a cross-sectional view showing an example of the structure of semiconductor device 1y according to Comparative Example 1 before BT testing. Figure 10 is a cross-sectional view showing an example of the structure of semiconductor device 1y according to Comparative Example 1 during BT testing. Figure 11 is a cross-sectional view showing an example of the structure of semiconductor device 1z according to Comparative Example 2 before BT testing. Figure 12 is a cross-sectional view showing an example of the structure of semiconductor device 1z according to Comparative Example 2 during BT testing. Figures 11 and 12 show the cross-section along XI-XI in Figure 7. Figures 9 and 10 also show cross-sectional views of semiconductor device 1y at positions corresponding to the cross-sectional views shown in Figures 11 and 12. 【0097】In Figures 10 and 12, the first gate pad G1, the first source pad S1, the drain pad D connected to the semiconductor substrate 32 which is a common drain region, and the body diode are hypothetically depicted. Note that the semiconductor device 1 according to this embodiment does not have a drain pad D. The drain pad D shown in Figures 10 and 12 corresponds to the second source pad S2 of the transistor 20, but since including the transistor 20 in the illustration would be complicated, it is described as the drain pad D for the sake of simplicity in the drawings. Also, in the BT test, as an example, 0V is applied to the first gate pad G1, 0V to the first source pad S1, and 23V to the drain pad D. Note that the voltage value applied to the drain pad D can be any voltage value within the guaranteed upper limit, for example, 23V as described above. 【0098】 First, we will explain the changes in semiconductor device 1y according to Comparative Example 1 as determined by the BT test. 【0099】 As shown in Figure 10, during the BT test, mobile ions in the interlayer insulating layer 34 move to the vicinity of the interface between the interlayer insulating layer 34 and the low-concentration impurity layer 33. The mobile ions are, for example, negative ions, and move to the vicinity of the interface between the interlayer insulating layer 34 and the low-concentration impurity layer 33 due to the influence of the electric field generated by the BT test. As a result, an inversion layer 331y is formed in the low-concentration impurity layer 33 near the interface between the interlayer insulating layer 34 and the low-concentration impurity layer 33. This inversion layer 331y is formed when ions with the same charge as the mobile ions in the interlayer insulating layer 34 move away from the vicinity of the interface between the interlayer insulating layer 34 and the low-concentration impurity layer 33, making that portion relatively positive. This inversion layer 331y connects to the first body region 18 and becomes a leak path. 【0100】 Next, we will explain the changes in semiconductor device 1z according to Comparative Example 2 as determined by the BT test. 【0101】Similar to Comparative Example 1, in Comparative Example 2, as shown in Figure 12, the inversion layers 331z and 332z are formed. However, in Comparative Example 2, the first drain wiring 113 is formed. Since 23V is applied to this first drain wiring 113, the inversion layers 331z and 332z are unlikely to form directly below the first drain wiring 113 (negative z-axis side). In other words, since the inversion layers 331z and 332z are not connected and are interrupted, they are unlikely to form a leak path. 【0102】 Figure 13 shows the electrical characteristics of semiconductor device 1y according to Comparative Example 1 and semiconductor device 1z according to Comparative Example 2 after BT testing. In Figure 13, the horizontal axis, VDSS, represents the drain-source voltage, and the vertical axis, IDSS, represents the drain-source current. 【0103】 After the BT test, semiconductor device 1y showed a waveform in which the IDSS increased significantly beyond the normal range associated with the increase in VDSS, compared to semiconductor device 1z. As described above, this is because a leak path occurred in semiconductor device 1y, and the BT test caused an abnormality in the electrical characteristics of semiconductor device 1y. On the other hand, in semiconductor device 1z, the increase in IDSS was within the normal range associated with the increase in VDSS, and no waveform indicating leakage appeared. This is because the semiconductor device 1z in Comparative Example 2 is equipped with a first drain wiring 113, a second drain wiring 123, and a common drain wiring 130, which suppressed the occurrence of a leak path. In other words, the abnormality in electrical characteristics caused by the BT test was suppressed in semiconductor device 1z. 【0104】 Since the semiconductor device 1 according to this embodiment is equipped with drain wiring 140, the occurrence of leak paths is suppressed, and the increase in IDSS leakage can be suppressed, similar to the semiconductor device 1z in Comparative Example 2. Here, the behavior of the semiconductor device 1 during BT testing near boundary 90C will be explained using Figure 14. 【0105】Figure 14 is a cross-sectional view showing an example of the structure of the semiconductor device 1 according to this embodiment during a BT test for transistor 10. Figure 15 is a cross-sectional view showing an example of the structure of the semiconductor device 1 according to this embodiment during a BT test for transistor 20. Figures 14 and 15, like Figure 1, show a cross-section along line I-I in Figure 2. 【0106】 In Figures 14 and 15, the first gate pad G1, the first source pad S1, the second gate pad G2, the second source pad S2, and the body diode are hypothetically represented. 【0107】 Furthermore, in the BT test for transistor 10, as an example, 0V is applied to the first gate pad G1 and the first source pad S1, and 23V is applied to the second gate pad G2 and the second source pad S2. In the BT test for transistor 20, as an example, 23V is applied to the first gate pad G1 and the first source pad S1, and 0V is applied to the second gate pad G2 and the second source pad S2. 【0108】 Here, we focus on the region between the first body region 18 and the second body region 28, that is, the area near the boundary 90C. In the semiconductor device 1, the mobile ions in the interlayer insulating layer 34 move to the vicinity of the interface between the interlayer insulating layer 34 and the low-concentration impurity layer 33, and an inversion layer 331 is formed in the low-concentration impurity layer 33 near the interface between the interlayer insulating layer 34 and the low-concentration impurity layer 33. 【0109】 However, in the BT test for transistor 10, the voltage applied to the second gate wiring 124 makes it difficult for the inversion layer 331 to form directly beneath the second gate wiring 124 (negative z-axis side). In other words, in this BT test, the second gate wiring 124 performs the same function as the first drain wiring 113 in Comparative Example 2 described in Figure 12. For this reason, a leak path is unlikely to form between the first body region 18 and the second body region 28. 【0110】Similarly, in the BT test for transistor 20, the voltage applied to the first gate wiring 114 makes it difficult for the inversion layer 331 to form directly beneath the first gate wiring 114 (negative z-axis side). In other words, in this BT test, the first gate wiring 114 performs the same function as the second drain wiring 123 in Comparative Example 2 described in Figure 12. For this reason, a leak path is unlikely to form between the first body region 18 and the second body region 28. 【0111】 Thus, even when a BT test is performed on the semiconductor device 1 according to this embodiment, leakage paths are less likely to form. In other words, abnormalities in electrical characteristics due to the BT test are suppressed in the semiconductor device 1. 【0112】 Here, we compare the semiconductor device 1 according to this embodiment with the semiconductor device 1z according to Comparative Example 2. Figure 16 is a cross-sectional view showing an example of the structure of the semiconductor device 1z according to Comparative Example 2. Figure 16 shows the cross-section at XVI-XVI in Figure 7. 【0113】 As described above, in this embodiment, the drain wiring 140 is not formed between the first gate wiring 114 and the second gate wiring 124. On the other hand, in Comparative Example 2, the common drain wiring 130 is formed between the first gate wiring 114 and the second gate wiring 124. 【0114】 In the semiconductor device 1 according to this embodiment, between the first gate wiring 114 and the second gate wiring 124, the second gate wiring 124 functions as an EQR in the BT test for transistor 10, and the first gate wiring 114 functions as an EQR in the BT test for transistor 20. Therefore, a semiconductor device 1 that can suppress leakage current is realized even if a drain wiring 140 is not formed between the first gate wiring 114 and the second gate wiring 124. 【0115】Furthermore, in semiconductor device 1, compared to semiconductor device 1z according to comparative example 2, the absence of a common drain wiring 130 allows for larger first active region 100 and second active region 200. Thus, semiconductor device 1, with larger first active region 100 and second active region 200, can achieve reduced on-resistance. 【0116】 Based on the above, the semiconductor device 1 according to this embodiment can reduce on-resistance while suppressing leakage current. 【0117】 Next, the semiconductor device 1 according to this embodiment will be described again using Figures 1 and 6. 【0118】 First, we will explain the relationship between the minimum width Wd of the drain wiring 140 shown in Figure 6 and the minimum width W1 of the first gate wiring 114 or the minimum width W2 of the second gate wiring 124 shown in Figure 1. 【0119】 As described above, in the drain wiring 140, the width of the drain wiring metal 141 (more specifically, the width of the film-like portion of the drain wiring metal 141) and the width of the drain wiring conductor 142 are the same. Therefore, the minimum width Wd of the drain wiring 140 is the minimum width of the drain wiring metal 141 (the width of the film-like portion of the drain wiring metal 141) and the minimum width of the drain wiring conductor 142. 【0120】 In the case of drain wiring 140, if the width of the drain wiring metal 141 (the width of the film-like portion of the drain wiring metal 141) and the width of the drain wiring conductor 142 do not match, the minimum value of the width Wd of the drain wiring 140 corresponds to the smaller of the minimum value of the width of the drain wiring metal 141 (the width of the film-like portion of the drain wiring metal 141) and the minimum value of the width of the drain wiring conductor 142. 【0121】 In the first gate wiring 114, the width of the first gate wiring conductor 1142 is greater than the width of the first gate wiring metal 1141. Here, the minimum width W1 of the first gate wiring 114 corresponds to the minimum width of the first gate wiring metal 1141 (more specifically, the width of the film-like portion of the first gate wiring metal 1141). 【0122】 In the second gate wiring 124, the width of the second gate wiring conductor 1242 is greater than the width of the second gate wiring metal 1241. Here, the minimum width W2 of the second gate wiring 124 corresponds to the minimum width of the second gate wiring metal 1241 (more specifically, the width of the film-like portion of the second gate wiring metal 1241). 【0123】 In this embodiment, the minimum width Wd of the drain wiring 140 is narrower than the minimum width W1 of the first gate wiring 114 or the minimum width W2 of the second gate wiring 124. More specifically, the minimum width Wd of the drain wiring 140 is narrower than the smaller of the minimum width W1 of the first gate wiring 114 and the minimum width W2 of the second gate wiring 124. 【0124】 Furthermore, as shown in Figure 1, the nearest neighbor distance D1 is defined as the distance between the first gate wiring 114 and the second gate wiring 124, which are positioned across the boundary 90C between the first region A1 and the second region A2. The nearest neighbor distance D1 can also be described as the nearest neighbor distance between the first gate wiring 114 and the second gate wiring 124, which are opposite each other across the boundary 90C. Note that, as shown in Figure 1, the nearest neighbor distance D1 is the distance from the end of the first gate wiring 114 (the end on the positive x-axis side) to the end of the second gate wiring 124 (the end on the negative x-axis side). 【0125】 This nearest-neighbor distance D1 is smaller than the sum of the minimum width Wd of the drain wiring 140 and the nearest-neighbor distance D2 (see Figure 6) between the drain wiring 140 and the first gate wiring 114 or the second gate wiring 124. Note that nearest-neighbor distance D2 is the shorter of the nearest-neighbor distance between the drain wiring 140 and the first gate wiring 114 and the nearest-neighbor distance between the drain wiring 140 and the second gate wiring 124. Here, we will explain assuming that nearest-neighbor distance D2 is the nearest-neighbor distance between the drain wiring 140 and the first gate wiring 114. Note that nearest-neighbor distance D2 is the distance from the end of the drain wiring 140 (the end on the positive x-axis side) to the end of the first gate wiring 114 (the end on the negative x-axis side), as shown in Figure 6. 【0126】The width Wd, widths W1 and W2, and nearest neighbor distances D1 and D2 are related as described above. As a result, the first gate wiring 114 and the second gate wiring 124 are so close together that, for example, near the boundary 90C, there is not enough space between them for a drain wiring 140 to be provided. This proximity creates extra space within the semiconductor device 1, which can be used as the first active region 100 and the second active region 200. In other words, the first active region 100 and the second active region 200 can be made larger, and the on-resistance of the semiconductor device 1 can be reduced more significantly. 【0127】 Furthermore, as shown in Figure 1, in a plan view, the nearest neighbor distance D3 is defined as the distance between the first body region 18 and the second body region 28, which are positioned across the boundary 90C between the first region A1 and the second region A2. The nearest neighbor distance D3 can also be described as the distance between the first body region 18 and the second body region 28, which face each other across the boundary 90C. Note that, as shown in Figure 1, the nearest neighbor distance D3 is the distance from the end of the first body region 18 (the end on the positive x-axis side) to the end of the second body region 28 (the end on the negative x-axis side). 【0128】 The nearest neighbor distance D3 is greater than the nearest neighbor distance D4 between the first gate wiring conductor 1142 and the second gate wiring conductor 1242, which are positioned across the boundary 90C between the first region A1 and the second region A2. The nearest neighbor distance D4 can also be said to be the nearest neighbor distance between the first gate wiring conductor 1142 and the second gate wiring conductor 1242, which are facing each other across the boundary 90C. Note that the nearest neighbor distance D4 is the distance from the end of the first gate wiring conductor 1142 (the end on the positive x-axis side) to the end of the second gate wiring conductor 1242 (the end on the negative x-axis side), as shown in Figure 1. 【0129】 In this embodiment, in a plan view, the x-positive end of the first gate wiring 114 coincides with the x-positive end of the first gate wiring conductor 1142, and the x-negative end of the second gate wiring 124 coincides with the x-negative end of the second gate wiring conductor 1242. Therefore, the nearest neighbor distance D1 coincides with the nearest neighbor distance D4. 【0130】As described above, the nearest-nearest distance D3 is greater than the nearest-nearest distance D4. That is, there is sufficient distance between the first body region 18 and the second body region 28, and the first gate wiring 114 and the second gate wiring 124 are provided above them, so a leak path is unlikely to form between the first body region 18 and the second body region 28. 【0131】 Furthermore, in a plan view, the first gate wiring 114 overlaps with the termination portion of the first body region 18 of transistor 10, and the second gate wiring 124 overlaps with the termination portion of the second body region 28 of transistor 20. 【0132】 In Figure 1, the first gate wiring conductor 1142 of the first gate wiring 114 overlaps with the end portion of the first body region 18, and the second gate wiring conductor 1242 of the second gate wiring 124 overlaps with the end portion of the second body region 28. Region A3 in Figure 1 is the region where the first gate wiring conductor 1142 overlaps with the end portion (positive x-axis end) of the first body region 18. Region A4 in Figure 1 is the region where the second gate wiring conductor 1242 overlaps with the end portion (negative x-axis end) of the second body region 28. 【0133】Furthermore, Figure 6 shows that the first gate wiring conductor 1142 of the first gate wiring 114 formed near the edge (short side 93) of the semiconductor layer 40 also overlaps with the end portion of the first body region 18. That is, region A5 in Figure 6 is the region where the first gate wiring conductor 1142 overlaps with the end portion (negative x-axis end) of the first body region 18. Although not shown, the same applies to other edges of the semiconductor layer 40 other than the short side 93, as described in Figure 6 for the first gate wiring conductor 1142. That is, the second gate wiring conductor 1242 of the second gate wiring 124 formed near the edge (short side 94) of the semiconductor layer 40 also overlaps with the end portion (positive x-axis end) of the second body region 28. The first gate wiring conductor 1142 formed near the edge (long side 91) of the semiconductor layer 40 also overlaps with the end portion (positive y-axis end) of the first body region 18. The second gate wiring conductor 1242 formed near the edge (long side 91) of the semiconductor layer 40 also overlaps with the end portion (positive y-axis end) of the second body region 28. The first gate wiring conductor 1142 formed near the edge (long side 92) of the semiconductor layer 40 also overlaps with the end portion (negative y-axis end) of the first body region 18. The second gate wiring conductor 1242 formed near the edge (long side 92) of the semiconductor layer 40 also overlaps with the end portion (negative y-axis end) of the second body region 28. 【0134】 As a result, the connection between the first body region 18 and the second body region 28 by the inversion layer 331 generated by the BT test is further suppressed, thereby realizing a semiconductor device 1 that can further suppress leakage current. 【0135】 Furthermore, the drain wiring 140 will be explained using Figure 17. 【0136】 Figure 17 is a plan view showing an example of the arrangement of electrodes in the semiconductor device 1 according to this embodiment. As with Figure 4, Figure 17 omits the interlayer insulating layer 34 and the passivation layer 35 so that they appear transparent. Also, as with Figure 4, in Figure 17, the first source pad 111, the first gate pad 119, the second source pad 121, and the second gate pad 129 are indicated by dashed lines at their corresponding positions. 【0137】Furthermore, Figure 17 shows an enlarged view of a portion of the drain wiring 140 within the area enclosed by a dotted rectangular frame. For simplicity, the second gate wiring 124 and other components are omitted in this enlarged view. 【0138】 The drain wiring 140 according to this embodiment has, in a plan view, one rectangular frame-shaped frame section 150, four corner sections 160, and four contact sections 170. 【0139】 The framed portion 150 is the part indicated by the dark dots in Figure 17. The framed portion 150 corresponds to the film-like portion of the drain wiring metal 141. The width of the framed portion 150 corresponds to the width of the film-like portion of the drain wiring metal 141, and is the width Wd. Figure 17 also shows the four corners C1, C2, C3, and C4 of the rectangular framed portion 150. 【0140】 Each of the four corners 160 is located inside each of the four corners C1, C2, C3, and C4 of the frame line 150, and in the enlarged view of Figure 17, these are shown as faint dots. Each of the four corners 160 is connected to each of the four corners C1, C2, C3, and C4, that is, there is a one-to-one correspondence between one corner 160 and one corner. In the enlarged view of Figure 17, one corner 160 is connected to corner C4, and there is a one-to-one relationship between that corner 160 and corner C4. 【0141】 The shape of each of the four corners 160 may be, for example, a rectangle, but is not limited to this. One corner 160 shown in the enlarged view of Figure 17 is a quadrant with corner C4 of the frame line 150 as its vertex. Corner C4 is the corner corresponding to the inner edge of the frame line 150 and is virtually represented as a circle in the enlarged view of Figure 17. In the enlarged view of Figure 17, corner C4a, which is the corner corresponding to the outer edge of the frame line 150, is also virtually represented as a circle, and one corner 160 may be a quadrant with corner C4a as its vertex. 【0142】Each of the four contact portions 170 connects to a common drain region. Each of the four contact portions 170 extends in the negative z-axis direction and connects to the low-concentration impurity layer 33. Each of the four contact portions 170 is positioned to overlap with each of the four corner portions 160 in a plan view. In other words, there is a one-to-one relationship between one contact portion 170 and one corner portion 160, such that they overlap in a plan view. In this embodiment, one contact portion 170 overlaps with the frame portion 150 and one corner portion 160, and more specifically, is contained within the frame portion 150 and one corner portion 160. 【0143】 The shape of each of the four contact portions 170 is rectangular, but not limited to this. Furthermore, the size of each of the four contact portions 170 should be greater than the width Wd. In the enlarged view of Figure 17, the length L of one side of one rectangular contact portion 170 is shown, and this length L should be greater than the width Wd. The same applies to the other three contact portions 170 not shown in the enlarged view of Figure 17. 【0144】 As a result, the four corners of the semiconductor device 1, which are surplus areas, can be used to form a contact portion 170 that is larger than the width Wd of the frame portion 150. 【0145】 Furthermore, in the diagram of Figure 17 showing the entire semiconductor device 1, for simplicity, the four corners 160 and four contact portions 170 of the drain wiring 140 are omitted, and only one frame portion 150 is shown. 【0146】 The following describes five modified examples of the embodiment. The following explanation will focus on the differences from the embodiment, omitting or simplifying the explanation of commonalities. 【0147】[Modification 1] Figure 18 is a cross-sectional view showing an example of the structure of a semiconductor device 1a according to Modification 1 of this embodiment. Figure 19 is a cross-sectional view showing an example of the structure of a semiconductor device 1a according to Modification 1 of this embodiment. Note that Figure 18 shows a cross-sectional view of the semiconductor device 1a at a position corresponding to the cross-sectional view shown in Figure 1 described in the embodiment, and Figure 19 shows a cross-sectional view of the semiconductor device 1a at a position corresponding to the cross-sectional view shown in Figure 6 described in the embodiment. 【0148】 The semiconductor device 1a according to this modified example has the same configuration as the semiconductor device 1 according to the embodiment, except that it is equipped with a first gate wiring 114a and a second gate wiring 124a instead of the first gate wiring 114 and the second gate wiring 124. 【0149】 The first gate wiring 114a has the same configuration as the first gate wiring 114 according to the embodiment, except that it has a first gate wiring metal 1141a instead of the first gate wiring metal 1141. 【0150】 The first gate wiring metal 1141a is wider than the first gate wiring metal 1141. Here, the width of the first gate wiring metal 1141a (more specifically, the width of the film-like portion of the first gate wiring metal 1141a) is the same as the width of the first gate wiring conductor 1142. 【0151】 The second gate wiring 124a has the same configuration as the second gate wiring 124 according to the embodiment, except that it has a second gate wiring metal 1241a instead of the second gate wiring metal 1241. 【0152】 The second gate wiring metal 1241a is wider than the second gate wiring metal 1241. Here, the width of the second gate wiring metal 1241a (more specifically, the width of the film-like portion of the second gate wiring metal 1241a) is the same as the width of the second gate wiring conductor 1242. 【0153】In this embodiment, the first gate wiring conductor 1142 overlaps with the end portion of the first body region 18, and the second gate wiring conductor 1242 overlaps with the end portion of the second body region 28. In this modified example, the first gate wiring metal 1141a overlaps with the end portion of the first body region 18, and the second gate wiring metal 1241a overlaps with the end portion of the second body region 28. 【0154】 Region A3a in Figure 18 is the region where the first gate wiring metal 1141a overlaps with the end portion (positive x-axis end) of the first body region 18. Region A4a in Figure 18 is the region where the second gate wiring metal 1241a overlaps with the end portion (negative x-axis end) of the second body region 28. 【0155】 Furthermore, Figure 19 shows that the first gate wiring metal 1141a formed near the edge (short side 93) of the semiconductor layer 40 also overlaps with the end portion of the first body region 18. That is, region A5a in Figure 19 is the region where the first gate wiring metal 1141a overlaps with the end portion (negative x-axis end) of the first body region 18. Although not shown, the same applies to other edges of the semiconductor layer 40 other than the short side 93, as described in Figure 19 for the first gate wiring metal 1141a. That is, the second gate wiring metal 1241a formed near the edge (short side 94) of the semiconductor layer 40 also overlaps with the end portion (positive x-axis end) of the second body region 28. The first gate wiring metal 1141a formed near the edge (long side 91) of the semiconductor layer 40 also overlaps with the end portion (positive y-axis end) of the first body region 18. The second gate wiring metal 1241a formed near the edge (long side 91) of the semiconductor layer 40 also overlaps with the end portion (positive y-axis end) of the second body region 28. The first gate wiring metal 1141a formed near the edge (long side 92) of the semiconductor layer 40 also overlaps with the end portion (negative y-axis end) of the first body region 18. The second gate wiring metal 1241a formed near the edge (long side 92) of the semiconductor layer 40 also overlaps with the end portion (negative y-axis end) of the second body region 28. 【0156】As a result, particularly between the first gate wiring 114a and the second gate wiring 124a (spanning the boundary 90C), the connection between the first body region 18 and the second body region 28 by the inversion layer 331 generated by the BT test is further suppressed, thereby realizing a semiconductor device 1a that can suppress leakage current. 【0157】 [Modification 2] Figure 20 is a cross-sectional view showing an example of the structure of the semiconductor device 1b according to Modification 2 of this embodiment. Figure 20 shows a cross-sectional view of the semiconductor device 1b at a position corresponding to the cross-sectional view shown in Figure 6 described in the embodiment. 【0158】 The semiconductor device 1b according to this modified example has the same configuration as the semiconductor device 1 according to the embodiment, except that it is equipped with a drain wiring 140b instead of a drain wiring 140. 【0159】 The drain wiring 140b is formed above the semiconductor layer 40, and more specifically, in contact with the upper surface of the interlayer insulating layer 34. The drain wiring 140b is made of metal, and more specifically, it is made of a metal that contains copper and is mainly composed of aluminum. 【0160】 Furthermore, in this embodiment, the drain wiring 140 is composed of two layers: drain wiring metal 141 and drain wiring conductor 142, but it is not limited to this. In this modified example, the drain wiring 140b is composed of one layer. More specifically, the drain wiring 140b is composed of a film-like portion of the drain wiring metal 141. 【0161】 In this modified example, the drain wiring 140b may also have the frame portion 150, four corner portions 160, and four contact portions 170 as described in Figure 17, and it is preferable that the size of the contact portions 170 is greater than the width of the frame portion 150. 【0162】 [Modification 3] Figure 21 is a cross-sectional view showing an example of the structure of the semiconductor device 1c according to Modification 3 of this embodiment. Figure 21 shows a cross-sectional view of the semiconductor device 1c at a position corresponding to the cross-sectional view shown in Figure 6 described in the embodiment. 【0163】The semiconductor device 1c according to this modified example has the same configuration as the semiconductor device 1 according to the embodiment, except that it is equipped with a drain wiring 140c instead of a drain wiring 140. 【0164】 The drain wiring 140c is formed above the semiconductor layer 40, and more specifically, is embedded within the interlayer insulating layer 34. The drain wiring 140c is made of a non-metallic conductor, and more specifically, of polysilicon. 【0165】 In this modified example, the drain wiring 140c is composed of a single layer. More specifically, the drain wiring 140c is composed of the drain wiring conductor 142 described in the embodiment. 【0166】 In this modified example, the drain wiring 140c may also have the frame portion 150, four corner portions 160, and four contact portions 170 as described in Figure 17, and the size of the contact portions 170 may be larger than the width of the frame portion 150. In this case, the frame portion 150 corresponds to the drain wiring conductor 142. 【0167】 [Modification 4] Figure 22 is a cross-sectional view showing an example of the structure of a semiconductor device 1d according to Modification 4 of this embodiment. Figure 22 shows a cross-sectional view of the semiconductor device 1d at a position corresponding to the cross-sectional view shown in Figure 6 described in the embodiment. 【0168】 The semiconductor device 1d according to this modified example has the same configuration as the semiconductor device 1 according to the embodiment, except that it is equipped with a drain wiring 140d instead of a drain wiring 140. 【0169】 In this modified example, the drain wiring 140d is a conductor embedded in a trench provided in the semiconductor layer 40. The trench is formed to a depth from the upper surface of the semiconductor layer 40 to a portion of the semiconductor layer 40. More specifically, the trench is formed to a depth from the upper surface of the low-concentration impurity layer 33 of the semiconductor layer 40 to a portion of the low-concentration impurity layer 33, and is formed to a depth that does not reach the semiconductor substrate 32. The drain wiring 140d is provided inside the trench, covered by the interlayer insulating layer 34. 【0170】The drain wiring 140d may, as an example without limitation, be polysilicon containing impurities. 【0171】 [Modification 5] Figure 23 is a cross-sectional view showing an example of the structure of a semiconductor device 1e according to Modification 5 of this embodiment. Figure 23 shows a cross-sectional view of the semiconductor device 1e at a position corresponding to the cross-sectional view shown in Figure 6 described in the embodiment. 【0172】 The semiconductor device 1e according to this modified example has the same configuration as the semiconductor device 1 according to the embodiment, except for the following two points. First, the semiconductor device 1e is equipped with a drain wiring 140e, an interlayer insulating layer 34e, and a passivation layer 35e instead of the drain wiring 140, interlayer insulating layer 34, and passivation layer 35. Second, the positional relationship between the drain wiring 140e and the first gate wiring 114 or the second gate wiring 124 differs from that of the embodiment. 【0173】 The drain wiring 140e is formed above the semiconductor layer 40, and more specifically, in contact with the upper surface of the interlayer insulating layer 34e. The drain wiring 140e is made of metal, and more specifically, it is made of a metal containing copper and mainly composed of aluminum. 【0174】 The drain wiring 140e, like the drain wiring 140b in the modified example 2, is composed of a single layer and is made up of a film-like portion of the drain wiring metal 141. 【0175】 Since the drain wiring 140e has the above configuration, the thickness of the interlayer insulating layer 34e directly beneath the drain wiring 140e can be made thinner than the thickness of the interlayer insulating layer 34e directly beneath the first gate wiring 114, which is composed of two layers. The interlayer insulating layer 34e has the same configuration as the interlayer insulating layer 34, except that its thickness differs directly beneath the drain wiring 140e and directly beneath the first gate wiring 114. 【0176】Since the drain wiring 140e is formed in contact with the upper surface of the interlayer insulating layer 34e, the upper surface 140eT of the drain wiring 140e is at a lower height than the upper surface 114T of the first gate wiring 114 or the upper surface of the second gate wiring 124. The upper surface 114T of the first gate wiring 114 is the main surface on the positive z-axis side of the first gate wiring metal 1141. The upper surface of the second gate wiring 124 is the main surface on the positive z-axis side of the second gate wiring metal 1241. 【0177】 The upper surface 140eT should be positioned lower in height than at least one of the upper surfaces 114T of the first gate wiring 114 and the upper surface of the second gate wiring 124. In other words, the upper surface 140eT should be positioned on the negative side of the z-axis in the z-axis direction relative to at least one of the upper surfaces 114T of the first gate wiring 114 and the upper surface of the second gate wiring 124. 【0178】 In Figure 23, the upper surface 140eT is at a lower height than the upper surface 114T. However, the upper surface 140eT may also be at a higher height than the upper surface of the second gate wiring 124. 【0179】 For example, when the upper surface 33T of the low-concentration impurity layer 33 is used as a reference, the height H1 from the upper surface 33T to the upper surface 140eT is lower than the height H2 from the upper surface 33T to the upper surface 114T. 【0180】 The passivation layer 35e covers the drain wiring 140e and the first gate wiring 114 (more specifically, the first gate wiring metal 1141) which are in this positional relationship. Since the upper surface 140eT is lower in height than the upper surface 114T, the height of the passivation layer 35e decreases from the center towards the edges of the semiconductor device 1e (towards the negative x-axis direction in Figure 23). That is, the position of the upper surface of the passivation layer 35e above the drain wiring 140e is located on the negative z-axis side than the position of the upper surface of the passivation layer 35e above the first gate wiring 114. For example, the height of the passivation layer 35e may decrease gradually from the center towards the edges of the semiconductor device 1e, or it may decrease in a stepped manner as shown in Figure 23. 【0181】In this way, the height of the passivation layer 35e decreases from the center to the edges of the semiconductor device 1e, making it easier for the passivation layer 35e to cover the layers located below it. In other words, the coverage rate by the passivation layer 35e is improved, and peeling of the passivation layer 35e is suppressed. That is, a semiconductor device 1e with long-term reliability is realized. 【0182】 [Effects, etc.] The semiconductor device 1 according to this embodiment includes a semiconductor substrate 32 on the back side, a semiconductor layer 40 on the front side which includes a first region A1 and a second region A2 adjacent to the first region A1 in a plan view of the semiconductor substrate 32, and whose area is divided into two equal parts by the first region A1 and the second region A2 in a plan view, a first vertical MOS transistor 10 formed in the first region A1 of the semiconductor layer 40, a second vertical MOS transistor 20 formed in the second region A2 of the semiconductor layer 40, and a metal layer 30 formed in contact with the back side of the semiconductor layer 40. The semiconductor substrate 32 is the common drain region of the first vertical MOS transistor 10 and the second vertical MOS transistor 20. In a plan view, the first region A1 has the first source electrode 11 of the first vertical MOS transistor 10 and the first gate electrode 19 of the first vertical MOS transistor 10 connected to the first gate wiring 114 surrounding the first source electrode 11, and the second region A2 has the second source electrode 21 of the second vertical MOS transistor 20 and the second gate electrode 29 of the second vertical MOS transistor 20 connected to the second gate wiring 114 surrounding the second source electrode 21. A gate wiring 124 is formed between the first gate wiring 114 and the second gate wiring 124, with the boundary 90C between the first region A1 and the second region A2 in between. A drain wiring 140 connected to a common drain region is formed on the outer periphery of the semiconductor layer 40. The drain wiring 140 surrounds the first gate wiring 114 and the second gate wiring 124, and no drain wiring 140 is formed between the first gate wiring 114 and the second gate wiring 124. 【0183】As a result, as explained in Figures 14 and 15, the first gate wiring 114 and the second gate wiring 124 function as EQRs, thereby realizing a semiconductor device 1 that can suppress leakage current. Furthermore, in the semiconductor device 1, a drain wiring 140 is not formed between the first gate wiring 114 and the second gate wiring 124. For this reason, compared to the semiconductor device 1z according to Comparative Example 2, for example, the first active region 100 and the second active region 200 can be made larger in the semiconductor device 1 because a common drain wiring 130 is not provided. In this way, the semiconductor device 1 with larger first active regions 100 and second active regions 200 can achieve reduced on-resistance. Thus, the semiconductor device 1 according to this embodiment can achieve reduced on-resistance while suppressing leakage current. 【0184】 In this embodiment, in a plan view, the minimum width Wd of the drain wiring 140 is narrower than the minimum width W1 of the first gate wiring 114 or the minimum width W2 of the second gate wiring 124, and the nearest neighbor distance D1 between the first gate wiring 114 and the second gate wiring 124, which are arranged across the boundary 90C between the first region A1 and the second region A2, is smaller than the sum of the minimum width Wd of the drain wiring 140 and the nearest neighbor distance D2 between the drain wiring 140 and the first gate wiring 114 or the second gate wiring 124. 【0185】 As a result, for example, near boundary 90C, the first gate wiring 114 and the second gate wiring 124 are in close proximity. This proximity creates extra space within the semiconductor device 1, which can be used as the first active region 100 and the second active region 200. In other words, the first active region 100 and the second active region 200 can be made larger, so the on-resistance of the semiconductor device 1 can be reduced more significantly. 【0186】 In this embodiment, in a plan view, the first gate wiring 114 overlaps with the termination portion of the first body region 18 of the first vertical MOS transistor 10, and the second gate wiring 124 overlaps with the termination portion of the second body region 28 of the second vertical MOS transistor 20. 【0187】 As a result, particularly between the first gate wiring 114 and the second gate wiring 124 (spanning the boundary 90C), the connection between, for example, the first body region 18 and the second body region 28 by the inversion layer 331 generated by the BT test is further suppressed, thereby realizing a semiconductor device 1 that can further suppress leakage current. 【0188】 In this embodiment, the first gate wiring 114 is composed of two layers: a first gate wiring metal 1141 and a first gate wiring conductor 1142 formed above the semiconductor layer 40. The second gate wiring 124 is composed of two layers: a second gate wiring metal 1241 and a second gate wiring conductor 1242 formed above the semiconductor layer 40. In a plan view, the first gate wiring conductor 1142 overlaps with the termination portion of the first body region 18 of the first vertical MOS transistor 10, and the second gate wiring conductor 1242 overlaps with the termination portion of the second body region 28 of the second vertical MOS transistor 20. 【0189】 As a result, the connection between, for example, the first body region 18 and the second body region 28 by the inversion layer 331 generated by the BT test is further suppressed, thereby realizing a semiconductor device 1 that can further suppress leakage current. 【0190】 In modified example 1, the first gate wiring 114a is composed of two layers: a first gate wiring metal 1141a and a first gate wiring conductor 1142 formed above the semiconductor layer 40. The second gate wiring 124a is composed of two layers: a second gate wiring metal 1241a and a second gate wiring conductor 1242 formed above the semiconductor layer 40. In a plan view, the first gate wiring metal 1141a overlaps with the termination portion of the first body region 18 of the first vertical MOS transistor 10, and the second gate wiring metal 1241a overlaps with the termination portion of the second body region 28 of the second vertical MOS transistor 20. 【0191】 As a result, the connection between, for example, the first body region 18 and the second body region 28 by the inversion layer 331 generated by the BT test is further suppressed, thereby realizing a semiconductor device 1a that can further suppress leakage current. 【0192】 In this embodiment, in a plan view, the nearest neighbor distance D3 between the first body region 18 and the second body region 28, which are arranged across the boundary 90C between the first region A1 and the second region A2, is greater than the nearest neighbor distance D4 between the first gate wiring conductor 1142 and the second gate wiring conductor 1242, which are arranged across the boundary 90C between the first region A1 and the second region A2. 【0193】 As a result, the first body region 18 and the second body region 28 are sufficiently separated, and the first gate wiring 114 and the second gate wiring 124 are provided above them, making it difficult for a leakage path to form between the first body region 18 and the second body region 28. In other words, the semiconductor device 1 according to this embodiment can further suppress leakage current. 【0194】 In the modified example 2, the drain wiring 140b is formed above the semiconductor layer 40 and is made of metal. 【0195】 This makes it possible to realize a drain wiring 140b made of metal. 【0196】 In the third modified example, the drain wiring 140c is formed above the semiconductor layer 40 and is made of a non-metallic conductor. 【0197】 This makes it possible to realize drain wiring 140c composed of non-metallic conductors. 【0198】 In modified example 4, the drain wiring 140d is a conductor embedded inside a trench formed to a depth from the upper surface of the semiconductor layer 40 to a part of the semiconductor layer 40. 【0199】 This makes it possible to implement drain wiring 140d embedded inside the trench. 【0200】In this embodiment, the drain wiring 140, in plan view, has a rectangular frame-shaped frame section 150, corner sections 160 located inside each of the four corners C1, C2, C3, and C4 of the frame section 150, and contact sections 170, each of which overlaps with each of the four corner sections 160 and connects to a common drain area. The size of each of the four contact sections 170 is greater than the width Wd of the frame section 150. 【0201】 As a result, the four corners of the semiconductor device 1, which are surplus areas, can be used to form a contact portion 170 that is larger than the width Wd of the frame portion 150. 【0202】 In this embodiment, the shape of each of the four corners 160 is a quadrant shape with the corners of the frame line portion 150 (for example, corners C1, C2, C3, and C4) as its vertices. In plan view, the shape of each of the four contact portions 170 is rectangular. In each of the four contact portions 170, the length of one side of the rectangle is greater than the width Wd of the frame line portion 150. 【0203】 This allows the four corners of the semiconductor device 1, which are otherwise unused areas, to be utilized more effectively, and the contact portion 170 to connect more reliably to the common drain area. 【0204】 In the modified example 2, the drain wiring 140b is composed of a single layer. 【0205】 This makes it possible to realize a drain wiring 140b consisting of a single layer. 【0206】 In modified example 5, the upper surface 140eT of the drain wiring 140e is at a lower height than the upper surface 114T of the first gate wiring 114 or the upper surface of the second gate wiring 124. 【0207】 As a result, the passivation layer 35e can more easily cover the layer located below it. In other words, the coverage rate by the passivation layer 35e is improved, and peeling of the passivation layer 35e is suppressed. This results in a semiconductor device 1e with long-term reliability. 【0208】(Other Embodiments) Although a semiconductor device according to one aspect of the present disclosure has been described above based on embodiments and various modifications, the present disclosure is not limited to these embodiments and various modifications. As long as they do not depart from the spirit of the present disclosure, various modifications that a person skilled in the art can conceive of may also be included within the scope of one or more aspects of the present disclosure. 【0209】 In this embodiment, the statement that the drain wiring 140 surrounds the first gate wiring 114 and the second gate wiring 124 includes cases where the drain wiring 140 surrounds them without any divisions, i.e., a complete frame, and cases where the drain wiring 140 is divided over a predetermined distance. The drain wiring 140 only needs to be provided in portions adjacent to the first gate wiring 114 and the second gate wiring 124 in a plan view, without including other components. When the drain wiring 140 is divided, the number of division points is not particularly limited, but may be, for example, one or multiple points. The points where the drain wiring 140 is divided are not particularly limited, but may be, for example, points where the boundary 90C and the drain wiring 140 intersect in a plan view (two points). 【0210】 This disclosure is widely applicable to semiconductor devices and the like that are mounted on a substrate. 【0211】1, 1a, 1b, 1c, 1d, 1e, 1y, 1z Semiconductor device 10 Transistor (first vertical MOS transistor) 11 First source electrode 14 First source region 15 First gate conductor 16 First gate oxide 17 First gate trench 18 First body region 19 First gate electrode 20 Transistor (second vertical MOS transistor) 21 Second source electrode 24 Second source region 25 Second gate conductor 26 Second gate oxide 27 Second gate trench 28 Second body region 29 Second gate electrode 30 Metal layer 32 Semiconductor substrate 33 Low-concentration impurity layer 33T, 114T, 140eT Top surface 34, 34e Interlayer insulating layer 35, 35e Passivation layer 40 Semiconductor layer 90 Center line 90C Boundary 91, 92 Long side 93, 94 Short side 100 First active region 111, S1 First source pad 113 First drain wiring 114, 114a First gate wiring 119, G1 First gate pad 121, S2 Second source pad 123 Second drain wiring 124, 124a Second gate wiring 129, G2 Second gate pad 130 Common drain wiring 140, 140b, 140c, 140d, 140e Drain wiring 141 Drain wiring metal 142 Drain wiring conductor 150 Frame section 160 Corner section 170 Contact section 200 Second active region 331, 331y, 331z, 332z Inversion layer 1141, 1141a First gate wiring metal 1142 First gate wiring conductor 1241, 1241a Second gate wiring metal 1242 Second gate wiring conductor A1 First region A2 Second region A3, A3a, A4, A4a, A5, A5a Region C1, C2, C3, C4, C4a Corner D Drain pad D1, D2, D3, D4 Nearest distance W1, W2, Wd Width

Claims

1. The semiconductor layer comprises a semiconductor substrate on its back side, a semiconductor layer on its front side including a first region and a second region adjacent to the first region in a plan view of the semiconductor substrate, the area of ​​which is divided into two equal parts by the first region and the second region in a plan view, a first vertical MOS transistor formed in the first region of the semiconductor layer, a second vertical MOS transistor formed in the second region of the semiconductor layer, and a metal layer formed in contact with the back side of the semiconductor layer, wherein the semiconductor substrate is a common drain region of the first vertical MOS transistor and the second vertical MOS transistor, in a plan view, the first region has a first source electrode of the first vertical MOS transistor and a first gate wiring connected to the first gate electrode of the first vertical MOS transistor and surrounding the first source electrode, and the second region has a second source electrode of the second vertical MOS transistor, A semiconductor device comprising: a second gate wiring connected to the second gate electrode of the second vertical MOS transistor and surrounding the second source electrode; the first gate wiring and the second gate wiring formed across the boundary between the first region and the second region; a drain wiring connected to the common drain region formed on the outer periphery of the semiconductor layer; the drain wiring surrounding the first gate wiring and the second gate wiring; and no drain wiring formed between the first gate wiring and the second gate wiring.

2. In the plan view, the minimum width of the drain wiring is narrower than the minimum width of the first gate wiring or the minimum width of the second gate wiring, and the nearest neighbor distance between the first gate wiring and the second gate wiring, which are arranged across the boundary between the first region and the second region, is smaller than the sum of the minimum width of the drain wiring and the nearest neighbor distance between the drain wiring and the first gate wiring or the second gate wiring, according to claim 1.

3. The semiconductor device according to claim 2, wherein, in the plan view, the first gate wiring overlaps with the termination portion of the first body region of the first vertical MOS transistor, and the second gate wiring overlaps with the termination portion of the second body region of the second vertical MOS transistor.

4. The semiconductor device according to claim 3, wherein the first gate wiring is composed of two layers: a first gate wiring metal and a first gate wiring conductor formed above the semiconductor layer, the second gate wiring is composed of two layers: a second gate wiring metal and a second gate wiring conductor formed above the semiconductor layer, and in a plan view, the first gate wiring conductor overlaps with the termination portion of the first body region of the first vertical MOS transistor, and the second gate wiring conductor overlaps with the termination portion of the second body region of the second vertical MOS transistor.

5. The semiconductor device according to claim 3, wherein the first gate wiring is composed of two layers: a first gate wiring metal and a first gate wiring conductor formed above the semiconductor layer, the second gate wiring is composed of two layers: a second gate wiring metal and a second gate wiring conductor formed above the semiconductor layer, and in a plan view, the first gate wiring metal overlaps with the termination portion of the first body region of the first vertical MOS transistor, and the second gate wiring metal overlaps with the termination portion of the second body region of the second vertical MOS transistor.

6. The semiconductor device according to claim 4 or 5, wherein, in the plan view, the nearest neighbor distance between the first body region and the second body region, which are arranged across the boundary between the first region and the second region, is greater than the nearest neighbor distance between the first gate wiring conductor and the second gate wiring conductor, which are arranged across the boundary between the first region and the second region.

7. The semiconductor device according to claim 2, wherein the drain wiring is formed above the semiconductor layer and is made of metal.

8. The semiconductor device according to claim 2, wherein the drain wiring is formed above the semiconductor layer and is composed of a non-metallic conductor.

9. The semiconductor device according to claim 2, wherein the drain wiring is a conductor embedded in a trench formed to a depth from the upper surface of the semiconductor layer to a part of the semiconductor layer.

10. The semiconductor device according to claim 1, 7, or 8, wherein the drain wiring, in plan view, has a rectangular frame-shaped frame line portion, corner portions located inside each of the four corners of the frame line portion, and contact portions, each of which overlaps with each of the four corner portions and connects to the common drain region, and the size of each of the four contact portions is greater than the width of the frame line portion.

11. The shape of each of the four corners is a quadrant shape with the corner of the frame line portion as its vertex, and in the plan view, the shape of each of the four contact portions is rectangular, and in each of the four contact portions, the length of one side of the rectangular shape is greater than the width of the frame line portion, the semiconductor device according to claim 10.

12. The semiconductor device according to claim 10, wherein the drain wiring is composed of one layer.

13. The semiconductor device according to claim 12, wherein the upper surface of the drain wiring is located at a lower height than the upper surface of the first gate wiring or the upper surface of the second gate wiring.

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