Semiconductor device

Abstract

A semiconductor device (100) includes: a gate field plate (131) that is electrically connected to a gate electrode (130), extends in a direction from the gate electrode (130) toward a drain electrode (150), and covers the side surface of a p-type semiconductor layer (120) on the drain electrode side; and a source field plate (142) that is electrically connected to a source electrode (140), extends in a direction from the source electrode (140) toward the drain electrode (150), and covers the side surface of the gate field plate (131) on the drain electrode side. The source field plate (142) extends from the source electrode (140) to a position at least 2.5 μm closer to the drain electrode (150) from the side surface of the gate field plate (131) on the drain electrode side.

Description

Semiconductor equipment 【0001】 This disclosure relates to a semiconductor device on which a GaN-based HEMT is formed. 【0002】 Group III nitride semiconductors, particularly those using gallium nitride (GaN) or aluminum gallium nitride (AlGaN), exhibit high dielectric breakdown voltages due to the wide bandgap of the material. Furthermore, heterostructures such as AlGaN / GaN can be easily formed in Group III nitride semiconductor devices. 【0003】 In an AlGaN / GaN heterostructure, the difference between the piezoelectric polarization generated by the lattice constant difference between the materials and the spontaneous polarization of AlGaN and GaN creates a high concentration of electrons on the GaN layer side of the interface between the AlGaN and GaN layers, forming a two-dimensional electron gas (2DEG) channel in the two-dimensional electron gas layer. Group III nitride semiconductor devices that utilize this two-dimensional electron gas channel have relatively high electron saturation rates, relatively high insulation resistance, and relatively high thermal conductivity, and are therefore used in high-frequency power devices and other applications. 【0004】 Furthermore, to mitigate electric field concentration at the ends of the gate electrode, it is known to form a gate field plate (GFP) integrated with the gate electrode on the drain electrode side. 【0005】 In recent years, semiconductor devices have been known that incorporate a Source Field Plate (SFP), which is at the same potential as the source electrode, between the gate electrode and the drain electrode. By providing an SFP, the electric field concentrated at the drain electrode end of the gate electrode can be mitigated. 【0006】 A semiconductor device in which a GaN-based HEMT is formed and a source field plate is provided is known (see, for example, Patent Document 1). 【0007】 U.S. Patent No. 1,0964,788 【0008】However, in the apparatus described in Patent Document 1, the source field plate cannot sufficiently reduce the electric field near the drain electrode side p-type semiconductor layer edge and the gate field plate edge of the channel layer where the electric field is concentrated. 【0009】 A semiconductor device according to one aspect of the present invention is a semiconductor device on which a GaN-based HEMT (high electron mobility transistor) is formed, comprising: a channel layer; a barrier layer formed above the channel layer; a source electrode, a p-type semiconductor layer, and a drain electrode formed above the barrier layer so as not to overlap each other; a gate electrode formed above the p-type semiconductor layer; a first insulating film covering the barrier layer between the drain electrode side surface of the p-type semiconductor layer and the drain electrode, as viewed from above the semiconductor device; a gate field plate electrically connected to the gate electrode, extending in the direction from the gate electrode toward the drain electrode, and as viewed from above the semiconductor device, covering the drain electrode side surface of the p-type semiconductor layer via the first insulating film; and the semiconductor device The semiconductor device comprises, when viewed from above, a second insulating film covering the gate field plate, and a source field plate electrically connected to the source electrode, extending in the direction from the source electrode toward the drain electrode, and when viewed from the top surface of the semiconductor device, covering the drain electrode side surface of the gate field plate via the second insulating film, wherein the gate field plate extends from the gate electrode to a position closer to the drain electrode than the drain electrode side surface of the p-type semiconductor layer, the source field plate extends in the direction from the source electrode toward the drain electrode, and the drain electrode side end of the source field plate is located at least 2.5 μm closer to the drain electrode side surface of the gate field plate toward the drain electrode. 【0010】Another aspect of the present invention relates to a semiconductor device on which a GaN-based HEMT (high electron mobility transistor) is formed, comprising: a channel layer; a barrier layer formed above the channel layer; a source electrode, a p-type semiconductor layer, and a drain electrode formed above the barrier layer; a gate electrode formed above the p-type semiconductor layer; a first insulating film covering the barrier layer from the drain electrode side surface of the p-type semiconductor layer to the drain electrode, as viewed from the top surface of the semiconductor device; a gate field plate electrically connected to the gate electrode, extending in the direction from the gate electrode toward the drain electrode, and covering the drain electrode side surface of the p-type semiconductor layer via the first insulating film, as viewed from the top surface of the semiconductor device; a second insulating film covering the gate field plate as viewed from the top surface of the semiconductor device; and a source field plate electrically connected to the source electrode, extending in the direction from the source electrode toward the drain electrode, and covering the drain electrode side surface of the gate field plate via the second insulating film, as viewed from the top surface of the semiconductor device, wherein the lowest surface of the gate field plate is located below the uppermost surface of the p-type semiconductor layer. 【0011】 Another aspect of the present invention relates to a semiconductor device on which a GaN-based HEMT (high electron mobility transistor) is formed, comprising: a channel layer; a barrier layer formed above the channel layer; a source electrode, a p-type semiconductor layer, and a drain electrode formed above the barrier layer; and a gate electrode formed above the p-type semiconductor layer, wherein the barrier layer has a recess, and the p-type semiconductor layer is formed above the recess and includes, as viewed from the top surface of the semiconductor device, a first extension portion extending from the drain electrode side surface of the recess to a position closer to the drain electrode than the drain electrode side surface of the recess, and, as viewed from the top surface of the semiconductor device, a second extension portion extending from the source electrode side surface of the recess to a position closer to the source electrode than the source electrode side surface of the recess, wherein the length of the first extension portion is greater than the length of the second extension portion in the direction from the source electrode to the drain electrode. 【0012】The present invention makes it possible to realize a semiconductor device equipped with a gate field plate that reduces the electric field concentrated near the edge of the p-type semiconductor layer on the drain electrode side of the channel layer, and a source field plate that sufficiently reduces the electric field concentrated near the edge of the gate field plate. 【0013】Figure 1 is a cross-sectional view of a semiconductor device according to an embodiment. Figure 2 is a cross-sectional view illustrating one step in the manufacturing method of the semiconductor device according to an embodiment. Figure 3 is a circuit diagram used to evaluate the effect of the semiconductor device. Figure 4 is a plot of the voltage change over time during the measurement period in the evaluation. Figure 5 is a table showing the relationship between the configuration of the semiconductor device under evaluation and the measurement results. Figure 6 is a cross-sectional view of another example of the semiconductor device according to an embodiment. Figure 7 is a plot of the relationship between the power supply voltage and the on-resistance ratio under various conditions of the semiconductor device according to an embodiment. Figure 8 is a plot of the relationship between the gate field plate length and the on-resistance ratio of the semiconductor device according to an embodiment under various conditions. Figure 9 is a plot of the relationship between the gate field plate length and the on-resistance ratio under various source field plate conditions of the semiconductor device according to an embodiment. Figure 10 is a plot of the relationship between the source field plate length and the on-resistance ratio under various gate field plate conditions of the semiconductor device according to an embodiment. Figure 11 is a plot of the relationship between the power supply voltage and the on-resistance ratio depending on the carbon concentration of the semiconductor device according to an embodiment under various conditions. Figure 12 is a plot of the relationship between the power supply voltage and the on-resistance ratio depending on the channel film thickness of the semiconductor device according to an embodiment under various conditions. Figure 13 is a cross-sectional view of a modified example 1 of the semiconductor device according to an embodiment. Figure 14 is a cross-sectional view of modified example 2 of the semiconductor device according to the embodiment. Figure 15 is a cross-sectional view of modified example 3 of the semiconductor device according to the embodiment. Figure 16 is a cross-sectional view of modified example 4 of the semiconductor device according to the embodiment. Figure 17 is a diagram illustrating one step in the manufacturing method of modified example 4 of the semiconductor device according to the embodiment. Figure 18 is a cross-sectional view of modified example 5 of the semiconductor device according to the embodiment. Figure 19 is a cross-sectional view illustrating one step in the manufacturing method of modified example 5 of the semiconductor device according to the embodiment. Figure 20 is a cross-sectional view and a plan view of modified example 6 of the semiconductor device according to the embodiment. Figure 21 is a cross-sectional view and a plan view of modified example 7 of the semiconductor device according to the embodiment. Figure 22 is a cross-sectional view of modified example 8 of the semiconductor device according to the embodiment. 【0014】The embodiments will be described in detail below with reference to the drawings. Note that the embodiments described below are all general or specific examples. The numerical values, shapes, materials, components, arrangement and connection configurations of components, steps, and the order of steps shown in the following embodiments are examples only and are not intended to limit the present invention. Furthermore, components in the following embodiments that are not described in an independent claim will be described as optional components. 【0015】 Please note that each figure is a schematic diagram and not necessarily a strictly accurate representation. Furthermore, in each figure, substantially identical components are denoted by the same reference numerals, and redundant explanations may be omitted or simplified. 【0016】 Furthermore, in this specification, the terms "upper (or top)" and "lower (or bottom)" do not refer to the upward (vertically upward) and downward (vertically downward) directions in absolute spatial perception, but rather are used as terms defined by the relative positional relationship based on the stacking order in a stacked configuration. In addition, the terms "upper (or top)" and "lower (or bottom)" apply not only when two components are spaced apart and another component exists between them, but also when two components are placed in close proximity and touching each other. 【0017】 Furthermore, in this specification, n-type and p-type refer to the conductivity types of semiconductors, and they are conductivity types with opposite polarities. 【0018】 Furthermore, in this specification, "main component" means the component with the highest content among all components constituting the member. For example, a component with a content of 50% or more is the main component. Components include materials, elements, or compounds. Also, "member A is composed of component B" means that member A substantially contains only component B. However, member A may contain impurities other than component B that are unavoidable to include during manufacturing. The content of such unavoidable impurities is 1% or less. 【0019】Furthermore, in this specification, ordinal numbers such as "first," "second," etc., do not mean the number or order of components unless otherwise specified, but are used to avoid confusion and to distinguish similar components. 【0020】 (Embodiment) Figure 1 is a cross-sectional view of a semiconductor device 100 according to an embodiment. 【0021】 The semiconductor device 100 shown in Figure 1 is a nitride semiconductor device in which the semiconductor stacked structure 110 mainly contains a nitride semiconductor. The nitride semiconductor is a group III nitride semiconductor containing one or more group III elements and nitrogen. Examples of group III elements include aluminum (Al), gallium (Ga), and indium (In). Examples of group III nitride semiconductors include GaN, AlN, InN, AlGaN, InGaN, and AlInGaN. In the following explanation, unless otherwise specified, when AlInGaN is written, it means that the group III nitride semiconductor contains Al, In, Ga, and N. The same applies to other notations such as AlGaN and GaN. 【0022】 The semiconductor device 100 shown in Figure 1 is a high electron mobility transistor (HEMT) that includes a two-dimensional electron gas (2DEG) as a channel, and is a normally-off type HEMT. The semiconductor device 100 comprises a semiconductor stacked structure 110, a p-type semiconductor layer 120, a gate electrode 130, a source electrode 140, a drain electrode 150, a gate field plate 131, a source pad 141, a source field plate 142, a drain pad 151, and insulating films 160 and 170. 【0023】The semiconductor multilayer structure 110 includes a two-dimensional electron gas (2DEG). The semiconductor multilayer structure 110 is a stack of multiple nitride semiconductors. The semiconductor multilayer structure 110 is supported on a substrate (not shown). For example, the substrate is a Si substrate, but it may also be an SOI (Silicon on Insulator) substrate. Alternatively, the substrate may be made of SiC, sapphire, diamond, GaN, or AlN, etc. The semiconductor multilayer structure 110 includes a channel layer 111 and a barrier layer 112 stacked on the channel layer 111. The channel layer 111 has a smaller band gap than the barrier layer 112. The channel layer 111 mainly contains, for example, i-type GaN. The barrier layer 112 mainly contains, for example, i-type AlGaN. The channel layer 111 and the barrier layer 112 form an AlGaN / GaN heterojunction. 2DEG occurs on the channel layer side near the interface between the channel layer 111 and the barrier layer 112. 【0024】 The channel layer 111 is sometimes called the electron transport layer, and the barrier layer 112 is sometimes called the electron supply layer. A layer for suppressing alloy scattering, such as AlN, may be provided between the channel layer 111 and the barrier layer 112. The semiconductor stacked structure 110 may also include at least one of a buffer layer for mitigating lattice mismatch between the substrate and the channel layer 111, and a back barrier layer provided between the channel layer 111 and the buffer layer. 【0025】The barrier layer 112 is provided with recesses 112a, 112b, and 112c. Recess 112a is provided in region 101 of the semiconductor stacked structure 110. Region 101 is adjacent to region 102 where the p-type semiconductor layer 120 is provided in cross-sectional view. Recess 112c is provided in region 103 of the semiconductor stacked structure 110. Region 103 is adjacent to region 102 where the p-type semiconductor layer 120 is provided in cross-sectional view, and is the region opposite to region 101 with region 102 in between. A drain electrode 150 is provided so as to cover a part of recess 112a, and an insulating film 160 covers the remaining part of recess 112a. A source electrode 140 is provided so as to cover a part of recess 112c, and an insulating film 160 covers the remaining part of recess 112c. Furthermore, the recess 112b is provided to form a depletion layer in 2DEG, which is formed on the upper surface of the channel layer 111 when no voltage is applied to the gate electrode 130. Hereinafter, the length GR of the recess 112b will be referred to as the gate length. 【0026】 The p-type semiconductor layer 120 is an example of a p-type semiconductor layer and is provided above the semiconductor stacked structure 110. Specifically, it is provided in contact with the upper surface of the channel layer 111 of region 102 via a barrier layer 112. The p-type semiconductor layer 120 mainly contains, for example, p-type GaN. As shown in Figure 1, the p-type semiconductor layer 120 includes a thin film portion 121 and a thick film portion 122. 【0027】 Because the p-type semiconductor layer 120 is provided, when a voltage of 0V or a negative voltage is applied to the gate electrode 130, a depletion layer spreads within the semiconductor stack structure 110 in the direction directly below the p-type semiconductor layer 120, and 2DEG disappears. As a result, the channel between the source electrode 140 and the drain electrode 150 is blocked, and the semiconductor device 100 turns off (non-conductive state, blocked state). When a positive voltage above a threshold voltage is applied to the gate electrode 130, the depletion layer directly below the p-type semiconductor layer 120 recedes, and 2DEG is generated. As a result, the channel between the source electrode 140 and the drain electrode 150 becomes conductive, and the semiconductor device 100 turns on (conductive state). 【0028】The gate electrode 130 is provided above the p-type semiconductor layer 120, and specifically, the gate electrode 130 is provided in contact with the upper surface of the p-type semiconductor layer 120. The gate electrode 130 mainly contains TiN, for example. The gate electrode 130 only needs to be conductive, and may mainly contain conductive materials such as metal nitrides other than TiN or metals. Furthermore, the gate electrode 130 may have a laminated structure of multiple metal films with different main components. 【0029】 The gate field plate 131 can mitigate the electric field concentrated near the drain electrode side p-type semiconductor layer edge of the channel layer 111. The gate field plate 131 contains, for example, TiN as its main component. 【0030】 The source electrode 140 and the drain electrode 150 are positioned with the gate electrode 130 in between. In the example shown in Figure 1, the distance between the source electrode 140 and the gate electrode 130 is shorter than the distance between the drain electrode 150 and the gate electrode 130, but this is not limited to this. 【0031】 The source electrode 140 and the drain electrode 150 mainly contain a conductive material that is in ohmic contact with an n-type nitride semiconductor. For example, the source electrode 140 and the drain electrode 150 mainly contain a TiAl alloy. The source electrode 140 and the drain electrode 150 may also mainly contain a conductive material such as a single metal like Ti or Al. Furthermore, the source electrode 140 and the drain electrode 150 may have a laminated structure of multiple metal films with different main components. In this embodiment, the source electrode 140 and the drain electrode 150 mainly contain the same material, but they may also mainly contain different materials. 【0032】 The insulating films 160 and 170 are layers mainly composed of insulating materials. For example, insulating film 160 mainly contains SiN. ２ It may also contain other insulating materials such as SiON as a main component. Furthermore, the insulating film 160 may have a laminated structure of multiple insulating films, each having different main components. 【0033】The source pad 141 provides a connection point between the semiconductor device 100 and an external device and is a component that serves as an outlet for current. The source pad 141 contains, for example, AlCu as a main component. 【0034】 The source field plate 142 can relax an electric field concentrated near the gate field plate end. The source field plate 142 contains, for example, AlCu as a main component. 【0035】 The drain pad 151 provides a connection point between the semiconductor device 100 and an external device and is a component that serves as an inlet for current. The drain pad 151 contains, for example, AlCu as a main component. 【0036】 The insulating film 160 is provided on the semiconductor stack structure 110. Also, the insulating film 160 is provided above the thin film portion 121 of the p-type semiconductor layer 120. Specifically, it contacts and covers the upper surface of the barrier layer 112, and the side and upper surfaces of the p-type semiconductor layer 120. By providing the insulating film 160, leakage current flowing through the upper surface of the semiconductor stack structure 110 can be suppressed. Also, the insulating film 160 functions as a protective film for the semiconductor stack structure 110 and the p-type semiconductor layer 120. 【0037】 An opening (gate opening) for exposing a part of the upper surface of the p-type semiconductor layer 120 is provided in the insulating film 160. Through the gate opening, the gate electrode 130 contacts the upper surface of the p-type semiconductor layer 120. Also, in the insulating film 160, an opening (source opening) for exposing a part of the recess 112c and an opening (drain opening) for exposing a part of the recess 112a are provided. Through the source opening, the source electrode 140 contacts the upper surface of a part of the barrier layer 112 and contacts the side and upper surfaces of the insulating film 160. Also, through the drain opening, the drain electrode 150 contacts the upper surface of a part of the barrier layer 112 and contacts the side and upper surfaces of the insulating film 160. 【0038】The insulating film 170 contacts and covers the upper surface of the insulating film 160. Further, the insulating film 170 contacts and covers a part of the upper surface and the side surface of the source electrode 140, the upper surface and the side surface of the gate electrode 130 and the gate field plate 131, and a part of the upper surface and the side surface of the drain electrode 150. Thereby, the leakage current between the gate electrode 130 and the source electrode 140 and between the gate electrode 130 and the drain electrode 150 can be suppressed. Further, the insulating film 170 also functions as a protective film for the semiconductor laminate structure 110 and the p-type semiconductor layer 120. 【0039】 The insulating film 170 is provided with openings for exposing a part of the upper surface of the source electrode 140 and a part of the upper surface of the drain electrode 150, respectively. Through the openings, the source pad 141, the source field plate 142, and the drain pad 151 are connected to the source electrode 140 and the drain electrode 150, respectively. 【0040】 [Configuration] Next, the main characteristic configuration of the semiconductor device 100 according to the present embodiment will be specifically described. 【0041】As shown in Figure 1, the p-type semiconductor layer 120 includes a thick film portion 122 and a thin film portion 121. The length GR of the thick film portion 122 is, for example, 0.1 μm or more and 2.0 μm or less, and is 0.8 μm as an example. The length GT of the p-type semiconductor layer 120 is, for example, 1.0 μm or more and 2.5 μm or less, and is 1.6 μm as an example. The length CP of the bottom surface of the gate electrode 130 is, for example, 0.5 μm or more and 2.0 μm or less, and is 0.8 μm as an example. The distance Lgs between the gate electrode side end of the bottom surface of the source electrode 140 and the source electrode side end of the bottom surface of the p-type semiconductor layer 120 is, for example, 0.1 μm or more and 2.0 μm or less, and is 1.4 μm as an example. Furthermore, the distance Lgd between the drain electrode side end of the upper surface of the p-type semiconductor layer 120 and the gate electrode side end of the bottom surface of the drain electrode 150 is, for example, 10.0 μm or more and 30.0 μm or less when the voltage applied to the drain electrode 150 is 600 V during operation of the semiconductor device 100. For example, it is 11.0 μm. The distance Lsfp between the drain electrode side end of the upper surface of the p-type semiconductor layer 120 and the drain electrode side end of the source field plate 142 is, for example, 2.5 μm or more. Preferably, it is 2.5 μm or more and 4.5 μm or less, for example, 4.5 μm. The distance Lgfp between the drain electrode side end of the upper surface of the p-type semiconductor layer 120 and the drain electrode side end of the gate field plate 131 is, for example, 0 μm or more. Preferably, it is 0 μm or more and 1.3 μm or less, for example, 0.7 m. The distance Lsfp-gfp between the drain electrode side end of the source field plate 142 and the drain electrode side end of the gate field plate 131 is, for example, 0 μm or more. As an example, it is 3.8 μm. The ratio Lsfp-gfp / Lgd of the distance between the drain electrode side end of the source field plate 142 and the drain electrode side end of the gate field plate 131 and the distance between the drain electrode side end of the upper surface of the p-type semiconductor layer 120 and the gate electrode side end of the bottom surface of the drain electrode 150 is, for example, 0.35. The ratio Lsfp / Lgd of the distance between the drain electrode side end of the upper surface of the p-type semiconductor layer 120 and the drain electrode side end of the source field plate 142 and the distance between the drain electrode side end of the upper surface of the p-type semiconductor layer 120 and the gate electrode side end of the bottom surface of the drain electrode 150 is, for example, 0.41.The ratio Lgfp / Lgd of the distance between the drain electrode side end of the upper surface of the p-type semiconductor layer 120 and the drain electrode side end of the gate field plate 131, and the distance between the drain electrode side end of the upper surface of the p-type semiconductor layer 120 and the gate electrode side end of the bottom surface of the drain electrode 150, is, for example, 0.06. The thickness of the channel layer 111 is, for example, 175 nm. The distance between the upper surface of the barrier layer 112 and the lower surface of the gate field plate 131 is Hgfp, and the distance between the upper surface of the barrier layer 112 and the lower surface of the source field plate 142 is Hsfp. 【0042】 [Manufacturing Method] Next, the manufacturing method of the semiconductor device 100 according to this embodiment will be described using Figures 2(a) to 2(g). Figure 2 is a cross-sectional view illustrating one step of the manufacturing method of the semiconductor device according to this embodiment. Figures 2(a) to 2(g) are all cross-sectional views illustrating one step of the manufacturing method of the semiconductor device 100 according to this embodiment. 【0043】 A method for manufacturing the semiconductor device 100 includes the steps of forming a semiconductor stacked structure 110 including a recess on a substrate (not shown) (Figure 2(a)), forming a p-type semiconductor layer 120 on the semiconductor stacked structure 110 (Figure 2(b)), forming an insulating film 160 (Figure 2(c)), forming a source electrode 140 and a drain electrode 150 (Figure 2(d)), forming a gate electrode 130 and a gate field plate 131 (Figure 2(e)), forming an insulating film 170 (Figure 2(f)), and forming a source pad 141, a source field plate 142, and a drain pad 151 (Figure 2(g)). 【0044】 First, as shown in Figure 2(a), a nitride semiconductor is grown by epitaxial growth such as metal-organic chemical vapor deposition (MOCVD) to form a buffer layer (not shown), a channel layer 111, and a barrier layer 112 on a substrate (not shown). Then, a recess 112b is formed in the barrier layer 112 by lithography. 【0045】Next, as shown in Figure 2(b), a p-type semiconductor layer 120 is formed over the entire upper surface of the barrier layer 112. Then, the p-type semiconductor layer 120 and a portion of the barrier layer 112 other than the region 102 containing the recess are etched away to form the p-type semiconductor layer 120. As a result, the thickness of the barrier layer 112 in regions 101 and 103 is different from the thickness of the barrier layer 112 at both ends of region 102. 【0046】 Then, as shown in Figure 2(c), an insulating film 160 is formed. For example, an insulating film 160 mainly composed of SiN is formed by a plasma CVD (Chemical Vapor Deposition) method using silane and ammonia. The insulating film 160 is formed to cover the entire upper surface of the barrier layer 112 and the upper and side surfaces of the p-type semiconductor layer 120. After that, only the insulating film 160 present in the regions 104 and 105 where the drain electrode and source electrode are provided is removed by etching, exposing the upper surface of the barrier layer 112. 【0047】 Next, as shown in Figure 2(d), the source electrode 140 and the drain electrode 150 are formed on a portion of the upper surface of the barrier layer 112, a portion of the upper surface of the insulating film 160, and on the side surface. 【0048】 Specifically, a Ti film with a thickness of 30 nm and an Al film with a thickness of 200 nm are sequentially deposited by vapor deposition or sputtering to form a laminated film. Then, the unnecessary laminated film is removed by a lift-off method to form a source electrode 140 and a drain electrode 150 of a predetermined shape, consisting of a laminated film of Ti and Al, on the upper surface of the barrier layer 112. 【0049】Next, as shown in Figure 2(e), the insulating film 160 formed in region 106 is etched away to expose a portion of the upper surface of the p-type semiconductor layer 120. Then, a metal film is deposited over the entire surface, including the exposed portion of the upper surface of the p-type semiconductor layer 120. After that, the gate electrode 130 and gate field plate 131 are formed by etching. Specifically, a laminated film is formed by sequentially depositing a TiN film with a thickness of 50 nm and an Al film with a thickness of 450 nm using the sputtering method. Then, the gate electrode 130 and gate field plate 131 are formed by lithography. At this time, in order to form the gate electrode 130 and gate field plate 131, a portion of the insulating film 160 in region 107 that is not in contact with the gate field plate 131 is also etched away, and insulating films 160 of different thicknesses are formed within region 101. 【0050】 Subsequently, as shown in Figure 2(f), an insulating film 170 is formed. For example, using the same method as for forming the insulating film 160, SiO ２ An insulating film 170 containing as the main component is formed. Subsequently, in order to form the source pad 141, the source field plate 142, and the drain pad 151, the insulating film 170 formed in regions 108 and 109 is etched off, and the upper surfaces of the source electrode 140 and the drain electrode 150 are exposed. 【0051】 Finally, as shown in Figure 2(g), the source pad 141, source field plate 142, and drain pad 151 are formed. First, a metal layer made of AlCu is formed over the entire surface, and then the metal layer formed in areas other than region 113 and region 114 is etched off to form the source pad 141, source field plate 142, and drain pad 151. 【0052】 Thus, by going through the series of steps from Figure 2(a) to Figure 2(g), the semiconductor device 100 with the structure shown in Figure 1 is completed. 【0053】[Measurement Results] The semiconductor device 100 according to this embodiment, manufactured by the above process, is provided with a gate field plate 131 that reduces the electric field concentrated near the drain electrode side p-type semiconductor layer edge of the channel layer 111, and a source field plate 142 that sufficiently reduces the electric field concentrated near the gate field plate edge. The details of the functions of the semiconductor device 100 will be described below. 【0054】 This disclosure describes a method and results for measuring the effect of the source field plate 142 and gate field plate 131 on the on-resistance by changing Lsfp, Lgfp, Hsfp, and Hgfp of the semiconductor device 100 of this disclosure to various values. 【0055】 Figure 3 shows the circuit diagram used to evaluate the effect of the semiconductor device 100. The measurement circuit shown in Figure 3 is used to evaluate the on-resistance of the semiconductor device 100 using double-pulse measurement with a load resistor. 【0056】 Figure 4 is a plot of the voltage change over time during the measurement period in the evaluation. The experimental conditions were as follows: First, the semiconductor device 100 was set to predetermined values ​​for Lsfp, Lgfp, Hsfp, and Hgfp. The source electrode was set to GND, and the power supply voltage Vdd applied to the load resistor was varied to 50, 100, 200, 300, and 400 V. In the simulation, a pulse voltage of 6 V (Vg) was applied to the gate electrode for 20 μs, and a power supply voltage Vdd of 50 V was applied to calculate the current Id flowing through the semiconductor device 100 and the voltage Vds between the drain electrode and source electrode of the semiconductor device 100. At this time, the reference on-resistance Ron was calculated from the measured Vds and Id. Then, after 20 μs, a pulse voltage of 6 V (Vg) was applied to the gate electrode again, and the current Id and voltage Vds flowing through the semiconductor device 100 were calculated at a predetermined power supply voltage Vdd. The on-resistance Ron was calculated from these two values, and the on-resistance ratio (Ron ratio) was calculated from the ratio with the above-mentioned reference on-resistance Ron. The influence of the source field plate 142 and gate field plate 131 of the semiconductor device 100 on the on-resistance was evaluated. 【0057】Figure 5 is a table showing the relationship between the configuration of the semiconductor device 100 under evaluation and the measurement results. For details, the simulation results of the semiconductor devices Sample 1 to Sample 5 are shown. "No.", "GR", "CP", "GT", "Lgs", "Lgfp", "Lsfp", "Lsfp-gfp", "Lsfp / Lgfp", "Hgfp / Lgfp", "Hsfp / Lsfp", "(Hsfp-Hgfp) / (Lsfp-Lgfp)", "Vth", "Ron", "Ig", and "Ron ratio" are as follows: "No." is the sample number, "GR" is the width of the thick film portion 122 of the p-type semiconductor layer 120, and "CP" is the upper surface of the p-type semiconductor layer 120 of the gate electrode 130. "GT" is the width of the region in contact with the source electrode, "Lgs" is the distance between the gate electrode side end of the bottom surface of the source electrode 140 and the source electrode side end of the bottom surface of the p-type semiconductor layer 120, "Lgfp" is the distance between the drain electrode side end of the p-type semiconductor layer 120 and the drain electrode side end of the gate field plate 131, "Lsfp" is the distance between the drain electrode side end of the p-type semiconductor layer 120 and the drain electrode side end of the source field plate 142, and "Ls "fp-gfp" is the distance between the drain electrode side end of the source field plate 142 and the drain electrode side end of the gate field plate 131, "Lsfp / Lgfp" is the ratio of the distance between the drain electrode side end of the p-type semiconductor layer 120 and the drain electrode side end of the source field plate 142 to the distance between the drain electrode side end of the p-type semiconductor layer 120 and the gate field plate 131, and "Hgfp / Lgfp" is the distance between the bottom surface of the gate field plate 131 and the burr The distance from the top surface of layer 112 (Hsfp) is the ratio of the distance between the drain electrode side end of the p-type semiconductor layer 120 and the drain electrode side end of the source field plate 142, and "Hsfp / Lsfp" is the ratio of the distance between the bottom surface of the source field plate 142 and the top surface of the barrier layer 112 (Hsfp) and the distance between the drain electrode side end of the p-type semiconductor layer 120 and the drain electrode side end of the source field plate 142, and "(Hsfp - Hgfp) / (Lsfp - Lgfp)" is,The ratio of the difference between the distance between the bottom surface of the source field plate 142 and the top surface of the barrier layer 112 (Hsfp) and the distance between the bottom surface of the gate field plate 131 and the top surface of the barrier layer 112 (Hgfp), and the difference between the distance between the drain electrode side end of the p-type semiconductor layer 120 and the drain electrode side end of the source field plate 142 and the distance between the drain electrode side end of the p-type semiconductor layer 120 and the gate field plate 131, where "Vth" is the threshold voltage of the semiconductor device at each sample number, and "Ron" is the value obtained by applying a pulse voltage of 6V (Vg) to the gate electrode of the semiconductor device at each sample number for 20μs and applying a power supply voltage Vdd of 50V. This involves calculating the current Id flowing through the semiconductor device and the voltage Vds across the drain and source electrodes of the semiconductor device. The on-resistance, which serves as the reference for the on-resistance ratio, is calculated from these two values. "Ig" is the pulsed current flowing through the gate electrode of the semiconductor device at each sample number. The "Ron ratio" is the ratio between the on-resistance calculated from the current Id flowing through the semiconductor device and the voltage Vds across the drain and source electrodes of the semiconductor device (calculated by applying a pulsed voltage of 6V (Vg) for 20μs to the gate electrode of the semiconductor device at each sample number, multiplying by a predetermined power supply voltage Vdd), and the aforementioned reference on-resistance Ron. 【0058】 Here, the semiconductor device of Sample 1 is a reference example semiconductor device that does not have a gate field plate 131 and does not satisfy the configuration of the semiconductor device 100 according to the embodiment. 【0059】 Furthermore, although the semiconductor device of Sample 4 satisfies the configuration of the semiconductor device 100 according to the embodiment, the Lgfp is longer than the Lsfp, so the arrangement of some components of the semiconductor device 100 is different, resulting in the semiconductor device 100A shown in Figure 6. 【0060】 The semiconductor device 100 in Sample 2, Sample 3, and Sample 5 has the same components and arrangement positions as the semiconductor device 100 according to the embodiment. 【0061】Figure 7 is a plot of the relationship between the power supply voltage Vdd and the on-resistance ratio (Ron ratio) under various conditions for the semiconductor device 100 according to the embodiment shown in Figure 5. Specifically, it is a plot of the relationship between the power supply voltage Vdd to the semiconductor device 100 of Sample 1 to Sample 5 and the measured on-resistance ratio (Ron ratio), with the vertical axis being the on-resistance ratio (Ron Ratio) and the horizontal axis being the power supply voltage Vdd. The plot of the semiconductor device 100 of Sample 1 is represented by a solid line, the plot of the semiconductor device 100 of Sample 2 is represented by a dashed line, the plot of the semiconductor device 100 of Sample 3 is represented by a dashed line, the plot of the semiconductor device 100 of Sample 4 is represented by a dashed line, and the plot of the semiconductor device 100 of Sample 5 is represented by a dotted line. 【0062】 As shown in Figure 7, the on-resistance ratio increases with the power supply voltage Vdd in all of the semiconductor devices 100 or semiconductor device 100A, Sample 1 to Sample 5. The semiconductor device 100 in Sample 5, where Lgfp is 2.0 μm and Lsfp is 4.5 μm, showed the slowest increase in the on-resistance ratio with respect to the increase in the power supply voltage Vdd. Furthermore, when Lgfp is 4.0 μm and Lsfp is 2.5 μm, that is, when the distance from the drain electrode 150 is shorter at the drain electrode side end of the gate field plate 131 than at the drain electrode side end of the source field plate 142 (see Sample 4 shown in Figure 6), the increase in the on-resistance ratio with respect to the increase in Vdd was the most rapid. Figure 6 is a cross-sectional view of another example (Sample 4) of the semiconductor device 100 according to the embodiment. 【0063】Furthermore, comparing the relationship between Vdd and on-resistance ratio in the semiconductor devices 100 of Sample 1 and Sample 5, where Lsfp-gfp is the same at 2.5 μm, the increase in on-resistance ratio with increasing power supply voltage Vdd is more gradual in the semiconductor device 100 of Sample 5, where Lgfp is 2.0 μm, compared to the semiconductor device 100 of Sample 1, where Lgfp is 0 μm, i.e., the gate field plate 131 is absent. From the above, it is shown that the gate field plate 131 of the semiconductor device 100 influences the electric field relaxation effect and suppresses current collapse during hard switching drive. 【0064】 Furthermore, when comparing the semiconductor devices 100 of Sample 3 and Sample 5, both having the same Lsfp-gfp of 2.0 μm, no difference is observed in the on-resistance ratio when Vdd is 100 and 200 V. However, when the power supply voltage Vdd is 300 V or higher, the on-resistance ratio of the semiconductor device 100 of Sample 3, with Lsfp-gfp of 0.5 μm, increases sharply with increasing power supply voltage Vdd, while the increase in the on-resistance ratio of the semiconductor device 100 of Sample 5, with Lsfp-gfp of 2.5 μm, increases more gradually with increasing Vdd. Here, Lsfp-gfp is the length that the end of the source field plate 142 extends beyond the end of the gate field plate 131 toward the drain electrode, and is the length that effectively covers the barrier layer only with respect to the source field plate 142. From the above, it was found that setting the effective length of the source field plate 142 to 2.5 μm at a relatively high power supply voltage Vdd had a positive effect on the electric field relaxation effect, suppressing current collapse during hard switching drive. 【0065】Figure 8 is a plot of the relationship between the gate field plate length and the on-resistance ratio under various conditions for the semiconductor device 100 according to the embodiment. Specifically, for the semiconductor device 100 from Sample 1 to Sample 5, the relationship between the on-resistance ratio and Lgfp is plotted at Vdd values ​​of 200, 300, and 400V, with the vertical axis representing the on-resistance ratio (On ​​Ratio) and the horizontal axis representing the length Lgfp of the gate field plate 131. In Figure 8(a), Vdd is 200V, in Figure 8(b), Vdd is 300V, and in Figure 8(c), Vdd is 400V. 【0066】 In Figures 8(a) to (c), the relationship between Lgfp and on-resistance ratio when Lsfp is 2.5 μm is shown by a solid line. However, only when Lgfp is 2 μm, the relationship between Lgfp and on-resistance ratio when Lsfp is 4.5 μm is shown by a white circle. 【0067】 From Figures 8(a) to 8(c), in the region where Lgfp is 1 μm or less, the on-resistance ratio decreases with increasing Lgfp for all Vdd values. This is because the gate field plate 131 mitigates the electric field concentration at the drain electrode side end of the p-type semiconductor layer 120. 【0068】 From Figures 8(a) to 8(c), in the region where Lgfp is 2 μm or greater, the on-resistance ratio increases with increasing Lgfp at high Vdd values ​​such as 300 and 400 V. This is because the gate field plate 131 protrudes further toward the drain electrode than the source field plate 142, which not only prevents the electric field concentration mitigation effect of the source field plate 142 from being exerted, but also causes the electric field to concentrate at the drain electrode end of the gate field plate 131. 【0069】On the other hand, when Lsfp is 4.5 μm, which is 2.5 μm longer than Lgfp is 2 μm (indicated by the white circle in the figure), the on-resistance ratio at Vdd of 300 and 400 V is smaller, even with the same Lgfp. This is because the tip of the source field plate 142 protrudes towards the drain electrode side relative to the tip of the gate field plate 131, which mitigates electric field concentration near the tip of the gate field plate 131 and suppresses current collapse during hard switching drive. 【0070】 Figure 9 plots the relationship between the gate field plate length and the on-resistance ratio under various source field plate conditions for the semiconductor device 100 according to the embodiment. The dimensions of the semiconductor device 100 used for measurement are the same as those of Sample 5, except for Lsfp and Lgfp. Specifically, the figure plots the relationship between the on-resistance ratio and Lgfp when Vdd is 400V and Lgfp is varied from 0μm to 1.3μm. The vertical axis is the on-resistance ratio (On ​​Ratio), and the horizontal axis is the length Lgfp of the gate field plate 131. In this case, the semiconductor device 100 with an LSFP of 2.5 μm is plotted as a solid line, the semiconductor device 100 with an LSFP of 3.0 μm is plotted as a dotted line, the semiconductor device 100 with an LSFP of 3.5 μm is plotted as a dashed line, the semiconductor device 100 with an LSFP of 4.0 μm is plotted as a dashed line, and the semiconductor device 100 with an LSFP of 4.5 μm is plotted as a dashed line. 【0071】 As shown in Figure 9, for all LSFPs, when Lgfp is 0.7 μm or longer, the on-resistance ratio increases with increasing Lgfp. Also, for all LSFPs, when Lgfp is 0.4 μm or less, the on-resistance ratio increases with decreasing Lgfp. From the above, a more preferable length for Lgfp is 0.4 μm or more and 0.7 μm or less, and in this case, a more preferable range for the ratio Lgfp / Lgd is 0.036 or more and 0.064 or less. 【0072】Figure 10 is a plot of the relationship between the source field plate length and the on-resistance ratio under various gate field plate conditions for the semiconductor device 100 according to the embodiment. 【0073】 For details, Figure 10(a) is a plot of the relationship between the on-resistance ratio and LSFP when Vdd is 400V and LSFP is varied between 2.5 μm and 4.5 μm. The vertical axis is the on-resistance ratio (Ron Ratio), and the horizontal axis is LSFP. The plot for semiconductor device 100 with LGFP of 0.4 μm is shown as a solid line, and the plot for semiconductor device 100 with LGFP of 0.7 μm is shown as a dashed line. 【0074】 Figure 10(b) is a plot of the relationship between the on-resistance ratio and Lsfp-gfp when Vdd is 400V and Lsfp is varied between 2.5μm and 4.5μm. The vertical axis is the on-resistance ratio (Ron Ratio), and the horizontal axis is Lsfp-gfp. The plot for semiconductor device 100 with Lgfp of 0.4μm is shown as a solid line, and the plot for semiconductor device 100 with Lgfp of 0.7μm is shown as a dashed line. 【0075】 The results in Figure 10(a) show that in all Lgfp configurations, the on-resistance ratio decreases with increasing Lsfp, indicating that a longer source field plate 142 is preferable. 【0076】 From the above, a more preferable length for Lsfp is 4 μm or longer. In this case, a more preferable ratio of Lsfp to Lgd, Lsfp / Lgd, is 0.36 or longer. 【0077】 Furthermore, the results in Figure 10(b) show that in all Lgfp configurations, the on-resistance ratio decreases as Lsfp-Lgfp increases, indicating that it is better for the drain electrode side end of the source field plate 142 and the drain electrode side end of the gate field plate 131 to be separated. 【0078】 From the above, a more preferable length for Lsfp-GFP is 3.3 μm or longer. In this case, a more preferable ratio of Lsfp-GFP to Lgd, Lsfp-GFP / Lgd, is 0.30 or longer. 【0079】 FIG. 11 is a diagram plotting the relationship between the power supply voltage Vdd and the on-resistance ratio depending on the carbon concentration in the channel layer 111 of the semiconductor device 100 according to the embodiment. Specifically, when the carbon concentration in the channel layer 111 of the semiconductor device 100 is 1×10 １６ cm －３ , 2×10 １６ cm －３ and different, it is a diagram comparing the relationship between the power supply voltage Vdd and the on-resistance ratio during hard switching drive. The vertical axis is the on-resistance ratio (Ron Ratio), the horizontal axis is the power supply voltage Vdd, and the solid line is when the carbon concentration in the channel layer 111 is 1×10 １６ cm －３ , and the dotted line is a plot showing the relationship between Vdd and the on-resistance ratio when the carbon concentration in the channel layer 111 is 2×10 １６ cm －３ . The dimensions of the semiconductor device 100 are equal to Sample5, Lgfp is 2 μm, and Lsfp-gfp is 2.5 μm. 【0080】 As shown in FIG. 11, a difference is seen in the results of the on-resistance ratio when Vdd is 400 V, and the semiconductor device 100 with a lower carbon concentration of 1×10 １６ cm －３ has a lower on-resistance ratio. This is because carbon in the channel layer 111 acts as a carrier trap, and current collapse caused by the carrier trap is suppressed by reducing the carbon concentration. Since the on-resistance ratio is preferably less than 1.5, the carbon concentration in the channel layer 111 is preferably 2×10 １６ cm －３ or less. 【0081】Figure 12 is a plot of the relationship between the power supply voltage Vdd and the on-resistance ratio, depending on the thickness of the channel layer 111 of the semiconductor device 100 according to the embodiment. Specifically, it is a figure comparing the relationship between the power supply voltage Vdd and the on-resistance ratio during hard switching drive when the thickness of the channel layer 111 of the semiconductor device 100 is 150 nm and 300 nm. The vertical axis is the on-resistance ratio (Ron Ratio), and the horizontal axis is the power supply voltage Vdd. The dashed line shows the relationship between Vdd and the on-resistance ratio when the thickness of the channel layer 111 is 150 nm, and the solid line shows the relationship when the thickness of the channel layer 111 is 300 nm. The dimensions of the semiconductor device 100 are the same as those of Sample 5, with Lgfp being 2 μm and Lsfp-gfp being 2.5 μm. 【0082】 Furthermore, the semiconductor device 100 used in the measurement in Figure 12(a) has an Al composition of 0.16 in the barrier layer 112 of the semiconductor device 100, while the semiconductor device 100 used in the measurement in Figure 12(b) has an Al composition of 0.27 in the barrier layer 112 of the semiconductor device 100. 【0083】 As shown in Figures 12(a) and (b), a difference was observed in the on-resistance ratio when Vdd was 200V or higher, with the semiconductor device 100 having a thicker channel layer 111 of 300nm showing a lower on-resistance ratio. This is because increasing the thickness of the channel layer 111 widens the gap between the channel layer 111 and the traps present in the layer below it, which has a higher carbon concentration, thereby suppressing current collapse caused by these traps. Since an on-resistance ratio of less than 1.5 is preferable, the thickness of the channel layer 111 is preferably 150nm or more. 【0084】 [Modified Examples] Next, several modified examples of the semiconductor device 100 according to the embodiment will be described. In the following, the differences from the semiconductor device 100 according to the embodiment will be the focus of the description, and the explanation of the common points will be omitted or simplified. 【0085】<Modification 1> Figure 13 is a cross-sectional view of a semiconductor device 100B according to Modification 1 of the embodiment. As shown in Figure 13, compared to the semiconductor device 100 shown in Figure 1, the semiconductor device 100B has the following features: firstly, there are no recesses in the barrier layer 112, the thickness of the p-type semiconductor layer 120 is uniform, and secondly, the height of the lower surface of the drain electrode side end of the gate field plate 131 is higher than the height of the upper surface of the p-type semiconductor layer 120. 【0086】 <Modification 2> Figure 14 is a cross-sectional view of a semiconductor device 100C according to modification 2 of the embodiment. As shown in Figure 14, compared to the semiconductor device 100 shown in Figure 1, the semiconductor device 100C firstly lacks a gate field plate 131, and has a drain electrode side extension relative to the source electrode side extension of the recess of the p-type semiconductor layer 120. This allows for a larger cross-sectional area while shortening the gate length, thus keeping the on-resistance low. Furthermore, by increasing the length of the drain electrode side extension of the p-type semiconductor layer 120, it becomes possible to suppress current collapse due to the electric field concentration mitigation effect near the drain electrode side end of the recess by the p-type semiconductor layer 120. 【0087】 <Modification 3> Figure 15 is a cross-sectional view of a semiconductor device 100D according to Modification 3 of the embodiment. As shown in Figure 15, in the semiconductor device 100D, compared to the semiconductor device 100 shown in Figure 1, the p-type semiconductor layer 120 is replaced with a p-type layer 123, and a cap layer 124 made of GaN or AlGaN with a low acceptor concentration exists between the p-type layer 123 and the gate electrode 130. The thickness of the cap layer 124 is, for example, 1 nm to 30 nm. This increases the Schottky barrier between the gate electrode 130 and the p-type layer 123, thereby suppressing excessive hole injection and suppressing current collapse caused by hole traps. The cap layer 124 may also have a stacked structure, which may consist of, for example, GaN and AlGaN. 【0088】<Modification 4> Figure 16 is a cross-sectional view of a semiconductor device 100E according to Modification 4 of the embodiment. As shown in Figure 16, in the semiconductor device 100E, compared to the semiconductor device 100 shown in Figure 1, the source field plate 142 completely covers the drain electrode side wall of the gate field plate 131 when viewed from the drain electrode side. As a result, the electric field strength near the lower part of the drain electrode side of the gate field plate 131 is reduced, and in particular, fluctuations in the electric field strength in the portion between the gate field plate 131 and the source field plate 142 are suppressed immediately after the gate voltage becomes 0V. 【0089】 [Manufacturing Method of Modified Example 4] The manufacturing method of the semiconductor device 100E according to Modified Example 4 of the embodiment differs in part from the manufacturing method of the semiconductor device 100. The steps of the manufacturing method of the semiconductor device 100E are the same up to the step of forming the gate electrode 130 and the gate field plate 131 (Figure 2(d)). After that, for example, using the same method as for forming the insulating film 160, SiO ２ An insulating film 170 containing as the main component is formed. Then, as shown in Figure 17(a), in order to form the source pad 141, source field plate 142, and drain pad 151, the insulating film 170 formed in regions 108, 109, and 115 is etched off, and the upper surfaces of the source electrode 140 and drain electrode 150 are exposed. 【0090】 Finally, as shown in Figure 17(b), the source pad 141, source field plate 142, and drain pad 151 are formed. First, a metal layer made of AlCu is formed over the entire surface, and then the metal layer formed in areas other than region 108, region 109, and region 115 is etched off to form the source pad 141, source field plate 142, and drain pad 151. 【0091】<Modification 5> Figure 18 is a cross-sectional view of a semiconductor device 100F according to Modification 5 of the embodiment. As shown in Figure 18, the semiconductor device 100F is provided with an insulating film 180 compared to the semiconductor device 100 shown in Figure 1, and the tip of the source field plate 142 near the drain electrode 150 extends inclined upward from below with respect to the direction from the source electrode 140 toward the drain electrode 150. As a result, the lower surface of the tip of the source field plate 142 near the drain electrode 150 is macroscopically inclined upward, which can reduce the peak value of the electric field strength near the drain electrode side end of the source field plate 142. The length Lsfp of the source field plate 142 of the semiconductor device 100F is, for example, 2.5 μm to 6.5 μm, and the length Ls of the portion of the tip of the source field plate 142 near the drain electrode 150 that extends inclined upward from below is, for example, 0.5 μm to 2.0 μm. 【0092】 [Manufacturing Method of Modified Example 5] The manufacturing method of the semiconductor device 100F according to Modified Example 5 of the embodiment differs in part from the manufacturing method of the semiconductor device 100. The steps of the manufacturing method of the semiconductor device 100F are the same up to the step of forming the insulating film 170 (Figure 2(f)). Thereafter, as shown in Figure 19(a), an insulating film 180 containing SiN as the main component is formed using the same method as for forming the insulating film 160. 【0093】 As shown in Figure 19(b), the source pad 141, source field plate 142, and drain pad 151 are formed. First, a metal layer made of AlCu is formed over the entire surface, and then the metal layer formed in areas other than region 115 and region 116 is etched off to form the source pad 141, source field plate 142, and drain pad 151. 【0094】<Modification 6> Figure 20 shows a cross-sectional view and a plan view of the semiconductor device 100G according to Modification 6 of the embodiment, and Figure 20(a) is a cross-sectional view of the semiconductor device 100G according to Modification 6 of the embodiment. As shown in Figure 20(a), in the semiconductor device 100G, compared to the semiconductor device 100 shown in Figure 1, a gap is formed between the gate electrode 130 on the p-type semiconductor layer 120 and the gate field plate 131, and the gate electrode 130 on the p-type semiconductor layer 120 and the gate field plate 131 are electrically connected in a region outside the channel layer 111 when viewed from the top surface of the semiconductor device 100G. Figure 20(b) is a plan view of the semiconductor device 100G when viewed from vertically upward, and more specifically, it is a plan view of only the structure of the gate electrode 130 and the gate field plate 131 of the semiconductor device 100G when viewed from vertically upward, and the double dashed line indicates the omission of other components. The dashed lines represent the active region of the semiconductor device 100G, that is, the region where the channel layer 111 and components other than the gate electrode 130 of the semiconductor device 100G stacked on the channel layer 111 exist, and the shaded area in the lower right represents the gate electrode 130 and the gate field plate 131. As a result, the area of ​​the gate field plate 131 extending toward the drain electrode is reduced by the void, thereby reducing the parasitic capacitance between the gate electrode 130 and the drain electrode 150 that affects the switching speed and power loss of the semiconductor device 100G. The length Lg1 of the void in the gate field plate 131 of the semiconductor device 100G is, for example, 0.2 μm to 1.0 μm, and the length Lgfp of the gate field plate 131 is 2.0 μm. 【0095】<Modification 7> Figure 21 is a cross-sectional view of a semiconductor device 100H according to Modification 7 of the embodiment. As shown in Figure 21, in the semiconductor device 100H, compared to the semiconductor device 100 shown in Figure 1, the source field plate 142 is electrically connected to the source electrode 140 via the source pad 141, a gap is formed between the source pad 141 and the source field plate 142, and the source pad 141 and the source field plate 142 are electrically connected in a region outside the channel layer 111 when viewed from the top surface of the semiconductor device 100H. Figure 21(b) is a plan view of the semiconductor device 100H when viewed from vertically upward, and more specifically, it is a plan view of only the structure of the source pad 141 and the source field plate 142 of the semiconductor device 100H when viewed from vertically upward, and the double dashed line indicates the omission of other components. The dashed area represents the active region of the semiconductor device 100H, that is, the region where components other than the channel layer 111 and the gate electrode 130 of the semiconductor device 100H stacked on the channel layer 111 exist, and the shaded area in the lower right represents the source pad 141 and the source field plate 142. This reduces the vertical overlap area between the source field plate 142 and the gate electrode 130 and gate field plate 131, thereby reducing parasitic capacitance between the source electrode 140 and the gate electrode 130, which affects switching speed and power loss. The width Lg2 between the source pad 141 and the p-type semiconductor layer 120 of the semiconductor device 100H is, for example, 1.0 μm, and the width Lg3 between the source field plate 142 and the p-type semiconductor layer 120 is, for example, 0.5 μm to 1.5 μm. 【0096】<Modification 8> Figure 22 is a cross-sectional view of a semiconductor device 100J according to Modification 8 of the embodiment. As shown in Figure 22, the semiconductor device 100J includes a p-type semiconductor layer 125 that is in contact with the barrier layer 112 and the drain electrode 150, compared to the semiconductor device 100 shown in Figure 1. This allows current collapse to be suppressed by the recombination of holes injected from the p-type semiconductor layer 125 with electrons trapped in the traps. The thickness Hdp of the p-type semiconductor layer 125 of the semiconductor device 100J is, for example, 0.185 μm, and the width Ldp is, for example, 0.6 μm to 1.8 μm. 【0097】 [Effects] Below, examples of embodiments obtained from the disclosures of this specification will be given, and the effects obtained from the exemplified embodiments will be explained. 【0098】Embodiment 1 is a semiconductor device 100 on which a GaN-based HEMT (high electron mobility transistor) is formed, comprising: a channel layer 111; a barrier layer 112 formed above the channel layer 111; a source electrode 140, a p-type semiconductor layer 120, and a drain electrode 150 formed above the barrier layer 112 so as not to overlap each other; a gate electrode 130 formed above the p-type semiconductor layer 120; an insulating film 160 covering the barrier layer 112 from the drain electrode side surface of the p-type semiconductor layer 120 to the drain electrode 150, as viewed from above the semiconductor device 100; a gate field plate 131 electrically connected to the gate electrode 130, extending in the direction from the gate electrode 130 toward the drain electrode 150, and covering the drain electrode side surface of the p-type semiconductor layer 120 via the insulating film 160, as viewed from above the semiconductor device 100; and the semiconductor device 1 The semiconductor device 100 comprises, viewed from above, an insulating film 170 covering the gate field plate 131, and a source field plate 142 that is electrically connected to the source electrode 140, extends in the direction from the source electrode 140 toward the drain electrode 150, and, viewed from above the semiconductor device 100, covers the drain electrode side surface of the gate field plate 131 via the insulating film 170. The gate field plate 131 extends from the gate electrode 130 to a position closer to the drain electrode 150 than the drain electrode side surface of the p-type semiconductor layer 120, and the source field plate 142 extends from the source electrode 140 toward the drain electrode 150, with the drain electrode side end of the source field plate 142 being located at least 2.5 μm closer to the drain electrode side surface of the gate field plate 131 toward the drain electrode 150. 【0099】 Such a semiconductor device 100 is equipped with a gate field plate 131 that reduces the electric field concentrated near the edge of the p-type semiconductor layer on the drain electrode side of the channel layer 111, and a source field plate 142 that sufficiently reduces the electric field concentrated near the edge of the gate field plate, thereby suppressing current collapse during hard switching drive when a high voltage is applied to the drain electrode 150. 【0100】Embodiment 2 is the semiconductor device 100 of Embodiment 1, wherein the lowest surface of the gate field plate 131 is located below the uppermost surface of the p-type semiconductor layer 120. 【0101】 In such a semiconductor device 100, the gate field plate 131 is adjacent to the drain electrode side of the p-type semiconductor layer 120. This allows for a sufficient reduction of the electric field near the drain electrode side p-type semiconductor layer edge and the gate field plate edge of the channel layer 111 where the electric field is concentrated, thereby suppressing current collapse during hard switching drive when a high voltage is applied to the drain electrode 150. Furthermore, when a voltage is applied to the gate electrode 130, the electric field generated between the channel layer 111 and the gate electrode 130 can be dispersed to the downwardly protruding gate field plate 131. This prevents a decrease in the current flowing through the drain electrode 150 due to electrons flowing out from 2DEG to the gate electrode 130, and prevents gate potential instability and failure of the insulating film 160 due to the flowing electrons being accelerated by the electric field, causing collision ionization and being trapped in traps present at the interface between the p-type semiconductor layer 120 and the insulating film 160. 【0102】Embodiment 3 is a semiconductor device 100 on which a GaN-based HEMT (high electron mobility transistor) is formed, comprising: a channel layer 111; a barrier layer 112 formed above the channel layer 111; a source electrode 140, a p-type semiconductor layer 120, and a drain electrode 150 formed above the barrier layer 112; a gate electrode 130 formed above the p-type semiconductor layer 120; and, as viewed from the top surface of the semiconductor device 100, an insulating film 160 covering the barrier layer 112 between the drain electrode side surface of the p-type semiconductor layer 120 and the drain electrode 150, electrically connected to the gate electrode 130 and extending in the direction from the gate electrode 130 toward the drain electrode 150, and a semiconductor The semiconductor device 100 comprises, as viewed from the top surface of the device 100, a gate field plate 131 that covers the drain electrode side of the p-type semiconductor layer 120 via an insulating film 160, an insulating film 170 that covers the gate field plate 131 as viewed from the top surface of the semiconductor device 100, and a source field plate 142 that is electrically connected to the source electrode 140, extends in the direction from the source electrode 140 toward the drain electrode 150, and covers the drain electrode side of the gate field plate 131 via the insulating film 170 as viewed from the top surface of the semiconductor device 100, wherein the lowest surface of the gate field plate 131 is located below the highest surface of the p-type semiconductor layer 120. 【0103】 Such a semiconductor device 100 can disperse the electric field generated between the p-type semiconductor layer 120 and the gate electrode 130 when a voltage is applied to the gate electrode 130 onto the gate field plate 131 that protrudes downward. This prevents a decrease in the current flowing through the drain electrode 150 due to electrons flowing out from 2DEG to the gate electrode 130, and prevents gate potential instability and failure of the insulating film 160 due to the outflowing electrons being accelerated by the electric field, causing collision ionization and being trapped in traps present at the interface between the p-type semiconductor layer 120 and the insulating film 160. 【0104】Embodiment 4 is a semiconductor device 100 according to any one of Embodiments 1 to 3, wherein the barrier layer 112 has a recess, the p-type semiconductor layer 120 is formed above the recess, and includes a first extension that, when viewed from the top surface of the semiconductor device 100, extends from the drain electrode side of the recess to a position closer to the drain electrode 150 than the drain electrode side of the recess. 【0105】 In such a semiconductor device 100, the electric field acting on the drain electrode side near the drain electrode side edge of the recess of the p-type semiconductor layer 120 due to the potential difference with the drain electrode 150 is mitigated by the first extended portion of the p-type semiconductor layer 120 being close to the drain electrode side. Furthermore, although the gate length GR is short, the upper surface area of ​​the p-type semiconductor layer 120 increases as the length of the first extended portion increases, so the mutual inductance can be increased while keeping the on-resistance of the semiconductor device 100 low. 【0106】 Embodiment 5 is a semiconductor device 100C on which a GaN-based HEMT (high electron mobility transistor) is formed, comprising a channel layer 111, a barrier layer 112 formed above the channel layer 111, a source electrode 140, a p-type semiconductor layer 120, and a drain electrode 150 formed above the barrier layer 112, and a gate electrode 130 formed above the p-type semiconductor layer 120, wherein the barrier layer 112 has a recess, and the p-type semiconductor layer 120 is formed above the recess, and the semiconductor device 10 The semiconductor device 100C includes, as viewed from the top surface of 0C, a first extension portion extending from the drain electrode side surface of the recess to a position closer to the drain electrode 150 than the drain electrode side surface of the recess, and a second extension portion extending from the source electrode side surface of the recess to a position closer to the source electrode 140 than the source electrode side surface of the recess, as viewed from the top surface of the semiconductor device 100, wherein the length of the first extension portion is greater than the length of the second extension portion in the direction from the source electrode 140 to the drain electrode 150. 【0107】In such a semiconductor device 100C, the electric field acting on the drain electrode side near the drain electrode side end of the recess of the p-type semiconductor layer 120 due to the potential difference with the drain electrode 150 is mitigated by the first extended portion of the p-type semiconductor layer 120 being close to the drain electrode side. Furthermore, by shortening the second extended portion, which does not have an electric field concentration mitigation effect, the resistance between the gate electrode 130 and the source electrode 140 can be reduced, the on-resistance can be reduced, and the transconductance can be improved, compared to when the length of the second extended portion is equal to the length of the first extended portion. 【0108】 Embodiment 6 is a semiconductor device 100 according to any of Embodiments 1 to 5, wherein the thickness of the channel layer 111 is 150 nm or more. 【0109】 In such a semiconductor device 100 or semiconductor device 100C, increasing the thickness of the channel layer 111 widens the gap between the channel layer 111 and carrier traps present in the layers below it, thereby suppressing current collapse caused by the carrier traps. 【0110】 In embodiment 7, the carbon concentration of the channel layer 111 is 2 × 10 １６ cm －３ The semiconductor device 100 is one of the following embodiments 1 to 6. 【0111】 In such a semiconductor device 100 or semiconductor device 100C, carbon acts as a carrier trap, and by having a low carbon concentration in the channel layer 111, current collapse caused by the carrier trap can be suppressed. 【0112】 Embodiment 8 is a semiconductor device 100D according to Embodiments 1 to 7, wherein the p-type semiconductor layer 120 has a p-type layer 123, and the semiconductor device 100D further comprises a cap layer 124 formed between the p-type layer 123 and the gate electrode 130, and the acceptor concentration in the cap layer 124 is lower than the acceptor concentration in the p-type layer 123. 【0113】 Such a semiconductor device suppresses excessive hole injection by increasing the Schottky barrier between the gate electrode 130 and the capping layer 124, thereby suppressing current collapse caused by hole traps. 【0114】Embodiment 9 is a semiconductor device 100E according to any of Embodiments 1 to 4, wherein the source field plate 142 covers the entire drain electrode side surface of the gate field plate 131 when viewed from the drain electrode 150 of the semiconductor device 100E. 【0115】 In such a semiconductor device 100E, the source field plate 142 protrudes so as to block the drain electrode side end of the gate field plate 131, thereby reducing the electric field strength applied to the drain electrode side end of the gate field plate 131, and also reducing the fluctuation in electric field strength between the gate field plate 131 and the source field plate 142 immediately after the voltage applied to the gate electrode 130 becomes 0V. 【0116】 Embodiment 10 is a semiconductor device 100F according to any of embodiments 1 to 4, 9, wherein the tip of the source field plate 142 near the drain electrode 150 extends inclined upward from below with respect to the direction from the source electrode 140 toward the drain electrode 150. 【0117】 In such a semiconductor device 100F, the drain electrode side end of the source field plate 142 is macroscopically inclined with respect to the direction toward the drain electrode 150, which allows for a reduction in the peak value of the electric field strength near the drain electrode side end of the source field plate 142. 【0118】 Embodiment 11 is a semiconductor device 100G according to any of embodiments 1 to 4, 9, or 10, wherein a gap is formed between the gate electrode 130 on the p-type semiconductor layer 120 and the gate field plate 131, and the gate electrode 130 on the p-type semiconductor layer 120 and the gate field plate 131 are electrically connected in a region outside the channel layer 111 when viewed from the upper surface of the semiconductor device 100G. 【0119】 Such a semiconductor device 100G can reduce the parasitic capacitance between the gate electrode and the drain electrode, which affects the switching speed and power loss of the semiconductor device 100G, by reducing the area of ​​the gate field plate 131 that extends toward the drain electrode. 【0120】Embodiment 12 further comprises a source pad 141 formed above the source electrode 140, the source field plate 142 is electrically connected to the source electrode 140 via the source pad 141, a gap is formed between the source pad 141 and the source field plate 142, and the source pad 141 and the source field plate 142 are electrically connected in a region outside the channel layer 111 when viewed from the upper surface of the semiconductor device 100H, wherein the semiconductor device 100H is one of embodiments 1 to 4, 9, 10, or 11. 【0121】 Such a semiconductor device 100H can reduce parasitic capacitance between the source electrode 140 and the gate electrode 130, which affects switching delay time and power loss, by reducing the overlapping area between the source field plate 142 and the gate electrode 130 and gate field plate 131. 【0122】 Embodiment 13 is a semiconductor device 100J according to any of embodiments 1 to 12, further comprising a p-type semiconductor layer 125 that is in contact with the barrier layer 112 and the drain electrode 150. 【0123】 In such a semiconductor device 100J, by providing the p-type semiconductor layer 125 in contact with the drain electrode 150, holes injected from the p-type semiconductor layer 125 recombine with electrons trapped in carrier traps, thereby suppressing the current collapse generated in the semiconductor device 100J. 【0124】 (Other Embodiments) Although semiconductor devices and methods for manufacturing the same according to one or more embodiments have been described above based on embodiments, this disclosure is not limited to these embodiments. Without departing from the spirit of this disclosure, various modifications to these embodiments that a person skilled in the art could conceive of, as well as forms constructed by combining components from different embodiments, are also included within the scope of this disclosure. 【0125】For example, the main components of each semiconductor layer in the semiconductor device 100 are not limited to the examples above. For instance, InGaN may be included as the main component instead of GaN, and GaN may be included as the main component instead of AlGaN. Furthermore, each semiconductor layer may contain AlInGaN, InN, AlN, etc., as its main component. 【0126】 Furthermore, each of the above embodiments may be modified, replaced, added, omitted, etc., within the scope of the claims or their equivalents. 【0127】 This disclosure can be used, for example, in power amplifiers for high-power or high-frequency applications, wireless communication base stations or terminal equipment in which such power amplifiers are used, or wireless power supply devices that perform power transmission using microwaves. 【0128】 100, 100A-100H, 100J Semiconductor device 101-108, 113-116 Region 110 Semiconductor stacked structure 111 Channel layer 112 Barrier layer 112a-112c Recess 120, 125 p-type semiconductor layer 121 Thin film portion 122 Thick film portion 123 p-type layer 124 Cap layer 130 Gate electrode 131 Gate field plate 140 Source electrode 141 Source pad 142 Source field plate 150 Drain electrode 151 Drain pad 160, 170, 180 Insulating film

Claims

1. A semiconductor device on which a GaN-based HEMT (high electron mobility transistor) is formed, comprising: a channel layer; a barrier layer formed above the channel layer; a source electrode, a p-type semiconductor layer, and a drain electrode formed above the barrier layer so as not to overlap each other; a gate electrode formed above the p-type semiconductor layer; a first insulating film covering the barrier layer from the drain electrode side surface of the p-type semiconductor layer to the drain electrode, as viewed from above the semiconductor device; a gate field plate electrically connected to the gate electrode, extending in the direction from the gate electrode toward the drain electrode, and as viewed from the top surface of the semiconductor device, covering the drain electrode side surface of the p-type semiconductor layer via the first insulating film; a second insulating film covering the gate field plate as viewed from above the semiconductor device; and a source field plate electrically connected to the source electrode, extending in the direction from the source electrode toward the drain electrode, and as viewed from the top surface of the semiconductor device, covering the drain electrode side surface of the gate field plate via the second insulating film, wherein the gate field plate extends from the gate electrode to a position closer to the drain electrode than the drain electrode side surface of the p-type semiconductor layer. A semiconductor device wherein the source field plate extends from the source electrode towards the drain electrode, and the drain electrode side end of the source field plate is located at least 2.5 μm closer to the drain electrode side surface of the gate field plate in the direction of the drain electrode.

2. The semiconductor device according to claim 1, wherein the lowest surface of the gate field plate is located below the uppermost surface of the p-type semiconductor layer.

3. A semiconductor device on which a GaN-based HEMT (high electron mobility transistor) is formed, comprising: a channel layer; a barrier layer formed above the channel layer; a source electrode, a p-type semiconductor layer, and a drain electrode formed above the barrier layer; a gate electrode formed above the p-type semiconductor layer; a first insulating film covering the barrier layer from the drain electrode side surface of the p-type semiconductor layer to the drain electrode, as viewed from the top surface of the semiconductor device; a gate field plate electrically connected to the gate electrode, extending in the direction from the gate electrode toward the drain electrode, and covering the drain electrode side surface of the p-type semiconductor layer via the first insulating film, as viewed from the top surface of the semiconductor device; a second insulating film covering the gate field plate as viewed from the top surface of the semiconductor device; and a source field plate electrically connected to the source electrode, extending in the direction from the source electrode toward the drain electrode, and covering the drain electrode side surface of the gate field plate via the second insulating film, as viewed from the top surface of the semiconductor device, wherein the lowest surface of the gate field plate is located below the uppermost surface of the p-type semiconductor layer.

4. The semiconductor device according to any one of claims 1 to 3, wherein the barrier layer has a recess, and the p-type semiconductor layer is formed above the recess and includes a first extension that, when viewed from the upper surface of the semiconductor device, extends from the drain electrode side of the recess to a position closer to the drain electrode than the drain electrode side of the recess.

5. A semiconductor device on which a GaN-based HEMT (high electron mobility transistor) is formed, comprising: a channel layer; a barrier layer formed above the channel layer; a source electrode, a p-type semiconductor layer, and a drain electrode formed above the barrier layer; and a gate electrode formed above the p-type semiconductor layer, wherein the barrier layer has a recess; the p-type semiconductor layer is formed above the recess and includes a first extension portion that, as viewed from the top surface of the semiconductor device, extends from the drain electrode side surface of the recess to a position closer to the drain electrode than the drain electrode side surface of the recess; and a second extension portion that, as viewed from the top surface of the semiconductor device, extends from the source electrode side surface of the recess to a position closer to the source electrode than the source electrode side surface of the recess, wherein in the direction from the source electrode to the drain electrode, the length of the first extension portion is greater than the length of the second extension portion.

6. The semiconductor device according to any one of claims 1 to 5, wherein the thickness of the channel layer is 150 nm or more.

7. The carbon concentration of the channel layer is 2 × 10 １６ cm －３ The semiconductor device according to any one of claims 1 to 6, which is as follows:

8. The semiconductor device according to any one of claims 1 to 7, wherein the p-type semiconductor layer has a p-type layer, and the semiconductor device further comprises a cap layer formed between the p-type layer and the gate electrode, and the concentration of acceptor in the cap layer is lower than the concentration of acceptor in the p-type layer.

9. The semiconductor device according to any one of claims 1 to 4, wherein the source field plate covers the entire drain electrode side surface of the gate field plate in a side view as seen from the drain electrode of the semiconductor device.

10. The semiconductor device according to any one of claims 1 to 4, 9, wherein the tip of the source field plate near the drain electrode extends inclined upward from below with respect to the direction from the source electrode to the drain electrode.

11. A gap is formed between the gate electrode on the p-type semiconductor layer and the gate field plate, and the gate electrode on the p-type semiconductor layer and the gate field plate are electrically connected in a region outside the channel layer when viewed from the upper surface of the semiconductor device, according to any one of claims 1 to 4, 9, or 10.

12. The semiconductor device according to any one of claims 1 to 4, 9, 10, or 11, further comprising a source pad formed above the source electrode, wherein the source field plate is electrically connected to the source electrode via the source pad, a gap is formed between the source pad and the source field plate, and the source pad and the source field plate are electrically connected in a region outside the channel layer as viewed from the upper surface of the semiconductor device.

13. The semiconductor device according to any one of claims 1 to 12, further comprising a p-type layer in contact with the barrier layer and in contact with the drain electrode.

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