Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device including a transistor section and a diode section, the semiconductor device comprising: a drift region of a first conductivity type provided in a semiconductor substrate; and a plurality of trenches extending in a predetermined trench extension direction in an upper portion of the drift region. The transistor section may include base regions of a second conductivity type provided above the drift region and a collector region of the second conductivity type provided below the drift region. The diode section may include anode regions of the second conductivity type provided above the drift region and cathode regions of the first conductivity type provided below the drift region and having a higher doping concentration than the drift region. The cathode regions may include a first cathode section and a second cathode section that is provided closer to the transistor section than is the first cathode section and has a smaller thickness in the depth direction of the semiconductor substrate.

Description

Semiconductor device and method for manufacturing a semiconductor device 【0001】 This invention relates to a semiconductor device and a method for manufacturing a semiconductor device. 【0002】 A semiconductor device is known in which a region of a second conductivity type is formed above the cathode region (see, for example, Patent Document 1 or 2). [Prior Art Documents] [Patent Documents] [Patent Document 1] Japanese Patent Application Publication No. 2021-174924 [Patent Document 2] Japanese Patent Application Publication No. 2019-125597 General disclosure 【0003】 (Problem to be solved) It is desirable to reduce the reverse recovery loss of semiconductor devices. (Means to solve the problem) 【0004】 In a first embodiment of the present invention, a semiconductor device is provided comprising a transistor portion and a diode portion, wherein the semiconductor device comprises a drift region of a first conductivity type provided on a semiconductor substrate, and a plurality of trench portions extending in a predetermined trench extension direction above the drift region. The transistor portion may have a base region of a second conductivity type provided above the drift region, and a collector region of a second conductivity type provided below the drift region. The diode portion may have an anode region of a second conductivity type provided above the drift region, and a cathode region of a first conductivity type provided below the drift region and having a higher doping concentration than the drift region. The cathode region may have a first cathode portion and a second cathode portion provided closer to the transistor portion than the first cathode portion and having a smaller thickness in the depth direction of the semiconductor substrate. 【0005】 In the semiconductor device described above, the second cathode portion may be in contact with a back-side electrode provided in contact with the back surface of the semiconductor substrate. 【0006】 In any of the above semiconductor devices, a second conductivity type region of a second conductivity type may be provided above the second cathode portion and in contact with the upper end of the second cathode portion. 【0007】In any of the semiconductor devices described above, the doping concentration in the second conductivity region may be smaller than the doping concentration in the collector region. 【0008】 In any of the semiconductor devices described above, the second conductivity region may extend from above the second cathode portion toward the transistor portion in the trench arrangement direction of the plurality of trench portions and terminate above the cathode region. 【0009】 In any of the above semiconductor devices, in the trench arrangement direction, L is the distance from the end of the second conductivity region closer to the transistor portion to the end of the second conductivity region further from the transistor portion, and W is the distance from the depth position of the lower end of the plurality of trenches to the depth position of the upper end of the collector region in the depth direction of the semiconductor substrate, such that 0.1W ≤ L ≤ W. 【0010】 In any of the semiconductor devices described above, the collector region may be provided spaced apart from the second conductivity type region. 【0011】 In any of the semiconductor devices described above, at least a portion of the second conductivity type region may be provided above the collector region. 【0012】 In any of the semiconductor devices described above, when L1 is the distance from the boundary position between the collector region and the cathode region in the trench arrangement direction of the plurality of trenches to the end of the second conductivity type region above the collector region, and W is the distance from the depth position of the lower end of the plurality of trenches to the depth position of the upper end of the collector region in the depth direction of the semiconductor substrate, then 0 ≤ L1 ≤ W. 【0013】 In any of the semiconductor devices described above, the second conductivity type region may be provided extending a predetermined distance L1 from the boundary position between the collector region and the cathode region in the trench arrangement direction of the plurality of trenches, and extending a predetermined distance L2 from the side where the collector region is provided, and on the side where the cathode region is provided. In this case, L1 ≤ L2. 【0014】In any of the semiconductor devices described above, the doping concentration in the second conductivity region may be greater than the doping concentration in the collector region. 【0015】 In any of the above semiconductor devices, the thickness of the second conductivity type region in the depth direction of the semiconductor substrate may be greater than 0% of the thickness of the cathode region and 50% or less. 【0016】 In any of the above semiconductor devices, the thickness of the second conductivity type region in the depth direction of the semiconductor substrate may be 0.1 μm or more and 0.3 μm or less. 【0017】 In any of the above semiconductor devices, the thickness of the collector region in the depth direction of the semiconductor substrate may be greater than the thickness of the cathode region. 【0018】 In any of the semiconductor devices described above, the depth position of the upper end of the second conductivity type region may be closer to the front surface of the semiconductor substrate than the depth position of the upper end of the cathode region in the depth direction of the semiconductor substrate. 【0019】 In any of the above semiconductor devices, a lifetime control region may be provided within the semiconductor substrate, extending from the diode portion toward the transistor portion and terminating above the cathode region. 【0020】 In any of the semiconductor devices described above, the lifetime control region may extend from the diode portion toward the transistor portion and terminate at the boundary between the transistor portion and the diode portion. 【0021】 In any of the above semiconductor devices, the lifetime control region may have an ion implantation peak in the depth direction of the semiconductor substrate. The ion implantation peak may attenuate toward the front surface of the semiconductor substrate. 【0022】 In any of the semiconductor devices described above, the end of the second conductivity type region may be positioned closer to the outer peripheral region of the semiconductor substrate than the end of the cathode region in the trench extension direction. 【0023】 In any of the above semiconductor devices, an interlayer insulating film may be provided above the front surface of the semiconductor substrate, with contact holes extending in the trench stretching direction. In the trench stretching direction, the ends of the contact holes may be positioned closer to the outer peripheral region of the semiconductor substrate than the ends of the cathode region. In the trench stretching direction, the ends of the second conductivity type region may be positioned closer to the outer peripheral region of the semiconductor substrate than the ends of the contact holes. 【0024】 In any of the semiconductor devices described above, the cathode region may have a third cathode portion of a second conductivity type having a higher doping concentration than the second conductivity type region. In the trench stretching direction, a region of a first conductivity type including the first cathode portion and the second cathode portion and a region of a second conductivity type including the third cathode portion may be arranged alternately and repeatedly. The second conductivity type region may be provided in the trench stretching direction corresponding to the second cathode portion. 【0025】 In any of the semiconductor devices described above, the second conductivity type region may be provided extending from the end of the second cathode portion in the trench extending direction by a predetermined length L3 when viewed from above. When Pt is the repeating period between the first conductivity type region and the second conductivity type region in the trench extending direction, 0 < L3 < 0.5Pt may be satisfied. 【0026】A second aspect of the present invention provides a method for manufacturing a semiconductor device comprising a transistor portion and a diode portion, comprising the steps of: preparing a semiconductor substrate provided with a drift region of a first conductivity type; forming a plurality of trench portions extended in a predetermined trench extension direction above the drift region; forming a collector region of a second conductivity type below the drift region in the transistor portion; and forming a cathode region of a first conductivity type having a higher doping concentration than the drift region below the drift region in the diode portion. The cathode region may have a first cathode portion and a second cathode portion provided closer to the transistor portion than the first cathode portion and having a smaller thickness in the depth direction of the semiconductor substrate. 【0027】 The above-described method for manufacturing a semiconductor device may include a step of forming a lifetime control region on the semiconductor substrate by irradiating it with ions from the front surface side of the semiconductor substrate. 【0028】 In any of the above methods for manufacturing a semiconductor device, the step of forming the lifetime control region may include a step of irradiating only the diode portion with ions. 【0029】 In any of the above-described methods for manufacturing a semiconductor device, the method may include a step of forming a second conductivity type region of a second conductivity type located above the second cathode portion and in contact with the upper end of the second cathode portion. The steps of forming the cathode region and forming the second conductivity type region may be performed after the step of forming the collector region. 【0030】 It should be noted that the above summary of the invention does not enumerate all of its features. Furthermore, subcombinations of these features may also constitute an invention. 【0031】This is an example of a top view of the semiconductor device 100. This is an example of a top view of the semiconductor device 100. This is an example of a cross-section a-a' in Figure 1B. This is a modified version of the cross-section a-a' in Figure 1B. This is a modified version of the cross-section a-a' in Figure 1B. This is a diagram for explaining the dopant concentration distribution of the semiconductor substrate 10. This is a modified version of the cross-section a-a' in Figure 1B. This is a diagram for explaining the dopant concentration distribution of the semiconductor substrate 10. This is a modified version of the cross-section a-a' in Figure 1B. This is an example of a cross-section b-b' in Figure 1B. This is a modified version of the cross-section b-b' in Figure 1B. This is an example of a method for manufacturing the semiconductor device 100. This is an example of a method for manufacturing the semiconductor device 100. This is a diagram for explaining the concentration distribution of the semiconductor substrate 10 having a lifetime control region 151. 【0032】 The present invention will be described below through embodiments, but these embodiments are not intended to limit the scope of the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention. 【0033】 In this specification, one side of a semiconductor substrate parallel to its depth direction is referred to as "upper," and the other side as "lower." Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as the upper surface, and the other surface as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction in which the semiconductor device is mounted. 【0034】 In this specification, technical matters may be described using the Cartesian coordinate axes X, Y, and Z. The Cartesian coordinate axes merely specify the relative positions of components and do not limit any particular direction. For example, the Z axis does not limit the direction to height relative to the ground. Note that the +Z axis direction and the -Z axis direction are opposite directions. When the sign is not specified and only the Z axis direction is written, it means the direction parallel to the +Z axis and the -Z axis. 【0035】In this specification, orthogonal axes parallel to the upper and lower surfaces of a semiconductor substrate are defined as the X-axis and the Y-axis. Also, an axis perpendicular to the upper and lower surfaces of the semiconductor substrate is defined as the Z-axis. In this specification, the direction of the Z-axis may sometimes be referred to as the depth direction. Further, in this specification, a direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and the Y-axis, may sometimes be referred to as the horizontal direction. 【0036】 In this specification, when referred to as "identical" or "equal", it may include cases having errors due to manufacturing variations or the like. Such errors are, for example, within 10%. 【0037】 In this specification, the conductivity type of a doped region doped with an impurity is described as P-type or N-type. In this specification, an impurity may sometimes mean either an N-type donor or a P-type acceptor, and may be referred to as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to obtain a semiconductor having an N-type conductivity type or a semiconductor having a P-type conductivity type. 【0038】 In this specification, the doping concentration means the concentration of a donor or the concentration of an acceptor in a thermal equilibrium state. In this specification, the net doping concentration means the net concentration obtained by adding, including the polarity of the charge, the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions. As an example, when the donor concentration is N Ｄ and the acceptor concentration is N Ａ , the net doping concentration at an arbitrary position is N Ｄ −N Ａ . In this specification, the net doping concentration may sometimes be simply referred to as the doping concentration. 【0039】Donors have the function of supplying electrons to a semiconductor. Acceptors have the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves. For example, vacancies (V), VOH defects where oxygen (O) and hydrogen (H) are bonded, Si-i-H defects where interstitial silicon (Si-i) is bonded to hydrogen, and CiOi-H defects where interstitial carbon (Ci) is bonded to interstitial oxygen (Oi) and hydrogen, all present in a semiconductor, function as electron-supplying donors. In this specification, these defects may be referred to as hydrogen donors. 【0040】 In this specification, when P+ type or N+ type is mentioned, it means a higher doping concentration than P type or N type, and when P- type or N- type is mentioned, it means a lower doping concentration than P type or N type. Furthermore, when P++ type or N++ type is mentioned in this specification, it means a higher doping concentration than P+ type or N+ type. 【0041】 In this specification, chemical concentration refers to the atomic density of impurities measured independently of the electrical activation state. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration described above can be measured by voltage-capacitance (CV) spectroscopy. Alternatively, the carrier concentration measured by broadened resistance (SR) spectroscopy may be used as the net doping concentration. A carrier refers to an electron or hole charge carrier. The carrier concentration measured by CV or SR spectroscopy may be the value at thermal equilibrium. Furthermore, in the N-type region, since the donor concentration is sufficiently larger than the acceptor concentration, the carrier concentration in that region may be used as the donor concentration. Similarly, in the P-type region, the carrier concentration in that region may be used as the acceptor concentration. In this specification, the doping concentration in the N-type region may be referred to as the donor concentration, and the doping concentration in the P-type region may be referred to as the acceptor concentration. 【0042】Also, when the concentration distribution of donors, acceptors, or net doping has a peak, the peak value may be taken as the concentration of donors, acceptors, or net doping in the region. In cases where the concentration of donors, acceptors, or net doping is substantially uniform, etc., the average value of the concentration of donors, acceptors, or net doping in the region may be taken as the concentration of donors, acceptors, or net doping. 【0043】 The carrier concentration measured by the SR method may be lower than the concentration of donors or acceptors. In the range where current flows when measuring the spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. The decrease in carrier mobility is caused by the scattering of carriers due to the disorder of the crystal structure (disorder) such as lattice defects. The reason for the decrease in carrier concentration is as follows. In the SR method, the spreading resistance is measured, and the carrier concentration is converted from the measured value of the spreading resistance. At this time, the mobility of the carriers is the mobility in the crystalline state. On the other hand, at the position where lattice defects are introduced, although the carrier mobility is decreased, the carrier concentration is calculated based on the carrier mobility in the crystalline state. Therefore, the actual carrier concentration, that is, a value lower than the concentration of donors or acceptors, is obtained. 【0044】 The concentration of donors or acceptors calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element indicating the donors or acceptors. As an example, in a silicon semiconductor, the donor concentration of phosphorus or arsenic that becomes a donor, or the acceptor concentration of boron (boron) that becomes an acceptor is about 99% of these chemical concentrations. On the other hand, the donor concentration of hydrogen that becomes a donor in a silicon semiconductor is about 0.1% to 10% of the chemical concentration of hydrogen. In this specification, the SI unit system is adopted. In this specification, the unit of distance or length may be represented by cm (centimeter). In this case, various calculations may be calculated after converting to m (meter). Regarding the numerical display of powers of 10, for example, the display of 1E+16 indicates 1×10 １６ and the display of 1E-16 indicates 1×10 －１６ is shown. 【0045】 Figure 1A is an example of a top view of a semiconductor device 100. The semiconductor device 100 comprises an active region 110, an outer peripheral region 120, and a gate pad 130. The semiconductor device 100 is a semiconductor chip comprising a transistor section 70 and a diode section 80. 【0046】 The transistor section 70 includes a transistor such as an IGBT (Insulated Gate Bipolar Transistor). The diode section 80 includes a diode such as a freewheel diode (FWD). The semiconductor device 100 in this example is a reverse-conducting IGBT (RC-IGBT) having the transistor section 70 and the diode section 80 on the same chip. In this example, the transistor in the transistor section 70 is an IGBT. 【0047】 The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, or gallium oxide. In this example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has an active region 110 and an outer peripheral region 120. 【0048】 The transistor section 70 and the diode section 80 may be arranged alternately and periodically in the XY plane. The semiconductor device 100 in this example comprises a plurality of transistor sections 70 and a plurality of diode sections 80. The transistor section 70 and the diode section 80 in this example have trench sections extending in the Y-axis direction. However, the transistor section 70 and the diode section 80 may also have trench sections extending in the X-axis direction. 【0049】 The active region 110 includes a transistor section 70 and a diode section 80. The active region 110 is the region in which the main current flows between the front and back surfaces of the semiconductor substrate 10 when the semiconductor device 100 is controlled to the ON state. That is, it is the region in which current flows in the depth direction within the semiconductor substrate 10, from the front surface to the back surface, or from the back surface to the front surface. In this specification, the transistor section 70 and the diode section 80 are referred to as the element section or element region, respectively. 【0050】 Furthermore, in a top view, the region sandwiched between the two element parts is also considered the active region 110. In this example, the region sandwiched between the element parts where the gate metal layer 50 is provided is also included in the active region 110. 【0051】 The gate metal layer 50 is formed from a metal-containing material. For example, the gate metal layer 50 is made of aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy. The gate metal layer 50 is electrically connected to the gate conductive portion of the transistor portion 70 and supplies a gate voltage to the transistor portion 70. In a top view, the gate metal layer 50 is provided so as to surround the outer periphery of the active region 110. The gate metal layer 50 is electrically connected to the gate pad 130 provided in the outer peripheral region 120. The gate metal layer 50 may be provided along the outer peripheral edge of the semiconductor substrate 10. The gate metal layer 50 may have a barrier metal formed of titanium or a titanium compound in the layer below the region formed of aluminum or the like. Also, in a top view, the gate metal layer 50 may be provided between the transistor portion 70 and the diode portion 80. 【0052】 The outer peripheral region 120 is the region between the outer peripheral edge of the semiconductor substrate 10 and the active region 110, as seen from above. The outer peripheral region 120 is provided surrounding the active region 110 as seen from above. The outer peripheral region 120 may have an edge termination structure. The edge termination structure mitigates electric field concentration on the front side of the semiconductor substrate 10. For example, the edge termination structure may have a guard ring, a field plate, a resurf, or a structure combining these. 【0053】 The gate pad 130 is electrically connected to the gate conductive part of the transistor section 70 via the gate metal layer 50. The gate pad 130 is set to the gate potential. In this example, the gate pad 130 is rectangular when viewed from above. 【0054】 Figure 1B shows an example of a top view of the semiconductor device 100. In this example, it shows an enlarged view of region A in Figure 1A. 【0055】The transistor section 70 is a region on the back surface of the semiconductor substrate 10 in which a collector region 22 is provided. The collector region 22 has a second conductivity type. The collector region 22 is, for example, P+ type. 【0056】 The diode section 80 is a region on the back surface of the semiconductor substrate 10 in which a first-conductivity cathode region is provided. The cathode region 82 has a first conductivity type. The cathode region 82 is, for example, N+ type. 【0057】 The semiconductor device 100 in this example comprises, on the front surface of the semiconductor substrate 10, a plurality of trenches including a dummy trench 30 and a gate trench 40, an anode region 11, an emitter region 12, a base region 14, a contact region 15, and an outer peripheral well region 17. The semiconductor device 100 in this example also comprises a front-side electrode 52 and a gate metal layer 50 provided above the front surface of the semiconductor substrate 10. 【0058】 The front-side electrode 52 is provided above the semiconductor substrate 10. The front-side electrode 52 is provided above the gate trench 40, dummy trench 30, anode region 11, emitter region 12, base region 14, contact region 15, and outer peripheral well region 17. The gate metal layer 50 is provided above the outer peripheral well region 17. In this example, the front-side electrode 52 is set to the emitter potential of the transistor 70. The front-side electrode 52 may be an emitter electrode. 【0059】 The gate metal layer 50 is electrically connected to the gate conductive portion of the transistor section 70 and supplies the gate voltage to the transistor section 70. The gate metal layer 50 is electrically connected to the gate pad 130. In a top view, the gate metal layer 50 is provided along the outer circumference of the active region 110. In a top view, the gate metal layer 50 may also be provided between the transistor section 70 and the diode section 80. 【0060】The front-side electrode 52 and the gate metal layer 50 are formed from a metal-containing material. For example, at least a portion of the front-side electrode 52 may be formed from aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy. The front-side electrode 52 may have a barrier metal formed from titanium or a titanium compound in the layer below the region formed from aluminum or the like. The front-side electrode 52 and the gate metal layer 50 are provided separately from each other. 【0061】 The front-side electrode 52 and the gate metal layer 50 are provided above the semiconductor substrate 10, with the interlayer insulating film 38 in between. The interlayer insulating film 38 is omitted in Figure 1B. Contact holes 54, 55, and 56 are provided through the interlayer insulating film 38. 【0062】 The contact hole 55 connects the gate metal layer 50 to the gate conductive portion within the gate trench 40. A plug made of tungsten or the like may be formed inside the contact hole 55. 【0063】 The contact hole 56 connects the front electrode 52 to the dummy conductive part in the dummy trench 30. A plug made of tungsten or the like may be formed inside the contact hole 56. 【0064】 The connecting portion 25 may electrically connect the front-side electrode 52 to the plug inside the contact hole 55. The connecting portion 25 may electrically connect the front-side electrode 52 to the plug inside the contact hole 56. The connecting portion 25 has a conductive material such as polysilicon doped with impurities. In this example, the connecting portion 25 is polysilicon doped with N-type impurities. When viewed from above, the connecting portion 25 covers a larger area than the contact hole 55. When viewed from above, the connecting portion 25 covers a larger area than the contact hole 56. The connecting portion 25 is provided above the front surface of the semiconductor substrate 10 via an insulating film such as an oxide film. 【0065】The gate trenches 40 are arranged at predetermined intervals along a predetermined alignment direction (in this example, the X-axis direction). The gate trenches 40 in this example may have two extended portions 41 that extend along an extension direction (in this example, the Y-axis direction) that is parallel to the front surface of the semiconductor substrate 10 and perpendicular to the alignment direction, and a connecting portion 43 that connects the two extended portions 41. 【0066】 Preferably, at least a portion of the connection portion 43 is formed in a curved shape. By connecting the ends of the two extended portions 41 of the gate trench portion 40, electric field concentration at the ends of the extended portions 41 can be mitigated. At the connection portion 43 of the gate trench portion 40, the gate metal layer 50 may be connected to the gate conductive portion. 【0067】 The dummy trench portion 30 is a trench portion electrically connected to the front-side electrode 52. The dummy trench portion 30, like the gate trench portion 40, is arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). The dummy trench portion 30 in this example, like the gate trench portion 40, may have a U-shape on the front surface of the semiconductor substrate 10. That is, the dummy trench portion 30 may have two extended portions 31 that extend along the stretching direction and a connecting portion 33 that connects the two extended portions 31. 【0068】 The outer periphery well region 17 is a region of a second conductivity type located on the front side of the semiconductor substrate 10, compared to the drift region 18, which will be described later. The outer periphery well region 17 is an example of a well region provided on the edge side of the semiconductor device 100. The outer periphery well region 17 is, for example, of P+ type. The outer periphery well region 17 is formed in a predetermined range from the end of the active region 110 on the side where the gate metal layer 50 is provided. The diffusion depth of the outer periphery well region 17 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. A portion of the gate trench portion 40 and the dummy trench portion 30 on the gate metal layer 50 side is formed in the outer periphery well region 17. The bottom of the extending end of the gate trench portion 40 and the dummy trench portion 30 may be covered by the outer periphery well region 17. 【0069】The contact holes 54 are formed above the emitter region 12 and the contact region 15 in the transistor section 70. The contact holes 54 are also provided above the anode region 11 and the base region 14 in the diode section 80. None of the contact holes 54 are provided above the outer peripheral well regions 17 located at both ends in the stretching direction. Thus, one or more contact holes 54 are formed in the interlayer insulating film 38. The one or more contact holes 54 may be provided extending in the stretching direction. 【0070】 Mesa portions 71 and 81 are mesa portions provided adjacent to the gate trench portion 40 or dummy trench portion 30 in a plane parallel to the front surface of the semiconductor substrate 10. A mesa portion is a part of the semiconductor substrate 10 sandwiched between two adjacent trench portions, and may be the portion from the front surface of the semiconductor substrate 10 to the depth of the deepest bottom of each trench portion. The extended portion of each trench portion may be considered as a single trench portion. That is, the region sandwiched between two extended portions may be considered as a mesa portion. 【0071】 The mesa portion 71 is provided in the transistor portion 70 adjacent to at least one of the dummy trench portion 30 or the gate trench portion 40. On the front surface of the semiconductor substrate 10, the mesa portion 71 has an outer well region 17, an emitter region 12, a base region 14, and a contact region 15. In the mesa portion 71, the emitter region 12 and the contact region 15 are provided alternately in the stretching direction. 【0072】The mesa portion 81 is provided in the diode portion 80 in the region sandwiched between adjacent dummy trench portions 30. On the front surface of the semiconductor substrate 10, the mesa portion 81 has an anode region 11, a base region 14, and an outer peripheral well region 17. The mesa portion 81 has an outer peripheral well region 17 at the ends of the plurality of trench portions in the trench extension direction. The base region 14 is provided inside the outer peripheral well region 17 in the mesa portion 81. The anode region 11 is provided inside the base region 14 in the mesa portion 81. The anode region 11 may extend from one base region 14 to the other base region 14 of the mesa portion 81 in the trench extension direction of the plurality of trench portions. 【0073】 The anode region 11 is a region of a second conductivity type provided on the front side of the semiconductor substrate 10 in the diode portion 80. The anode region 11 is, for example, P-type. The anode region 11 may be provided extending in the alignment direction from one of the two trench portions flanking the mesa portion 81 to the other. The emitter region 12 is also provided below the contact hole 54. 【0074】 The emitter region 12 is a first conductivity type region with a higher doping concentration than the drift region 18. The emitter region 12 is, for example, N+ type. An example of a dopant for the emitter region 12 is arsenic (As). The emitter region 12 is provided on the front surface of the mesa portion 71, in contact with the gate trench portion 40. The emitter region 12 may extend in the alignment direction from one of the two trench portions flanking the mesa portion 71 to the other. The emitter region 12 is also provided below the contact hole 54. 【0075】 Furthermore, the emitter region 12 may or may not be in contact with the dummy trench portion 30. In this example, the emitter region 12 is in contact with the dummy trench portion 30. 【0076】The base region 14 is a second conductivity type region provided on the front side of the semiconductor substrate 10 in the transistor portion 70 and the diode portion 80. The base region 14 is, for example, P-type. The doping concentration of the base region 14 may be the same as, or greater than, the doping concentration of the anode region 11. The base region 14 may be provided at both ends of the mesa portion 71 and mesa portion 81 in the stretching direction on the front surface of the semiconductor substrate 10. Note that Figure 1B shows only one end of the base region 14 in the stretching direction. 【0077】 The contact region 15 is a region of a second conductivity type with a higher doping concentration than the base region 14. The contact region 15 is, for example, of the P+ type. In this example, the contact region 15 is provided on the front surface of the mesa portion 71. The contact region 15 may be provided in the alignment direction from one of the two trench portions flanking the mesa portion 71 to the other. The contact region 15 may or may not be in contact with the gate trench portion 40. Also, the contact region 15 may or may not be in contact with the dummy trench portion 30. In this example, the contact region 15 is in contact with the dummy trench portion 30 and the gate trench portion 40. The contact region 15 is also provided below the contact hole 54. The contact region 15 may also be provided on the mesa portion 81. 【0078】 Figure 2 shows an example of the a-a' cross-section in Figure 1B. The a-a' cross-section is the XZ plane passing through the emitter region 12 in the transistor section 70. The semiconductor device 100 in this example has a semiconductor substrate 10 with an anode region 11, an emitter region 12, a base region 14, a storage region 16, a drift region 18, a second conductivity type region 19, a field stop region 20, a collector region 22, and a cathode region 82 in the a-a' cross-section, an interlayer insulating film 38, a front-side electrode 52, and a back-side electrode 24. The front-side electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38. 【0079】The drift region 18 is a region of a first conductivity type provided on the semiconductor substrate 10. In this example, the drift region 18 is N-type. The drift region 18 may be a region remaining on the semiconductor substrate 10 without other doping regions being formed. That is, the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10. 【0080】 The field stop region 20 is a region of the first conductivity type located below the drift region 18. In this example, the field stop region 20 is N-type. The doping concentration of the field stop region 20 may be higher than the doping concentration of the drift region 18. The field stop region 20 prevents the depletion layer spreading from the lower surface of the base region 14 from reaching the collector region 22 of the second conductivity type and the cathode region 82 of the first conductivity type. 【0081】 The collector region 22 is located below the drift region 18 in the transistor section 70. In this example, the collector region 22 is located below the field stop region 20. The collector region 22 has a predetermined thickness W22 in the depth direction of the semiconductor substrate 10. The predetermined thickness W22 may be the same as or different from the thickness W181 of the first cathode section 181, which will be described later. In the example of Figure 2, the thickness W22 of the collector region 22 is the same as the thickness W181 of the first cathode section 181. The thickness W22 of the collector region 22 may be 0.1 μm or more, 0.5 μm or more, or 1 μm or more. The thickness W22 of the collector region 22 may be 3 μm or less, 2 μm or less, 1 μm or less, or 0.5 μm or less. 【0082】 The cathode region 82 is located below the drift region 18 in the diode section 80 and is a first conductivity type region with a higher doping concentration than the drift region 18. In this example, the cathode region 82 is located below the field stop region 20. The boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor section 70 and the diode section 80. The cathode region 82 has a first cathode section 181 and a second cathode section 182. 【0083】The first cathode portion 181 is a region of a first conductivity type located below the field stop region 20 in the diode portion 80. The first cathode portion 181 is, for example, of the N+ type. 【0084】 The second cathode portion 182 is provided in the diode portion 80 closer to the transistor portion 70 than the first cathode portion 181, and is a first conductivity type region in which the thickness in the depth direction of the semiconductor substrate 10 is smaller than that of the first cathode portion 181. The second cathode portion 182 is, for example, an N+ type. The doping concentration of the second cathode portion 182 may be the same as or different from the doping concentration of the first cathode portion 181. 【0085】 The thickness W182 of the second cathode portion 182 is smaller than the thickness W181 of the first cathode portion 181. For example, the thickness W182 of the second cathode portion 182 is 50% or more and 70% or less of the thickness W181 of the first cathode portion 181. The thickness W182 of the second cathode portion 182 may be 90% or less, 80% or less, 70% or less, or 60% or less of the thickness W181 of the first cathode portion 181. The thickness W182 of the second cathode portion 182 may be 10% or more, 20% or more, 30% or more, 40% or more, 50% or more, 60% or more, or 70% or more of the thickness W181 of the first cathode portion 181. 【0086】 The thickness W181 of the first cathode portion 181 may be 0.1 μm or more, and may be 0.5 μm or less. For example, the thickness W181 of the first cathode portion 181 is 0.3 μm. The thickness W182 of the second cathode portion 182 may be 0.1 μm or more, and may be 0.3 μm or less. For example, the thickness W182 of the second cathode portion 182 is 0.2 μm. The thickness W181 of the first cathode portion 181 may also be the thickness of the cathode region 82. 【0087】The second cathode portion 182 contacts the back-side electrode 24 on the back surface 23 of the semiconductor substrate 10. The back-side electrode 24 is formed on the back surface 23 of the semiconductor substrate 10. The back-side electrode 24 is made of a conductive material such as metal. The back-side electrode 24 may be a collector electrode. In the diode portion 80, the contact between the second cathode portion 182, which is of the first conductivity type, and the back-side electrode 24 on the back surface 23 of the semiconductor substrate 10 improves the forward voltage Vf of the diode portion 80 compared to the case where the region of the second conductivity type and the back-side electrode 24 are in contact. 【0088】 The second conductivity type region 19 is a region of the second conductivity type provided above the second cathode portion 182 and in contact with the upper end of the second cathode portion 182. In this example, the second conductivity type region 19 is provided on the entire upper surface of the second cathode portion 182. The doping concentration of the second conductivity type region 19 may be smaller than the doping concentration of the base region 14 and may be smaller than the doping concentration of the collector region 22. The second conductivity type region 19 is, as an example, P-type. 【0089】 The second conductivity region 19 does not have to be provided above the collector region 22. The second conductivity region 19 may extend from above the second cathode region 182 toward the transistor region 70 in the trench arrangement direction of the plurality of trenches (in this example, the X direction) and terminate above the cathode region 82. In this example, the second conductivity region 19 extends from above the second cathode region 182 toward the transistor region 70 and terminates at the boundary position between the collector region 22 and the cathode region 82. By providing the second conductivity region 19, hole injection from the transistor region 70 toward the diode region 80 can be suppressed, and the reverse recovery loss Err of the semiconductor device 100 can be reduced. 【0090】 The second conductivity region 19 has a predetermined length L in the trench arrangement direction. The length L may be the distance from the end of the second conductivity region 19 closer to the transistor portion 70 to the end of the second conductivity region 19 further away from the transistor portion 70, in the trench arrangement direction. In this example, the length L is the distance from the boundary position of the collector region 22 and the cathode region 82 to the boundary position of the first cathode portion 181 and the second cathode portion 182. 【0091】 The length L satisfies 0.1W ≤ L ≤ W, where W is the distance from the depth position of the lower end of the multiple trenches to the depth position of the upper end of the collector region 22 in the depth direction of the semiconductor substrate 10. The length L may also satisfy 0.2W ≤ L, 0.3W ≤ L, and 0.5W ≤ L. The length L may also satisfy L ≤ 0.8W, L ≤ 0.5W, and L ≤ 0.3W. As the distance W increases, the range over which holes flow from the transistor section 70 to the diode section 80 widens. Therefore, by changing the length L according to the distance W, the reverse recovery loss Err of the semiconductor device 100 can be reduced without lowering the forward voltage Vf of the diode section 80. 【0092】 The second conductivity region 19 has a predetermined thickness W19 in the depth direction of the semiconductor substrate 10. The thickness W19 of the second conductivity region 19 is smaller than the thickness of the cathode region 82. The thickness W19 of the second conductivity region 19 in the depth direction of the semiconductor substrate 10 may be greater than 0% of the thickness of the cathode region 82 and 50% or less. For example, the thickness W19 of the second conductivity region 19 is 30% or more and 50% or less of the thickness of the cathode region 82. In the depth direction of the semiconductor substrate 10, the thickness W19 of the second conductivity region 19 may be 0.1 μm or more and 0.3 μm or less. 【0093】 The depth position of the upper end of the second conductivity type region 19 in the depth direction of the semiconductor substrate 10 may be the same as or different from the depth position of the upper end of the cathode region 82. In this example, the depth position of the upper end of the second conductivity type region 19 is the same as the depth position of the upper end of the first cathode portion 181. 【0094】 The anode region is a second conductivity type region located above the drift region 18 in the mesa portion 81 of the diode portion 80. The anode region 11 is provided in contact with the dummy trench portion 30. The anode region 11 may also be provided in contact with the gate trench portion 40. 【0095】The emitter region 12 is a first-conductivity region located above the base region 14 in the mesa portion 71. The emitter region 12 is provided in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30. 【0096】 The base region 14 is a second conductivity type region located above the drift region 18 in the mesa region 71 of the transistor region 70. The doping concentration of the base region 14 may be the same as, or greater than, the doping concentration of the anode region 11. The base region 14 is provided in contact with the gate trench region 40. The base region 14 may be provided in contact with the dummy trench region 30. 【0097】 The storage region 16 is a first conductivity type region located on the front surface 21 side of the semiconductor substrate 10, relative to the drift region 18. In this example, the storage region 16 is N+ type. In this example, the storage region 16 is provided in the transistor section 70 and not in the diode section 80. The storage region 16 may also be provided in the diode section 80. 【0098】 The storage region 16 is provided in contact with the gate trench portion 40. The storage region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration of the storage region 16 is higher than the doping concentration of the drift region 18. By providing the storage region 16, the carrier injection promotion effect (IE effect) can be enhanced, and the on-voltage of the transistor portion 70 can be reduced. 【0099】One or more gate trenches 40 and one or more dummy trenches 30 are provided on the front surface 21. Each trench extends from the front surface 21 to the drift region 18. In regions where at least one of the anode region 11, emitter region 12, base region 14, contact region 15, and storage region 16 is provided, each trench penetrates these regions as well and reaches the drift region 18. The statement that a trench penetrates a doping region is not limited to those manufactured in the order of forming the doping region before forming the trenches. Even when doping regions are formed between trenches after the trenches have been formed, the trenches are still considered to penetrate the doping region. 【0100】 The gate trench portion 40 has a gate trench formed on the front surface 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor of the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench, on the inside of the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate trench portion 40 is covered on the front surface 21 by an interlayer insulating film 38. 【0101】 The gate conductive portion 44 includes a region in the depth direction of the semiconductor substrate 10 that faces an adjacent base region 14 on the mesa portion 71 side, with the gate insulating film 42 in between. When a predetermined voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is created on the surface layer of the interface in contact with the gate trench within the base region 14. 【0102】The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and is formed inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 is covered on the front surface 21 by an interlayer insulating film 38. 【0103】 The interlayer insulating film 38 is provided above the front surface 21. A front surface side electrode 52 is provided above the interlayer insulating film 38. The interlayer insulating film 38 is provided with one or more contact holes 54 for electrically connecting the front surface side electrode 52 and the semiconductor substrate 10. Contact holes 55 and 56 may also be provided through the interlayer insulating film 38. 【0104】 The lifetime control region 151 is a region in the semiconductor substrate 10 in which lifetime killers have been intentionally introduced by injecting impurities or the like. The lifetime values ​​of electron or hole carriers in the region in which lifetime killers have been intentionally introduced are smaller than the lifetimes of carriers in the region in which lifetime killers have not been intentionally introduced. The lifetime killers are carrier recombination centers and may be crystal defects, such as vacancies, double vacancies, dangling bonds formed by vacancies, composite defects between these and the elements constituting the semiconductor substrate 10, dislocations, noble gas elements such as helium and neon, and metallic elements such as platinum. As an example, the lifetime control region 151 is formed by irradiating the depth position with ions such as helium. 【0105】 The lifetime control region 151 is provided on the front surface 21 side of the semiconductor substrate 10. The lifetime control region 151 is selectively formed at a predetermined depth position between the center of the semiconductor substrate 10 in the depth direction and the front surface 21 of the semiconductor substrate 10. 【0106】In this example, the lifetime control region 151 is provided in the diode section 80 and not in the transistor section 70. The lifetime control region 151 is provided inside the semiconductor substrate 10, extending from the diode section 80 toward the transistor section 70 and terminating above the cathode region 82. In this example, the lifetime control region 151 extends from the diode section 80 toward the transistor section 70 and terminates at the boundary between the transistor section 70 and the diode section 80. 【0107】 By providing a lifetime control region 151 in the diode section 80, the carrier lifetime in the diode section 80 can be adjusted to reduce the reverse recovery loss Err of the semiconductor device 100. Furthermore, when forming the lifetime control region 151 by irradiating the semiconductor substrate 10 with ions such as helium from the front surface 21, defects may occur in the insulating film of multiple trench sections, causing fluctuations in the threshold voltage, etc. In this example, since a lifetime control region 151 is not provided in the transistor section 70, the gate insulating film 42, etc. in the transistor section 70 are not damaged. Therefore, fluctuations in the threshold voltage, etc. in the transistor section 70 can be suppressed. 【0108】 Figure 3 shows a modified example of the a-a' section in Figure 1B. The differences from Figure 2 will be explained using Figure 3. 【0109】The example in Figure 3 differs from the example in Figure 2 in that the second conductivity region 19 is spaced apart from the collector region 22. The second conductivity region 19 is spaced apart from the collector region 22 by a predetermined distance d19. The predetermined distance d19 may be greater than the thickness W22 of the collector region 22 in the depth direction of the semiconductor substrate 10. The distance d19 may be 0.1 μm or more, 1 μm or more, 30 μm or more, or 100 μm or more. The distance d19 may be 300 μm or less, 200 μm or less, 100 μm or less, 50 μm or less, or 30 μm or less. In one example, the distance d19 is 1 μm. Even when the second conductivity region 19 is spaced apart from the collector region 22, hole injection from the transistor portion 70 to the diode portion 80 can be suppressed, and the reverse recovery loss Err of the semiconductor device 100 can be reduced. 【0110】 Figure 4A shows a modified example of the a-a' section in Figure 1B. The differences from Figure 2 will be explained using Figure 4A. 【0111】 In the example shown in Figure 4A, at least a portion of the second conductivity region 19 is provided above the collector region 22, which is different from the example in Figure 2. In this example, the second conductivity region 19 is provided across both the cathode region 82 and the collector region 22. That is, in the trench arrangement direction, the second conductivity region 19 extends from above the second cathode portion 182 toward the transistor portion 70 and terminates above the collector region 22. By providing at least a portion of the second conductivity region 19 above the collector region 22, holes that have flowed from the transistor portion 70 to the diode portion 80 can be more easily released back to the transistor portion 70, thereby reducing the reverse recovery loss Err of the semiconductor device 100. 【0112】The second conductivity region 19 is provided so as to extend a predetermined length L1 from the boundary position between the collector region 22 and the cathode region 82 in the trench arrangement direction toward the side where the collector region 22 is provided, and terminate above the collector region 22. That is, in the trench arrangement direction, the distance from the boundary position between the collector region 22 and the cathode region 82 to the end of the second conductivity region 19 above the collector region 22 is L1. The length L1 satisfies 0 ≤ L1 ≤ W, where W is the distance from the depth position of the lower end of the plurality of trenches to the depth position of the upper end of the collector region 22 in the depth direction of the semiconductor substrate 10. 【0113】 The second conductivity region 19 is provided so as to extend a predetermined length L2 from the boundary position between the collector region 22 and the cathode region 82 in the trench arrangement direction toward the side where the cathode region 82 is provided, and terminate above the cathode region 82. That is, the width of the second conductivity region 19 in the trench arrangement direction is L1 + L2. 【0114】 In this example, length L2 satisfies L1 ≤ L2. That is, in the trench arrangement direction, the width of the second conductivity type region 19 provided above the collector region 22 is less than or equal to the width of the second conductivity type region 19 provided above the cathode region 82. Length L1 may be 80% or less, 60% or less, or 50% or less of length L2. 【0115】 Figure 4B is a diagram illustrating the dopant concentration distribution of the semiconductor substrate 10. The m-m' cross section is a cross section of the transistor portion 70 that does not pass through the second conductivity type region 19. The n-n' cross section is a cross section of the transistor portion 70 that passes through the second conductivity type region 19. In this example, the net doping concentration distribution in the Z-axis direction is shown for the m-m' and n-n' cross sections. 【0116】Referring to the m-m' cross section, the doping concentration of the second conductivity type dopant in the collector region 22 is highest on the back surface 23 and decreases toward the front surface 21. Referring to the n-n' cross section, the doping concentration of the second conductivity type dopant decreases more rapidly toward the front surface 21 in the region where the second conductivity type region 19 is provided than in the region where the second conductivity type region 19 is not provided. That is, the doping concentration in the second conductivity type region 19 is lower than the doping concentration in the collector region 22. 【0117】 As an example, such a concentration distribution can be achieved by separately forming a collector region 22 below the region where the second conductivity type region 19 is provided and a collector region 22 below the region where the second conductivity type region 19 is not provided. After forming the collector region 22 over the entire surface of the back surface 23 of the semiconductor substrate 10 in the transistor section 70, a second conductivity type region 19 with a lower doping concentration than the collector region 22 may be formed in a part of the collector region 22 by injecting a dopant of the first conductivity type. 【0118】 Figure 5A shows a modified example of the a-a' section in Figure 1B. The differences from Figure 4A will be explained using Figure 5A. 【0119】 In the example shown in Figure 5A, the doping concentration in the second conductivity region 19 is greater than that of the collector region 22, which is different from the example in Figure 4A. The doping concentration in the second conductivity region 19 may have a gradient in the trench arrangement direction. In this example, the doping concentration of the second conductivity region 19 located above the collector region 22 is greater than that of the second conductivity region 19 located above the cathode region 82. For example, the second conductivity region 19 located above the collector region 22 is P+ type, and the second conductivity region 19 located above the cathode region 82 is P type. Alternatively, the doping concentration of the second conductivity region 19 located above the cathode region 82 may be greater than that of the second conductivity region 19 located above the collector region 22. 【0120】Figure 5B is a diagram illustrating the dopant concentration distribution of the semiconductor substrate 10. The o-o' cross section is a cross section of the transistor portion 70 that passes through the second conductivity type region 19. In this example, the net doping concentration distribution in the Z-axis direction of the o-o' cross section is shown. In Figure 5B, the net doping concentration distribution in the Z-axis direction of a cross section that does not pass through the second conductivity type region 19 is shown by a dotted line. 【0121】 Referring to the o-o' cross section, the second conductivity type region 19 in this example has a doping concentration peak P1. The doping concentration of the second conductivity type region 19 is greater than that of the collector region 22 shown by the dotted line. As an example, after forming the collector region 22 over the entire surface of the back surface 23 of the semiconductor substrate 10 in the transistor section 70, injecting a dopant of the second conductivity type can form a second conductivity type region 19 with a higher doping concentration than the collector region 22 in a part of the collector region 22. 【0122】 Figure 6 shows a modified example of the a-a' section in Figure 1B. The differences from Figure 2 will be explained using Figure 6. 【0123】 The example in Figure 6 differs from the example in Figure 2 in that the thickness W22 of the collector region 22 and the thickness W82 of the cathode region in the depth direction of the semiconductor substrate 10 are different. In this example, in the depth direction of the semiconductor substrate 10, the thickness W22 of the collector region 22 is thicker than the thickness W82 of the cathode region 82. The thickness W22 of the collector region 22 may be 1.1 times or more the thickness W82 of the cathode region 82, and may be 1.2 times or more. The thickness W22 of the collector region 22 may be 0.5 μm or more, and may be 0.8 μm or less. In one example, the thickness W22 of the collector region 22 is 0.6 μm. 【0124】The thickness W19 of the second conductivity region 19 may be changed according to the thickness W22 of the collector region 22. In the embodiment where the thickness W22 of the collector region 22 is thicker than the thickness W82 of the cathode region 82, the thickness W19 of the second conductivity region 19 may be thicker than in the embodiment where the thickness W22 of the collector region 22 is the same as the thickness W82 of the cathode region 82. The thickness W19 of the second conductivity region 19 may be thicker than the thickness W82 of the cathode region 82. In this example, the thickness W19 of the second conductivity region 19 is 0.4 μm or more and 0.8 μm or less. 【0125】 In the depth direction of the semiconductor substrate 10, the depth position of the upper end of the second conductivity region 19 may differ from the depth position of the upper end of the cathode region 82. In this example, the depth position of the upper end of the second conductivity region 19 is set closer to the front surface 21 of the semiconductor substrate 10 than the depth position of the upper end of the cathode region 82. Even in this case, hole injection from the transistor portion 70 to the diode portion 80 can be suppressed, and the reverse recovery loss Err of the semiconductor device 100 can be reduced. 【0126】 Figure 7A shows an example of the b-b' cross-section in Figure 1B. The b-b' cross-section is the YZ plane passing through the contact hole 54 in the diode section 80. 【0127】 The cathode region 82 may have a third cathode portion 183 of the second conductivity type with a higher doping concentration than the second conductivity type region 19. The third cathode portion 183 is, for example, of the P+ type. The third cathode portion 183 may have the same thickness as the second cathode portion 182 in the depth direction of the semiconductor substrate 10. 【0128】 The diode portion 80 may have a structure in which a region of a first conductivity type including a first cathode portion 181 and a second cathode portion 182 and a region of a second conductivity type including a third cathode portion 183 are alternately and repeatedly arranged in the trench extension direction. In the b-b' cross section, the back surface 23 of the semiconductor substrate 10 has a structure in which a second cathode portion 182 of the first conductivity type and a third cathode portion 183 of the second conductivity type are alternately and repeatedly arranged in the trench extension direction. 【0129】The second conductivity region 19 is provided above the second cathode portion 182 and the third cathode portion 183. The second conductivity region 19 may be provided so as to cover the upper surfaces of the second cathode portion 182 and the third cathode portion 183. In the trench extension direction, the end Y19 of the second conductivity region 19 may be provided on the negative side in the Y-axis direction compared to the end Y182 of the second cathode portion 182. In this example, in the trench extension direction, the end of the second conductivity region 19 is provided closer to the outer peripheral region 120 of the semiconductor substrate 10 than the end of the cathode region 82. 【0130】 In the trench extension direction, the end Y54 of the contact hole 54 may be located on the negative side in the Y-axis direction compared to the end Y182 of the second cathode portion 182. In this example, in the trench extension direction, the end of the contact hole 54 is located closer to the outer peripheral region 120 of the semiconductor substrate 10 than the end of the cathode region 82. In the trench extension direction, the end Y19 of the second conductivity region 19 may be located on the negative side in the Y-axis direction compared to the end Y54 of the contact hole 54. In this example, in the trench extension direction, the end of the second conductivity region 19 is located closer to the outer peripheral region 120 of the semiconductor substrate 10 than the end of the contact hole 54. The end Y54 of the contact hole 54 may be located between the end Y19 of the second conductivity region 19 and the end Y182 of the second cathode portion 182. 【0131】 Figure 7B shows a modified example of the b-b' cross-section in Figure 1B. The differences between Figure 7B and Figure 7A will be explained using Figure 7B. 【0132】 In the example of Figure 7B, the second conductivity type region 19 is provided corresponding to the second cathode portion 182 in the trench extension direction, which differs from the example of Figure 7A. The second conductivity type region 19 is provided so as to cover the upper surface of the second cathode portion 182 and so as to cover at least a part of the upper surface of the third cathode portion 183. Above the third cathode portion 183, there may be an area where the second conductivity type region 19 is not provided. 【0133】The second conductive region 19 is provided as an extension of a predetermined length L3 from the end of the second cathode portion 182 in the trench extending direction when viewed from above. The second conductive region 19 may be provided as an extension of a length L3 from both ends of the second cathode portion 182 in the trench extending direction. This allows the second conductive region 19 to be provided so as to cover the upper surface of the second cathode portion 182. 【0134】 The length L3 satisfies the condition 0 < L3 < 0.5Pt, where Pt is the repeating period between the first conductivity type region and the second conductivity type region in the trench extension direction. In this example, the repeating period Pt is the sum of the width of the second cathode portion 182 and the width of the third cathode portion 183 in the trench extension direction. By satisfying 0 < L3 for length L3, the upper surface of the second cathode portion 182 is covered with the second conductivity type region 19, thereby reducing the reverse recovery loss Err of the semiconductor device 100. 【0135】 Figure 8 shows an example of a method for manufacturing the semiconductor device 100. In this example, the order of each step may be changed as appropriate. 【0136】 In step S100, a semiconductor substrate 10 is prepared, which has a first conductivity type drift region 18. The drift region 18 may be a region remaining in the semiconductor substrate 10 where no other doping regions have been formed. In step S100, the semiconductor substrate 10 with the drift region 18 may be fabricated by growing single crystal silicon. 【0137】 In step S110, a plurality of trenches are formed above the drift region 18, extending in a predetermined trench stretching direction. Step S110 may include the steps of forming a plurality of trenches on the front surface 21 of the semiconductor substrate 10, forming a trench insulating film by thermal oxidation of the bottom and inner walls of the trenches, and forming trench conductive parts inside the trench insulating film. 【0138】In step S120, a collector region 22 of the second conductivity type is formed on the semiconductor substrate 10. The collector region 22 is formed below the drift region 18 in the transistor section 70. The collector region 22 may be formed by thermal diffusion of a dopant of the second conductivity type introduced on the back surface 23 of the semiconductor substrate 10. 【0139】 In step S130, a cathode region 82 of the first conductivity type is formed on the semiconductor substrate 10. The cathode region 82 is formed below the drift region 18 in the diode portion 80. The doping concentration of the cathode region 82 is higher than that of the drift region 18. The cathode region 82 may be formed by thermal diffusion of a dopant of the first conductivity type introduced on the back surface 23 of the semiconductor substrate 10. Step S130, in which the cathode region 82 is formed, may be performed after step S120, in which the collector region 22 is formed. 【0140】 The cathode region 82 has a first cathode portion 181 and a second cathode portion 182 which is provided closer to the transistor portion 70 than the first cathode portion 181 and has a thickness in the depth direction of the semiconductor substrate 10 that is smaller than that of the first cathode portion 181. In step S130, the first cathode portion 181 and the second cathode portion 182 may be formed simultaneously or separately. Step S130 for forming the cathode region 82 may include the step of forming the first cathode portion 181 and the step of forming the second cathode portion 182, or it may include the step of forming the first cathode portion 181 and the second cathode portion 182. 【0141】 In step S140, a second conductivity type region 19 is formed. The second conductivity type region 19 is formed above the second cathode portion 182 and in contact with the second cathode portion 182. The second conductivity type region 19 may be formed by injecting a second conductivity type dopant from the front surface 21 side of the semiconductor substrate 10, or by injecting a second conductivity type dopant from the back surface 23 side of the semiconductor substrate 10. Step S140, in which the second conductivity type region 19 is formed, may be performed after step S120, in which the collector region 22 is formed. 【0142】The step S130 for forming the cathode region 82 and the step S140 for forming the second conductivity region 19 may be performed in either order. The second conductivity region 19 may be formed by injecting a dopant of the second conductivity type into a part of the cathode region 82 of the first conductivity type. After the second conductivity region 19 is formed, the cathode region 82 having a first cathode portion 181 and a second cathode portion 182 may be formed by thermal diffusion of the dopant of the first conductivity type introduced into the back surface 23 of the semiconductor substrate 10. In this example, the second conductivity region 19 is formed after the cathode region 82 is formed. 【0143】 In step S150, a lifetime control region 151 is formed on the semiconductor substrate 10. In step S150, the lifetime control region 151 may be formed by irradiating the semiconductor substrate 10 with ions such as helium from the front surface 21 side. By irradiating the semiconductor substrate 10 with ions from the front surface 21 side, the ion irradiation position can be made shallower, and the depth position of the lifetime control region 151 can be controlled with high precision. In addition, compared to the case where ions such as helium are irradiated from the back surface 23 side of the semiconductor substrate 10, the acceleration energy for irradiating with ions such as helium can be reduced, so the cost of masks, etc. can be reduced. The acceleration energy for irradiating with ions such as helium may be a value such that the irradiated ions do not penetrate (go through) the semiconductor substrate 10. 【0144】 Figure 9 shows an example of a manufacturing method for the semiconductor device 100. Using Figure 9, we will explain in detail step S150, in which a lifetime control region 151 is formed on the semiconductor substrate 10. 【0145】 Step S150, which forms a lifetime control region 151 on the semiconductor substrate 10, includes step S155, in which only the diode portion 80 is irradiated with ions. In step S155, a mask 60 is formed above the transistor portion 70, and ions such as helium are irradiated from the front surface 21 side, thereby irradiating only the diode portion 80 with ions and forming the lifetime control region 151. 【0146】The mask 60 is used in the process of forming the lifetime control region 151. The mask 60 may be formed by applying a resist or the like and patterning it into a predetermined shape. The lifetime control region 151 is not formed in the area covered by the mask 60. 【0147】 The mask 60, formed by applying a resist or the like, may be formed so as to be in contact with a structure formed on the front surface 21 of the semiconductor substrate 10. In this example, the structure formed on the front surface 21 of the semiconductor substrate 10 is the front-side electrode 52. Hard masks made of materials such as metal or silicon must be formed at a predetermined distance (in the +Z axis direction) from the front-side electrode 52 to the outside of the front surface 21 (+Z axis direction) to avoid damaging or degrading structures such as electrodes, protective films, and interlayer insulating films formed on the front surface 21 of the semiconductor substrate 10. As a result, precise alignment with surface structures located inside the front surface 21 of the semiconductor substrate 10 or outside the front surface 21 becomes difficult. By forming the mask 60 so as to be in contact with a structure formed on the front surface 21 of the semiconductor substrate 10, as in this example, precise alignment with extremely fine surface structures becomes easier. 【0148】 Figure 10 is a diagram illustrating the concentration distribution of a semiconductor substrate 10 having a lifetime control region 151. In this example, the lifetime control region 151 is formed by irradiating the semiconductor substrate 10 with helium ions from the front surface 21 side. Hydrogen ions may be implanted instead of helium ions. The p-p' cross section is an arbitrary cross section of the diode portion 80 where the lifetime control region 151 is provided. In this example, the concentration distribution and carrier lifetime distribution in the Z-axis direction of the recombination center in the lifetime control region 151 are shown in the p-p' cross section. 【0149】The lifetime control region 151 has an ion implantation peak in the depth direction of the semiconductor substrate 10. The concentration of lifetime killers (recombination centers) in the lifetime control region 151 reaches a peak concentration Np at a predetermined depth position. This depth position is located in the drift region 18 on the front surface 21 side of the center in the depth direction of the semiconductor substrate 10. The lifetime control region 151 may be defined as a region having a lifetime killer concentration higher than the half value of the peak concentration Np, which is 0.5 Np. 【0150】 When helium ions or the like are irradiated from the front surface 21 side, the lifetime killer at a concentration lower than the peak concentration Np is distributed from the peak position to the front surface 21 of the semiconductor substrate 10, creating a trailing effect. That is, the ion implantation peak attenuates toward the front surface 21 of the semiconductor substrate 10. On the other hand, the concentration of the lifetime killer on the back surface 23 side of the semiconductor substrate 10 decreases more sharply than the concentration of the lifetime killer on the front surface 21 side of the semiconductor substrate 10. The concentration distribution in the lifetime control region 151 does not need to reach the back surface 23. If the ion implantation peak distribution attenuates toward the front surface 21 of the semiconductor substrate 10, the depth position of the peak concentration Np may be on the back surface 23 side rather than the midpoint in the depth direction of the semiconductor substrate 10. 【0151】 The concentration distribution of recombination centers shown in Figure 10 may represent helium concentration, hydrogen ions, or crystal defect density formed by helium irradiation or hydrogen ion implantation, as described above. Crystal defects may be interstitial helium, interstitial hydrogen, vacancies, double vacancies, dangling bonds formed by vacancies, etc. These crystal defects form carrier recombination centers. Carrier recombination is promoted through the energy levels (trap levels) of the formed recombination centers. The recombination center concentration corresponds to the trap level density. 【0152】 The carrier lifetime distribution shown in Figure 10 has a minimum value τ at a position that roughly corresponds to the peak concentration position of the recombination center concentration. ｍｉｎ In the base region 14 near the front surface 21, the carrier lifetime distribution is τｍｉｎ a value τ larger than １ may be had. In other depth-direction regions where no lifetime killer is introduced, the carrier lifetime distribution may be distributed at a substantially uniform value (τ ０ shall be assumed) in a region deeper than the peak concentration position of the recombination center concentration. In the field stop region 20, due to the termination effect of holes and dangling bonds by hydrogen, the carrier lifetime may be distributed at a value on the order of τ ０ . 【0153】 As described above, the present invention has been described using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear from the description of the claims that forms with such changes or improvements can also be included in the technical scope of the present invention. 【0154】 It should be noted that the execution order of each process such as operations, procedures, steps, and stages in the devices, systems, programs, and methods shown in the claims, the specification, and the drawings is not explicitly stated as "earlier" or "preceding", etc., and can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the specification, and the drawings, even if it is described using "first", "next", etc. for convenience, it does not mean that it is essential to perform in this order. 【0155】10... Semiconductor substrate, 11... Anode region, 12... Emitter region, 14... Base region, 15... Contact region, 16... Accumulation region, 17... Outer well region, 18... Drift region, 19... Second conductivity region, 20... Field stop region, 21... Front surface, 22... Collector region, 23... Back surface, 24... Back surface electrode, 25... Connection portion, 30... Dummy trench portion, 31... Extending portion, 32... Dummy insulating film, 33... Connection portion, 34... Dummy conductive portion, 38... Interlayer insulating film, 40... Gate trench portion, 41... Extending portion, 4 2...Gate insulating film, 43...Connection portion, 44...Gate conductive portion, 50...Gate metal layer, 52...Front side electrode, 54...Contact hole, 55...Contact hole, 56...Contact hole, 60...Mask, 70...Transistor portion, 71...Mesa portion, 80...Diode portion, 81...Mesa portion, 82...Cathode region, 100...Semiconductor device, 110...Active region, 120...Outer peripheral region, 130...Gate pad, 151...Lifetime control region, 181...First cathode portion, 182...Second cathode portion, 183...Third cathode portion

Claims

1. A semiconductor device comprising a transistor and a diode, the semiconductor device comprising: a drift region of a first conductivity type provided on a semiconductor substrate; a plurality of trenches extending in a predetermined trench extension direction above the drift region; the transistor having a base region of a second conductivity type provided above the drift region; and a collector region of a second conductivity type provided below the drift region; the diode having an anode region of a second conductivity type provided above the drift region; and a cathode region of a first conductivity type provided below the drift region and having a higher doping concentration than the drift region; the cathode region having a first cathode portion; and a second cathode portion provided closer to the transistor portion than the first cathode portion and having a smaller thickness in the depth direction of the semiconductor substrate.

2. The semiconductor device according to claim 1, wherein the second cathode portion is in contact with a back-side electrode provided in contact with the back surface of the semiconductor substrate.

3. The semiconductor device according to claim 1, further comprising a second conductivity type region of a second conductivity type provided above the second cathode portion and in contact with the upper end of the second cathode portion.

4. The semiconductor device according to claim 3, wherein the doping concentration of the second conductivity region is smaller than the doping concentration of the collector region.

5. The semiconductor device according to claim 3, wherein the second conductivity region extends from above the second cathode portion toward the transistor portion in the trench arrangement direction of the plurality of trench portions and terminates above the cathode region.

6. The semiconductor device according to claim 5, wherein, in the trench arrangement direction, L is the distance from the end of the second conductivity type region closer to the transistor portion to the end of the second conductivity type region further from the transistor portion, and W is the distance from the depth position of the lower end of the plurality of trench portions to the depth position of the upper end of the collector region in the depth direction of the semiconductor substrate, such that 0.1W ≤ L ≤ W.

7. The semiconductor device according to claim 3, wherein the collector region is provided spaced apart from the second conductivity type region.

8. The semiconductor device according to claim 3, wherein at least a portion of the second conductivity type region is provided above the collector region.

9. The semiconductor device according to claim 8, wherein, in the trench arrangement direction of the plurality of trenches, L1 is the distance from the boundary position of the collector region and the cathode region to the end of the second conductivity type region above the collector region, and W is the distance from the depth position of the lower end of the plurality of trenches to the depth position of the upper end of the collector region in the depth direction of the semiconductor substrate, such that 0 ≤ L1 ≤ W.

10. The semiconductor device according to claim 8, wherein the second conductivity type region is provided in the trench arrangement direction of the plurality of trenches, extending from the boundary position between the collector region and the cathode region by a predetermined distance L1 on the side where the collector region is provided, and extending by a predetermined distance L2 on the side where the cathode region is provided, such that L1 ≤ L2.

11. The semiconductor device according to claim 8, wherein the doping concentration of the second conductivity type region is greater than the doping concentration of the collector region.

12. The semiconductor device according to any one of claims 3 to 11, wherein in the depth direction of the semiconductor substrate, the thickness of the second conductivity type region is greater than 0% and 50% or less of the thickness of the cathode region.

13. The semiconductor device according to any one of claims 3 to 11, wherein the thickness of the second conductivity type region in the depth direction of the semiconductor substrate is 0.1 μm or more and 0.3 μm or less.

14. The semiconductor device according to any one of claims 3 to 11, wherein the thickness of the collector region in the depth direction of the semiconductor substrate is greater than the thickness of the cathode region.

15. The semiconductor device according to any one of claims 3 to 11, wherein, in the depth direction of the semiconductor substrate, the depth position of the upper end of the second conductivity type region is closer to the front surface of the semiconductor substrate than the depth position of the upper end of the cathode region.

16. The semiconductor device according to any one of claims 1 to 11, comprising a lifetime control region provided within the semiconductor substrate, extending from the diode portion toward the transistor portion and terminating above the cathode region.

17. The semiconductor device according to claim 16, wherein the lifetime control region extends from the diode portion toward the transistor portion and terminates at the boundary position between the transistor portion and the diode portion.

18. The semiconductor device according to claim 16, wherein the lifetime control region has an ion implantation peak in the depth direction of the semiconductor substrate, and the ion implantation peak is attenuated toward the front surface of the semiconductor substrate.

19. The semiconductor device according to any one of claims 3 to 11, wherein, in the trench extension direction, the end of the second conductivity type region is provided closer to the outer peripheral region of the semiconductor substrate than the end of the cathode region.

20. A semiconductor device according to any one of claims 3 to 11, comprising an interlayer insulating film having a contact hole extending in the trench stretching direction above the front surface of the semiconductor substrate, wherein in the trench stretching direction, the end of the contact hole is provided closer to the outer peripheral region of the semiconductor substrate than the end of the cathode region, and in the trench stretching direction, the end of the second conductivity type region is provided closer to the outer peripheral region of the semiconductor substrate than the end of the contact hole.

21. The semiconductor device according to any one of claims 3 to 11, wherein the cathode region has a third cathode portion of a second conductivity type having a higher doping concentration than the second conductivity type region, and in the trench stretching direction, a region of a first conductivity type including the first cathode portion and the second cathode portion and a region of a second conductivity type including the third cathode portion are alternately and repeatedly arranged, and the second conductivity type region is provided corresponding to the second cathode portion in the trench stretching direction.

22. The semiconductor device according to claim 21, wherein the second conductivity type region is provided in a top view by extending from the end of the second cathode portion by a predetermined length L3 in the trench extending direction, and when Pt is the repeating period between the first conductivity type region and the second conductivity type region in the trench extending direction, 0 < L3 < 0.5Pt.

23. A method for manufacturing a semiconductor device comprising a transistor and a diode, comprising the steps of: preparing a semiconductor substrate provided with a drift region of a first conductivity type; forming a plurality of trenches extending in a predetermined trench extension direction above the drift region; forming a collector region of a second conductivity type below the drift region in the transistor portion; and forming a cathode region of a first conductivity type having a higher doping concentration than the drift region below the drift region in the diode portion, wherein the cathode region comprises a first cathode portion and a second cathode portion provided closer to the transistor portion than the first cathode portion and having a smaller thickness in the depth direction of the semiconductor substrate.

24. The method for manufacturing a semiconductor device according to claim 23, further comprising the step of forming a lifetime control region on the semiconductor substrate by irradiating the semiconductor substrate with ions from the front surface side of the semiconductor substrate.

25. The method for manufacturing a semiconductor device according to claim 24, wherein the step of forming the lifetime control region includes the step of irradiating only the diode portion with ions.

26. A method for manufacturing a semiconductor device according to any one of claims 23 to 25, comprising the step of forming a second conductivity type region of a second conductivity type provided above the second cathode portion in contact with the upper end of the second cathode portion, wherein the step of forming the cathode region and the step of forming the second conductivity type region are performed after the step of forming the collector region.

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