Three-dimensional flash memory with composite vertical channel pattern

Abstract

Disclosed are a three-dimensional flash memory and a method for manufacturing the three-dimensional flash memory, in which a data storage pattern and a composite vertical channel pattern constitute memory cells corresponding to word lines, and each of vertical channel structures extending in the vertical direction on a substrate, through the word lines, comprises: the composite vertical channel pattern extending in the vertical direction; and the data storage pattern formed in contact with an outer wall of the composite vertical channel pattern, wherein the composite vertical channel pattern comprises a P-type vertical channel pattern formed of a P-type oxide semiconductor material and an N-type vertical channel pattern formed of an N-type oxide semiconductor material.

Description

3D flash memory with a complex vertical channel pattern

[0001] The following embodiments describe a three-dimensional flash memory having a composite vertical channel pattern.

[0002] Flash memory devices are electrically programmable and eraseable read-only memory (EEPROM) that controls data input and output electrically through FN tunneling (Fowler-Nordheim tunneling) or thermionic electron injection, and can be commonly used in computers, digital cameras, MP3 players, game systems, memory sticks, etc.

[0003] In these flash memory devices, it is required to increase the integration density to meet the excellent performance and low cost demanded by consumers, so a three-dimensional structure in which memory cell transistors (MCTs) are arranged in a vertical direction to form a memory cell string (CSTR) has been proposed.

[0004] Conventional 3D flash memory generally has the disadvantage of being unable to perform hole injection-based erasure operations because the vertical channel pattern connecting memory cell transistors is formed using an N-type oxide semiconductor material, making hole supply impossible.

[0005] In addition, conventional 3D flash memory implements the vertical channel pattern connecting memory cell transistors as a single-layer structure, so the area through which cell current flows in the vertical channel pattern of the single-layer structure is small, which has the problem of degraded cell current characteristics.

[0006] Therefore, it is necessary to propose a technique for performing hole injection-based erasure operations and a technique for improving cell current characteristics.

[0007]

[0008] One embodiment proposes a three-dimensional flash memory based on a composite vertical channel pattern comprising a P-type vertical channel pattern formed of a P-type oxide semiconductor material and an N-type vertical channel pattern formed of an N-type oxide semiconductor material to enable hole injection-based erasure operation.

[0009] In addition, some embodiments propose a three-dimensional flash memory having a composite film structure of a composite vertical channel pattern to improve cell current characteristics.

[0010] At this time, one embodiment proposes a three-dimensional flash memory having a structure in which an ion movement barrier is interposed between vertical channel patterns to prevent ion movement between vertical channel patterns included in a composite vertical channel pattern.

[0011] However, the technical problems that the present invention aims to solve are not limited to the above problems and can be expanded in various ways without departing from the technical concept and scope of the present invention.

[0012] According to one embodiment, a three-dimensional flash memory comprises: word lines formed extending in a horizontal direction on a substrate and stacked while being spaced apart from each other in a vertical direction; and vertical channel structures formed extending in a vertical direction on the substrate through the word lines—each of the vertical channel structures includes a composite vertical channel pattern formed extending in the vertical direction and a data storage pattern formed in contact with the outer wall of the composite vertical channel pattern, wherein the data storage pattern and the composite vertical channel pattern constitute memory cells corresponding to the word lines—and the composite vertical channel pattern may be characterized by including a P-type vertical channel pattern formed of a P-type oxide semiconductor material and an N-type vertical channel pattern formed of an N-type oxide semiconductor material.

[0013] According to one aspect, the P-type vertical channel pattern may be formed of the P-type oxide semiconductor material to supply holes to the data storage pattern during a hole injection-based erasure operation, and the N-type vertical channel pattern may be formed of the N-type oxide semiconductor material to supply electrons to the data storage pattern during a program operation or a read operation.

[0014] According to another aspect, the P-type vertical channel pattern may be formed in contact with the data storage pattern, and the N-type vertical channel pattern may be formed in contact with the inner wall of the P-type vertical channel pattern.

[0015] According to another aspect, the N-type vertical channel pattern may be formed in contact with the data storage pattern, and the P-type vertical channel pattern may be formed in contact with the inner wall of the N-type vertical channel pattern.

[0016] According to one embodiment, a method for manufacturing a three-dimensional flash memory comprising: word lines formed extending in a horizontal direction on a substrate and stacked while being spaced apart from each other in a vertical direction; and vertical channel structures formed extending in a vertical direction on the substrate through the word lines—each of the vertical channel structures comprising a composite vertical channel pattern formed extending in the vertical direction and a data storage pattern formed in contact with the outer wall of the composite vertical channel pattern, wherein the data storage pattern and the composite vertical channel pattern constitute memory cells corresponding to the word lines—may include the step of configuring the composite vertical channel pattern with a P-type vertical channel pattern formed of a P-type oxide semiconductor material and an N-type vertical channel pattern formed of an N-type oxide semiconductor material.

[0017] According to one aspect, the above-described steps may include: forming a P-type vertical channel pattern with the P-type oxide semiconductor material to supply holes to the data storage pattern during a hole injection-based erasure operation; and forming an N-type vertical channel pattern with the N-type oxide semiconductor material to supply electrons to the data storage pattern during a program operation or a read operation.

[0018] According to one embodiment, a three-dimensional flash memory comprises: word lines formed extending in a horizontal direction on a substrate and stacked while being spaced apart from each other in a vertical direction; and vertical channel structures formed extending in a vertical direction on the substrate through the word lines—each of the vertical channel structures comprising a composite vertical channel pattern formed extending in the vertical direction and a data storage pattern formed in contact with the outer wall of the composite vertical channel pattern, wherein the data storage pattern and the composite vertical channel pattern constitute memory cells corresponding to the word lines—the composite vertical channel pattern comprises at least one ion migration barrier interposed between the vertical channel patterns.

[0019] According to one aspect, the three-dimensional flash memory is characterized in that at least one ion migration barrier prevents ions from migrating between vertical channel patterns formed of different semiconductor materials.

[0020] According to another aspect, the at least one ion migration barrier is TiO x , GaO x , Al2O3, SiO2, or SiN xA three-dimensional flash memory characterized by being formed from a base insulating material, formed by doping Ga, Ti, Sn, Zn, or In into the insulating material, or formed into a multilayer structure by stacking the insulating material in multiple layers.

[0021] According to another aspect, the vertical channel patterns may be characterized by being formed of a material having different electron mobilities, each supplying electrons to the memory cells.

[0022] According to another aspect, any one of the vertical channel patterns may be formed of a material that supplies holes to the memory cells, and the remaining one of the vertical channel patterns, excluding any one of the vertical channel patterns, may be formed of a material that supplies electrons to the memory cells.

[0023] According to another aspect, any one of the vertical channel patterns may be formed of a material that supplies holes and electrons to the memory cells, and the remaining one of the vertical channel patterns, excluding any one of the vertical channel patterns, may be formed of a material that supplies electrons to the memory cells.

[0024] According to another aspect, the vertical channel patterns may be characterized by being formed with different thicknesses.

[0025] One embodiment proposes a three-dimensional flash memory based on a composite vertical channel pattern comprising a P-type vertical channel pattern formed of a P-type oxide semiconductor material and an N-type vertical channel pattern formed of an N-type oxide semiconductor material, thereby achieving a technical effect capable of performing hole injection-based erasure operations.

[0026] In addition, some embodiments can improve cell current characteristics by proposing a three-dimensional flash memory having a composite film structure of a composite vertical channel pattern.

[0027] At this time, one embodiment proposes a three-dimensional flash memory having a structure in which an ion migration barrier is interposed between vertical channel patterns included in a composite vertical channel pattern, thereby preventing ion migration between vertical channel patterns.

[0028] However, the effects of the present invention are not limited to the above effects and can be extended in various ways without departing from the technical concept and scope of the present invention.

[0029] FIG. 1 is a simplified circuit diagram illustrating an array of three-dimensional flash memory according to an embodiment.

[0030] FIG. 2 is a plan view illustrating the structure of a three-dimensional flash memory according to an embodiment.

[0031] FIG. 3 is a cross-sectional view illustrating the structure of a three-dimensional flash memory according to one embodiment, corresponding to the cross-section of FIG. 2 cut along the line A-A'.

[0032] FIG. 4 is a cross-sectional view illustrating the structure of a three-dimensional flash memory according to another embodiment, corresponding to the cross-section of FIG. 2 cut along the line A-A'.

[0033] FIG. 5 is a flowchart illustrating a program operation method of a three-dimensional flash memory according to embodiments.

[0034] FIG. 6 is a flowchart illustrating a read operation method of a three-dimensional flash memory according to one embodiment.

[0035] FIG. 7 is a cross-sectional view illustrating a program operation or read operation of a three-dimensional flash memory according to embodiments.

[0036] FIG. 8 is a flowchart illustrating an erasure operation method of a three-dimensional flash memory according to one embodiment.

[0037] FIG. 9 is a cross-sectional view illustrating the erasure operation of a three-dimensional flash memory according to embodiments.

[0038] FIG. 10 is a flowchart illustrating a method for manufacturing a three-dimensional flash memory according to an embodiment.

[0039] FIG. 11 is a cross-sectional view illustrating the structure of a three-dimensional flash memory according to one embodiment, corresponding to the cross-section of FIG. 2 cut along the line A-A'.

[0040] FIG. 12 is a cross-sectional view illustrating a composite vertical channel pattern in a three-dimensional flash memory according to one embodiment.

[0041] FIG. 13 is a flowchart illustrating a program operation method of a three-dimensional flash memory according to one embodiment.

[0042] FIG. 14 is a flowchart illustrating a method of reading a three-dimensional flash memory according to one embodiment.

[0043] FIG. 15 is a flowchart illustrating an erasure operation method of a three-dimensional flash memory according to one embodiment.

[0044] FIG. 16 is a flowchart illustrating a method for manufacturing a three-dimensional flash memory according to one embodiment.

[0045] FIG. 17 is a schematic perspective view illustrating an electronic system including a three-dimensional flash memory according to an embodiment.

[0046]

[0047] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited or restricted by the embodiments. Also, the same reference numerals in each drawing indicate the same components.

[0048] Furthermore, the terminology used in this specification is used to appropriately describe preferred embodiments of the present invention, and may vary depending on the intent of the viewer or operator, or the conventions of the field to which the present invention belongs. Accordingly, the definitions of these terms should be based on the content throughout this specification. For example, in this specification, the singular form includes the plural form unless specifically stated otherwise in the text. Also, the terms "comprises" and / or "comprising" used in this specification do not exclude the presence or addition of one or more other components, steps, actions, and / or elements to the mentioned components, steps, actions, and / or elements. Additionally, although terms such as "first," "second," etc., are used in this specification to describe various regions, directions, shapes, etc., these regions, directions, and shapes should not be limited by such terms. These terms are used merely to distinguish one specific region, direction, or shape from another region, direction, or shape. Accordingly, a part referred to as the first part in one embodiment may be referred to as the second part in another embodiment.

[0049] Furthermore, it should be understood that various embodiments of the present invention are different but need not be mutually exclusive. For example, specific shapes, structures, and characteristics described herein may be implemented in other embodiments without departing from the technical spirit and scope of the present invention in relation to one embodiment. Additionally, it should be understood that the location, arrangement, or configuration of individual components within each presented category of embodiments may be changed without departing from the technical spirit and scope of the present invention.

[0050] Hereinafter, with reference to the drawings, a three-dimensional flash memory capable of performing hole injection-based erasure operations, a method of operation thereof, and a method of manufacturing thereof will be described in detail.

[0051]

[0052] FIG. 1 is a simplified circuit diagram illustrating an array of three-dimensional flash memory according to embodiments.

[0053] Referring to FIG. 1, an array of three-dimensional flash memory according to one embodiment may include a common source line (CSL), a plurality of bit lines (BL0, BL1, BL2), and a plurality of cell strings (CSTR) disposed between the common source line (CSL) and the bit lines (BL0, BL1, BL2).

[0054] Bit lines (BL0, BL1, BL2) can be arranged two-dimensionally, spaced apart from each other along the first direction (D1), while extending in the second direction (D2). Here, the first direction (D1), the second direction (D2), and the third direction (D3) can each form a Cartesian coordinate system defined by the X, Y, and Z axes, which are orthogonal to each other.

[0055] A plurality of cell strings (CSTR) may be connected in parallel to each of the bit lines (BL0, BL1, BL2). The cell strings (CSTR) may be provided between the bit lines (BL0, BL1, BL2) and a common source line (CSL) and may be commonly connected to the common source line (CSL). In this case, the common source line (CSL) may be provided in multiple numbers, and the plurality of common source lines (CSL) may be formed extending in a first direction (D1) and spaced apart from each other along a second direction (D2) and arranged two-dimensionally. The same electrical voltage may be applied to the plurality of common source lines (CSL), but is not limited to or restricted thereto, and different voltages may be applied by each of the plurality of common source lines (CSL) being electrically controlled independently.

[0056] Cell strings (CSTRs) may be formed extending in a third direction (D3) and arranged spaced apart from each other along a second direction (D2) by bit line. According to an embodiment, each cell string (CSTR) may be composed of a ground select transistor (GST) connected to a common source line (CSL), first and second string select transistors (SST1, SST2) connected in series and connected to bit lines (BL0, BL1, BL2), memory cell transistors (MCTs) connected in series and positioned between the ground select transistor (GST) and the first and second string select transistors (SST1, SST2), and an erase control transistor (ECT). Additionally, each memory cell transistor (MCT) may include a data storage element.

[0057] For example, each cell string (CSTR) may include first and second string select transistors (SST1, SST2) connected in series, and the second string select transistor (SST2) may be connected to one of the bit lines (BL0, BL1, BL2). However, not limited thereto, each cell string (CSTR) may include a single string select transistor. As another example, the ground select transistor (GST) in each cell string (CSTR) may be composed of a plurality of MOS transistors connected in series, similar to the first and second string select transistors (SST1, SST2).

[0058] A cell string (CSTR) may be composed of multiple memory cell transistors (MCTs) at different distances from common source lines (CSL). That is, the memory cell transistors (MCTs) may be connected in series along a third direction (D3) between a first string select transistor (SST1) and a ground select transistor (GST). An erase control transistor (ECT) may be connected between the ground select transistor (GST) and the common source lines (CSL). Each cell string (CSTR) may further include dummy cell transistors (DMCs) connected between the first string select transistor (SST1) and the highest of the memory cell transistors (MCTs), and between the ground select transistor (GST) and the lowest of the memory cell transistors (MCTs), respectively.

[0059] According to an embodiment, the first string select transistor (SST1) can be controlled by the first string select lines (SSL1-1, SSL1-2, SSL1-3), and the second string select transistor (SST2) can be controlled by the second string select lines (SSL2-1, SSL2-2, SSL2-3). Memory cell transistors (MCT) can each be controlled by a plurality of word lines (WL0-WLn), and dummy cell transistors (DMC) can each be controlled by a dummy word line (DWL). The ground select transistor (GST) can be controlled by the ground select lines (GSL0, GSL1, GSL2), and the erase control transistor (ECT) can be controlled by the erase control line (ECL). The erase control transistor (ECT) can be provided in multiple numbers. Common source lines (CSL) can be commonly connected to the sources of erase control transistors (ECT).

[0060] The gate electrodes of memory cell transistors (MCTs), provided at substantially the same distance from the common source lines (CSL), may be in an equipotential state by being commonly connected to one of the word lines (WL0-WLn, DWL). However, without being limited to this, even if the gate electrodes of memory cell transistors (MCTs) are provided at substantially the same level from the common source lines (CSL), the gate electrodes provided in different rows or columns may be controlled independently.

[0061] Ground select lines (GSL0, GSL1, GSL2), first string select lines (SSL1-1, SSL1-2, SSL1-3), and second string select lines (SSL2-1, SSL2-2, SSL2-3) can be arranged two-dimensionally, extending along a first direction (D1) and spaced apart from each other in a second direction (D2). Ground select lines (GSL0, GSL1, GSL2), first string select lines (SSL1-1, SSL1-2, SSL1-3), and second string select lines (SSL2-1, SSL2-2, SSL2-3), provided at substantially the same level from common source lines (CSL), can be electrically isolated from each other. Additionally, erase control transistors (ECTs) of different cell strings (CSTR) can be controlled by a common erase control line (ECL). The erase control transistors (ECT) may generate Gate Induced Drain Leakage (GIDL) during the erase operation of the memory cell array. In some embodiments, during the erase operation of the memory cell array, an erase voltage may be applied to the bit lines (BL0, BL1, BL2) and / or common source lines (CSL), and a gate-induced leakage current may be generated in the string select transistor (SST) and / or the erase control transistors (ECT).

[0062] The string selection line (SSL) described above may be represented as the upper selection line (USL), and the ground selection line (GSL) may be represented as the lower selection line.

[0063]

[0064] FIG. 2 is a plan view illustrating the structure of a three-dimensional flash memory according to an embodiment, FIG. 3 is a cross-sectional view illustrating the structure of a three-dimensional flash memory according to one embodiment, corresponding to the cross-section cut along line A-A' of FIG. 2, and FIG. 4 is a cross-sectional view illustrating the structure of a three-dimensional flash memory according to another embodiment, corresponding to the cross-section cut along line A-A' of FIG. 2.

[0065] Referring to FIGS. 2 to 4, the substrate (SUB) may be a semiconductor substrate such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a monocrystalline silicon substrate. The substrate (SUB) may be doped with a first conductivity type impurity (e.g., a P-type impurity).

[0066] Stacked structures (ST) may be disposed on a substrate (SUB). The stacked structures (ST) may be formed extending in a first direction (D1) and arranged two-dimensionally along a second direction (D2). Additionally, the stacked structures (ST) may be spaced apart from each other in the second direction (D2).

[0067] Each of the stacked structures (ST) may include gate electrodes (EL1, EL2, EL3) and interlayer insulating layers (ILD) alternately stacked in a vertical direction perpendicular to the upper surface of the substrate (SUB) (e.g., third direction (D3)). The stacked structures (ST) may have a substantially flat upper surface. That is, the upper surface of the stacked structures (ST) may be parallel to the upper surface of the substrate (SUB). Hereinafter, the vertical direction refers to the third direction (D3) or the reverse direction of the third direction (D3).

[0068] Referring again to FIG. 1, each gate electrode (EL1, EL2, EL3) may be one of an erase control line (ECL), ground select lines (GSL0, GSL1, GSL2), word lines (WL0-WLn, DWL), first string select lines (SSL1-1, SSL1-2, SSL1-3), and second string select lines (SSL2-1, SSL2-2, SSL2-3) stacked in order on a substrate (SUB).

[0069] Each of the gate electrodes (EL1, EL2, EL3) may have a substantially identical thickness in the third direction (D3) while being formed extending in the first direction (D1). Hereinafter, thickness refers to the thickness in the third direction (D3). Each of the gate electrodes (EL1, EL2, EL3) may be formed from a conductive material. For example, each of the gate electrodes (EL1, EL2, EL3) may include at least one selected from doped semiconductors (e.g., doped silicon, etc.), metals (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.). Each of the gate electrodes (EL1, EL2, EL3) may include at least one of all metal materials that can be formed by ALD in addition to the described metal materials.

[0070] More specifically, the gate electrodes (EL1, EL2, EL3) may include a first gate electrode (EL1) at the bottom, a third gate electrode (EL3) at the top, and a plurality of second gate electrodes (EL2) between the first gate electrode (EL1) and the third gate electrode (EL3). Although the first gate electrode (EL1) and the third gate electrode (EL3) are each shown and described in singular form, this is exemplary and not limited thereto, and the first gate electrode (EL1) and the third gate electrode (EL3) may be provided in plurality as needed. The first gate electrode (EL1) may correspond to any one of the ground select lines (GSL0, GSL1, GLS2) shown in FIG. 1. The second gate electrode (EL2) may correspond to any one of the word lines (WL0-WLn, DWL) shown in FIG. 1. The third gate electrode (EL3) may correspond to any one of the first string selection lines (SSL1-1, SSL1-2, SSL1-3) of FIG. 1 or any one of the second string selection lines (SSL2-1, SSL2-2, SSL2-3).

[0071] Although not illustrated, each end of the stacked structures (ST) may have a stepwise structure along the first direction (D1). More specifically, the gate electrodes (EL1, EL2, EL3) of the stacked structures (ST) may have a length in the first direction (D1) that decreases as they move away from the substrate (SUB). The third gate electrode (EL3) may have the shortest length in the first direction (D1) and the largest distance from the substrate (SUB) in the third direction (D3). The first gate electrode (EL1) may have the longest length in the first direction (D1) and the smallest distance from the substrate (SUB) in the third direction (D3). Due to the stepped structure, the thickness of each of the stacked structures (ST) may decrease as it moves away from the outermost one of the vertical channel structures (VS) described later, and the sidewalls of the gate electrodes (EL1, EL2, EL3) may be spaced apart at regular intervals along the first direction (D1) in a planar view.

[0072] Each of the interlayer insulating layers (ILD) may have a different thickness. For example, the bottom and top interlayer insulating layers (ILD) may have a smaller thickness than other interlayer insulating layers (ILD). However, this is exemplary and not limited thereto, and the thickness of each interlayer insulating layer (ILD) may have different thicknesses or all be set to the same thickness depending on the characteristics of the semiconductor device. The interlayer insulating layers (ILD) may be formed of an insulating material to provide insulation between the gate electrodes (EL1, EL2, EL3). For example, the interlayer insulating layers (ILD) may be formed of silicon oxide.

[0073] Additionally, depending on the implementation example, the interlayer insulating layers (ILD) may be omitted. In this case, the gate electrodes (EL1, EL2, EL3) are stacked and spaced apart from each other in a vertical direction (e.g., a third direction (D3)), and an air gap may be interposed between the gate electrodes (EL1, EL2, EL3).

[0074] A plurality of channel holes (CH) penetrating a portion of the stacked structures (ST) and the substrate (SUB) may be provided. Vertical channel structures (VS) may be provided within the channel holes (CH). The vertical channel structures (VS) may be formed as a plurality of cell strings (CSTR) as shown in FIG. 1, extending in a third direction (D3) while connected to the substrate (SUB). The connection of the vertical channel structures (VS) to the substrate (SUB) may be achieved by the lower surface of each portion of the vertical channel structures (VS) coming into contact with the upper surface of the substrate (SUB), but is not limited thereto and may also be achieved by being embedded inside the substrate (SUB). When a portion of each vertical channel structure (VS) is embedded inside the substrate (SUB), the lower surface of the vertical channel structures (VS) may be located at a lower level than the upper surface of the substrate (SUB).

[0075] Columns of vertical channel structures (VS) penetrating any one of the stacked structures (ST) may be provided in multiple numbers. As previously described, since the gate electrodes (EL1, EL2, EL3) are formed in a plate shape, the vertical channel structures (VS) may form an array consisting of multiple columns and rows on the horizontal plane formed by the gate electrodes (EL1, EL2, EL3). For example, as shown in FIG. 2, 12 vertical channel structures (VS) may penetrate one of the stacked structures (ST) by forming 6 columns and 4 rows. However, the number of vertical channel structures (VS) forming the array is not limited to or restricted therefrom.

[0076] As such, by forming an array consisting of multiple columns and rows on the horizontal plane of the gate electrodes (EL1, EL2, EL3) formed in the shape of a plate, the 3D flash memory can have a structure in which the integration density of the memory cell string is improved.

[0077] At this time, vertical channel structures (VS) included in an adjacent pair of columns may be shifted and arranged so as to be offset from each other, forming different rows on a horizontal plane. For example, vertical channel structures (VS) included in the first column may be arranged in the first and third rows, and vertical channel structures (VS) included in the second column may be arranged in the second and fourth rows, and vertical channel structures (VS) included in the second column may be arranged in a zigzag shape along the first direction (D1). Accordingly, the density of the memory cell string may be further improved compared to the case where vertical channel structures (VS) included in an adjacent pair of columns are arranged side by side in the same row on a horizontal plane.

[0078] Each of the vertical channel structures (VS) may be formed to extend from the substrate (SUB) in a third direction (D3). Although the drawings show each of the vertical channel structures (VS) having a column shape with equal widths at the top and bottom, they are not limited to this and may have a shape in which the width increases in the first direction (D1) and the second direction (D2) as they move toward the third direction (D3). The upper surface of each of the vertical channel structures (VS) may have a circular shape, an elliptical shape, a square shape, or a bar shape.

[0079] Each of the vertical channel structures (VS) may include a data storage pattern (DSP), a composite vertical channel pattern (CVCP), a vertical embedding pattern (VFP), and a capping layer (CAP). In each of the vertical channel structures (VS), the data storage pattern (DSP) and the composite vertical channel pattern (CVCP) may have an open bottom pipe shape or a macaroni shape, and the vertical embedding pattern (VFP) may have a shape that fills the inner space of the composite vertical channel pattern (CVCP). However, without being limited to or restricted thereto, the composite vertical channel pattern (CVCP) may have a closed bottom pipe shape or a macaroni shape.

[0080] The data storage pattern (DSP) covers the inner wall of each channel hole (CH), surrounds the outer wall of the composite vertical channel pattern (CVCP) on the inside, and can contact the side walls of the gate electrodes (EL1, EL2, EL3) on the outside. Accordingly, the regions of the data storage pattern (DSP) corresponding to the second gate electrodes (EL2), together with the regions of the composite vertical channel pattern (CVCP) corresponding to the second gate electrodes (EL2), can form memory cells in which memory operations (program operation, read operation, or erase operation) are performed by the voltage applied through the second gate electrodes (EL2). The memory cells correspond to the memory cell transistors (MCT) shown in FIG. 1.

[0081] To this end, the data storage pattern (DSP) can serve as a data storage in a three-dimensional flash memory by trapping electrons or holes by the voltage applied through the second gate electrodes (EL2) or by maintaining the state of the electrons (e.g., the polarization state of the charges). For example, an ONO (tunnel oxide-charge storage nitride-blocking oxide) layer or a ferroelectric layer may be used as the data storage pattern (DSP). Such a data storage pattern (DSP) can represent binary data values ​​or multi-valued data values ​​based on changes in trapped charges or holes, or binary data values ​​or multi-valued data values ​​based on changes in the state of the charges.

[0082] Although it has been described that the data storage pattern (DSP) is connected in a vertical direction and extended, it is not limited to or restricted thereto and may be segmented into multiple parts and formed only in the portions corresponding to the second gate electrodes (EL), thereby configuring memory cells together with the regions corresponding to the second gate electrodes (EL2) among the composite vertical channel pattern (CVCP).

[0083] A composite vertical channel pattern (CVCP) is a component that supplies electrons or holes to transfer charge to a data storage pattern (DSP), and can be formed by covering the inner wall of the data storage pattern (DSP) to form or boost a channel by an applied voltage and extending in a vertical direction (e.g., a third direction (D3)). More specifically, the composite vertical channel pattern (CVCP) may include a P-type vertical channel pattern (VCP-P) and an N-type vertical channel pattern (VCP-N).

[0084] A P-type vertical channel pattern (VCP-P) can be formed of a P-type oxide semiconductor material to supply holes to a data storage pattern (DSP) (memory cells) during a hole injection-based erase operation.

[0085] For example, the P-type vertical channel pattern (VCP-P) uses SnO and CuO to supply holes to the data storage pattern (DSP) (memory cells). x or CuMO x It can be formed from at least one material selected from delafossite, polysilicon, or silicon crystalline material. As for delafossite, CuFeO2 or Cu 1+ Fe 3+ At least one of O2 can be used.

[0086] An N-type vertical channel pattern (VCP-N) can be formed of an N-type oxide semiconductor material to supply electrons to a data storage pattern (DSP) (memory cells) during a program operation or a read operation.

[0087] For example, an N-type vertical channel pattern (VCP-N) can be formed of an oxide semiconductor material containing at least one metal ion of In, Ga, Zn, Sn, Ni, Cu, Al, or Sr to supply electrons to a data storage pattern (DSP) (memory cells).

[0088] As another example, the N-type vertical channel pattern (VCP-N) can be formed from a compound semiconductor material comprising at least one of GaAs, InP, ZnO, SiC, or SiGe.

[0089] In such a composite vertical channel pattern (CVCP), the positions of the P-type vertical channel pattern (VCP-P) and the N-type vertical channel pattern (VCP-N) can be freely adjusted and determined. For example, as shown in FIG. 3, the P-type vertical channel pattern (VCP-P) can be formed on the outer edge in contact with the data storage pattern (DSP), and the N-type vertical channel pattern (VCP-N) can be formed in contact with the inner wall of the P-type vertical channel pattern (VCP-P). As another example, as shown in FIG. 4, the N-type vertical channel pattern (VCP-N) can be formed on the outer edge in contact with the data storage pattern (DSP), and the P-type vertical channel pattern (VCP-P) can be formed in contact with the inner wall of the N-type vertical channel pattern (VCP-N).

[0090] The thickness of each of the P-type vertical channel pattern (VCP-P) and N-type vertical channel pattern (VCP-N) can be adaptively adjusted according to the design intent below, satisfying the conditions for supplying holes and supplying electrons, respectively.

[0091] The upper surface of the composite vertical channel pattern (CVCP) may substantially co-plan with the upper surface of the vertical embedded pattern (VFP) and may be located at a higher level than the upper surface of the uppermost of the second gate electrodes (EL2). More specifically, the upper surface of the composite vertical channel pattern (CVCP) may be located between the upper and lower surfaces of the third gate electrode (EL3). The lower surface of the composite vertical channel pattern (CVCP) may co-plan with the upper surface of the substrate (SUB) (i.e., the lower surface of the lowest of the interlayer insulating layers (ILD)). However, without being limited to this, the lower surface of the composite vertical channel pattern (CVCP) may be located at a lower level than the upper surface of the substrate (SUB) (i.e., the lower surface of the lowest of the interlayer insulating layers (ILD)).

[0092] Additionally, the composite vertical channel pattern (CVCP) may have a structure including a P-type vertical channel pattern (VCP-P) and an N-type vertical channel pattern (VCP-N), and an insulating film (not shown) interposed between the P-type vertical channel pattern (VCP-P) and the N-type vertical channel pattern (VCP-N).

[0093] The vertical embedded pattern (VFP) can be surrounded by a composite vertical channel pattern (CVCP). The upper surface of the vertical embedded pattern (VFP) can be in contact with a capping layer (CAP), and the lower surface of the vertical embedded pattern (VFP) can be in contact with the uppermost surface of the substrate (SUB). The vertical embedded pattern (VFP) can be spaced apart from the substrate (SUB) in a third direction (D3). In other words, the vertical embedded pattern (VFP) can be electrically floating from the substrate (SUB).

[0094] Although a structure in which a vertical embedded pattern (VFP) is located inside a composite vertical channel pattern (CVCP) has been described, the 3D flash memory is not limited to or restricted thereto and may have a structure including a back gate (BG; not shown) instead of a vertical embedded pattern (VFP). In such a case, the back gate (BG) may be formed to be in contact with the composite vertical channel pattern (CVCP) while being partially wrapped by the composite vertical channel pattern (CVCP) and to apply voltage to the composite vertical channel pattern (CVCP) for memory operation. To this end, the back gate (BG) may be formed from a conductive material comprising at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). The back gate (BG) may include at least one of all metal materials that can be formed by ALD in addition to the described metal material. Additionally, in this case, an insulating film (not shown) may be placed between the back gate (BG) and the composite vertical channel pattern (CVCP) to prevent the back gate (BG) from coming into direct contact with the composite vertical channel pattern (CVCP). The insulating film may be formed of an insulating material such as silicon oxide, similar to the interlayer insulating layers (ILD). However, the insulating film may be omitted depending on the embodiment.

[0095] Referring again to FIG. 1, the vertical channel structures (VS) may correspond to the channels of the erase control transistor (ECT), the first and second string select transistors (SST1, SST2), the ground select transistor (GST), and the memory cell transistors (MCT).

[0096] A capping layer (CAP) may be provided on the upper surface of the composite vertical channel pattern (CVCP). The capping layer (CAP) may be connected to the upper surface of the composite vertical channel pattern (CVCP). The sidewalls of the capping layer (CAP) may be surrounded by a data storage pattern (DSP). The upper surface of the capping layer (CAP) may be substantially co-planar with the upper surface of each of the stacked structures (ST) (i.e., the upper surface of the uppermost of the interlayer insulating layers (ILD)). The lower surface of the capping layer (CAP) may be located at a lower level than the upper surface of the third gate electrode (EL3). More specifically, the lower surface of the capping layer (CAP) may be located between the upper and lower surfaces of the third gate electrode (EL3). That is, at least a portion of the capping layer (CAP) may overlap horizontally with the third gate electrode (EL3).

[0097] The capping layer (CAP) can be formed of a material having a contact resistance lower than the contact resistance that the composite vertical channel pattern (CVCP) has with respect to the bit line contact plug (BLPG). Accordingly, the capping layer (CAP) can reduce the contact resistance between the bit line (BL) and the composite vertical channel pattern (CVCP) described later.

[0098] A separation trench (TR; not shown) extending in a first direction (D1) may be provided between adjacent stacked structures (ST). A common source region (CSR; not shown) may be provided inside a substrate (SUB) exposed by the separation trench (TR). The common source region (CSR) may extend in the first direction (D1) within the substrate (SUB). The common source region (CSR) may be formed of a semiconductor material doped with impurities of a second conductivity type (e.g., N-type impurities). The common source region (CSR) may correspond to the common source line (CSL) of FIG. 1.

[0099] A common source plug (CSP; not shown) may be provided within a separation trench (TR). The common source plug (CSP) may be connected to a common source region (CSR). The upper surface of the common source plug (CSP) may be substantially co-planar with the upper surface of each of the laminated structures (ST) (i.e., the upper surface of the uppermost of the interlayer insulation layers (ILD)). The common source plug (CSP) may have a plate shape extending in a first direction (D1) and a third direction (D3). In this case, the common source plug (CSP) may have a shape in which the width in the second direction (D2) increases as it extends toward the third direction (D3).

[0100] Insulating spacers (SP; not shown) may be interposed between the common source plug (CSP) and the stacked structures (ST). The insulating spacers (SP) may be provided facing each other between adjacent stacked structures (ST). For example, the insulating spacers (SP) may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

[0101] A capping insulating film (CAP-INS) may be provided on the stacked structures (ST), vertical channel structures (VS), and common source plug (CSP). The capping insulating film (CAP-INS) may cover the upper surface of the uppermost of the interlayer insulating layers (ILD), the upper surface of the capping layer (CAP), and the upper surface of the common source plug (CSP). The capping insulating film (CAP-INS) may be formed of an insulating material different from that of the interlayer insulating layers (ILD). A bit line contact plug (BLPG) electrically connected to the capping layer (CAP) may be provided inside the capping insulating film (CAP-INS). The bit line contact plug (BLPG) may have a shape in which the width in the first direction (D1) and the second direction (D2) increases as it moves toward the third direction (D3).

[0102] A bit line (BL) may be provided on a capping insulating film (CAP-INS) and a bit line contact plug (BLPG). The bit line (BL) corresponds to any one of the plurality of bit lines (BL0, BL1, BL2) shown in FIG. 1 and may be formed by extending a conductive material along a second direction (D2). The conductive material constituting the bit line (BL) may be the same material as the conductive material forming each of the aforementioned gate electrodes (EL1, EL2, EL3).

[0103] A bit line (BL) can be electrically connected to vertical channel structures (VS) through a bit line contact plug (BLPG). Here, being connected to the vertical channel structures (VS) means being connected to a composite vertical channel pattern (CVCP) included in the vertical channel structures (VS).

[0104] A three-dimensional flash memory according to one embodiment is not limited to or restricted to the described structure, and can be implemented in various structures according to an example of implementation, provided that it includes gate electrodes (EL1, EL2, EL3) to which a voltage for memory operation is applied, a bit line (BL), a common source line (CSL), a composite vertical channel pattern (CVCP) forming a channel, and a data storage pattern (DSP) for data storage.

[0105] With the structure of the composite vertical channel patterns (CVCP) proposed in this way, the 3D flash memory according to the embodiment can supply holes to memory cells during a hole injection-based erase operation using a P-type vertical channel pattern (VCP-P) and supply electrons to memory cells during a memory operation or read operation using an N-type vertical channel pattern (VCP-N).

[0106]

[0107] FIG. 5 is a flowchart illustrating a programming operation method of a three-dimensional flash memory according to embodiments, FIG. 6 is a flowchart illustrating a reading operation method of a three-dimensional flash memory according to one embodiment, and FIG. 7 is a cross-sectional view for explaining a programming operation or a reading operation of a three-dimensional flash memory according to embodiments.

[0108] It is assumed that the entity performing the memory operation (program operation or read operation) described below is a three-dimensional flash memory of the structure described with reference to FIGS. 1 to 4.

[0109] Referring to FIG. 5 in relation to program operation, in step (S510), the three-dimensional flash memory can supply electrons to at least one memory cell among the memory cells in an N-type vertical channel pattern (VCP-N) included in a composite vertical channel pattern (CVCP) in response to a voltage applied to each of the word lines (WLs).

[0110] Accordingly, in step (S520), the three-dimensional flash memory can perform a program operation on at least one memory cell in response to electrons being supplied to at least one memory cell.

[0111] Referring to FIG. 6 in relation to the read operation, in step (S610), the three-dimensional flash memory can supply electrons to at least one memory cell among the memory cells in an N-type vertical channel pattern (VCP-N) included in a composite vertical channel pattern (CVCP) in response to a voltage applied to each of the word lines (WLs).

[0112] Accordingly, in step (S620), the three-dimensional flash memory can perform a read operation on at least one memory cell in response to electrons being supplied to at least one memory cell.

[0113] The band structure during program operation or read operation is as shown in FIG. 7. FIG. 7 was created based on a three-dimensional flash memory of the structure shown in FIG. 4.

[0114]

[0115] FIG. 8 is a flowchart illustrating a method for erasing a three-dimensional flash memory according to one embodiment, and FIG. 9 is a cross-sectional view for explaining the erasing operation of a three-dimensional flash memory according to embodiments.

[0116] It is assumed that the entity performing the memory operation (erasure operation) described below is a three-dimensional flash memory of the structure described with reference to FIGS. 1 to 4.

[0117] Referring to FIG. 8 regarding the erase operation, in step (S810), the three-dimensional flash memory can supply holes to at least one memory cell among the memory cells in a P-type vertical channel pattern (VCP-P) included in a composite vertical channel pattern (CVCP) in response to a voltage applied to each of the word lines (WLs).

[0118] Accordingly, in step (S820), the three-dimensional flash memory can perform a hole injection-based erase operation on at least one memory cell in response to a hole being supplied to at least one memory cell.

[0119] The band structure during the erase operation is as shown in FIG. 9. FIG. 7 was created based on the 3D flash memory of the structure shown in FIG. 4.

[0120]

[0121] FIG. 10 is a flowchart illustrating a method for manufacturing a three-dimensional flash memory according to an embodiment.

[0122] The three-dimensional flash memory manufactured through the manufacturing method described below may have the structure described above with reference to FIGS. 1 to 4, and the manufacturing method described below is based on the premise that it is performed by an automated and mechanized manufacturing system.

[0123] In step (S1010), the manufacturing system can form a composite vertical channel pattern (CVCP) with a P-type vertical channel pattern (VCP-P) formed of a P-type oxide semiconductor material and an N-type vertical channel pattern (VCP-N) formed of an N-type oxide semiconductor material.

[0124] More specifically, the manufacturing system may form a P-type vertical channel pattern (VCP-P) using a P-type oxide semiconductor material to supply holes to a data storage pattern (DSP) during a hole injection-based erase operation, and form an N-type vertical channel pattern (VCP-N) using an N-type oxide semiconductor material to supply electrons to the data storage pattern (DSP) during a program operation or a read operation. The formation order of the P-type vertical channel pattern (VCP-P) and the N-type vertical channel pattern (VCP-N) may be changed depending on which vertical channel pattern is positioned on the outer edge.

[0125] For example, if a P-type vertical channel pattern (VCP-P) is to be positioned on the outer edge, the manufacturing system can form a data storage pattern (DSP) within each of the channel holes (C), and sequentially form a P-type vertical channel pattern (VCP-P) and an N-type vertical channel pattern (VCP-N) within the channel holes (C) where the data storage pattern (DSP) is formed.

[0126] As another example, if an N-type vertical channel pattern (VCP-N) is to be positioned on the outer edge, the manufacturing system can form a data storage pattern (DSP) within each of the channel holes (C), and sequentially form an N-type vertical channel pattern (VCP-N) and a P-type vertical channel pattern (VCP-P) within the channel holes (C) where the data storage pattern (DSP) is formed.

[0127] The manufacturing method described above may, while essentially including the step of configuring a composite vertical channel pattern (CVCP) into a P-type vertical channel pattern (VCP-P) and an N-type vertical channel pattern (VCP-N), obviously include the manufacturing steps included in the manufacturing method of a conventional 3D flash memory.

[0128] For example, when a word line replacement manufacturing method is applied, the manufacturing system performs a manufacturing method comprising: a first step of preparing a semiconductor structure in which sacrificial layers and interlayer insulating layers (ILD) are alternately stacked; a second step of forming channel holes (CH) in a vertical direction in the semiconductor structure; a third step of removing sacrificial layers through the channel holes (CH); a fourth step of forming word lines (WL0-WLn) in the space where the sacrificial layers were removed; a fifth step of forming a data storage pattern (DSP) on the inner wall of each channel hole (CH); a sixth step of forming a composite vertical channel pattern (CVCP) on the inner wall of the data storage pattern (DSP); and a seventh step of forming a vertical embedded pattern (VFP) on the inner wall of the composite vertical channel pattern (CVCP), or a first step of preparing a semiconductor structure in which sacrificial layers and interlayer insulating layers (ILD) are alternately stacked; and a second step of forming channel holes (CH) in a vertical direction in the semiconductor structure; A manufacturing method can be performed comprising: a third step of forming a data storage pattern (DSP) on the inner wall of each channel hole (CH); a fourth step of forming a composite vertical channel pattern (CVCP) on the inner wall of the data storage pattern (DSP); a fifth step of forming a vertical embedded pattern (VFP) on the inner wall of the composite vertical channel pattern (CVCP); a sixth step of forming a separation trench (TR) in the semiconductor structure; a seventh step of removing sacrificial layers through the separation trench (TR); and an eighth step of forming word lines (WL0-WLn) in the space where the sacrificial layers have been removed.

[0129] As another example, when a gate-first manufacturing method is applied, the manufacturing system may perform a manufacturing method comprising: a first step of preparing a semiconductor structure in which word lines (WL0-WLn) and interlayer insulating layers (ILD) are alternately stacked; a second step of forming channel holes (CH) in a vertical direction in the semiconductor structure; a third step of forming a data storage pattern (DSP) on the inner wall of each channel hole (CH); a fourth step of forming a composite vertical channel pattern (CVCP) on the inner wall of the data storage pattern (DSP); and a fifth step of forming a vertical embedded pattern (VFP) on the inner wall of the composite vertical channel pattern (CVCP).

[0130]

[0131] Hereinafter, with reference to the drawings, a three-dimensional flash memory that improves cell current characteristics while preventing ion movement between vertical channel patterns included in a composite vertical channel pattern, a method of operation thereof, and a method of manufacturing thereof will be described in detail.

[0132]

[0133] FIG. 11 is a cross-sectional view illustrating the structure of a three-dimensional flash memory according to one embodiment, corresponding to the cross-section cut along the line A-A' of FIG. 2, and FIG. 12 is a cross-sectional view for explaining a composite vertical channel pattern in a three-dimensional flash memory according to one embodiment.

[0134] Referring to FIGS. 2 and 11, the substrate (SUB) may be a semiconductor substrate such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a monocrystalline epitaxial layer grown on a monocrystalline silicon substrate. The substrate (SUB) may be doped with a first conductivity type impurity (e.g., a P-type impurity).

[0135] Stacked structures (ST) may be disposed on a substrate (SUB). The stacked structures (ST) may be formed extending in a first direction (D1) and arranged two-dimensionally along a second direction (D2). Additionally, the stacked structures (ST) may be spaced apart from each other in the second direction (D2).

[0136] Each of the stacked structures (ST) may include gate electrodes (EL1, EL2, EL3) and interlayer insulating layers (ILD) alternately stacked in a vertical direction perpendicular to the upper surface of the substrate (SUB) (e.g., third direction (D3)). The stacked structures (ST) may have a substantially flat upper surface. That is, the upper surface of the stacked structures (ST) may be parallel to the upper surface of the substrate (SUB). Hereinafter, the vertical direction refers to the third direction (D3) or the reverse direction of the third direction (D3).

[0137] Referring again to FIG. 1, each gate electrode (EL1, EL2, EL3) may be one of an erase control line (ECL), ground select lines (GSL0, GSL1, GSL2), word lines (WL0-WLn, DWL), first string select lines (SSL1-1, SSL1-2, SSL1-3), and second string select lines (SSL2-1, SSL2-2, SSL2-3) stacked in order on a substrate (SUB).

[0138] Each of the gate electrodes (EL1, EL2, EL3) may have a substantially identical thickness in the third direction (D3) while being formed extending in the first direction (D1). Hereinafter, thickness refers to the thickness in the third direction (D3). Each of the gate electrodes (EL1, EL2, EL3) may be formed from a conductive material. For example, each of the gate electrodes (EL1, EL2, EL3) may include at least one selected from doped semiconductors (e.g., doped silicon, etc.), metals (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.). Each of the gate electrodes (EL1, EL2, EL3) may include at least one of all metal materials that can be formed by ALD in addition to the described metal materials.

[0139] More specifically, the gate electrodes (EL1, EL2, EL3) may include a first gate electrode (EL1) at the bottom, a third gate electrode (EL3) at the top, and a plurality of second gate electrodes (EL2) between the first gate electrode (EL1) and the third gate electrode (EL3). Although the first gate electrode (EL1) and the third gate electrode (EL3) are each shown and described in singular form, this is exemplary and not limited thereto, and the first gate electrode (EL1) and the third gate electrode (EL3) may be provided in plurality as needed. The first gate electrode (EL1) may correspond to any one of the ground select lines (GSL0, GSL1, GLS2) shown in FIG. 1. The second gate electrode (EL2) may correspond to any one of the word lines (WL0-WLn, DWL) shown in FIG. 1. The third gate electrode (EL3) may correspond to any one of the first string selection lines (SSL1-1, SSL1-2, SSL1-3) of FIG. 1 or any one of the second string selection lines (SSL2-1, SSL2-2, SSL2-3).

[0140] Although not illustrated, each end of the stacked structures (ST) may have a stepwise structure along the first direction (D1). More specifically, the gate electrodes (EL1, EL2, EL3) of the stacked structures (ST) may have a length in the first direction (D1) that decreases as they move away from the substrate (SUB). The third gate electrode (EL3) may have the shortest length in the first direction (D1) and the largest distance from the substrate (SUB) in the third direction (D3). The first gate electrode (EL1) may have the longest length in the first direction (D1) and the smallest distance from the substrate (SUB) in the third direction (D3). Due to the stepped structure, the thickness of each of the stacked structures (ST) may decrease as it moves away from the outermost one of the vertical channel structures (VS) described later, and the sidewalls of the gate electrodes (EL1, EL2, EL3) may be spaced apart at regular intervals along the first direction (D1) in a planar view.

[0141] Each of the interlayer insulating layers (ILD) may have a different thickness. For example, the bottom and top interlayer insulating layers (ILD) may have a smaller thickness than other interlayer insulating layers (ILD). However, this is exemplary and not limited thereto, and the thickness of each interlayer insulating layer (ILD) may have different thicknesses or all be set to the same thickness depending on the characteristics of the semiconductor device. The interlayer insulating layers (ILD) may be formed of an insulating material to provide insulation between the gate electrodes (EL1, EL2, EL3). For example, the interlayer insulating layers (ILD) may be formed of silicon oxide.

[0142] Additionally, depending on the implementation example, the interlayer insulating layers (ILD) may be omitted. In this case, the gate electrodes (EL1, EL2, EL3) are stacked and spaced apart from each other in a vertical direction (e.g., a third direction (D3)), and an air gap may be interposed between the gate electrodes (EL1, EL2, EL3).

[0143] A plurality of channel holes (CH) penetrating a portion of the stacked structures (ST) and the substrate (SUB) may be provided. Vertical channel structures (VS) may be provided within the channel holes (CH). The vertical channel structures (VS) may be formed as a plurality of cell strings (CSTR) as shown in FIG. 1, extending in a third direction (D3) while connected to the substrate (SUB). The connection of the vertical channel structures (VS) to the substrate (SUB) may be achieved by the lower surface of each portion of the vertical channel structures (VS) coming into contact with the upper surface of the substrate (SUB), but is not limited thereto and may also be achieved by being embedded inside the substrate (SUB). When a portion of each vertical channel structure (VS) is embedded inside the substrate (SUB), the lower surface of the vertical channel structures (VS) may be located at a lower level than the upper surface of the substrate (SUB).

[0144] Columns of vertical channel structures (VS) penetrating any one of the stacked structures (ST) may be provided in multiple numbers. As previously described, since the gate electrodes (EL1, EL2, EL3) are formed in a plate shape, the vertical channel structures (VS) may form an array consisting of multiple columns and rows on the horizontal plane formed by the gate electrodes (EL1, EL2, EL3). For example, as shown in FIG. 2, 12 vertical channel structures (VS) may penetrate one of the stacked structures (ST) by forming 6 columns and 4 rows. However, the number of vertical channel structures (VS) forming the array is not limited to or restricted therefrom.

[0145] As such, by forming an array consisting of multiple columns and rows on the horizontal plane of the gate electrodes (EL1, EL2, EL3) formed in the shape of a plate, the 3D flash memory can have a structure in which the integration density of the memory cell string is improved.

[0146] At this time, vertical channel structures (VS) included in an adjacent pair of columns may be shifted and arranged so as to be offset from each other, forming different rows on a horizontal plane. For example, vertical channel structures (VS) included in the first column may be arranged in the first and third rows, and vertical channel structures (VS) included in the second column may be arranged in the second and fourth rows, and vertical channel structures (VS) included in the second column may be arranged in a zigzag shape along the first direction (D1). Accordingly, the density of the memory cell string may be further improved compared to the case where vertical channel structures (VS) included in an adjacent pair of columns are arranged side by side in the same row on a horizontal plane.

[0147] Each of the vertical channel structures (VS) may be formed to extend from the substrate (SUB) in a third direction (D3). Although the drawings show each of the vertical channel structures (VS) having a column shape with equal widths at the top and bottom, they are not limited to this and may have a shape in which the width increases in the first direction (D1) and the second direction (D2) as they move toward the third direction (D3). The upper surface of each of the vertical channel structures (VS) may have a circular shape, an elliptical shape, a square shape, or a bar shape.

[0148] Each of the vertical channel structures (VS) may include a data storage pattern (DSP), a composite vertical channel pattern (CVCP), a vertical embedding pattern (VFP), and a capping layer (CAP). In each of the vertical channel structures (VS), the data storage pattern (DSP) and the composite vertical channel pattern (CVCP) may have an open bottom pipe shape or a macaroni shape, and the vertical embedding pattern (VFP) may have a shape that fills the inner space of the composite vertical channel pattern (CVCP). However, without being limited to or restricted thereto, the composite vertical channel pattern (CVCP) may have a closed bottom pipe shape or a macaroni shape.

[0149] The data storage pattern (DSP) covers the inner wall of each channel hole (CH), surrounds the outer wall of the composite vertical channel pattern (CVCP) on the inside, and can contact the side walls of the gate electrodes (EL1, EL2, EL3) on the outside. Accordingly, the regions of the data storage pattern (DSP) corresponding to the second gate electrodes (EL2), together with the regions of the composite vertical channel pattern (CVCP) corresponding to the second gate electrodes (EL2), can form memory cells in which memory operations (program operation, read operation, or erase operation) are performed by the voltage applied through the second gate electrodes (EL2). The memory cells correspond to the memory cell transistors (MCT) shown in FIG. 1.

[0150] To this end, the data storage pattern (DSP) can serve as a data storage in a three-dimensional flash memory by trapping electrons or holes by the voltage applied through the second gate electrodes (EL2) or by maintaining the state of the electrons (e.g., the polarization state of the charges). For example, an ONO (tunnel oxide-charge storage nitride-blocking oxide) layer or a ferroelectric layer may be used as the data storage pattern (DSP). Such a data storage pattern (DSP) can represent binary data values ​​or multi-valued data values ​​based on changes in trapped charges or holes, or binary data values ​​or multi-valued data values ​​based on changes in the state of the charges.

[0151] Although it has been described that the data storage pattern (DSP) is connected in a vertical direction and extended, it is not limited to or restricted thereto and may be segmented into multiple parts and formed only in the portions corresponding to the second gate electrodes (EL), thereby configuring memory cells together with the regions corresponding to the second gate electrodes (EL2) among the composite vertical channel pattern (CVCP).

[0152] A composite vertical channel pattern (CVCP) is a component that supplies electrons or holes to transfer charge to a data storage pattern (DSP), and can be formed by covering the inner wall of the data storage pattern (DSP) to form or boost a channel by an applied voltage and extending in a vertical direction (e.g., a third direction (D3)). More specifically, the composite vertical channel pattern (CVCP) may be composed of a plurality of vertical channel patterns (VCP1, VCP2) and at least one ion transport barrier (IMP) interposed between the vertical channel patterns (VCP1, VCP2).

[0153] In the following description, the composite vertical channel pattern (CVCP) is described as including two vertical channel patterns (VCP1, VCP2), but is not limited thereto and may include three or more vertical channel patterns. In such cases, two ion migration barriers may be disposed in the two spaces between the three or more vertical channel patterns.

[0154] The vertical channel patterns (VCP1, VCP2) can be formed from different semiconductor materials.

[0155] For example, any one of the vertical channel patterns (VCP1, VCP2) (e.g., a first vertical channel pattern (VCP1) formed in contact with a data storage pattern (DSP)) may be formed of a material that supplies holes to memory cells, and the other vertical channel pattern among the vertical channel patterns (VCP1, VCP2) (e.g., a second vertical channel pattern (VCP2)) may be formed of a material that supplies electrons to memory cells. More specifically, any one vertical channel pattern (VCP1) may be used as a channel in a hole injection-based erase operation of a 3D flash memory by being formed of a material that supplies holes to memory cells, and the other vertical channel pattern (VCP2) may be used as a channel in a program operation or read operation of a 3D flash memory by being formed of a material that supplies electrons to memory cells.

[0156] In this case, the second vertical channel pattern (VCP2) may be formed from a material having a different band gap from the first vertical channel pattern (VCP1) or a material that does not contain holes. For example, while the first vertical channel pattern (VCP1) is formed from at least one material among polysilicon or silicon crystal material, the second vertical channel pattern (VCP2) may be formed from an oxide semiconductor material containing at least one metal ion among In, Ga, Zn, Sn, Ni, Cu, Al, or Sr, so that the second vertical channel pattern (VCP2) may have a wider band gap than the first vertical channel pattern (VCP1). As another example, while the first vertical channel pattern (VCP1) is formed from at least one material among polysilicon or silicon crystal material, the second vertical channel pattern (VCP2) is formed from a compound semiconductor material including at least one of GaAs, InP, ZnO, SiC, or SiGe, so that the second vertical channel pattern (VCP2) may have a narrower band gap than the first vertical channel pattern (VCP1).

[0157] As described, in order for only the second vertical channel pattern (VCP2) to supply electrons to the memory cells in memory operation, it is desirable to have a condition in which the first vertical channel pattern (VCP1) does not supply electrons to the memory cells.

[0158] In this regard, a situation occurs where current does not flow due to surface scattering in the range of 1 nm from the interface of the data storage pattern (DSP) to the outside. To utilize this principle, the first vertical channel pattern (VCP1) is formed with a thickness within a range of 1 nm from the interface of the data storage pattern (DSP), thereby preventing electrons from being supplied to memory cells during programming or reading operations (no current flows). That is, the first vertical channel pattern (VCP1) can be formed in contact with the data storage pattern (DSP) at a thickness less than or equal to a preset thickness that causes surface scattering. For example, the first vertical channel pattern (VCP1) is formed with a thickness of 1 nm or less, so that it is included within a range of 1 nm from the interface of the data storage pattern (DSP), and thus current does not flow due to surface scattering.

[0159] The thickness of the second vertical channel pattern (VCP2) is not limited or restricted to these conditions, but can be formed with a thickness thicker than that of the first vertical channel pattern (VCP1). For example, the second vertical channel pattern (VCP2) can be formed with a thickness of 5 nm.

[0160] Accordingly, the first vertical channel pattern (VCP1) and the second vertical channel pattern (VCP2) can be formed with different thicknesses.

[0161] For the above, it has been described that the first vertical channel pattern (VCP1) supplies holes and the second vertical channel pattern (VCP2) supplies electrons, but is not limited to or restricted thereto, and the first vertical channel pattern (VCP1) may supply electrons and the second vertical channel pattern (VCP2) may supply holes.

[0162] The first vertical channel pattern (VCP1) is not limited to being formed from a material that supplies only holes as described, but can also be formed from a material that supplies electrons. That is, the vertical channel patterns (VCP1, VCP2) can be formed from materials that supply electrons to memory cells, each having different electron mobilities.

[0163] More specifically, the first vertical channel pattern (VCP1) is formed from a polysilicon or silicon crystalline material and is formed in contact with the data storage pattern (DSP) with a thickness exceeding a preset thickness that causes surface scattering, thereby supplying not only holes but also electrons to the memory cells. For example, the first vertical channel pattern (VCP1) is formed with a thickness exceeding 1 nm that causes surface scattering from the interface of the data storage pattern (DSP), thereby supplying electrons to the memory cells during a program operation or a read operation (current flows).

[0164] In this case, only the first vertical channel pattern (VCP1) that supplies holes is used for the hole injection-based erase operation for the memory cells, and in the program operation or read operation, the first vertical channel pattern (VCP1) that supplies electrons may be used together with the second vertical channel pattern (VCP2) that supplies electrons.

[0165] As such, the first vertical channel pattern (VCP1) can supply only holes or supply holes and electrons together depending on the thickness of the formation.

[0166] For the above, it has been described that the first vertical channel pattern (VCP1) supplies holes and electrons and the second vertical channel pattern (VCP2) supplies electrons, but is not limited to or restricted thereto, and the first vertical channel pattern (VCP1) may supply electrons and the second vertical channel pattern (VCP2) may supply holes and electrons.

[0167] As described, if ion movement occurs between vertical channel patterns (VCP1, VCP2) as the vertical channel patterns (VCP1, VCP2) are formed of different semiconductor materials, the cell current characteristics may be degraded.

[0168] Therefore, at least one ion transport barrier (IMP) can prevent ions from moving between vertical channel patterns (VCP1, VCP2) formed of different semiconductor materials. For example, at least one ion transport barrier (IMP) is TiO x , GaO x , Al2O3, SiO2, or SiN x The movement of ions between vertical channel patterns (VCP1, VCP2) can be prevented by being formed with a base insulating material, by being formed by doping Ga, Ti, Sn, Zn, or In within the insulating material, or by stacking the insulating material in multiple layers to form a multilayer structure.

[0169] The upper surface of the composite vertical channel pattern (CVCP) may substantially co-plan with the upper surface of the vertical embedded pattern (VFP) and may be located at a higher level than the upper surface of the uppermost of the second gate electrodes (EL2). More specifically, the upper surface of the composite vertical channel pattern (CVCP) may be located between the upper and lower surfaces of the third gate electrode (EL3). The lower surface of the composite vertical channel pattern (CVCP) may co-plan with the upper surface of the substrate (SUB) (i.e., the lower surface of the lowest of the interlayer insulating layers (ILD)). However, without being limited to this, the lower surface of the composite vertical channel pattern (CVCP) may be located at a lower level than the upper surface of the substrate (SUB) (i.e., the lower surface of the lowest of the interlayer insulating layers (ILD)).

[0170] The vertical embedded pattern (VFP) can be surrounded by the second vertical channel pattern (VCP2) of the composite vertical channel pattern (CVCP). The upper surface of the vertical embedded pattern (VFP) can be in contact with the capping layer (CAP), and the lower surface of the vertical embedded pattern (VFP) can be in contact with the uppermost surface of the substrate (SUB). The vertical embedded pattern (VFP) can be spaced apart from the substrate (SUB) in a third direction (D3). In other words, the vertical embedded pattern (VFP) can be electrically floating from the substrate (SUB).

[0171] Although a structure in which a vertical embedded pattern (VFP) is located inside a composite vertical channel pattern (CVCP) has been described, the 3D flash memory is not limited to or restricted thereto and may have a structure including a back gate (BG; not shown) instead of a vertical embedded pattern (VFP). In such a case, the back gate (BG) may be formed to be in contact with the composite vertical channel pattern (CVCP) while being partially wrapped by the composite vertical channel pattern (CVCP) and to apply voltage to the composite vertical channel pattern (CVCP) for memory operation. To this end, the back gate (BG) may be formed from a conductive material comprising at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). The back gate (BG) may include at least one of all metal materials that can be formed by ALD in addition to the described metal material. Additionally, in this case, an insulating film (INS; not shown) may be placed between the back gate (BG) and the composite vertical channel pattern (CVCP) to prevent the back gate (BG) from coming into direct contact with the composite vertical channel pattern (CVCP). The insulating film (INS) may be formed of an insulating material such as silicon oxide, similar to the interlayer insulating layers (ILD). However, the insulating film (INS) may be omitted depending on the implementation example.

[0172] Referring again to FIG. 1, the vertical channel structures (VS) may correspond to the channels of the erase control transistor (ECT), the first and second string select transistors (SST1, SST2), the ground select transistor (GST), and the memory cell transistors (MCT).

[0173] A capping layer (CAP) may be provided on the upper surface of the composite vertical channel pattern (CVCP). The capping layer (CAP) may be connected to the upper surface of the composite vertical channel pattern (CVCP). The sidewalls of the capping layer (CAP) may be surrounded by a data storage pattern (DSP). The upper surface of the capping layer (CAP) may be substantially co-planar with the upper surface of each of the stacked structures (ST) (i.e., the upper surface of the uppermost of the interlayer insulating layers (ILD)). The lower surface of the capping layer (CAP) may be located at a lower level than the upper surface of the third gate electrode (EL3). More specifically, the lower surface of the capping layer (CAP) may be located between the upper and lower surfaces of the third gate electrode (EL3). That is, at least a portion of the capping layer (CAP) may overlap horizontally with the third gate electrode (EL3).

[0174] The capping layer (CAP) may be formed of a material having a contact resistance lower than that of the second vertical channel pattern (VCP2) to the bit line contact plug (BLPG) (e.g., polysilicon or silicon crystal material identical to the first vertical channel pattern (VCP1)). Accordingly, the capping layer (CAP) can reduce the contact resistance between the bit line (BL) and the composite vertical channel pattern (CVCP) described later.

[0175] A separation trench (TR; not shown) extending in a first direction (D1) may be provided between adjacent stacked structures (ST). A common source region (CSR; not shown) may be provided inside a substrate (SUB) exposed by the separation trench (TR). The common source region (CSR) may extend in the first direction (D1) within the substrate (SUB). The common source region (CSR) may be formed of a semiconductor material doped with impurities of a second conductivity type (e.g., N-type impurities). The common source region (CSR) may correspond to the common source line (CSL) of FIG. 1.

[0176] A common source plug (CSP; not shown) may be provided within a separation trench (TR). The common source plug (CSP) may be connected to a common source region (CSR). The upper surface of the common source plug (CSP) may be substantially co-planar with the upper surface of each of the laminated structures (ST) (i.e., the upper surface of the uppermost of the interlayer insulation layers (ILD)). The common source plug (CSP) may have a plate shape extending in a first direction (D1) and a third direction (D3). In this case, the common source plug (CSP) may have a shape in which the width in the second direction (D2) increases as it extends toward the third direction (D3).

[0177] Insulating spacers (SP; not shown) may be interposed between the common source plug (CSP) and the stacked structures (ST). The insulating spacers (SP) may be provided facing each other between adjacent stacked structures (ST). For example, the insulating spacers (SP) may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

[0178] A capping insulating film (CAP-INS) may be provided on the stacked structures (ST), vertical channel structures (VS), and common source plug (CSP). The capping insulating film (CAP-INS) may cover the upper surface of the uppermost of the interlayer insulating layers (ILD), the upper surface of the capping layer (CAP), and the upper surface of the common source plug (CSP). The capping insulating film (CAP-INS) may be formed of an insulating material different from that of the interlayer insulating layers (ILD). A bit line contact plug (BLPG) electrically connected to the capping layer (CAP) may be provided inside the capping insulating film (CAP-INS). The bit line contact plug (BLPG) may have a shape in which the width in the first direction (D1) and the second direction (D2) increases as it moves toward the third direction (D3).

[0179] A bit line (BL) may be provided on a capping insulating film (CAP-INS) and a bit line contact plug (BLPG). The bit line (BL) corresponds to any one of the plurality of bit lines (BL0, BL1, BL2) shown in FIG. 1 and may be formed by extending a conductive material along a second direction (D2). The conductive material constituting the bit line (BL) may be the same material as the conductive material forming each of the aforementioned gate electrodes (EL1, EL2, EL3).

[0180] A bit line (BL) can be electrically connected to vertical channel structures (VS) through a bit line contact plug (BLPG). Here, being connected to the vertical channel structures (VS) means being connected to a composite vertical channel pattern (CVCP) included in the vertical channel structures (VS).

[0181] A three-dimensional flash memory according to one embodiment is not limited to or restricted to the described structure, and can be implemented in various structures according to an example of implementation, provided that it includes gate electrodes (EL1, EL2, EL3) to which a voltage for memory operation is applied, a bit line (BL), a common source line (CSL), a composite vertical channel pattern (CVCP) forming a channel, and a data storage pattern (DSP) for data storage.

[0182] As such, by proposing a structure of a composite vertical channel pattern (CVCP) including vertical channel patterns (VCP1, VCP2) and at least one ion migration barrier (IMP), cell current can flow through the vertical channel patterns (VCP1, VCP2) in which ion migration is prevented by at least one ion migration barrier (IMP) as shown in FIG. 12, thereby improving cell current characteristics.

[0183]

[0184] FIG. 13 is a flowchart illustrating a programming operation method of a three-dimensional flash memory according to one embodiment, FIG. 14 is a flowchart illustrating a reading operation method of a three-dimensional flash memory according to one embodiment, and FIG. 15 is a flowchart illustrating an erasure operation method of a three-dimensional flash memory according to one embodiment.

[0185] It is assumed that the entity performing the memory operation (program operation, read operation, or erase operation) described below is a three-dimensional flash memory of the structure described with reference to FIGS. 1 and 2 and FIGS. 11 and 12.

[0186] Referring to FIG. 13 in relation to program operation, in step (S1310), the three-dimensional flash memory can supply electrons to at least one memory cell among the memory cells in vertical channel patterns (VCP1, VCP2) included in the composite vertical channel pattern (CVCP) in response to a voltage applied to each of the word lines (WLs).

[0187] The supply of electrons in the vertical channel patterns (VCP1, VCP2) can be achieved by at least one of the vertical channel patterns (VCP1, VCP2).

[0188] At this time, in step (S1310), the 3D flash memory can prevent ions from moving between vertical channel patterns (VCP1, VCP2) formed of different semiconductor materials by using at least one ion movement barrier (IMP).

[0189] Accordingly, in step (S1320), the three-dimensional flash memory can perform a program operation on at least one memory cell in response to electrons being supplied to at least one memory cell.

[0190] Referring to FIG. 14 in relation to the read operation, in step (S1410), the three-dimensional flash memory can supply electrons to at least one memory cell among the memory cells in vertical channel patterns (VCP1, VCP2) included in the composite vertical channel pattern (CVCP) in response to a voltage applied to each of the word lines (WLs).

[0191] The supply of electrons in the vertical channel patterns (VCP1, VCP2) can be achieved by at least one of the vertical channel patterns (VCP1, VCP2).

[0192] At this time, in step (S1410), the 3D flash memory can prevent ions from moving between vertical channel patterns (VCP1, VCP2) formed of different semiconductor materials by using at least one ion movement barrier (IMP).

[0193] Accordingly, in step (S1420), the three-dimensional flash memory can perform a read operation on at least one memory cell in response to electrons being supplied to at least one memory cell.

[0194] Referring to FIG. 15 in relation to the erase operation, in step (S1510), the three-dimensional flash memory can supply holes to at least one memory cell among the memory cells in the vertical channel patterns (VCP1, VCP2) included in the composite vertical channel pattern (CVCP) in response to the voltage applied to each of the word lines (WLs).

[0195] At this time, in step (S1510), the 3D flash memory can prevent ions from moving between vertical channel patterns (VCP1, VCP2) formed of different semiconductor materials by using at least one ion movement barrier (IMP).

[0196] Accordingly, in step (S1520), the three-dimensional flash memory can perform a hole injection-based erase operation on at least one memory cell in response to a hole being supplied to at least one memory cell.

[0197]

[0198] FIG. 16 is a flowchart illustrating a method for manufacturing a three-dimensional flash memory according to one embodiment.

[0199] The three-dimensional flash memory manufactured through the manufacturing method described below may have the structure described above with reference to FIGS. 1 to 2 and FIGS. 11 to 12, and the manufacturing method described below is based on the premise that it is performed by an automated and mechanized manufacturing system.

[0200] In step (S1610), the manufacturing system can form a composite vertical channel pattern (CVCP) with vertical channel patterns (VCP1, VCP2) and at least one ion migration barrier (IMP) interposed between the vertical channel patterns (VCP1, VCP2).

[0201] More specifically, the manufacturing system can form a data storage pattern (DSP) within each of the channel holes (C), and then sequentially form one of the vertical channel patterns (VCP1, VCP2), at least one ion transport barrier (IMP), and the remaining vertical channel pattern (VCP2) within the channel holes (C) where the data storage pattern (DSP) is formed.

[0202] The manufacturing method described above manufactures a three-dimensional flash memory having a structure comprising a composite vertical channel pattern (CVCP) composed of vertical channel patterns (VCP1, VCP2) and at least one ion migration barrier (IMP) interposed between the vertical channel patterns (VCP1, VCP2), and essentially includes the step of configuring the composite vertical channel pattern (CVCP), while also obviously including the manufacturing steps included in the manufacturing method of a conventional three-dimensional flash memory.

[0203] For example, when a word line replacement manufacturing method is applied, the manufacturing system comprises: a first step of preparing a semiconductor structure in which sacrificial layers and interlayer insulating layers (ILD) are alternately stacked; a second step of forming channel holes (CH) in a vertical direction in the semiconductor structure; a third step of removing sacrificial layers through the channel holes (CH); a fourth step of forming word lines (WL0-WLn) in the space where the sacrificial layers have been removed; a fifth step of forming a data storage pattern (DSP) on the inner wall of each channel hole (CH); a sixth step of forming one vertical channel pattern (VCP1) of a composite vertical channel pattern (CVCP) on the inner wall of the data storage pattern (DSP); a seventh step of forming at least one ion migration barrier (IMP) on the inner wall of one vertical channel pattern (VCP1); and an eighth step of forming the remaining vertical channel pattern (VCP2) of a composite vertical channel pattern (CVCP) on the inner wall of at least one ion migration barrier (IMP). A manufacturing method comprising: a ninth step of forming a vertical embedded pattern (VFP) on the inner wall of the remaining vertical channel pattern (VCP2); a first step of preparing a semiconductor structure in which sacrificial layers and interlayer insulating layers (ILD) are alternately stacked; a second step of forming channel holes (CH) in a vertical direction in the semiconductor structure; a third step of forming a data storage pattern (DSP) on the inner wall of each channel hole (CH); a fourth step of forming one of the vertical channel patterns (VCP1) of the composite vertical channel pattern (CVCP) on the inner wall of the data storage pattern (DSP); a fifth step of forming at least one ion migration barrier (IMP) on the inner wall of one of the vertical channel patterns (VCP1); a sixth step of forming the remaining vertical channel pattern (VCP2) of the composite vertical channel pattern (CVCP) on the inner wall of at least one ion migration barrier (IMP); and a seventh step of forming a vertical embedded pattern (VFP) on the inner wall of the remaining vertical channel pattern (VCP2). Step 8, forming a separation trench (TR) in a semiconductor structure;A manufacturing method can be performed comprising: a 9th step of removing sacrificial layers through a separation trench (TR); and a 10th step of forming word lines (WL0-WLn) in the space where the sacrificial layers have been removed.;

[0204] As another example, when a gate-first manufacturing method is applied, the manufacturing system may perform a manufacturing method comprising: a first step of preparing a semiconductor structure in which word lines (WL0-WLn) and interlayer insulating layers (ILD) are alternately stacked; a second step of forming channel holes (CH) in a vertical direction in the semiconductor structure; a third step of forming a data storage pattern (DSP) on the inner wall of each channel hole (CH); a fourth step of forming one vertical channel pattern (VCP1) of a composite vertical channel pattern (CVCP) on the inner wall of the data storage pattern (DSP); a fifth step of forming at least one ion migration barrier (IMP) on the inner wall of one vertical channel pattern (VCP1); a sixth step of forming the remaining vertical channel pattern (VCP2) of a composite vertical channel pattern (CVCP) on the inner wall of at least one ion migration barrier (IMP); and a seventh step of forming a vertical embedded pattern (VFP) on the inner wall of the remaining vertical channel pattern (VCP2).

[0205]

[0206] FIG. 17 is a schematic perspective view illustrating an electronic system including a three-dimensional flash memory according to an embodiment.

[0207] Referring to FIG. 17, an electronic system (1700) including a three-dimensional flash memory according to embodiments may include a main board (1701), a controller (1702) mounted on the main board (1701), one or more semiconductor packages (1703) and a DRAM (1704).

[0208] The semiconductor package (1703) and DRAM (1704) can be connected to the controller (1702) by wiring patterns (1705) provided on the main board (1701).

[0209] The main board (1701) may include a connector (1706) comprising a plurality of pins that are coupled to an external host. The number and arrangement of the plurality of pins in the connector (1706) may vary depending on the communication interface between the electronic system (1700) and the external host.

[0210] The electronic system (1700) can communicate with an external host according to any one of the interfaces, for example, USB (Universal Serial Bus), PCI Express (Peripheral Component Interconnect Express), SATA (Serial Advanced Technology Attachment), and M-Phy for UFS (Universal Flash Storage). The electronic system (1700) can operate by power supplied from an external host, for example, through a connector (1706). The electronic system (1700) may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from an external host to a controller (1702) and a semiconductor package (1703).

[0211] The controller (1702) can write data to the semiconductor package (1703) or read data from the semiconductor package (1703), and can improve the operating speed of the electronic system (1700).

[0212] The DRAM (1704) may be a buffer memory to mitigate the speed difference between the semiconductor package (1703), which is a data storage space, and an external host. The DRAM (1704) included in the electronic system (1700) may also function as a type of cache memory and may provide a space for temporarily storing data during control operations on the semiconductor package (1703). When the electronic system (1700) includes the DRAM (1704), the controller (1702) may further include a DRAM controller for controlling the DRAM (1704) in addition to the NAND controller for controlling the semiconductor package (1703).

[0213] A semiconductor package (1703) may include first and second semiconductor packages (1703a, 1703b) spaced apart from each other. The first and second semiconductor packages (1703a, 1703b) may each be a semiconductor package including a plurality of semiconductor chips (1720). Each of the first and second semiconductor packages (1703a, 1703b) may include a package substrate (1710), semiconductor chips (1720) on the package substrate (1710), adhesive layers (1730) disposed on the lower surface of each of the semiconductor chips (1720), connection structures (1740) electrically connecting the semiconductor chips (1720) and the package substrate (1710), and a molding layer (1750) covering the semiconductor chips (1720) and the connection structures (1740) on the package substrate (1710).

[0214] The package substrate (1710) may be a printed circuit board including package upper pads (1711). Each semiconductor chip (1720) may include input / output pads (1721). Each semiconductor chip (1720) may include the three-dimensional flash memory described above with reference to FIGS. 1 to 4 and FIGS. 11 to 12. More specifically, each semiconductor chip (1720) may include gate stacking structures (1722) and memory channel structures (1723). The memory channel structures (1723) may correspond to the vertical channel structures (VS) described above.

[0215] The connection structures (1740) may be, for example, bonding wires that electrically connect the input / output pads (1721) and the package upper pads (1711). Accordingly, in each of the first and second semiconductor packages (1703a, 1703b), the semiconductor chips (1720) may be electrically connected to each other by a bonding wire method and may be electrically connected to the package upper pads (1711) of the package substrate (1710). According to embodiments, in each of the first and second semiconductor packages (1703a, 1703b), the semiconductor chips (1720) may be electrically connected to each other by through-silicon vias instead of the bonding wire connection structures (1740).

[0216] Unlike what is described, the controller (1702) and the semiconductor chips (1720) may be included in a single package. The controller (1702) and the semiconductor chips (1720) may be mounted on a separate interposer substrate different from the main substrate (1701), and the controller (1702) and the semiconductor chips (1720) may be connected to each other by wiring provided on the interposer substrate.

[0217]

[0218] Although the embodiments have been described above with reference to limited examples and drawings, those skilled in the art can make various modifications and variations from the description above. For example, suitable results can be achieved even if the described techniques are performed in a different order than described, and / or the components of the described system, structure, device, circuit, etc. are combined or assembled in a form different from described, or replaced or substituted by other components or equivalents.

[0219] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims set forth below.

Claims

1. Word lines formed extending horizontally on a substrate and stacked while spaced apart from each other in the vertical direction; and Vertical channel structures extending in the vertical direction on the substrate through the above word lines—each of the vertical channel structures includes a composite vertical channel pattern extending in the vertical direction and a data storage pattern formed in contact with the outer wall of the composite vertical channel pattern, wherein the data storage pattern and the composite vertical channel pattern constitute memory cells corresponding to the word lines. Includes, The above composite vertical channel pattern is, A three-dimensional flash memory characterized by including a P-type vertical channel pattern formed of a P-type oxide semiconductor material and an N-type vertical channel pattern formed of an N-type oxide semiconductor material.

2. In Paragraph 1, The above P-type vertical channel pattern is, It is formed with the P-type oxide semiconductor material to supply holes to the data storage pattern during a hole injection-based erasure operation, and The above N-type vertical channel pattern is, A three-dimensional flash memory characterized by being formed of the N-type oxide semiconductor material to supply electrons to the data storage pattern during program operation or read operation.

3. In Paragraph 1, The above P-type vertical channel pattern is, Formed in contact with the above data storage pattern, The above N-type vertical channel pattern is, A three-dimensional flash memory characterized by being formed in contact with the inner wall of the above-mentioned P-type vertical channel pattern.

4. In Paragraph 1, The above N-type vertical channel pattern is, Formed in contact with the above data storage pattern, The above P-type vertical channel pattern is, A three-dimensional flash memory characterized by being formed in contact with the inner wall of the above-mentioned N-type vertical channel pattern.

5. Word lines formed extending in a horizontal direction on a substrate and stacked while spaced apart from each other in a vertical direction; and vertical channel structures formed extending in a vertical direction on the substrate through the word lines—each of the vertical channel structures includes a composite vertical channel pattern formed extending in the vertical direction and a data storage pattern formed in contact with the outer wall of the composite vertical channel pattern, wherein the data storage pattern and the composite vertical channel pattern constitute memory cells corresponding to the word lines—in a method for manufacturing a three-dimensional flash memory, A step of configuring the composite vertical channel pattern with a P-type vertical channel pattern formed of a P-type oxide semiconductor material and an N-type vertical channel pattern formed of an N-type oxide semiconductor material A method for manufacturing a three-dimensional flash memory including 6. In Paragraph 5, The steps of configuring the above are, A step of forming a P-type vertical channel pattern with the P-type oxide semiconductor material to supply holes to the data storage pattern during a hole injection-based erasure operation; and A step of forming the N-type vertical channel pattern with the N-type oxide semiconductor material to supply electrons to the data storage pattern during program operation or read operation. A method for manufacturing a three-dimensional flash memory characterized by including 7. Word lines formed extending horizontally on the substrate and stacked while spaced apart from each other in the vertical direction; and Vertical channel structures extending in the vertical direction on the substrate through the above word lines—each of the vertical channel structures includes a composite vertical channel pattern extending in the vertical direction and a data storage pattern formed in contact with the outer wall of the composite vertical channel pattern, and the data storage pattern and the composite vertical channel pattern constitute memory cells corresponding to the word lines. Includes, The above composite vertical channel pattern is, A three-dimensional flash memory characterized by comprising vertical channel patterns and at least one ion migration barrier interposed between the vertical channel patterns.

8. In Paragraph 7, The above at least one ion migration barrier is, A three-dimensional flash memory characterized by preventing ion movement between the vertical channel patterns formed of different semiconductor materials.

9. In Paragraph 8, The above at least one ion migration barrier is, TiO x , GaO x , Al2O3, SiO2, or SiN x A three-dimensional flash memory characterized by being formed from a base insulating material, formed by doping Ga, Ti, Sn, Zn, or In into the insulating material, or formed into a multilayer structure by stacking the insulating material in multiple layers.

10. In Paragraph 7, The above vertical channel patterns are, A three-dimensional flash memory characterized by supplying electrons to each of the memory cells and being formed of a material having different electron mobilities.

11. In Paragraph 7, Any one of the above vertical channel patterns is, It is formed of a material that supplies holes to the memory cells above, and Among the above vertical channel patterns, the remaining vertical channel pattern excluding any one of the above vertical channel patterns is, A three-dimensional flash memory characterized by being formed of a material that supplies electrons to the memory cells.

12. In Paragraph 7, Any one of the above vertical channel patterns is, It is formed of a material that supplies holes and electrons to the above memory cells, and Among the above vertical channel patterns, the remaining vertical channel pattern excluding any one of the above vertical channel patterns is, A three-dimensional flash memory characterized by being formed of a material that supplies electrons to the memory cells.

13. In Paragraph 7, The above vertical channel patterns are, A three-dimensional flash memory characterized by being formed with different thicknesses.

Images