Method and device for performing brain analysis using artificial intelligence

Abstract

A brain analysis method according to an embodiment of the present invention may comprise the steps of: identifying a plurality of pieces of functional connectivity data generated through a plurality of different brain atlases on the basis of brain image data; generating a plurality of feature vectors respectively corresponding to the plurality of pieces of functional connectivity data through a plurality of artificial intelligence algorithm modules; updating the plurality of feature vectors on the basis of the plurality of feature vectors and a bottleneck token through a transformer layer; and performing brain analysis on the basis of the updated feature vectors.

Description

Method and apparatus for performing brain analysis using artificial intelligence

[0001] The present disclosure describes a method and apparatus for performing brain analysis using artificial intelligence.

[0002]

[0003] With the advancement of technology, new research on various brain analysis methods is underway, and accordingly, the diagnosis of brain-related diseases is becoming more accurate and specific.

[0004] In particular, the approach of non-invasively visualizing the structure and function of the brain through imaging to diagnose diseases and research treatments is considered a major field.

[0005] Among brain imaging techniques, magnetic resonance imaging (MRI) has made it possible to observe the detailed structures of the brain. Recently, functional MRI (fMRI) has been used to evaluate neural activity by measuring changes in blood flow to specific regions of the brain when the brain is utilized.

[0006] fMRI is confirmed to be the most efficient method for analyzing functional changes in brain diseases (Alzheimer's disease, Parkinson's disease, and autism spectrum disorder). In particular, since studies have shown that autism spectrum disorder is related to the brain's functional connectivity networks, it is most efficient to construct the functional connectivity network—not just individual functions—and diagnose based on it.

[0007] Atlases are utilized as standardized reference maps that precisely define the structure of the brain and systematically segment and map specific regions. Atlases serve as essential tools for the analysis, comparison, and standardization of brain imaging data and can be designed using fMRI. However, conventionally, only one type of brain atlas has been used in the process of segmenting brain regions, and predictive performance may vary depending on which atlas is employed.

[0008] Therefore, research on brain analysis models capable of performing analyses of various aspects using multiple atlases is required.

[0009]

[0010] The present disclosure aims to provide a method and apparatus for improving the performance of determining brain diseases through brain analysis.

[0011] The present disclosure aims to provide a method for analyzing brain diseases by utilizing multiple brain atlases.

[0012]

[0013] A brain analysis method according to an embodiment of the present disclosure may include: identifying a plurality of functional connectivity data generated through a plurality of different brain atlases based on brain imaging data; generating a plurality of feature vectors corresponding to each of the plurality of functional connectivity data through a plurality of artificial intelligence algorithm modules; updating the plurality of feature vectors based on the plurality of feature vectors and bottleneck tokens through a transformer layer; and performing brain analysis based on the updated feature vectors.

[0014] In one embodiment, the brain imaging data may include fMRI (functional magnetic resonance imaging) image data.

[0015] In one embodiment, the functional connectivity data may include a graph showing the time-series correlation of brain signals in at least two of the brain regions segmented by the brain atlas.

[0016] In one embodiment, the plurality of artificial intelligence algorithm modules are pre-trained graph neural network modules, and the pre-trained graph neural network module includes a GIN (graph isomorphism network) based network, and the graph neural network module can be pre-trained to output a feature vector by taking graph-shaped functional connectivity data as input.

[0017] In one embodiment, the plurality of feature vectors include a classify token (CLS), and the CLS may represent a feature of the functional connectivity data.

[0018] In one embodiment, the step of updating the feature vectors may include: updating the plurality of feature vectors through a self-attention operation based on the association between the plurality of feature vectors in the transformer layer; updating the bottleneck token in the transformer layer by concatenating it with the plurality of feature vectors; and updating the plurality of feature vectors through a self-attention operation based on the self-attention operation plurality of feature vectors and the updated bottleneck token.

[0019] In one embodiment, the step of performing brain analysis based on updated feature vectors may include the step of inputting the updated feature vectors into a pre-trained MLP model; and the step of evaluating the severity of the disease in the brain based on the updated feature vectors in the pre-trained MLP model.

[0020] In one embodiment, the disease severity may include the severity of the autism spectrum disorder of the brain.

[0021] An electronic device according to an embodiment of the present disclosure comprises: a memory; a modem; and a processor connected to the modem and the memory, wherein the processor is configured to identify a plurality of functional connectivity data generated through a plurality of different brain atlases based on brain imaging data, generate a plurality of feature vectors corresponding to each of the plurality of functional connectivity data through a plurality of artificial intelligence algorithm modules, update the plurality of feature vectors based on the plurality of feature vectors and bottleneck tokens through a transformer layer, and perform brain analysis based on the updated feature vectors.

[0022]

[0023] According to one embodiment of the present disclosure, the computational load for brain analysis can be reduced by utilizing a bottleneck method.

[0024] According to one embodiment of the present disclosure, disease prediction performance can be improved by performing brain analysis based on the correlation between the analysis results of various atlases.

[0025]

[0026] A brief description of each drawing is provided to help to better understand the drawings cited in the detailed description of the present disclosure.

[0027] FIG. 1 is a conceptual diagram illustrating the basic principles of an artificial intelligence structure according to one embodiment of the present disclosure.

[0028] FIG. 2 is a diagram showing brain imaging data according to one embodiment of the present disclosure.

[0029] FIG. 3 is a diagram illustrating a method for generating functional connectivity data based on brain data according to one embodiment of the present disclosure.

[0030] FIG. 4 is a diagram showing the structure of a brain analysis device according to one embodiment of the present disclosure.

[0031] FIG. 5 is a block diagram of an electronic device for performing brain analysis according to one embodiment of the present disclosure.

[0032] FIG. 6 is a flowchart illustrating a brain analysis method according to one embodiment of the present disclosure.

[0033]

[0034] The technical concept of the present disclosure is subject to various modifications and may have various embodiments. Specific embodiments are illustrated in the drawings and described in detail through the detailed description. However, this is not intended to limit the technical concept of the present disclosure to specific embodiments, and it should be understood that it includes all modifications, equivalents, and substitutions that fall within the scope of the technical concept of the present disclosure.

[0035] In describing the technical concept of the present disclosure, detailed descriptions of related prior art are omitted if it is determined that such descriptions would unnecessarily obscure the essence of the present disclosure. Furthermore, numbers used in the description of this specification (e.g., First, Second, etc.) are merely identifiers to distinguish one component from another.

[0036] In addition, when a component is described in this specification as being "connected" or "connected" to another component, it should be understood that the component may be directly connected to or directly connected to the other component, but unless otherwise specifically stated, it may also be connected or connected through another component in between.

[0037] In addition, terms such as “~part,” “~device,” “~device,” and “~module” described in this specification refer to a unit that processes at least one function or operation, and may be implemented as hardware or software or a combination of hardware and software such as a processor, microprocessor, microcontroller, CPU (Central Processing Unit), GPU (Graphics Processing Unit), APU (Accelerate Processor Unit), DSP (Drive Signal Processor), ASIC (Application Specific Integrated Circuit), and FPGA (Field Programmable Gate Array), and may also be implemented in a form combined with memory that stores data necessary for processing at least one function or operation.

[0038] Furthermore, it is intended to clarify that the classification of components in this specification is merely based on the primary function each component is responsible for. That is, two or more components described below may be combined into a single component, or a single component may be divided into two or more components based on more subdivided functions. Additionally, each component described below may additionally perform some or all of the functions of other components in addition to the primary function it is responsible for, and it is obvious that some of the primary functions of each component may be exclusively performed by other components.

[0039] In describing the embodiments of the present disclosure, specific descriptions of related functions or configurations are omitted if it is determined that such detailed descriptions would unnecessarily obscure the essence of the present disclosure. Furthermore, the terms used below are defined in consideration of their functions within the present disclosure, and these definitions may vary depending on the intent or convention of the user or operator. Therefore, their definitions should be based on the content throughout this specification.

[0040] For the same reason, some components in the attached drawings may be exaggerated, omitted, or schematically depicted. Additionally, the size of each component does not entirely reflect its actual size. Identical or corresponding components in each drawing have been assigned the same reference number.

[0041] The advantages and features of the present disclosure and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below but may be implemented in various different forms. The embodiments are provided merely to make the description of the present disclosure complete and to fully inform those skilled in the art of the scope of the invention, and the scope of the claims of the present disclosure is defined only by the scope of the claims.

[0042] At this point, it will be understood that each block of the drawings showing the process flow diagram and combinations of the process flow diagrams can be executed by computer program instructions. Since these computer program instructions can be loaded into the processor of a general-purpose computer, a specialized computer, or other programmable data processing equipment, the instructions executed through the processor of the computer or other programmable data processing equipment create means to perform the functions described in the flow diagram block(s). Since these computer program instructions can also be stored in computer-available or computer-readable memory that can be directed toward the computer or other programmable data processing equipment to implement the function in a specific way, the instructions stored in computer-available or computer-readable memory can also produce a manufactured item containing the means of instruction to perform the function described in the flow diagram block(s). Since computer program instructions can be loaded onto a computer or other programmable data processing equipment, instructions that perform a series of operation steps on the computer or other programmable data processing equipment to create a process executed by the computer can also provide steps for executing the functions described in the flowchart block(s).

[0043] Additionally, each block may represent a module, segment, or part of code containing one or more executable instructions for executing a specified logical function(s). It should also be noted that in some alternative execution examples, the functions mentioned in the blocks may occur out of order. For instance, two blocks described in succession may actually be executed substantially simultaneously, or the blocks may be executed in reverse order according to their corresponding functions.

[0044] As used in this disclosure, the term “unit or part” refers to a software or hardware component, such as a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC), and the “part” may be configured to perform specific roles. However, the “part” is not limited to software or hardware. The “part” may be configured to reside in an addressable storage medium or to execute one or more processors. Thus, by example, the “part” includes components such as software components, object-oriented software components, class components, and task components, as well as processes, functions, attributes, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables. The functions provided within the components and “parts” may be combined into a smaller number of components and “parts” or further separated into additional components and “parts.” In addition, the components and 'parts' may be implemented to utilize one or more CPUs within the device or secure multimedia card. Also, in the embodiments, 'parts' may include one or more processors and / or devices.

[0045]

[0046] Hereinafter, embodiments according to the technical concept of the present disclosure will be described in detail in turn.

[0047]

[0048] FIG. 1 is a conceptual diagram illustrating the basic principles of an artificial intelligence structure according to one embodiment of the present disclosure.

[0049] Referring to Figure 1, the basic principle of how learning is performed in an artificial intelligence structure is illustrated.

[0050] Artificial intelligence (AI) technology refers to techniques designed to solve cognitive problems primarily associated with human intelligence, such as learning, problem-solving, and perception. AI can be trained through machine learning (ML) and deep learning (DL). Machine learning is primarily used in techniques for pattern recognition and learning, representing algorithms that learn from recorded data to predict future data. It represents a technology that learns autonomously from data rather than relying on predefined rules or patterns. On the other hand, deep learning is a subfield of machine learning that differs in that it processes data based on Artificial Neural Networks (ANN). Because deep learning utilizes artificial neural networks, it can handle more complex and sophisticated computations than machine learning. Types of algorithms for deep learning include Convolutional Neural Networks (CNN), Artificial Neural Networks (ANN), and Recurrent Neural Networks (RNN).

[0051] Referring to FIG. 1, the artificial intelligence structure can be represented as an artificial intelligence module (110). The artificial intelligence module (110) receives predetermined input data (105), performs learning through a predetermined method determined in the module, and outputs output data (115) corresponding to the input data according to the learning result. According to one embodiment, the input data (105) may include predetermined data, brain image data, fMRI data, input sequence, etc. The output data (115) may include brain disease scores, brain analysis results, output sequence, etc.

[0052]

[0053] FIG. 2 is a diagram showing brain imaging data according to one embodiment of the present disclosure.

[0054] Brain imaging data may include MRI, CT (computed tomography), PET (positron emission tomography), EEG (electroencephalography), fMRI, and DTI (diffusion tensor imaging).

[0055] Figure 2 is a diagram illustrating brain imaging data using fMRI.

[0056] fMRI can represent an imaging technique that measures functional brain activation based on blood oxygen concentration.

[0057] fMRI can represent activation information of brain regions as four-dimensional data by including both temporal and spatial dimensions. fMRI can show how each part of the brain becomes activated over time.

[0058] fMRI can be divided into three spatial dimensions (210) and one temporal dimension (220).

[0059] In the spatial dimension (210), it is divided into horizontal (x), vertical (y), and depth (z) axes and can be expressed in units of voxels (230). Each voxel can represent a specific location in the brain.

[0060] In the time dimension (220), it is composed of multiple frames according to time and can be represented as time series data. Signals measured at regular time intervals in each voxel can be recorded on the time axis. Time can have a range from 1 to T.

[0061] Therefore, fMRI data can be represented in a four-dimensional form of (x,y,z,t).

[0062] fMRI can evaluate the brain's response to stimuli or activities by analyzing temporal signal changes in specific voxels.

[0063]

[0064] FIG. 3 is a diagram illustrating a method for generating functional connectivity data based on brain data according to one embodiment of the present disclosure.

[0065] Figure 3 may illustrate how a brain atlas generates functional connectivity data based on brain imaging data.

[0066] The brain atlas (305) can parcel (315) brain regions based on brain imaging data (e.g., fMRI data) (310). The brain atlas (305) can calculate time-series average signals (325a, 325b) within each region of interest (ROI) within the parceled brain regions (320).

[0067] The brain atlas (305) can calculate a time-series correlation (330) for a combination of first average signals (325a) to second average signals (325b) for any divided region.

[0068] The brain atlas (305) can form a functional connectivity network (340) between brain regions based on time-series correlations.

[0069] The functional connectivity network (340) represents the correlation of simultaneous neural activity between different regions of the brain, and functional connectivity may appear when regions of the divided brain are simultaneously activated or show similar neural signals.

[0070] The functional connectivity network (340) appears in the form of a graph and can visualize the connection strength of each brain region. The results of the functional connectivity network (340) may vary depending on which brain atlas is used.

[0071] The functional connectivity network (340) can be preprocessed and represented as brain region connectivity data (350) that indicates region-specific connectivity on the brain structure.

[0072]

[0073] FIG. 4 is a diagram showing the structure of a brain analysis device according to one embodiment of the present disclosure.

[0074] The brain analysis device (400) of Fig. 4 can determine brain diseases and brain connectivity by utilizing an artificial intelligence algorithm model based on brain imaging data.

[0075] The brain analysis device (400) can perform a data preprocessing step (S405), a tokenization step (S410), and a fusion step (S415) according to the procedure.

[0076] In the data preprocessing step (S405), the brain analysis device (400) can input brain image data (420) into a plurality of brain atlases (425a, 425b, ..., 425p) and generate functional connectivity networks (430a, 430b, ..., 430p) corresponding to each. Each of the plurality of brain atlases (425a, 425b, ..., 425p) can divide the brain image data (420) according to their respective methods and generate different functional connectivity networks (430a, 430b, ..., 430p) based thereon. Here, the functional connectivity networks may appear in the form of graphs.

[0077] In the tokenization step (S410), the brain analysis device (400) can input each of the generated functional connectivity networks (430a, 430b, ..., 430p) into different pre-trained graph neural networks (GNN) (440a, 440b, ..., 440p). The graph neural networks (440a, 440b, ..., 440p) are networks for processing and analyzing graph data and can be used to perform analysis on data structures composed of nodes and edges. Through the graph neural networks, each node can generate a feature vector by collecting information about its neighboring nodes.

[0078] For example, multiple graph neural networks (440a, 440b, .., 440p) may utilize a GIN (graph isomorphism network) based network. Multiple graph neural networks (440a, 440b, .., 440p) may be pre-trained through a contrastive learning method.

[0079] Each of the multiple graph neural networks (440a, 440b, .., 440p) can output feature vectors (445a, 445b, .., 445p) by taking only one of the multiple functional connectivity networks as input.

[0080] Here, the feature vectors (445a, 445b, .., 445p) appear as tokens and can be represented as classify tokens (CLS). CLS is a token used to represent feature vectors that represent a graph and can be used to train an artificial intelligence algorithm model.

[0081] Feature vectors (445a, 445b, ..., 445p) generated from multiple graph neural networks (440a, 440b, ..., 440p) and a bottleneck token (450) can be passed together to a transformer layer (460) for fusion of feature vector information. Here, the bottleneck token (450) can be used to compress input data and summarize important information during the training of an artificial intelligence algorithm model. The bottleneck token (450) can collect information from feature vectors and integrate them to generate a single summary vector. By utilizing the bottleneck token (460), not only can the core information of each feature vector be fused, but computational efficiency can also be increased because there is no need for each feature vector to be directly computed.

[0082] The transformer layer (460) can utilize a multi-modal bottleneck transformer (MBT) structure to fuse the extracted information.

[0083] Information can be updated by performing a self-attention-based transformer layer between feature vectors (445a, 445b, .., 445p) in the initial layer of the transformer layer (460). The self-attention method can be a method of identifying the association between one's own feature vectors and updating the feature vectors based on this. In this update process, the importance of the feature vectors is determined, and different weights are assigned according to the importance, thereby effectively updating the feature vectors.

[0084] In the latter layer of the transformer layer (460), information exchange between feature vectors (445a, 445b, ..., 445p) can be performed using bottleneck tokens (450). Transformer operations can be performed by concatenating the bottleneck tokens (450) with each feature vector (445a, 445b, ..., 445p). The tokens output from each operation can be passed to the next layer. The average of the output bottleneck tokens can be calculated and passed to the bottleneck token of the next layer.

[0085] Since the number of bottleneck tokens (450) is less than the number of each feature vector (445a, 445b, ..., 445p), the information of each feature vector (445a, 445b, ..., 445p) can be compressed and transmitted to the bottleneck token (450) during the process of performing the operation. The bottleneck token (450) can be transmitted to the next layer by calculating the average with other bottleneck tokens output by operation in the layer together with multiple feature vectors. In addition, by using the bottleneck token (450), the direct self-attention process between feature vectors can be reduced, thereby reducing the computational load.

[0086] In the transformer layer (460), feature vectors (445a, 445b, .., 445p) can be updated through operations using self-attention, bottleneck tokens, etc., and updated feature vectors (465a, 465b, .., 465p) can be output.

[0087] The updated feature vectors (465a, 465b, .., 465p) can be input into a multi-layer perceptron (MLP) model (470). The MLP model (470) is a model with a multi-layer structure that can learn patterns and relationships for the input data.

[0088] The MLP model (470) can evaluate the severity (480) of a brain disease using updated feature vectors (465a, 465b, .., 465p) as input.

[0089] Brain diseases can include various brain-related disorders, such as autism spectrum disorder (ASD), Alzheimer's disease, and depression. The symptoms and severity of ASD can vary from person to person.

[0090] The MLP model (470) can determine the severity (480) based on updated feature vectors (465a, 465b, .., 465p) and can distinguish between the autism group (ASD) and the normal group (Typical control) using the severity (480). Here, the severity (480) can be expressed as a concept such as a score based on the state of the brain or indicating the presence or absence of a disability.

[0091] The brain analysis device (400) shown in FIG. 4 is based on an embodiment that determines the severity of autism spectrum disorder based on fMRI, but it is obvious that the severity of various brain diseases can be determined by changing brain imaging data and changing the application of the brain atlas.

[0092]

[0093] FIG. 5 is a block diagram of an electronic device for performing brain analysis according to one embodiment of the present disclosure.

[0094] The electronic device (510) of FIG. 5 may include the brain atlas (305) described in FIG. 2 to 4, the brain analysis device (400), and the artificial intelligence algorithm model for brain analysis.

[0095] Referring to FIG. 5, the electronic device (510) may include a modem (MODEM, 520), a memory (MEMORY, 540), and a processor (PROCESSOR, 530).

[0096] The modem (520) may be a communication modem that is electrically connected to other electronic devices to enable mutual communication. In particular, the modem (520) may receive data input and transmit it to the processor (530), and the processor (530) may store the input data value in memory (540). Additionally, information output by an artificial intelligence algorithm learned in the system may be transmitted to other electronic devices.

[0097] The memory (540) is configured to store various information and program instructions for the operation of the electronic device (510), and may be a storage device such as a hard disk or an SSD (Solid State Drive). In particular, the memory (540) may store one or more data values ​​input from the modem (520) under the control of the processor (530). Additionally, the memory (540) may store brain analysis artificial intelligence algorithm models (including Transformer Layer, GNN, MLP, etc.) executable by the processor (530) and program instructions for data preprocessing.

[0098] The processor (530) is composed of at least one processor and can perform calculations on data by utilizing brain analysis artificial intelligence algorithms, data preprocessing operations, tokenization operations, etc. using data and program instructions stored in memory (540). The processor (530) can control and calculate all artificial intelligence algorithm models described in FIGS. 1 to 4 (e.g., brain analysis artificial intelligence algorithm model, transformer layer, GNN, MLP).

[0099]

[0100] FIG. 6 is a flowchart illustrating a brain analysis method according to one embodiment of the present disclosure.

[0101] The electronic device of FIG. 6 may include the artificial intelligence algorithm model described in FIG. 1 to FIG. 5.

[0102] With reference to FIG. 6 below, the operation of the brain analysis device and the execution method of the artificial intelligence algorithm model described with reference to FIGs. 1 to 5 will be summarized and explained. Each operation is not an operation that must be necessarily included in the series of processes, and only some of them may be configured and operated depending on the situation.

[0103] In step S610, the electronic device (e.g., the electronic device (510) of FIG. 5) can identify a plurality of functional connectivity data (e.g., the functional connectivity network (340) of FIG. 3, the functional connectivity network (430a, 430b, .., 430p) of FIG. 4).

[0104] In one embodiment, the functional connectivity data may be generated through a plurality of different brain atlases (e.g., a plurality of brain atlases (425a, 425b, .., 425p) of FIG. 4) based on brain imaging data (e.g., brain imaging data (310) of FIG. 3, brain imaging data (420) of FIG. 4).

[0105] In one embodiment, the brain imaging data may include fMRI (functional magnetic resonance imaging) image data.

[0106] In one embodiment, the functional connectivity data may include a graph showing the time-series correlation of brain signals in at least two of the brain regions segmented by the brain atlas.

[0107] In step S620, the electronic device can generate a plurality of feature vectors (e.g., feature vectors of FIG. 4 (445a, 445b, .., 445p)) corresponding to each of the plurality of functional connectivity data through a plurality of artificial intelligence algorithm modules (e.g., GNN of FIG. 4 (440a, 440b, .., 440p)).

[0108] In one embodiment, the plurality of artificial intelligence algorithm modules are pre-trained graph neural network modules, and the pre-trained graph neural network module includes a GIN (graph isomorphism network) based network, and the graph neural network module can be pre-trained to output a feature vector by taking graph-shaped functional connectivity data as input.

[0109] In one embodiment, the plurality of feature vectors include a classify token (CLS), and the CLS may represent a feature of the functional connectivity data.

[0110] In step S630, the electronic device can update the plurality of feature vectors based on the plurality of feature vectors and the bottleneck token (e.g., the bottleneck token (450) of FIG. 4) through a transformer layer (e.g., the transformer layer (460) of FIG. 4).

[0111] In one embodiment, the electronic device can update the plurality of feature vectors through a self-attention operation based on the association between the plurality of feature vectors in the transformer layer, update the bottleneck token in the transformer layer by concatenating it with the plurality of feature vectors, and update the plurality of feature vectors through a self-attention operation based on the plurality of feature vectors and the updated bottleneck token.

[0112] In step S640, the electronic device can perform brain analysis based on updated feature vectors (e.g., updated feature vectors of FIG. 4 (465a, 465b, .., 465p)).

[0113] In one embodiment, the electronic device inputs the updated feature vectors into a pre-trained MLP model (e.g., the MLP model (470) of FIG. 4) and can evaluate the severity of the disease in the brain (e.g., the severity (480) of FIG. 4) based on the updated feature vectors in the pre-trained MLP model.

[0114] In one embodiment, the disease severity may include the severity of the autism spectrum disorder of the brain.

[0115]

[0116] Although the technical concept of the present disclosure has been described in detail with reference to various embodiments, the technical concept of the present disclosure is not limited to the above embodiments, and various modifications and changes can be made by those skilled in the art within the scope of the technical concept of the present disclosure.

Claims

1. Regarding brain analysis methods, A step of identifying multiple functional connectivity data generated through multiple different brain atlases based on brain imaging data; A step of generating a plurality of feature vectors corresponding to each of the plurality of functional connectivity data through a plurality of artificial intelligence algorithm modules; A step of updating the plurality of feature vectors based on the plurality of feature vectors and bottleneck tokens through a transformer layer; A method including the step of performing brain analysis based on updated feature vectors.

2. In Paragraph 1, The above brain imaging data includes a method comprising fMRI (functional magnetic resonance imaging) imaging data.

3. In Paragraph 1, The above functional connectivity data includes a graph representing the time-series correlation of brain signals in at least two of the brain regions segmented by a brain atlas.

4. In Paragraph 1, The above plurality of artificial intelligence algorithm modules are pre-trained graph neural network modules, and The above-mentioned pre-trained graph neural network module includes a GIN (graph isomorphism network) based network, and A method in which the above graph neural network module is pre-trained to output a feature vector by taking graph-shaped functional connectivity data as input.

5. In Paragraph 1, The above plurality of feature vectors include a classify token (CLS), and The above CLS is a method for representing the characteristics of the above functional connectivity data.

6. In Paragraph 1, The step of updating the above feature vectors is: A step of updating the plurality of feature vectors through a self-attention operation based on the association between the plurality of feature vectors in the transformer layer; A step of updating the bottleneck token in the transformer layer by concatenating it with the plurality of feature vectors; and A method comprising the step of updating a plurality of self-attention computed feature vectors based on the plurality of self-attention computed feature vectors and the updated bottleneck token.

7. In Paragraph 1, The step of performing brain analysis based on updated feature vectors is: The step of inputting the above-mentioned updated feature vectors into a pre-trained MLP model; and A method comprising the step of evaluating the severity of the disease in the brain based on the updated feature vectors in the above-mentioned pre-trained MLP model.

8. In Paragraph 7, A method in which the severity of the above disease includes the severity of the autism spectrum disorder of the above brain.

9. In electronic devices, Memory; Modem; and It includes the above modem and a processor connected to the above memory, The above processor is: Identifying multiple functional connectivity data generated through multiple different brain atlases based on brain imaging data, and Generating multiple feature vectors corresponding to each of the aforementioned multiple functional connectivity data through multiple artificial intelligence algorithm modules, and Update the plurality of feature vectors based on the plurality of feature vectors and bottleneck tokens through a transformer layer, and An electronic device configured to perform brain analysis based on updated feature vectors.

10. In Paragraph 9, The above functional connectivity data is an electronic device comprising a graph showing the time-series correlation of brain signals in at least two of the brain regions segmented by a brain atlas.

11. In Paragraph 9, The above plurality of artificial intelligence algorithm modules are pre-trained graph neural network modules, and The above-mentioned pre-trained graph neural network module includes a GIN (graph isomorphism network) based network, and The above graph neural network module is an electronic device that is pre-trained to output a feature vector using graph-shaped functional connectivity data as input.

12. In Paragraph 9, The above plurality of feature vectors include a classify token (CLS), and The above CLS is an electronic device that represents the characteristics of the above functional connectivity data.

13. In Paragraph 9, The above processor is: In the transformer layer above, the plurality of feature vectors are updated through a self-attention operation based on the association between the plurality of feature vectors, and In the above transformer layer, the bottleneck token is updated by concatenating it with the plurality of feature vectors, and An electronic device configured to update multiple feature vectors that have undergone self-attention computation based on the multiple feature vectors that have undergone self-attention computation and the updated bottleneck token.

14. In Paragraph 9, The above processor is: The above updated feature vectors are input into a pre-trained MLP model, and An electronic device configured to evaluate the severity of disease in the brain based on the updated feature vectors in the above-mentioned pre-trained MLP model.

15. In Paragraph 9, The above disease severity is an electronic device including the severity of the autism spectrum disorder of the brain.

Images