Miniaturized custom-built quantum ai nanomagnetic chips for operating small- and medium-sized language models
A hybrid quantum-classical system with nanomagnetic and CMOS components operates at room temperature, addressing scalability and thermal management issues, enabling efficient quantum computation for small- and medium-sized language models.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- UNIV OF MIAMI
- Filing Date
- 2025-09-29
- Publication Date
- 2026-06-18
AI Technical Summary
Existing quantum computing hardware platforms require cryogenic temperatures and face scalability limitations, making them impractical for small- and medium-sized language models, which need scalable room-temperature solutions compatible with conventional semiconductor technology.
A hybrid system integrating a quantum system with nanomagnetic components and a semiconductor component, which includes a quantum system with a semiconductor component, and a nanomagnetic component, where the nanomagnetic component comprises a quantum system with an array of mutually entangled nanomagnets for parallel quantum operations, and a semiconductor component with a CMOS circuit for input and output operations, operating at room temperature.
Enables efficient, scalable, and energy-efficient quantum computation for small- and medium-sized language models, overcoming thermal management and integration challenges, and providing enhanced thermal stability and memory capacity.
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Abstract
Description
[0001] DESCRIPTION
[0002] MINIATURIZED CUSTOM-BUILT QUANTUM Al NANOMAGNETIC CHIPS FOR OPERATING SMALL- AND MEDIUM-SIZED LANGUAGE MODELS
[0003] CROSS-REFERENCE TO RELATED APPLICATION
[0004] This application claims the benefit of U.S. Provisional Application Serial No. 63 / 701,190, filed September 30, 2024, the disclosure of which is hereby incorporated by reference in its entirety, including all figures, tables, and drawings.
[0005] BACKGROUND
[0006] Quantum computing hardware has made significant advances and quantum algorithms have shown theoretical advantages in accelerating artificial intelligence (Al) training particularly in operations such as large matrix multiplication. These algorithms promise substantial improvements in energy efficiency and computational speed. However, existing quantum computing hardware platforms such as superconducting losephson junctions and trapped ion technologies operate at cryogenic temperatures and exhibit scalability limitations. Consequently, current hardware is limited in its ability to fully leverage the potential benefits of quantum algorithms for Al applications. There remains a need for scalable room-temperature quantum computing hardware compatible with conventional semiconductor technology.
[0007] BRIEF SUMMARY
[0008] In view of the challenges discussed in the Background, embodiments of the subject invention provide novel and advantageous systems, devices, and methods for generating miniaturized, custom-built, quantum artificial intelligence (Al) nanomagnetic chips for operating small- and medium-sized language models. In contrast to conventional quantum computing hardware platforms, which require operation at cryogenic temperatures near absolute zero and present substantial challenges related to thermal management, system complexity, and quantum element integration density, the embodiments offer novel approaches that mitigate or eliminate these limitations. The disclosed technology enables the fabrication and deployment of quantum Al nanomagnetic chips that operate under less extreme thermal conditions while maintaining high performance and scalability. These
[0009] J:\UM\l llXClPCT\Application\Application - asfiled.docx / ke chips are designed to support efficient processing of language models within a compact form factor, offering significant advantages in energy efficiency, integration potential, and cost-effectiveness. The systems and methods described herein allow for enhanced thermal stability, improved quantum state element density, and reduced operational complexity, thereby facilitating the broader adoption and deployment of quantum Al technologies in practical, real-world applications.
[0010] In an embodiment, a system for generating (miniaturized, custom-built) quantum Al nanomagnetic chips for operating small- and medium-sized language models can comprise: a nanomagnetic component comprising a quantum system including an array of mutually entangled nanomagnets configured to perform parallel quantum operations to enable massively parallel, energy-efficient quantum computation; and a semiconductor component comprising a complementary metal oxide semiconductor (CMOS) circuit, the semiconductor component configured to provide input and output operations to and from the nanomagnetic component via standard electronic communication protocols, wherein the nanomagnetic component is integrated with the semiconductor component in a hybrid platform. The quantum system can comprise: a bias nanomagnet layer and a quantum bit (qubit) nanomagnet layer, each of the bias nanomagnet layer and the qubit nanomagnet layer being formed of a magnetic material (e.g., comprising at least one of a ferromagnetic material, a ferrimagnetic material, and an antiferromagnetic material), wherein each of the bias nanomagnet layer and the qubit nanomagnet layer comprises at least one of nanorods, nanodots, nanospheres, nanoplates, and other nanoscale geometries (e.g., including cylindrical, rectangular, or spherical shapes), and wherein each of the bias nanomagnet layer and the qubit nanomagnet layer has a size in a sub -5 -nanometer (nm) range, with linear dimensions along x, y, and z axes each ranging from approximately 0.1 nm to 3 nm or more (e.g., approximately 5 nm); a non-magnetic separation layer, comprising at least one of dielectric materials including magnesium oxide (MgO) and conductive materials including copper (Cu), disposed between the bias nanomagnet layer and the qubit nanomagnet layer, the bias nanomagnet layer and the qubit nanomagnet layer being separated by a physical distance of less than 2 nm (or less than approximately 2 nm), wherein the non-magnetic separation layer is configured to provide structural stability to the quantum system and enable quantum-mechanical spin-exchange coupling between the bias nanomagnet layer and the qubit nanomagnet layer to facilitate quantum entanglement
[0011] J:\UM\l llXClPCT\Application\Application - asfiled.docx / ke between two qubits, and wherein the quantum-mechanical spin-exchange coupling is configured to implement a two-qubit gate comprising a controlled-NOT (CNOT) gate, a SWAP gate, and other quantum logic gates configured (and / or suitable) for constructing quantum computing circuits; and an exchange layer configured to mediate the quantummechanical spin-exchange coupling between two qubit nanomagnet layers, the quantummechanical spin-exchange coupling serving as a primary mechanism for generating quantum entanglement between the two qubit nanomagnet layers. The quantum system can comprise qubits represented by spin projections along a symmetry axis, wherein a singlequbit gate comprises a Hadamard gate and an inverter gate and is configured to control a state of a qubit via at least one of spin-transfer torque (STT), spin-orbit torque (SOT), voltage-controlled magnetic anisotropy (VCMA), and application of a magnetic field; wherein the SOT effect is implemented via a three-terminal device embodiment; and wherein the STT effect is implemented via a two-terminal device embodiment. The VCMA is configured to control quantum entanglement between two qubits, and the VCMA is configured to serve as a voltage-controlled entanglement switch. The single-qubit gate is implemented via the STT effect, wherein the STT effect is implemented by attaching a bias nanomagnet layer and applying a spin-polarized current in one of two possible directions across a junction. The single-qubit gate is implemented via the SOT effect, wherein the SOT effect is implemented by attaching a non-magnetic separation layer to a qubit nanomagnet layer and applying a charge current along plane of a junction. The single-qubit gate is implemented via application of the magnetic field generated by a wire positioned in proximity to a qubit nanomagnet layer, wherein implementation of a selected single-qubit gate is achieved by applying the magnetic field in a specific orientation for a specific duration, wherein applying the magnetic field perpendicular to a main axis of the qubit nanomagnet layer for a duration matched to an energy of the state of the qubit implements the Hadamard gate, and wherein applying the magnetic field along the main axis of the qubit nanomagnet layer implements the inverter gate. The quantum system is configured such that a collapsed quantum state of each qubit is read using at least one of giant magnetoresistance (GMR), tunneling magnetoresistance (TMR), and magnetoelectricity. The array of mutually entangled nanomagnets is configured to serve as an ultra-high- density volatile memory device, wherein an array of N quantum gates is capable of storing 2Nbits of information, and wherein the array of mutually entangled nanomagnets enables
[0012] J:\UM\l llXClPCT\Application\Application - asfiled.docx / ke exploitation of enhanced memory capacity. The hybrid platform is configured to operate at room temperature and to provide scalable quantum-classical processing capabilities, wherein the hybrid platform comprises an Autonomous Hybrid Quantum Nanochip (AHQN) configured to dynamically optimize distribution of computational tasks between the nanomagnetic component and the semiconductor component using Al, and wherein the AHQN is further configured to serve as a platform for executing small- and medium-sized language model applications.
[0013] In another embodiment, a method for generating (miniaturized, custom-built) quantum Al nanomagnetic chips for operating small- and medium-sized language models can comprise: providing a nanomagnetic component comprising a quantum system including an array of mutually entangled nanomagnets configured to perform parallel quantum operations to enable massively parallel, energy-efficient quantum computation; providing a semiconductor component comprising a CMOS circuit, the semiconductor component configured to provide input and output operations to and from the nanomagnetic component via standard electronic communication protocols; and integrating the nanomagnetic component with the semiconductor component to form a hybrid platform. The quantum system can comprise: a bias nanomagnet layer and a quantum bit (qubit) nanomagnet layer, each of the bias nanomagnet layer and the qubit nanomagnet layer being formed of a magnetic material (e.g., comprising at least one of a ferromagnetic material, a ferrimagnetic material, and an antiferromagnetic material), wherein each of the bias nanomagnet layer and the qubit nanomagnet layer comprises at least one of nanorods, nanodots, nanospheres, nanoplates, and other nanoscale geometries (e.g., including cylindrical, rectangular, or spherical shapes), and wherein each of the bias nanomagnet layer and the qubit nanomagnet layer has a size in a sub -5 -nanometer (nm) range, with linear dimensions along x, y, and z axes each ranging from approximately 0.1 nm to 3 nm or more (e.g., approximately 5 nm); a non-magnetic separation layer, comprising at least one of dielectric materials including magnesium oxide (MgO) and conductive materials including copper (Cu), disposed between the bias nanomagnet layer and the qubit nanomagnet layer, the bias nanomagnet layer and the qubit nanomagnet layer being separated by a physical distance of less than 2 nm (or less than approximately 2 nm), wherein the non-magnetic separation layer is configured to provide structural stability to the quantum system and enable quantum-mechanical spin-exchange coupling between the
[0014] J:\UM\l llXClPCT\Application\Application - asfiled.docx / ke bias nanomagnet layer and the qubit nanomagnet layer to facilitate quantum entanglement between two qubits, and wherein the quantum-mechanical spin-exchange coupling is configured to implement a two-qubit gate comprising a controlled-NOT (CNOT) gate, a SWAP gate, and other quantum logic gates configured (and / or suitable) for constructing quantum computing circuits; and an exchange layer configured to mediate the quantummechanical spin-exchange coupling between two qubit nanomagnet layers, the quantummechanical spin-exchange coupling serving as a primary mechanism for generating quantum entanglement between the two qubit nanomagnet layers. The quantum system can comprise qubits represented by spin projections along a symmetry axis, wherein a singlequbit gate comprises a Hadamard gate and an inverter gate and is configured to control a state of a qubit via at least one of STT, SOT, VCMA, and application of a magnetic field; wherein the SOT effect is implemented via a three-terminal device embodiment; and wherein the STT effect is implemented via a two-terminal device embodiment. The VCMA is configured to control quantum entanglement between two qubits, and the VCMA is configured to serve as a voltage-controlled entanglement switch. The single-qubit gate is implemented via the STT effect, wherein the STT effect is implemented by attaching a bias nanomagnet layer and applying a spin-polarized current in one of two possible directions across a junction. The single-qubit gate is implemented via the SOT effect, wherein the SOT effect is implemented by attaching a non-magnetic separation layer to a qubit nanomagnet layer and applying a charge current along plane of a junction. The single-qubit gate is implemented via application of the magnetic field generated by a wire positioned in proximity to a qubit nanomagnet layer, wherein implementation of a selected single-qubit gate is achieved by applying the magnetic field in a specific orientation for a specific duration, wherein applying the magnetic field perpendicular to a main axis of the qubit nanomagnet layer for a duration matched to an energy of the state of the qubit implements the Hadamard gate, and wherein applying the magnetic field along the main axis of the qubit nanomagnet layer implements the inverter gate. The quantum system is configured such that a collapsed quantum state of each qubit is read using at least one of GMR, TMR, and magnetoelectricity. The array of mutually entangled nanomagnets is configured to serve as an ultra-high-density volatile memory device, wherein an array of A quantum gates is capable of storing 1Nbits of information, and wherein the array of mutually entangled nanomagnets enables exploitation of enhanced memory capacity, wherein the hybrid
[0015] J:\UM\l llXClPCT\Application\Application - asfiled.docx / ke platform is configured to operate at room temperature and to provide scalable quantum- classical processing capabilities, wherein the hybrid platform comprises an AHQN configured to dynamically optimize distribution of computational tasks between the nanomagnetic component and the semiconductor component using Al, and wherein the AHQN is further configured to serve as a platform for executing small- and medium-sized language model applications.
[0016] BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 shows a hybrid system comprising a quantum core and a classical complementary metal oxide semiconductor (CMOS) module, according to an embodiment of the subject invention.
[0018] Figure 2 shows a two-quantum bit (qubit) gate with entanglement between two qubits controlled via quantum-mechanical spin-exchange coupling, according to an embodiment of the subject invention.
[0019] Figure 3A shows a two-qubit gate with magnetization oriented in-plane, according to an embodiment of the subject invention.
[0020] Figure 3B shows a two-qubit gate with magnetization oriented out-of-plane, according to an embodiment of the subject invention.
[0021] Figure 4 shows ab initio calculations indicating that a large inter-spin distance (approximately 15 nanometers (nm)) yields incoherent dynamics with a short spin decoherence time, while a small spacing (approximately 3 nm) yields coherent precession with a long de-coherence time (see also, Hong et al., Energy-efficient spin-transfer torque magnetization reversal in sub-10-nm magnetic tunneling junction point contacts, lournal of Nanoparticle Research 15(4), April 2013, doi: 10.1007 / sl 1051-013-1599-0).
[0022] Figure 5 shows simultaneous writing and reading of states of two qubits via a spintransfer torque (STT) effect (see also, Hong et al., 3D multilevel spin transfer torque devices, Appl. Phys. Lett. 112, 112402, 2018, doi. org / 10.1063 / 1.5021336).
[0023] Figure 6 shows magnetic qubit switching in a qubit nanomagnet layer via the STT effect. Current values denoted as IP-AP and IAP-P correspond to switching currents at which magnetization orientation transitions from anti-parallel to parallel state and from parallel to anti-parallel state, respectively. A tunneling magnetoresistance (TMR) effect serves as a
[0024] J:\UM\l llXClPCT\Application\Application - asfiled.docx / ke reading back mechanism. Resistance measured depends on the relative orientation of magnetization in a bias nanomagnet layer and qubit nanomagnet layer.
[0025] Figure 7 shows magnetic qubit switching in the qubit nanomagnet layer via a spinorbit torque (SOT) effect. An additional non-magnetic metal layer is positioned adjacent to the qubit nanomagnet layer. Electrons flowing along a non-magnetic layer generate a torque on the electrons in the qubit nanomagnet layer, causing switching or oscillations at resonant frequencies, typically within the gigahertz (GHz) range. Unlike the STT effect, the SOT effect involves two distinct current directions for write and read operations. The write current is applied parallel to the junction, while the read current is applied perpendicular to the junction. Accordingly, the SOT device is typically implemented as a three-terminal device, in contrast to a two-terminal configuration of the STT device.
[0026] Figure 8 shows magnetic qubit switching in the qubit nanomagnet layer via a voltage-controlled magnetic anisotropy (VCMA) effect. A voltage of 5 V is shown as an example. The exact value can vary depending on material composition and layer configuration. Under the application of positive and negative voltages, magnetocrystalline anisotropy transitions between a perpendicular (out-of-plane) orientation and a longitudinal (in-plane) orientation. During the in-plane anisotropy phase (V > 0), the application of a small external magnetic field is sufficient to determine the final direction of the magnetization when the system returns to the perpendicular state at V = 0. The STT effect is employed during the in-plane anisotropy phase (V > 0), to reduce the required switching currents (AP-AP and AAP-P), thereby defining the final perpendicular magnetization state as the voltage returns to zero.
[0027] Figure 9 shows the VCMA effect functioning as an optional entanglement switch. The VCMA effect is utilized to enable or disable quantum entanglement between two qubits, thereby operating as an entanglement control mechanism.
[0028] Figure 10A shows the implementation of a Hadamard gate via magnetic field biasing. The application of a magnetic field H perpendicular to the initial magnetization direction of the qubit nanomagnet layer, for a predetermined duration, causes a quantum state rotation corresponding to a Hadamard operation.
[0029] Figure 10B shows the implementation of an inverter gate implementing a logical NOT function via magnetic field biasing. The application of a magnetic field H along the
[0030] J:\UM\l llXClPCT\Application\Application - asfiled.docx / ke initial magnetization direction of the qubit nanomagnet layer, for a predetermined duration, causes a state flip corresponding to an inverter gate operation.
[0031] DETAILED DESCRIPTION
[0032] Embodiments of the subject invention provide novel and advantageous systems, devices, and methods for generating miniaturized, custom-built, quantum artificial intelligence (Al) nanomagnetic chips for operating small- and medium-sized language models. A hybrid device, also referred to herein as a “quantum chip,” can comprise two primary components: (i) a nanomagnetic component comprising a quantum system including an array of mutually entangled nanomagnets configured to perform parallel quantum operations to enable massively parallel, energy-efficient quantum computation; and (ii) a semiconductor component comprising a complementary metal oxide semiconductor (CMOS) circuit, the semiconductor component configured to provide input and output operations to and from the nanomagnetic component via standard electronic communication protocols. A quantum processor is operably coupled to the quantum system and is configured to coordinate with classical control logic to perform quantum operations on the bias nanomagnet layer and quantum bit (qubit) nanomagnet layer, enabling hybrid processing for language model execution. The miniaturized hybrid device can be custom- built hardware configured for various applications, such as executing middleware components designed to facilitate the operation and management of language models across diverse computational environments. The array of quantum-mechanically entangled nanomagnets can be designed such that the quantum computing response to input signals and the initial qubit states is optimized for addressing computationally intensive Al training tasks, for example, large matrix multiplications. Given that the nanomagnetic component occupies a micrometer (pm) scale footprint and includes nanomagnetic elements with dimensions in the sub-5-nanometer (nm) range, the nanomagnetic component can be fabricated using advanced patterning techniques and integrated with the CMOS module in a hybrid configuration to provide classical input and output operations.
[0033] Quantum computing is ideally suited for enabling massively parallel computation, with numerous quantum algorithms already developed for Al training. However, despite the widespread interest in quantum computing algorithms, existing hardware implementations are prohibitively expensive and impractical for small-chip Al
[0034] J:\UM\l llXClPCT\Application\Application - asfiled.docx / ke applications, as current quantum computing technologies require unconventional operating conditions, such as extremely low temperatures and high vacuum environments. Embodiments of the subject invention include compact, room -temperature devices comprising quantum cores formed by arrays of entangled nanomagnets with dimensions in the sub-5-nm range. These devices are capable of performing ultra-fast and energy-efficient quantum computing-based parallel computations, making them highly suitable for efficient machine learning (ML) training in small-chip applications. Moreover, any 7V-qubit quantum computing device can be realized by employing only single- and two-qubit gates, which can be accessed simultaneously.
[0035] The quantum-mechanical spin-exchange coupling between the two qubits in each entangled pair governs the degree of entanglement. Accordingly, an important aspect of embodiments of the subject invention is the use of pairs of nanomagnets separated by a distance sufficiently small to enable quantum-mechanical spin-exchange coupling. The exchange coupling energy between the two qubits in each pair can be controlled through effects including spin-transfer torque (STT), spin-orbit torque (SOT), voltage-controlled magnetic anisotropy (VCMA), application of a magnetic field, and other established roomtemperature effects. Each qubit state, defined as the spin projection along a symmetry axis, is similarly controlled via these effects, including STT, SOT, and / or VCMA. Furthermore, parametrization for Al training optimization can be achieved by varying any of these effects, for example, applying a magnetic field for a predetermined duration to facilitate a desired operation, such as a controlled-NOT (cNOT) two-qubit gate. The CMOS-based input and output module can be integrated directly with the quantum nanomagnetic array component to form a hybrid chip, or alternatively, provided as an independent modular component, such as a programmed microcontroller chip. Together, these components enable fabrication of a quantum chip with a maximum dimension not exceeding a few millimeters, for example, no greater than 10 millimeters (mm) or 5 mm.
[0036] An important feature of quantum computing is its “massive quantum parallelism”, which arises from the quantum physics principles of linear state superposition and quantum entanglement. Consequently, the number of basis states utilized for computation increases exponentially with the number of qubits, N, according to 2V. If each basis state is considered equivalent to a single single-qubit processor in classical computation, then N qubits correspond to 2Nprocessors operating in parallel, with each parallel path yielding an
[0037] J:\UM\l llXClPCT\Application\Application - asfiled.docx / ke independent and distinct solution. For example, a 10-qubit computation is equivalent to 210, or 1,024 processors functioning in parallel. The most time- and energy-intensive step in Al applications is the training of ML models, which typically involves computationally demanding operations such as large matrix multiplications. Accordingly, state-of-the-art ML models distribute such computations across thousands of processors (cores), such as those found in graphics processing unit (GPU)-based Al chips. Particularly in the context of emerging small-scale (local) ML applications, minimizing computational time and power consumption is critically important. These local ML applications can be implemented using localized Al chips, which represent transformative technology impacting a broad range of societal sectors including healthcare, commerce, and national security. According to embodiments of the subject invention, a miniaturized array comprising approximately ten closely packed, entangled nanomagnets can achieve computational performance equivalent to that of 1,024 cores operating in parallel.
[0038] Contrary to quantum computing approaches discussed in the Background, nanomagnetic devices exhibit quantum effects at room temperature, thereby enabling potentially high-fidelity single- and two-qubit gates. Nanomagnetic devices demonstrate exceptional scalability as evidenced in the magnetic data storage industry, including ultra- high-density heat-assisted magnetic recording media capable of storing trillions of bits per square inch, with individual bit dimensions in the sub-10-nm range. Additionally, alternative technologies exist that convert electric currents or voltages into magnetic signals, including STT, SOT, VCMA, Rabi oscillations, and others. Accordingly, the present approach leverages both CMOS technology and established magnetic storage techniques to realize a hybrid system incorporating small nanomagnetic quantum chips with classical input and output operations. Such a hybrid system is particularly advantageous for implementing small-model Al applications.
[0039] Figure 1 shows a hybrid system comprising a quantum core and a classical CMOS module. The number of qubits, N, can range from fewer than 10 to more than 1000. In the illustrated example, Ais 10. The hybrid system comprises: (i) a quantum core including A + M entangled nanomagnetic quantum bits; and (ii) a CMOS module configured to provide classical input and output. The CMOS component, such as a microcontroller, is configured to encode classical input quantum bit states, for example, by initializing the Sz spin state of the nanomagnets. The term “& spin state of the nanomagnets” refers to the component of
[0040] J:\UM\l llXClPCT\Application\Application - asfiled.docx / ke the spin angular momentum of the nanomagnets measured along the z-axis, which is typically defined as the quantization or measurement axis.
[0041] The TV + M qubits, each represented by a nanomagnet, are entangled, for example, through pairwise entanglements. Prior to entanglement, quantum superposition among the qubits can be established by applying a Hadamard gate to each qubit. A unitary matrix, Uf, corresponding to a function f(x) can be constructed from: (a) single-qubit gates, such as Hadamard (H), inverter (X), rotator (Y), projector (Z) gates, and others; and (b) two-qubit gates, such as cNOT, SWAP, and others. All single- and two-qubit gates can be implemented using nanomagnets, wherein the electron spin projection of each nanomagnet serves as the qubit state.
[0042] Single-qubit states can be determined by measuring the Sz spin projection of each nanomagnet. Two-qubit states can be represented by pairs of nanomagnets separated by a physical distance sufficiently small to enable quantum-mechanical spin-exchange coupling. The exchange coupling energy between the two qubits in each pair can be controlled via effects including STT, SOT, VCMA, application of a magnetic field, or other established room-temperature effects. Parametrization for Al training can be achieved by varying at least one of these effects, for example, by applying a magnetic field for a specified time period to enable a desired operation such as a cNOT two-qubit gate.
[0043] Nanomagnets within a pair can be arranged in various configurations, provided they maintain quantum-mechanical entanglement. It is generally understood that any A-qubit quantum computing device can be implemented using only single- and two-qubit gates, accessed simultaneously. The quantum-mechanical spin-exchange coupling between the two qubits in each entangled pair governs the degree of entanglement. The entanglement strength can be controlled by factors including the nanomagnet dimensions along all three axes, the separation distance between nanomagnets in each pair, the materials employed, the voltage applied between two qubits, a bias magnetic field oriented in a specific direction for a defined period, and other parameters. Multiple room-temperature physical effects permit control of each qubit’s state through classical input and output parameters such as electric voltage and current. These mechanisms include, without limitation, STT, SOT, VCMA, and others.
[0044] X and Y represent input and output quantum registers, respectively, each comprising 10 qubits corresponding to 210basis states. The function f(X) is an operation represented by
[0045] J:\UM\l llXClPCT\Application\Application - asfiled.docx / ke a unitary operator or matrix, Uf, which can correspond to an Al training operation such as large matrix multiplication.
[0046] Each qubit state can be reset to an initial value using various methods applying a magnetic field by driving a current through a wire positioned adjacent to the qubit, or by employing a reference high-anisotropy ferromagnetic or antiferromagnetic layer separated from the qubit nanomagnet layer by a thin non-magnetic layer, for example, approximately 1 nm thick, and applying a spin-polarized current. During a reset operation, an entanglement switch voltage can be applied to reduce the energy barrier associated with initiating the magnetic states of the qubits, thereby facilitating state initialization. Positioning an initiation wire and / or parametrization coils in close proximity to the respective qubits is critical for maximizing the applied magnetic field H, which is inversely proportional to the distance r between the wire or coil and the qubit (i.e., H oc 1 / r).
[0047] Figure 2 shows a two-qubit gate with the entanglement controlled via quantummechanical spin-exchange coupling with out-of-plane spin orientation. Alternative in-plane orientations are also possible. Embodiments utilize two nanomagnetic structures (nanomagnets), namely a bias nanomagnet layer and a qubit nanomagnet layer, composed of ferromagnetic, ferrimagnetic, or antiferromagnetic materials, with cobalt-iron-boron (CoFeB) being an example of a ferromagnetic material. These nanomagnets can have shapes such as nanorods, nanodots, nanospheres, nanoplates, or other geometries, including cylindrical, rectangular, or spherical forms. Each nanomagnet has linear dimensions along the x, y, and z axes ranging from 0.1 to over 3 nm, with a size in the sub-5-nm range. The nanomagnets are separated by less than approximately 2 nm, optionally filled with a nonmagnetic conducting or non-conducting layer, such as a dielectric thin film such as magnesium oxide (MgO) or a conducting thin film such as copper (Cu), to ensure controlled quantum-mechanical spin-exchange coupling. This coupling enables implementation of two-qubit gates, such as CNOT, SWAP, or others, which serve as building blocks for quantum computing circuits.
[0048] Each qubit can be defined by the spin orientation within a magnetic layer relative to a bias nanomagnet layer (or reference layer), wherein the two layers are separated by a thin non-magnetic spacer layer. The spin orientation can be determined by the selection of materials exhibiting distinct magnetocrystalline anisotropy properties. The two bias nanomagnet layers are configured to maintain a stable magnetization orientation
[0049] J:\UM\l llXClPCT\Application\Application - asfiled.docx / ke throughout the operational lifetime of the quantum gate. To ensure such non-volatility, the bias nanomagnet layers can comprise, for example: (A) high-anisotropy ferromagnetic materials, characterized by magnetic moments of atoms aligned parallel to each other resulting in a strong net magnetization; (B) high-anisotropy ferrimagnetic materials, characterized by magnetic moments of atoms aligned antiparallel with unequal magnitudes, resulting in a net magnetization; and / or (C) high-anisotropy antiferromagnetic layers, characterized by magnetic moments of atoms aligned antiparallel with equal magnitudes, resulting in no net magnetization, wherein the atomic layers exhibit magnetization aligned in a preferred direction.
[0050] The non-magnetic separation layers, which serve to isolate each bias nanomagnet layer from the corresponding qubit nanomagnet layer, can be selected to facilitate control and detection of the respective qubit states by defining or measuring the qubit states relative to the bias states. For example, control and detection of the qubit states relative to the bias states can be achieved by applying a spin-polarized current through each qubit junction. To read the qubit state, the magnitude of the applied current is maintained below the threshold necessary to induce switching of the qubit state via the STT effect. Under such conditions, each qubit state corresponds to a distinct junction resistance, which depends on the relative spin orientations of the qubit nanomagnet layer and the associated bias nanomagnet layer. This resistance can be determined by measuring the voltage across the junction. To write or switch the state of each qubit, the spin-polarized current applied through the junction must exceed the STT switching threshold, thereby inducing a change in the magnetization orientation of the qubit nanomagnet layer.
[0051] The exchange layer is configured to determine the quantum-mechanical spinexchange coupling between the two qubit nanomagnet layers. This coupling serves as the primary mechanism for generating quantum entanglement between the qubits. The magnitude and characteristics of the coupling can be controlled by at least one of the thickness of the exchange layer, the selection of materials comprising the exchange layer, and / or a voltage applied between the two qubit nanomagnet layers. Accordingly, in embodiments of the subject invention, the voltage applied across the exchange layer can be referred to as an entanglement switch voltage, as the applied voltage governs the activation or modulation of the entanglement interaction between two qubit nanomagnet layers.
[0052] J:\UM\l llXClPCT\Application\Application - asfiled.docx / ke The two bias coils can be utilized to apply bias magnetic fields by driving electrical currents through the coils, wherein the coils can optionally comprise different numbers of turns and can be oriented in one of two possible directions. The applied magnetic fields can be used to initiate and / or reset the magnetic states of the two qubits. Additionally, the same bias coils can be employed to perform parametrized optimization of the two-qubit system performance, for example, by adjusting current amplitude, polarity, or temporal profiles to tune operational characteristics.
[0053] Embodiments of the subject invention further provide practical implementations of room-temperature nanomagnetic single-qubit and two-qubit gates, thereby enabling the continued advancement of room-temperature quantum computing systems. Questions relating to quantum supremacy remain unresolved, particularly in the context of cybersecurity and encryption technologies. Addressing such questions requires the development of a scalable quantum computing architecture, wherein hundreds of thousands of physical qubits are made available for computational operations.
[0054] Figure 3 A shows a two-qubit gate configuration with in-plane magnetization, while Figure 3B shows two-qubit gate configuration with out-of-plane magnetization. As described above, each qubit is implemented using a magnetic layer and a corresponding bias nanomagnet layer, separated by a non-magnetic spacer. The distinction between the two configurations lies in the orientation of the magnetization vectors, which can be engineered through material selection, structural design, and anisotropy control. These variations allow for different implementations of qubit states while maintaining nonvolatile operation as previously described.
[0055] The qubit initiation wire can be configured to deliver a magnetic field by driving a current through at least one wire, facilitating the initiation or resetting of qubit states. In some embodiments, a second initiation wire can be arranged in a symmetric configuration above the structure to enhance field uniformity.
[0056] Traditional semiconductor devices are known to exhibit failure when their dimensions are reduced below approximately 5 nm due to charge leakage. In contrast, nanomagnetic devices demonstrate an exponential increase in spin de-coherence time as device size decreases. For example, ab initio physics calculations illustrating the spin decoherence times for nanomagnetic devices with characteristic sizes of approximately 15 nm and 3 nm, respectively, are shown in Figure 4. Further reduction of the qubit size below
[0057] J:\UM\l llXClPCT\Application\Application - asfiled.docx / ke 3 nm is expected to increase the de-coherence time to beyond one millisecond or even seconds, depending on the material employed. This increase in decoherence time is attributed to the strong isolation of the magnetic spin-based quantum-mechanical system from its surrounding environment.
[0058] According to the unitary linear representation of the quantum state machine, any quantum circuit can be constructed using single-qubit and two-qubit gates. In conventional quantum computing theory, information written into the initial input and output register qubits is typically represented as a basis state within a 2 -dimensional Hilbert space, where N denotes the number of qubits. A Hilbert space is a mathematical construct that defines a complete vector space with an inner product, allowing for the representation and manipulation of quantum states as complex vectors. Although the quantum computing machine can operate on complex wavefunctions, which are linear superpositions of multiple basis states within this space, between the initial and final state registers, the final register readout, corresponding to quantum collapse (projection), yields only a single basis state of the N qubit system.
[0059] Following the initiation / reset operation to align the magnetic spins to a predefined orientation (e.g., resetting the two qubit states to (0,0)), any specified qubit states can be achieved by applying a predetermined sequence of electric currents. Such currents can be driven either independently through each qubit junction or collectively through a junction comprising both qubits, in accordance with the underlying physical principles described herein.
[0060] Setting each qubit state independently: As mentioned herein, each qubit state can be controlled independently (single-qubit control) utilizing the STT, SOT, or VCA effects. For example, via the STT effect, driving a spin-polarized current through a junction made of the bias nanomagnet layer and the qubit nanomagnet layer, separated by the thin nonmagnetic separation layer (e.g., less than approximately 1 nm thick), and exceeding the STT switching threshold, enables selective switching of the qubit state. Alternatively, according to the VCA physics, sequential application of voltages QI and Q2, in conjunction with a bias magnetic field of a specified polarity (e.g., generated by the reset wire), can be employed to achieve the target qubit states. Additionally, the relative spin orientations of the qubits (i.e., their quantum states) can be controlled by applying a specialized sequence
[0061] J:\UM\l llXClPCT\Application\Application - asfiled.docx / ke of electric currents through a junction formed by the two qubits, as described in further detail herein.
[0062] Setting two qubit states simultaneously: According to the STT effect, the states of the two qubits can be set simultaneously by applying specific sequences of electric currents to control their relative spin states, as demonstrated using an experimental prototype setup. Further, the relative spin states and consequently the two qubit states can be read back using the STT effect. The underlying physics governing these operations is summarized in Figure 5.
[0063] Reading back qubit states: The readback operation can be performed using established mechanisms such as giant magnetoresistance (GMR), including tunneling magnetoresistance (TMR), wherein the resistance of a junction comprising two magnetic layers depends on the relative orientation of adjacent spins. Alternatively, magnetoelectric effects can be utilized, which exploit the dependence of a magnetic layer’s polarization on its magnetization orientation. These mechanisms enable retrieval of the quantum mechanically collapsed state of each qubit following a measurement operation.
[0064] Figure 6 illustrates magnetic qubit switching in the qubit nanomagnet layer via the STT effect. The current thresholds denoted as IP-AP and IAP-P correspond to the switching currents at which the magnetization orientation transitions from the parallel to anti-parallel state and from the anti-parallel to parallel state, respectively. The TMR effect is used as the readback mechanism, wherein the resistance measured across the junction depends on the relative magnetization orientations of the bias nanomagnet layer and the qubit nanomagnet layer. A one qubit logic gate, such as an inverter or a Hadamard gate, can be implemented using the STT effect. This can be achieved by incorporating a reference magnetic layer, such as a ferromagnetic, ferrimagnetic, or antiferromagnetic material, and applying a spin polarized current across the junction in one of two possible directions.
[0065] Figure 7 illustrates magnetic qubit switching in the qubit nanomagnet layer via the SOT effect. In this configuration, a non-magnetic metal layer is positioned adjacent to the qubit nanomagnet layer. When an electric current is applied along the non-magnetic metal layer, it generates a torque on the spins in the qubit nanomagnet layer, resulting in magnetization switching or inducing oscillations at resonant frequencies, typically within the gigahertz (GHz) range. Unlike the STT effect, which uses a single current path for both write and read operations, the SOT effect utilizes two distinct current directions: the write
[0066] J:\UM\l llXClPCT\Application\Application - asfiled.docx / ke current is applied parallel to the junction, while the read current is applied perpendicular to the junction. As a result, the SOT-based device is typically implemented in a three-terminal configuration, as opposed to the two-terminal configuration used for STT-based devices. A one qubit logic gate, such as an inverter or a Hadamard gate, can be implemented using the SOT effect by incorporating a non-magnetic metal layer adjacent to the qubit nanomagnet layer and applying a current along the junction to induce SOT-based switching of the qubit nanomagnet layer.
[0067] Figure 8 shows magnetic qubit switching in the qubit nanomagnet layer via the VCMA effect. A voltage of 5 V is shown as an example. The exact value can vary depending on the material composition and layer configuration. Under the application of positive and negative voltages, the magnetocrystalline anisotropy transitions between a perpendicular (out-of-plane) orientation and a longitudinal (in-plane) orientation. During the in-plane anisotropy phase (V > 0), the application of a small external magnetic field is sufficient to determine the final direction of the magnetization when the system returns to the perpendicular state at V = 0. The STT effect is employed during the in-plane anisotropy phase (V > 0), to reduce the required switching currents (AP-AP and AAP-P), thereby defining the final perpendicular magnetization state as the voltage returns to zero.
[0068] Figure 9 shows the VCMA effect functioning as an optional entanglement switch. The VCMA effect is utilized to enable or disable quantum entanglement between two qubits, thereby operating as an entanglement control mechanism.
[0069] A single-qubit gate, such as an inverter or a Hadamard gate, can be implemented via the application of a magnetic field generated by a wire positioned in close proximity to the qubit. To achieve the optimal qubit state transformation, the magnetic field must be applied in a specific orientation and for a predetermined duration. For example, the application of a magnetic field perpendicular to the initial magnetization direction of the qubit nanomagnet layer, for a defined period of time matched to the energy of the quantum state, induces a quantum state rotation corresponding to a Hadamard gate operation, as shown in Figure 10A. Conversely, applying the magnetic field along the initial magnetization direction for a predetermined duration results in a complete state flip, implementing a logical NOT function corresponding to an inverter gate, as shown in Figure 10B.
[0070] J:\UM\l llXClPCT\Application\Application - asfiled.docx / ke An entangled array comprising the aforementioned two-qubit and single-qubit gates can be employed to realize an ultra-high-density data storage device, suitable for volatile memory applications. Utilizing an array of N gates, the system can store 2Nbits of information. For instance, with only 100 qubits, approximately 2100(~ 1033) bits (equivalent to 1032bytes) of information can be stored within a remarkably small volume occupied by 100 sub-5-nm qubits. For comparison, a large-scale internet data center typically stores on the order of 10 exabytes (1019bytes), which is significantly less than the storage capacity of a quantum system comprising merely 100 qubits. When integrated with conventional semiconductor technology in a hybrid configuration, this substantial memory capacity can be effectively utilized.
[0071] The nanomagnet-based quantum computing architecture can be integrated with existing semiconductor technology to form a hybrid quantum-semiconductor platform enabling highly scalable, room-temperature operation. This technology combines the quantum computational capabilities of the nanomagnetic components with the classical input and output operations provided by conventional semiconductor electronics to realize an Autonomous Hybrid Quantum Nanochip (AHQN). The AHQN employs Al to optimize the allocation of computational tasks between the quantum and classical elements. The AHQN platform can serve as a foundation for a new generation of small- and mediumsized language model applications.
[0072] Embodiments of the subject invention provide a focused technical solution to the focused technical problem of how to generate (miniaturized, custom-built) quantum Al nanomagnetic chips for operating small- and medium-sized language models. The solution is provided by a hybrid platform integrating a nanomagnetic quantum system with mutually entangled nanomagnets for parallel, energy-efficient computation, and a CMOS-based semiconductor circuit for input and output via standard electronic protocols. The hybrid platform is configured for room-temperature operation and scalable quantum-classical processing, comprising an AHQN that dynamically optimizes task distribution between the nanomagnetic and semiconductor components using Al, and serves as a platform for executing small- and medium-sized language model applications. The system operates at room temperature because the nanomagnetic materials retain stable spin states under typical thermal conditions, while the semiconductor integration enables efficient control and readout mechanisms without the need for cryogenic environments. The technical solution
[0073] J:\UM\l llXClPCT\Application\Application - asfiled.docx / ke provided by embodiments of the subject invention is specific to computer technology, addresses a technical problem within the field of computer technology, and results in improved computer systems by enabling massively parallel, energy-efficient quantum computation through parallel quantum operations and enhancing memory capacity.
[0074] The methods and processes described herein can be embodied as code and / or data. The software code and data described herein can be stored on one or more machine- readable media (e.g., computer-readable media), which may include any device or medium that can store code and / or data for use by a computer system. When a computer system and / or processor reads and executes the code and / or data stored on a computer-readable medium, the computer system and / or processor performs the methods and processes embodied as data structures and code stored within the computer-readable storage medium.
[0075] It should be appreciated by those skilled in the art that computer-readable media include removable and non-removable structures / devices that can be used for storage of information, such as computer-readable instructions, data structures, program modules, and other data used by a computing system / environment. A computer-readable medium includes, but is not limited to, volatile memory such as random access memories (RAM, DRAM, SRAM); and non-volatile memory such as flash memory, various read-only- memories (ROM, PROM, EPROM, EEPROM), magnetic and ferromagnetic / ferroelectric memories (MRAM, FeRAM), and magnetic and optical storage devices (hard drives, magnetic tape, CDs, DVDs); network devices; or other media now known or later developed that are capable of storing computer-readable information / data. Computer- readable media should not be construed or interpreted to include any propagating signals. A computer-readable medium of embodiments of the subject invention can be, for example, a compact disc (CD), digital video disc (DVD), flash memory device, volatile memory, or a hard disk drive (HDD), such as an external HDD or the HDD of a computing device, though embodiments are not limited thereto. A computing device can be, for example, a laptop computer, desktop computer, server, cell phone, or tablet, though embodiments are not limited thereto.
[0076] When the term module is used herein, it can refer to software and / or one or more algorithms to perform the function of the module; alternatively, the term module can refer to a physical device configured to perform the function of the module (e.g., by having software and / or one or more algorithms stored thereon).
[0077] J:\UM\l llXClPCT\Application\Application - asfiled.docx / ke When ranges are used herein, combinations and subcombinations of ranges (including any value or subrange contained therein) are intended to be explicitly included. When the term “about” or “approximately” is used herein, in conjunction with a numerical value, it is understood that the value can be in a range of 95% of the value to 105% of the value, i.e. the value can be + / - 5% of the stated value. For example, “about 1 kg” means from 0.95 kg to 1.05 kg.
[0078] It should be understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application.
[0079] All patents, patent applications, provisional applications, and publications referred to or cited herein (including in the “References” section) are incorporated by reference in their entirety, including all figures and tables, to the extent they are not inconsistent with the explicit teachings of this specification.
[0080] J:\UM\l llXClPCT\Application\Application - asfiled.docx / ke REFERENCES
[0081] [1] J. M. Hong, P. Liang, V. L. Safonov, and S. Khizroev, "Energy-efficient spintransfer torque magnetization reversal in sub-10-nm magnetic tunneling junction point contacts," (in English), J Nanopart Res, vol. 15, no. 4, Apr 2013, doi: ARTN 1599 10.1007 / S11051-013-1599-0.
[0082] [2] J. Hong et al., "A Dual Magnetic Tunnel Junction-Based Neuromorphic Device," (in English), Adv Intell Syst-Ger, vol. 2, no. 12, Dec 2020, doi: ARTN 2000143
[0083] 10.1002 / aisy.202000143.
[0084] [3] B. Navarrete et al., "Nanomagnetic Particle-Based Information Processing," (in English), leee T Nanotechnol, vol. 18, pp. 983-988, 2019, doi:
[0085] 10.1109 / Tnano.2019.2939009.
[0086] [4] J. M. Hong et al., "Demonstration of spin transfer torque (STT) magnetic recording," (in English), Appl Phys Lett, vol. 114, no. 24, Jun 17 2019, doi: Artn 243101
[0087] 10.1063 / 1.5097546. [5] Hong et al., Energy -efficient spin-transfer torque magnetization reversal in sub-
[0088] 10-nm magnetic tunneling junction point contacts, Journal of Nanoparticle Research 15(4), April 2013, doi: 10.1007 / sl 1051-013-1599-0.
[0089] [6] Hong et al., 3D multilevel spin transfer torque devices, Appl. Phys. Lett. 112, 112402, 2018, doi. org / 10.1063 / 1.5021336.
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Claims
CLAIMSWhat is claimed is:
1. A system for generating quantum artificial intelligence (Al) nanomagnetic chips for operating small- and medium-sized language models, the system comprising: a nanomagnetic component comprising a quantum system including an array of mutually entangled nanomagnets configured to perform parallel quantum operations to enable massively parallel, energy-efficient quantum computation; and a semiconductor component comprising a complementary metal oxide semiconductor (CMOS) circuit, the semiconductor component configured to provide input and output operations to and from the nanomagnetic component via standard electronic communication protocols, wherein the nanomagnetic component is integrated with the semiconductor component in a hybrid platform.
2. The system according to claim 1, wherein the quantum system comprises: a bias nanomagnet layer and a quantum bit (qubit) nanomagnet layer, each of the bias nanomagnet layer and the qubit nanomagnet layer being formed of a magnetic material comprising at least one of a ferromagnetic material, a ferrimagnetic material, and an antiferromagnetic material, wherein each of the bias nanomagnet layer and the qubit nanomagnet layer comprises at least one of nanorods, nanodots, nanospheres, nanoplates, and other nanoscale geometries, including cylindrical, rectangular, or spherical shapes, and wherein each of the bias nanomagnet layer and the qubit nanomagnet layer has a size in a sub-5-nanometer (nm) range, with linear dimensions along x, y, and z axes each ranging from approximately 0.1 nm to approximately 5 nm; a non-magnetic separation layer, comprising at least one of dielectric materials including magnesium oxide (MgO) and conductive materials including copper (Cu), disposed between the bias nanomagnet layer and the qubit nanomagnet layer, the bias nanomagnet layer and the qubit nanomagnet layer being separated by a physical distance of less than 2 nm, wherein the non-magnetic separation layer is configured to provide structural stability to the quantum system and enable quantum-mechanical spin-exchangeJ:\UM\l llXClPCT\Application\Application - asfiled.docx / kecoupling between the bias nanomagnet layer and the qubit nanomagnet layer to facilitate quantum entanglement between two qubits, and wherein the quantum-mechanical spinexchange coupling is configured to implement a two-qubit gate comprising a controlled- NOT (CNOT) gate, a SWAP gate, and other quantum logic gates configured for constructing quantum computing circuits; and an exchange layer that is configured to mediate the quantum-mechanical spinexchange coupling between two qubit nanomagnet layers, the quantum-mechanical spinexchange coupling serving as a primary mechanism for generating quantum entanglement between the two qubit nanomagnet layers.
3. The system according to any of claims 1-2, wherein the quantum system comprises qubits represented by spin projections along a symmetry axis, wherein a single-qubit gate comprises a Hadamard gate and an inverter gate and is configured to control a state of a qubit via at least one of spin-transfer torque (STT), spinorbit torque (SOT), voltage-controlled magnetic anisotropy (VCMA), and application of a magnetic field, wherein the SOT effect is implemented via a three-terminal device embodiment, and wherein the STT effect is implemented via a two-terminal device embodiment.
4. The system according to claim 3, wherein the VCMA is configured to control quantum entanglement between two qubits, and wherein the VCMA is configured to serve as a voltage-controlled entanglement switch.
5. The system according to any of claims claim 3-4, wherein the single-qubit gate is implemented via the STT effect, wherein the STT effect is implemented by attaching a bias nanomagnet layer and applying a spin-polarized current in one of two possible directions across a junction.
6. The system according to any of claims 3-5, wherein the single-qubit gate is implemented via the SOT effect, wherein the SOT effect is implemented by attaching aJ:\UM\l llXClPCT\Application\Application - asfiled.docx / kenon-magnetic separation layer to a qubit nanomagnet layer and applying a charge current along plane of a junction.
7. The system according to any of claims 3-6, wherein the single-qubit gate is implemented via application of the magnetic field generated by a wire positioned in proximity to a qubit nanomagnet layer, wherein implementation of a selected single-qubit gate is achieved by applying the magnetic field in a specific orientation for a specific duration, wherein applying the magnetic field perpendicular to a main axis of the qubit nanomagnet layer for a duration matched to an energy of the state of the qubit implements the Hadamard gate, and wherein applying the magnetic field along the main axis of the qubit nanomagnet layer implements the inverter gate.
8. The system according to any of claims 1-7, wherein the quantum system is configured such that a collapsed quantum state of each qubit is read using at least one of giant magnetoresistance (GMR), tunneling magnetoresistance (TMR), and magnetoel ectri city .
9. The system according to any of claims 1-8, wherein the array of mutually entangled nanomagnets is configured to serve as an ultra-high-density volatile memory device, wherein an array of N quantum gates is capable of storing 2Nbits of information, and wherein the array of mutually entangled nanomagnets enables exploitation of enhanced memory capacity.
10. The system according to any of claims 1-9, wherein the hybrid platform is configured to operate at room temperature and to provide scalable quantum-classical processing capabilities,J:\UM\l llXClPCT\Application\Application - asfiled.docx / kewherein the hybrid platform comprises an Autonomous Hybrid Quantum Nanochip (AHQN) configured to dynamically optimize distribution of computational tasks between the nanomagnetic component and the semiconductor component using Al, and wherein the AHQN is further configured to serve as a platform for executing small- and medium-sized language model applications.
11. A method for generating quantum artificial intelligence (Al) nanomagnetic chips for operating small- and medium-sized language models, the method comprising: providing a nanomagnetic component comprising a quantum system including an array of mutually entangled nanomagnets configured to perform parallel quantum operations to enable massively parallel, energy-efficient quantum computation; providing a semiconductor component comprising a complementary metal oxide semiconductor (CMOS) circuit, the semiconductor component configured to provide input and output operations to and from the nanomagnetic component via standard electronic communication protocols; and integrating the nanomagnetic component with the semiconductor component to form a hybrid platform.
12. The method according to claim 11, wherein the quantum system comprises: a bias nanomagnet layer and a quantum bit (qubit) nanomagnet layer, each of the bias nanomagnet layer and the qubit nanomagnet layer being formed of a magnetic material comprising at least one of a ferromagnetic material, a ferrimagnetic material, and an antiferromagnetic material, wherein each of the bias nanomagnet layer and the qubit nanomagnet comprises at least one of nanorods, nanodots, nanospheres, nanoplates, and other nanoscale geometries, including cylindrical, rectangular, or spherical shapes, and wherein each of the bias nanomagnet layer and the qubit nanomagnet layer has a size in a sub-5-nanometer range, having linear dimensions along x, y, and z axes each ranging from approximately 0.1 nm to approximately 5 nm; a non-magnetic separation layer between the bias nanomagnet layer and the qubit nanomagnet layer, the non-magnetic separation layer comprising at least one of dielectric materials including magnesium oxide (MgO) and conductive materials including copper (Cu), and wherein the bias nanomagnet layer and the qubit nanomagnet layer are separatedJ:\UM\l llXClPCT\Application\Application - asfiled.docx / keby a physical distance of less than 2 nm, wherein the non-magnetic separation layer is configured to provide structural stability to the quantum system and to enable quantummechanical spin-exchange coupling between the bias nanomagnet layer and the qubit nanomagnet layer to facilitate quantum entanglement between two qubits, and wherein the quantum-mechanical spin-exchange coupling is configured to implement a two-qubit gate comprising at least one of a controlled-NOT (CNOT) gate, a SWAP gate, and other quantum logic gates configured for constructing quantum computing circuits, via the quantum-mechanical spin-exchange coupling; and an exchange layer that is configured to mediate the quantum-mechanical spinexchange coupling between two qubit nanomagnet layers, the quantum-mechanical spinexchange coupling serving as a primary mechanism for generating quantum entanglement between the two qubit nanomagnet layers.
13. The method according to any of claims 11-12, wherein the quantum system comprises qubits represented by spin projections along a symmetry axis, wherein a single-qubit gate comprises a Hadamard gate and an inverter gate and is configured to control a state of a qubit via at least one of spin-transfer torque (STT), spinorbit torque (SOT), voltage-controlled magnetic anisotropy (VCMA), and application of a magnetic field, wherein the SOT effect is implemented via a three-terminal device embodiment, and wherein the STT effect is implemented via a two-terminal device embodiment.
14. The method according to claim 13, wherein the VCMA is configured to control quantum entanglement between two qubits, and wherein the VCMA is configured to serve as a voltage-controlled entanglement switch.
15. The method according to any of claims 13-14, wherein the single-qubit gate is implemented via the STT effect, wherein the STT effect is implemented by attaching a bias nanomagnet layer and applying a spin-polarized current in one of two possible directions across a junction.J:\UM\l llXClPCT\Application\Application - asfiled.docx / ke16. The method according to any of claims 13-15, wherein the single-qubit gate is implemented via the SOT effect, wherein the SOT effect is implemented by attaching a non-magnetic separation layer to a qubit nanomagnet layer and applying a charge current along plane of a junction.
17. The method according to any of claims 13-16, wherein the single-qubit gate is implemented via application of the magnetic field generated by a wire positioned in proximity to a qubit nanomagnet layer, wherein implementation of a selected single-qubit gate is achieved by applying the magnetic field in a specific orientation for a specific duration, wherein applying the magnetic field perpendicular to a main axis of the qubit nanomagnet layer for a duration matched to an energy of the state of the qubit implements the Hadamard gate, and wherein applying the magnetic field along the main axis of the qubit nanomagnet layer implements the inverter gate.
18. The method according to any of claims 11-17, wherein the quantum system is configured such that a collapsed quantum state of each qubit is read using at least one of giant magnetoresistance (GMR), tunneling magnetoresistance (TMR), and magnetoel ectri city .
19. The method according to any of claims 11-18, wherein the array of mutually entangled nanomagnets is configured to serve as an ultra-high-density volatile memory device, wherein an array of N quantum gates is capable of storing 2Nbits of information, and wherein the array of mutually entangled nanomagnets enables exploitation of enhanced memory capacity.
20. The method according to any of claims 11-19, wherein the hybrid platform is configured to operate at room temperature and to provide scalable quantum-classical processing capabilities,J:\UM\l llXClPCT\Application\Application - asfiled.docx / kewherein the hybrid platform comprises an Autonomous Hybrid Quantum Nanochip (AHQN) configured to dynamically optimize distribution of computational tasks between the nanomagnetic component and the semiconductor component using Al, and wherein the AHQN is further configured to serve as a platform for executing small- and medium-sized language model applications.J:\UM\l llXClPCT\Application\Application - asfiled.docx / ke