Multiple transform selection with reduced storage for video coding

Abstract

A device for decoding video data is configured to determine a size of a block of the encoded video data; determine that the size of the block exceeds a threshold; in response to the size of the block being greater than the threshold, select a reduced set of transform pairs from the set of transform pairs, wherein the reduced set of transform pairs includes fewer than all transform pairs of the set of transform pairs; select a transform pair from the reduced set of transform pairs; inverse transform transform coefficients based on the selected transform pair to determine a residual block for the block of video data; determine a decoded representation of the block using the residual block; and output the decoded representation of the block.

Description

PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 1MULTIPLE TRANSFORM SELECTION WITH REDUCED STORAGE FOR VIDEO CODING

[0001] This application is a PCT application that claims benefit of U.S. Provisional Patent Application No. 63 / 742,741, filed 7 January 2025 and U.S. Provisional Patent Application No. 63 / 730,377, filed 10 December 2024, the entire content of each application being incorporated herein by reference.TECHNICAL FIELD

[0002] This disclosure relates to video encoding and video decoding.BACKGROUND

[0003] Digital video capabilities can be incorporated into a wide range of devices, including digital televisions, digital direct broadcast systems, wireless broadcast systems, personal digital assistants (PDAs), laptop or desktop computers, tablet computers, e-book readers, digital cameras, digital recording devices, digital media players, video gaming devices, video game consoles, cellular or satellite radio telephones, so-called “smart phones,” video teleconferencing devices, video streaming devices, and the like. Digital video devices implement video coding techniques, such as those described in the standards defined by MPEG-2, MPEG-4, ITU-T H.263, ITU-T H.264 / MPEG-4, Part 10, Advanced Video Coding (AVC), ITU-T H.265 / High Efficiency Video Coding (HEVC), ITU-T H.266 / Versatile Video Coding (VVC), and extensions of such standards, as well as proprietary video codecs / formats such as AOMedia Video 1 (AVI) that was developed by the Alliance for Open Media. The video devices may transmit, receive, encode, decode, and / or store digital video information more efficiently by implementing such video coding techniques.

[0004] Video coding techniques include spatial (intra-picture) prediction and / or temporal (inter-picture) prediction to reduce or remove redundancy inherent in video sequences. For block-based video coding, a video slice (e.g., a video picture or a portion of a video picture) may be partitioned into video blocks, which may also be referred to as coding tree units (CTUs), coding units (CUs) and / or coding nodes. Video blocks in an intracoded (I) slice of a picture are encoded using spatial prediction with respect to reference samples in neighboring blocks in the same picture. Video blocks in an inter-coded (P or B) slice of a picture may use spatial prediction with respect to reference samples in1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 2 neighboring blocks in the same picture or temporal prediction with respect to reference samples in other reference pictures. Pictures may be referred to as frames, and reference pictures may be referred to as reference frames.SUMMARY

[0005] The techniques of this disclosure relate to multiple transform selection (MTS) for intra coding. MTS allows a video coder to select a transform pair from a set of available transforms, such as a discrete cosine transform of type 2 (DCT2), DCT8, or a discrete sine transform of type 7 (DST7). These transforms are realized using separable horizontal and vertical transform kernels. To support MTS across all block sizes, these distinct transform kernels may be defined for all possible block dimensions, which can range up to 256x256 samples. Defining and storing this large number of kernels for every potential block size results in significant memory (e.g., read-only memory (ROM)) requirements, which can be challenging and costly for hardware implementations.

[0006] The techniques of this disclosure address this issue by constraining the use of MTS based on block size. According to these techniques, a video coder determines a size for a block of video data and compares the size to a threshold. In response to the size of the block being greater than the threshold, the video coder selects a transform pair from a reduced set of transform pairs that is smaller than the full set available for smaller blocks. For blocks with a size less than or equal to the threshold, the full set of transform pairs remains available for selection. In some examples, for blocks larger than the threshold, the reduced set may include only a single default transform pair, such as DCT2 for both horizontal and vertical transforms.

[0007] By limiting the available transforms for larger block sizes, the techniques of this disclosure reduce the overall memory requirements for a video coder. Because transform kernels for certain transform types are no longer needed for larger dimensions, the memory required to store those transform kernels may be reduced or eliminated, allowing for smaller sized memory or allowing memory to be available for other operations, which promotes faster processing. Furthermore, these techniques may also reduce encoding complexity, as an encoder has fewer transform candidates to evaluate for larger blocks. This reduction in memory and complexity is achieved with little to no negative impact on compression performance, as the alternative transforms used in MTS provide diminishing returns for larger, more homogeneous blocks of video data.1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 3

[0008] The techniques of this disclosure also include signaling the threshold in the encoded bitstream. By signaling the threshold in the encoded bitstream, video encoders may be able to customize bitstreams based on the hardware that will be used to decode the bitstreams. For example, a video encoder may be configured to produce a basic bitstream for simpler hardware with lower memory space, setting a lower threshold for simpler hardware and an enhanced bitstream for more advanced hardware with higher memory space, setting a higher threshold for more advanced hardware.

[0009] According to an example of this disclosure, a method of decoding a bitstream of encoded video data includes: determining that the size of the block exceeds a threshold; in response to the size of the block being greater than the threshold, selecting a reduced set of transform pairs from a set of transform pairs, wherein the reduced set of transform pairs includes fewer than all transform pairs of the set of transform pairs; selecting a transform pair from the reduced set of transform pairs; inverse transforming transform coefficients based on the selected transform pair to determine a residual block for the block of video data; determining a decoded representation of the block using the residual block; and outputting the decoded representation of the block.

[0010] According to an example of this disclosure, a device for decoding a bitstream of encoded video data includes: at least one memory configured to store a set of transform pairs; and processing circuitry communicatively coupled to the at least one memory, the processing circuitry configured to: determine a size of a block of the encoded video data; determine that the size of the block exceeds a threshold; in response to the size of the block being greater than the threshold, select a reduced set of transform pairs from the set of transform pairs, wherein the reduced set of transform pairs includes fewer than all transform pairs of the set of transform pairs; select a transform pair from the reduced set of transform pairs; inverse transform transform coefficients based on the selected transform pair to determine a residual block for the block of video data; determine a decoded representation of the block using the residual block; and output the decoded representation of the block.

[0011] According to an example of this disclosure, an apparatus for decoding a bitstream of encoded video data includes: means for storing a set of transform pairs; means for determining a size of a block of the encoded video data; means for determining that the size of the block exceeds a threshold; means for selecting a reduced set of transform pairs from the set of transform pairs in response to the size of the block being greater than the threshold, wherein the reduced set of transform pairs includes fewer than all transform1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 4 pairs of the set of transform pairs; means for selecting a transform pair from the reduced set of transform pairs; means for inverse transforming transform coefficients based on the selected transform pair to determine a residual block for the block of video data; means for determining a decoded representation of the block using the residual block; and means for outputting the decoded representation of the block.

[0012] A computer-readable storage medium stores instructions that when executed by one or more processors cause the one or more processors to: determine a size of a block of encoded video data; determine that the size of the block exceeds a threshold; in response to the size of the block being greater than the threshold, select a reduced set of transform pairs from the set of transform pairs, wherein the reduced set of transform pairs includes fewer than all transform pairs of the set of transform pairs; select a transform pair from the reduced set of transform pairs; inverse transform transform coefficients based on the selected transform pair to determine a residual block for the block of video data; determine a decoded representation of the block using the residual block; and output the decoded representation of the block.

[0013] According to an example of this disclosure, a method of encoding video data includes: storing a set of transform pairs; determining a size of a block of the video data; determining that the size of the block exceeds a threshold; in response to the size of the block being greater than the threshold, selecting a reduced set of transform pairs from the set of transform pairs, wherein the reduced set of transform pairs includes fewer than all transform pairs of the set of transform pairs; selecting a transform pair from the reduced set of transform pairs; generating a residual block for the block of video data; transforming the residual block based on the selected transform pair to determine transform coefficients; and encoding the transform coefficients into a bitstream.

[0014] According to an example of this disclosure, a device for encoding video data includes: at least one memory configured to store a set of transform pairs; and processing circuitry communicatively coupled to the at least one memory, the processing circuitry configured to: determine a size of a block of the video data; determine that the size of the block exceeds a threshold; in response to the size of the block being greater than the threshold, select a reduced set of transform pairs from the set of transform pairs, wherein the reduced set of transform pairs includes fewer than all transform pairs of the set of transform pairs; select a transform pair from the reduced set of transform pairs; generate a residual block for the block of video data; transform the residual block based on the1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 5 selected transform pair to determine transform coefficients; and encode the transform coefficients into a bitstream.

[0015] According to an example of this disclosure, an apparatus for encoding video data includes: means for storing a set of transform pairs; means for determining a size of a block of the video data; means for determining that the size of the block exceeds a threshold; means for selecting a reduced set of transform pairs from the set of transform pairs in response to the size of the block being greater than the threshold, wherein the reduced set of transform pairs includes fewer than all transform pairs of the set of transform pairs; means for selecting a transform pair from the reduced set of transform pairs; means for generating a residual block for the block of video data; means for transforming the residual block based on the selected transform pair to determine transform coefficients; and means for encoding the transform coefficients into a bitstream.

[0016] A computer-readable storage medium stores instructions that when executed by one or more processors cause the one or more processors to: determine a size of a block of video data; determine that the size of the block exceeds a threshold; in response to the size of the block being greater than the threshold, select a reduced set of transform pairs from a set of transform pairs, wherein the reduced set of transform pairs includes fewer than all transform pairs of the set of transform pairs; select a transform pair from the reduced set of transform pairs; generate a residual block for the block of video data; transform the residual block based on the selected transform pair to determine transform coefficients; and encode the transform coefficients into a bitstream.

[0017] The details of one or more examples are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will be apparent from the description, drawings, and claims.BRIEF DESCRIPTION OF DRAWINGS

[0018] FIG. 1 is a block diagram illustrating an example video encoding and decoding system that may perform the techniques of this disclosure.

[0019] FIG. 2 is a block diagram illustrating an example video encoder that may perform the techniques of this disclosure.

[0020] FIG. 3 is a block diagram illustrating an example video decoder that may perform the techniques of this disclosure.

[0021] FIG. 4 is a flowchart illustrating an example process for encoding a current block in accordance with the techniques of this disclosure.1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 6

[0022] FIG. 5 is a flowchart illustrating an example process for decoding a current block in accordance with the techniques of this disclosure.

[0023] FIG. 6 is a flowchart illustrating an example process for decoding a current block in accordance with the techniques of this disclosure.DETAILED DESCRIPTION

[0024] Video coding (e.g., video encoding and / or video decoding) typically involves predicting a block of video data from either an already coded block of video data in the same picture (e.g., intra prediction) or an already coded block of video data in a different picture (e.g., inter prediction). A video encoder or a video decoder may generate a prediction block using this already coded block. In some instances, the video encoder also calculates residual data by comparing the prediction block to the original block. Thus, the residual data represents a difference between the prediction block and the original block. To reduce the number of bits needed to signal the residual data, the video encoder transforms and quantizes the residual data and signals the transformed and quantized residual data in the encoded bitstream. The compression achieved by the transform and quantization processes may be lossy, meaning that transform and quantization processes may introduce distortion into the decoded video data.

[0025] A video decoder decodes and adds the residual data to the prediction block to produce a reconstructed video block that matches the original video block more closely than the prediction block alone. Due to the loss introduced by the transforming and quantizing of the residual data, the reconstructed block may have distortion or artifacts. One common type of artifact or distortion is referred to as blockiness, where the boundaries of the blocks used to code the video data are visible.

[0026] To further improve the quality of decoded video, a video decoder can perform one or more filtering operations on the reconstructed video blocks. Examples of these filtering operations include deblocking filtering, sample adaptive offset (SAO) filtering, and adaptive loop filtering (ALF). Parameters for these filtering operations may either be determined by a video encoder and explicitly signaled in the encoded video bitstream or may be implicitly determined by a video decoder without needing the parameters to be explicitly signaled in the encoded video bitstream.

[0027] The techniques of this disclosure relate to multiple transform selection (MTS) for intra coding. As described above, a video encoder transforms the residual data to generate transform coefficients, and a video decoder inverse transforms the transform coefficients1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 7 to generate the residual data. There may be a plurality of transforms that the video encoder applies to transform and the video decoder applies to inverse transform. Accordingly, the video encoder and the video decoder may each determine which transform to apply, such as using the techniques described in this disclosure.

[0028] MTS allows a video coder to select a transform pair from a set of available transforms, such as a discrete cosine transform of type 2 (DCT2), DCT8, or a discrete sine transform of type 7 (DST7). These transforms are realized using separable horizontal and vertical transform kernels. To support MTS across all block sizes, these distinct transform kernels may be defined for all possible block dimensions, which can range up to 256x256 samples. Defining and storing this large number of kernels for every potential block size results in significant read-only memory (ROM) requirements, which can be challenging and costly for hardware implementations.

[0029] The techniques of this disclosure address this issue by constraining the use of MTS based on block size. According to these techniques, a video coder determines a size for a block of video data and compares it to a threshold. In response to the size of the block being greater than the threshold, the video coder selects a transform pair from a reduced set of transform pairs that is smaller than the full set available for smaller blocks. For blocks with a size less than or equal to the threshold, the full set of transform pairs remains available for selection. In some examples, forblocks larger than the threshold, the reduced set may include only a single default transform pair, such as DCT2 for both horizontal and vertical transforms.

[0030] By limiting the available transforms for larger block sizes, the techniques of this disclosure reduce the overall memory requirements for a video coder. Because transform kernels for certain transform types are no longer needed for larger dimensions, the ROM required to store them is eliminated. Furthermore, these techniques may also reduce encoding complexity, as an encoder has fewer transform candidates to evaluate for larger blocks. This reduction in memory and complexity is achieved with little to no negative impact on compression performance, as the alternative transforms used in MTS provide diminishing returns for larger, more homogeneous blocks of video data.

[0031] The techniques of this disclosure also include signaling the threshold in the encoded bitstream. By signaling the threshold in the encoded bitstream, video encoders may be able to customize bitstreams based on the hardware that will be used to decode the bitstreams. For example, a video encoder may be configured to produce a basic bitstream for simpler hardware and an enhanced bitstream for more advanced hardware.1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 8

[0032] FIG. 1 is a block diagram illustrating an example video encoding and decoding system 100 that may perform the techniques of this disclosure. The techniques of this disclosure are generally directed to coding (encoding and / or decoding) video data. In general, video data includes any data for processing a video. Thus, video data may include raw, unencoded video, encoded video, decoded (e.g., reconstructed) video, and video metadata, such as signaling data.

[0033] As shown in FIG. 1, system 100 includes a source device 102 that provides encoded video data to be decoded and displayed by a destination device 116, in this example. In particular, source device 102 provides the video data to destination device 116 via a computer-readable medium 110. Source device 102 and destination device 116 may be or include any of a wide range of devices, such as desktop computers, notebook (i.e., laptop) computers, mobile devices, tablet computers, set-top boxes, telephone handsets such as smartphones, televisions, cameras, display devices, digital media players, video gaming consoles, video streaming device, broadcast receiver devices, or the like. In some cases, source device 102 and destination device 116 may be equipped for wireless communication, and thus may be referred to as wireless communication devices.

[0034] In the example of FIG. 1, source device 102 includes video source 104, memory 106, video encoder 200, and output interface 108. Destination device 116 includes input interface 122, video decoder 300, memory 120, and display device 118. In accordance with this disclosure, video encoder 200 of source device 102 and video decoder 300 of destination device 116 may be configured to apply the techniques for MTS in intra coding. Thus, source device 102 represents an example of a video encoding device, while destination device 116 represents an example of a video decoding device. In other examples, a source device and a destination device may include other components or arrangements. For example, source device 102 may receive video data from an external video source, such as an external camera. Likewise, destination device 116 may interface with an external display device, rather than include an integrated display device.

[0035] System 100 as shown in FIG. 1 is merely one example. In general, any digital video encoding and / or decoding device may perform techniques for MTS in intra coding. Source device 102 and destination device 116 are merely examples of such coding devices in which source device 102 generates coded video data for transmission to destination device 116. This disclosure refers to a “coding” device as a device that performs coding (encoding and / or decoding) of data. Thus, video encoder 200 and video decoder 3001616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 9 represent examples of coding devices, in particular, a video encoder and a video decoder, respectively. In some examples, source device 102 and destination device 116 may operate in a substantially symmetrical manner such that each of source device 102 and destination device 116 includes video encoding and decoding components. Hence, system 100 may support one-way or two-way video transmission between source device 102 and destination device 116, e.g., for video streaming, video playback, video broadcasting, or video telephony.

[0036] In general, video source 104 represents a source of video data (i.e., raw, unencoded video data) and provides a sequential series of pictures (also referred to as “frames”) of the video data to video encoder 200, which encodes data for the pictures. Video source 104 of source device 102 may include a video capture device, such as a video camera, a video archive containing previously captured raw video, and / or a video feed interface to receive video from a video content provider. As a further alternative, video source 104 may generate computer graphics-based data as the source video, or a combination of live video, archived video, and computer-generated video. In each case, video encoder 200 encodes the captured, pre-captured, or computer-generated video data. Video encoder 200 may rearrange the pictures from the received order (sometimes referred to as “display order”) into a coding order for coding. Video encoder 200 may generate a bitstream including encoded video data. Source device 102 may then output the encoded video data via output interface 108 onto computer-readable medium 110 for reception and / or retrieval by, e.g., input interface 122 of destination device 116.

[0037] Memory 106 of source device 102 and memory 120 of destination device 116 represent general purpose memories. In some examples, memories 106, 120 may store raw video data, e.g., raw video from video source 104 and raw, decoded video data from video decoder 300. Additionally or alternatively, memories 106, 120 may store software instructions executable by, e.g., video encoder 200 and video decoder 300, respectively. Although memory 106 and memory 120 are shown separately from video encoder 200 and video decoder 300 in this example, it should be understood that video encoder 200 and video decoder 300 may also include internal memories for functionally similar or equivalent purposes. Furthermore, memories 106, 120 may store encoded video data, e.g., output from video encoder 200 and input to video decoder 300. In some examples, portions of memories 106, 120 may be allocated as one or more video buffers, e.g., to store raw, decoded, and / or encoded video data.1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 10

[0038] Computer-readable medium 110 may represent any type of medium or device capable of transporting the encoded video data from source device 102 to destination device 116. In one example, computer-readable medium 110 represents a communication medium to enable source device 102 to transmit encoded video data directly to destination device 116 in real-time, e.g., via a radio frequency network or computer-based network. Output interface 108 may modulate a transmission signal including the encoded video data, and input interface 122 may demodulate the received transmission signal, according to a communication standard, such as a wireless communication protocol. The communication medium may include any wireless or wired communication medium, such as a radio frequency (RF) spectrum or one or more physical transmission lines. The communication medium may form part of a packet-based network, such as a local area network, a wide-area network, or a global network such as the Internet. The communication medium may include routers, switches, base stations, or any other equipment that may be useful to facilitate communication from source device 102 to destination device 116.

[0039] In some examples, source device 102 may output encoded data from output interface 108 to storage device 112. Similarly, destination device 116 may access encoded data from storage device 112 via input interface 122. Storage device 112 may include any of a variety of distributed or locally accessed data storage media such as a hard drive, Blu-ray discs, DVDs, CD-ROMs, flash memory, volatile or non-volatile memory, or any other suitable digital storage media for storing encoded video data.

[0040] In some examples, source device 102 may output encoded video data to file server 114 or another intermediate storage device that may store the encoded video data generated by source device 102. Destination device 116 may access stored video data from file server 114 via streaming or download.

[0041] File server 114 may be any type of server device capable of storing encoded video data and transmitting that encoded video data to the destination device 116. File server 114 may represent a web server (e.g., for a website), a server configured to provide a file transfer protocol service (such as File Transfer Protocol (FTP) or File Delivery over Unidirectional Transport (FLUTE) protocol), a content delivery network (CDN) device, a hypertext transfer protocol (HTTP) server, a Multimedia Broadcast Multicast Service (MBMS) or Enhanced MBMS (eMBMS) server, and / or a network attached storage (NAS) device. File server 114 may, additionally or alternatively, implement one or more HTTP streaming protocols, such as Dynamic Adaptive Streaming over HTTP (DASH),1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 11HTTP Live Streaming (HLS), Real Time Streaming Protocol (RTSP), HTTP Dynamic Streaming, or the like.

[0042] Destination device 116 may access encoded video data from file server 114 through any standard data connection, including an Internet connection. This may include a wireless channel (e.g., a Wi-Fi connection), a wired connection (e.g., digital subscriber line (DSL), cable modem, etc.), or a combination of both that is suitable for accessing encoded video data stored on file server 114. Input interface 122 may be configured to operate according to any one or more of the various protocols discussed above for retrieving or receiving media data from file server 114, or other such protocols for retrieving media data.

[0043] Output interface 108 and input interface 122 may represent wireless transmitters / receivers, modems, wired networking components (e.g., Ethernet cards), wireless communication components that operate according to any of a variety of IEEE 802.11 standards, or other physical components. In examples where output interface 108 and input interface 122 include wireless components, output interface 108 and input interface 122 may be configured to transfer data, such as encoded video data, according to a cellular communication standard, such as 4G, 4G-LTE (Long-Term Evolution), LTE Advanced, 5G, or the like. In some examples where output interface 108 includes a wireless transmitter, output interface 108 and input interface 122 may be configured to transfer data, such as encoded video data, according to other wireless standards, such as an IEEE 802.11 specification, an IEEE 802.15 specification (e.g., ZigBee™), a Bluetooth™ standard, or the like. In some examples, source device 102 and / or destination device 116 may include respective system-on-a-chip (SoC) devices. For example, source device 102 may include an SoC device to perform the functionality attributed to video encoder 200 and / or output interface 108, and destination device 116 may include an SoC device to perform the functionality attributed to video decoder 300 and / or input interface 122.

[0044] The techniques of this disclosure may be applied to video coding in support of any of a variety of multimedia applications, such as over-the-air television broadcasts, cable television transmissions, satellite television transmissions, Internet streaming video transmissions, such as dynamic adaptive streaming over HTTP (DASH), digital video that is encoded onto a data storage medium, decoding of digital video stored on a data storage medium, or other applications.1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 12

[0045] Input interface 122 of destination device 116 receives an encoded video bitstream from computer-readable medium 110 (e.g., a communication medium, storage device 112, file server 114, or the like). The encoded video bitstream may include signaling information defined by video encoder 200, which is also used by video decoder 300, such as syntax elements having values that describe characteristics and / or processing of video blocks or other coded units (e.g., slices, pictures, groups of pictures, sequences, or the like). Display device 118 displays decoded pictures of the decoded video data to a user. Display device 118 may represent any of a variety of display devices such as a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, or another type of display device.

[0046] Although not shown in FIG. 1, in some examples, video encoder 200 and video decoder 300 may each be integrated with an audio encoder and / or audio decoder (e.g., audio codec), and may include appropriate MUX-DEMUX units, or other hardware and / or software, to handle multiplexed streams including both audio and video in a common data stream. Example audio codecs may include AAC, AC-3, AC-4, ALAC, ALS, AMBE, AMR, AMR-WB (G.722.2), AMR-WB+, aptx (various versions), ATRAC, BroadVoice (BV16, BV32), CELT, Enhanced AC-3 (E-AC-3), EVS, FLAC, G.711, G.722, G.722.1, G.722.2 (AMR-WB). G.723.1, G.726, G.728, G.729, G.729.1, GSM-FR, HE-AAC, iLBC, iSAC, LA Lyra, Monkey's Audio, MP1, MP2 (MPEG-1, 2 Audio Layer II), MP3, Musepack, Nellymoser Asao, OptimFROG, Opus, Sac, Satin, SBC, SILK, Siren 7, Speex, SVOPC, True Audio (TTA), TwinVQ, USAC, Vorbis (Ogg), WavPack, and Windows Media Aud.

[0047] Video encoder 200 and video decoder 300 each may be implemented as any of a variety of suitable encoder and / or decoder circuitry that includes a processing system, such as one or more microprocessors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), discrete logic, software, hardware, firmware or any combinations thereof. When the techniques are implemented partially in software, a device may store instructions for the software in a suitable, non-transitory computer-readable medium and execute the instructions in hardware using one or more processors to perform the techniques of this disclosure. Each of video encoder 200 and video decoder 300 may be included in one or more encoders or decoders, either of which may be integrated as part of a combined encoder / decoder (CODEC) in a respective device. A device including video encoder 200 and / or video decoder 300 may implement video encoder 200 and / or video decoder 300 in processing1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 13 circuitry such as an integrated circuit and / or a microprocessor. Such a device may be a wireless communication device, such as a cellular telephone, or any other type of device described herein.

[0048] Video encoder 200 and video decoder 300 may operate according to a video coding standard, such as ITU-T H.265, also referred to as High Efficiency Video Coding (HEVC) or extensions thereto, such as the multi-view and / or scalable video coding extensions. Alternatively, video encoder 200 and video decoder 300 may operate according to other proprietary or industry standards, such as ITU-T H.266, also referred to as Versatile Video Coding (VVC). In other examples, video encoder 200 and video decoder 300 may operate according to a proprietary video codec / format, such as AOMedia Video 1 (AVI), extensions of AVI, and / or successor versions of AVI (e.g., AV2). In other examples, video encoder 200 and video decoder 300 may operate according to other proprietary formats or industry standards. The techniques of this disclosure, however, are not limited to any particular coding standard or format. In general, video encoder 200 and video decoder 300 may be configured to perform the techniques of this disclosure in conjunction with any video coding techniques that use transforms with intra coding.

[0049] In general, video encoder 200 and video decoder 300 may perform block-based coding of pictures. The term “block” generally refers to a structure including data to be processed (e.g., encoded, decoded, or otherwise used in the encoding and / or decoding process). For example, a block may include a two-dimensional matrix of samples of luminance and / or chrominance data. In general, video encoder 200 and video decoder 300 may code video data represented in a YUV (e.g., Y, Cb, Cr) format. That is, rather than coding red, green, and blue (RGB) data for samples of a picture, video encoder 200 and video decoder 300 may code luminance and chrominance components, where the chrominance components may include both red hue and blue hue chrominance components. In some examples, video encoder 200 converts received RGB formatted data to a YUV representation prior to encoding, and video decoder 300 converts the YUV representation to the RGB format. Alternatively, pre- and post-processing units (not shown) may perform these conversions.

[0050] This disclosure may generally refer to coding (e.g., encoding and decoding) of pictures to include the process of encoding or decoding data of the picture. Similarly, this disclosure may refer to coding of blocks of a picture to include the process of encoding or decoding data for the blocks, e.g., prediction and / or residual coding. An encoded video1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 14 bitstream generally includes a series of values for syntax elements representative of coding decisions (e.g., coding modes) and partitioning of pictures into blocks. Thus, references to coding a picture or a block should generally be understood as coding values for syntax elements forming the picture or block.

[0051] HEVC defines various blocks, including coding units (CUs), prediction units (PUs), and transform units (TUs). According to HEVC, a video coder (such as video encoder 200) partitions a coding tree unit (CTU) into CUs according to a quadtree structure. That is, the video coder partitions CTUs and CUs into four equal, nonoverlapping squares, and each node of the quadtree has either zero or four child nodes. Nodes without child nodes may be referred to as “leaf nodes,” and CUs of such leaf nodes may include one or more PUs and / or one or more TUs. The video coder may further partition PUs and TUs. For example, in HEVC, a residual quadtree (RQT) represents partitioning of TUs. In HEVC, PUs represent inter-prediction data, while TUs represent residual data. CUs that are intra-predicted include intra-prediction information, such as an intra-mode indication.

[0052] As another example, video encoder 200 and video decoder 300 may be configured to operate according to VVC. According to VVC, a video coder (such as video encoder 200) partitions a picture into a plurality of CTUs. Video encoder 200 may partition a CTU according to a tree structure, such as a quadtree-binary tree (QTBT) structure or Multi-Type Tree (MTT) structure. The QTBT structure removes the concepts of multiple partition types, such as the separation between CUs, PUs, and TUs of HEVC. A QTBT structure includes two levels: a first level partitioned according to quadtree partitioning, and a second level partitioned according to binary tree partitioning. A root node of the QTBT structure corresponds to a CTU. Leaf nodes of the binary trees correspond to CUs.

[0053] In an MTT partitioning structure, blocks may be partitioned using a quadtree (QT) partition, a binary tree (BT) partition, and one or more types of triple tree (TT) (also called ternary tree (TT)) partitions. A triple or ternary tree partition is a partition where a block is split into three sub-blocks. In some examples, a triple or ternary tree partition divides a block into three sub-blocks without dividing the original block through the center. The partitioning types in MTT (e.g., QT, BT, and TT), may be symmetrical or asymmetrical.

[0054] When operating according to the AVI codec, video encoder 200 and video decoder 300 may be configured to code video data in blocks. In AVI, the largest coding block that can be processed is called a superblock. In AVI, a superblock can be either 128x128 luma samples or 64x64 luma samples. However, in successor video coding formats (e.g.,1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 15AV2), a superblock may be defined by different (e.g., larger) luma sample sizes. In some examples, a superblock is the top level of a block quadtree. Video encoder 200 may further partition a superblock into smaller coding blocks. Video encoder 200 may partition a superblock and other coding blocks into smaller blocks using square or nonsquare partitioning. Non-square blocks may include N / 2xN, NxN / 2, N / 4xN, and NxN / 4 blocks. Video encoder 200 and video decoder 300 may perform separate prediction and transform processes on each of the coding blocks.

[0055] AVI also defines a tile of video data. A tile is a rectangular array of superblocks that may be coded independently of other tiles. That is, video encoder 200 and video decoder 300 may encode and decode, respectively, coding blocks within a tile without using video data from other tiles. However, video encoder 200 and video decoder 300 may perform filtering across tile boundaries. Tiles may be uniform or non-uniform in size. Tile-based coding may enable parallel processing and / or multi-threading for encoder and decoder implementations.

[0056] In some examples, video encoder 200 and video decoder 300 may use a single QTBT or MTT structure to represent each of the luminance and chrominance components, while in other examples, video encoder 200 and video decoder 300 may use two or more QTBT or MTT structures, such as one QTBT / MTT structure for the luminance component and another QTBT / MTT structure for both chrominance components (or two QTBT / MTT structures for respective chrominance components).

[0057] Video encoder 200 and video decoder 300 may be configured to use quadtree partitioning, QTBT partitioning, MTT partitioning, superblock partitioning, or other partitioning structures.

[0058] In some examples, a CTU includes a coding tree block (CTB) of luma samples, two corresponding CTBs of chroma samples of a picture that has three sample arrays, or a CTB of samples of a monochrome picture or a picture that is coded using three separate color planes and syntax structures used to code the samples. A CTB may be an NxN block of samples for some value of N such that the division of a component into CTBs is a partitioning. A component is an array or single sample from one of the three arrays (luma and two chroma) that compose a picture in 4:2:0, 4:2:2, or 4:4:4 color format or the array or a single sample of the array that compose a picture in monochrome format. In some examples, a coding block is an MxN block of samples for some values of M and N such that a division of a CTB into coding blocks is a partitioning.1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 16

[0059] The blocks (e.g., CTUs or CUs) may be grouped in various ways in a picture. As one example, a brick may refer to a rectangular region of CTU rows within a particular tile in a picture. A tile may be a rectangular region of CTUs within a particular tile column and a particular tile row in a picture. A tile column refers to a rectangular region of CTUs having a height equal to the height of the picture and a width specified by syntax elements (e.g., such as in a picture parameter set). A tile row refers to a rectangular region of CTUs having a height specified by syntax elements (e.g., such as in a picture parameter set) and a width equal to the width of the picture.

[0060] In some examples, a tile may be partitioned into multiple bricks, each of which may include one or more CTU rows within the tile. A tile that is not partitioned into multiple bricks may also be referred to as a brick. However, a brick that is a true subset of a tile may not be referred to as a tile. The bricks in a picture may also be arranged in a slice. A slice may be an integer number of bricks of a picture that may be exclusively contained in a single network abstraction layer (NAL) unit. In some examples, a slice includes either a number of complete tiles or only a consecutive sequence of complete bricks of one tile.

[0061] This disclosure may use “NxN” and “N by N” interchangeably to refer to the sample dimensions of a block (such as a CU or other video block) in terms of vertical and horizontal dimensions, e.g., 16x16 samples or 16 by 16 samples. In general, a 16x16 CU will have 16 samples in a vertical direction (y = 16) and 16 samples in a horizontal direction (x = 16). Likewise, an NxN CU generally has N samples in a vertical direction and N samples in a horizontal direction, where N represents a nonnegative integer value. The samples in a CU may be arranged in rows and columns. Moreover, CUs need not necessarily have the same number of samples in the horizontal direction as in the vertical direction. For example, CUs may include NxM samples, where M is not necessarily equal to N.

[0062] Video encoder 200 encodes video data for CUs representing prediction and / or residual information, and other information. The prediction information indicates how the CU is to be predicted in order to form a prediction block for the CU. The residual information generally represents sample-by-sample differences between samples of the CU prior to encoding and the prediction block.

[0063] To predict a CU, video encoder 200 may generally form a prediction block for the CU through inter-prediction or intra-prediction. Inter-prediction generally refers to predicting the CU from data of a previously coded picture, whereas intra-prediction1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 17 generally refers to predicting the CU from previously coded data of the same picture. To perform inter-prediction, video encoder 200 may generate the prediction block using one or more motion vectors. Video encoder 200 may generally perform a motion search to identify a reference block that closely matches the CU, e.g., in terms of differences between the CU and the reference block. Video encoder 200 may calculate a difference metric using a sum of absolute difference (SAD), sum of squared differences (SSD), mean absolute difference (MAD), mean squared differences (MSD), or other such difference calculations to determine whether a reference block closely matches the current CU. In some examples, video encoder 200 may predict the current CU using uni-directional prediction or bi-directional prediction.

[0064] Some examples of VVC also provide an affine motion compensation mode, which may be considered an inter-prediction mode. In affine motion compensation mode, video encoder 200 may determine two or more motion vectors that represent non-translational motion, such as zoom in or out, rotation, perspective motion, or other irregular motion types.

[0065] To perform intra-prediction, video encoder 200 may select an intra-prediction mode to generate the prediction block. Some examples of VVC provide sixty-seven intraprediction modes, including various directional modes, as well as planar mode and DC mode. In general, video encoder 200 selects an intra-prediction mode that describes neighboring samples to a current block (e.g., a block of a CU) from which to predict samples of the current block. Such samples may generally be above, above and to the left, or to the left of the current block in the same picture as the current block, assuming video encoder 200 codes CTUs and CUs in raster scan order (left to right, top to bottom).

[0066] Video encoder 200 encodes data representing the prediction mode for a current block. For example, for inter-prediction modes, video encoder 200 may encode data representing which of the various available inter-prediction modes is used, as well as motion information for the corresponding mode. For uni-directional or bi-directional inter-prediction, for example, video encoder 200 may encode motion vectors using advanced motion vector prediction (AMVP) or merge mode. Video encoder 200 may use similar modes to encode motion vectors for affine motion compensation mode.

[0067] AVI includes two general techniques for encoding and decoding a coding block of video data. The two general techniques are intra prediction (e.g., intra frame prediction or spatial prediction) and inter prediction (e.g., inter frame prediction or temporal prediction). In the context of AVI, when predicting blocks of a current frame of video1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 18 data using an intra prediction mode, video encoder 200 and video decoder 300 do not use video data from other frames of video data. For most intra prediction modes, video encoder 200 encodes blocks of a current frame based on the difference between sample values in the current block and predicted values generated from reference samples in the same frame. Video encoder 200 determines predicted values generated from the reference samples based on the intra prediction mode.

[0068] Following prediction, such as intra-prediction or inter-prediction of a block, video encoder 200 may calculate residual data for the block. The residual data, such as a residual block, represents sample by sample differences between the block and a prediction block for the block, formed using the corresponding prediction mode. Video encoder 200 may apply one or more transforms to the residual block, to produce transformed data in a transform domain instead of the sample domain. For example, video encoder 200 may apply a discrete cosine transform (DCT), an integer transform, a wavelet transform, or a conceptually similar transform to residual video data. Additionally, video encoder 200 may apply a secondary transform following the first transform, such as a mode-dependent non-separable secondary transform (MDNSST), a signal dependent transform, a Karhunen-Loeve transform (KLT), or the like. Video encoder 200 produces transform coefficients following application of the one or more transforms.

[0069] As noted above, following any transforms to produce transform coefficients, video encoder 200 may perform quantization of the transform coefficients. Quantization generally refers to a process in which transform coefficients are quantized to possibly reduce the amount of data used to represent the transform coefficients, providing further compression. By performing the quantization process, video encoder 200 may reduce the bit depth associated with some or all of the transform coefficients. For example, video encoder 200 may round an n-bit value down to an m-bit value during quantization, where n is greater than m. In some examples, to perform quantization, video encoder 200 may perform a bitwise right-shift of the value to be quantized.

[0070] Following quantization, video encoder 200 may scan the transform coefficients, producing a one-dimensional vector from the two-dimensional matrix including the quantized transform coefficients. The scan may be designed to place higher energy (and therefore lower frequency) transform coefficients at the front of the vector and to place lower energy (and therefore higher frequency) transform coefficients at the back of the vector. In some examples, video encoder 200 may utilize a predefined scan order to scan the quantized transform coefficients to produce a serialized vector, and then entropy1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 19 encode the quantized transform coefficients of the vector. In other examples, video encoder 200 may perform an adaptive scan. After scanning the quantized transform coefficients to form the one-dimensional vector, video encoder 200 may entropy encode the one-dimensional vector, e.g., according to context-adaptive binary arithmetic coding (CABAC). Video encoder 200 may also entropy encode values for syntax elements describing metadata associated with the encoded video data for use by video decoder 300 in decoding the video data.

[0071] To perform CABAC, video encoder 200 may assign a context within a context model to a symbol to be transmitted. The context may relate to, for example, whether neighboring values of the symbol are zero-valued or not. The probability determination may be based on a context assigned to the symbol.

[0072] Video encoder 200 may further generate syntax data, such as block-based syntax data, picture-based syntax data, and sequence-based syntax data, to video decoder 300, e.g., in a picture header, a block header, a slice header, or other syntax data, such as a sequence parameter set (SPS), picture parameter set (PPS), or video parameter set (VPS). Video decoder 300 may likewise decode such syntax data to determine how to decode corresponding video data.

[0073] In this manner, video encoder 200 may generate a bitstream including encoded video data, e.g., syntax elements describing partitioning of a picture into blocks (e.g., CUs) and prediction and / or residual information for the blocks. Ultimately, video decoder 300 may receive the bitstream and decode the encoded video data.

[0074] In general, video decoder 300 performs a reciprocal process to that performed by video encoder 200 to decode the encoded video data of the bitstream. For example, video decoder 300 may decode values for syntax elements of the bitstream using CABAC in a manner substantially similar to, albeit reciprocal to, the CABAC encoding process of video encoder 200. The syntax elements may define partitioning information for partitioning of a picture into CTUs, and partitioning of each CTU according to a corresponding partition structure, such as a QTBT structure, to define CUs of the CTU. The syntax elements may further define prediction and residual information for blocks (e.g., CUs) of video data.

[0075] The residual information may be represented by, for example, quantized transform coefficients. Video decoder 300 may inverse quantize and inverse transform the quantized transform coefficients of a block to reproduce a residual block for the block. Video decoder 300 uses a signaled prediction mode (intra- or inter-prediction) and related1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 20 prediction information (e.g., motion information for inter-prediction) to form a prediction block for the block. Video decoder 300 may then combine the prediction block and the residual block (on a sample-by-sample basis) to reproduce the original block. Video decoder 300 may perform additional processing, such as performing a deblocking process to reduce visual artifacts along boundaries of the block.

[0076] Any of the video encoding or video decoding processes described above may be performed using a neural network (NN). Additionally or alternatively, a neural network may be trained to efficiently compress video data without necessarily separately performing prediction and residual coding. Studies have shown that embedding neural networks into the hybrid video coding framework of video encoder 200 and video decoder 300 can improve compression efficiency. Neural networks may be used for intra prediction and inter prediction to improve the prediction efficiency. NN-based in-loop filtering and / or post-filtering have also performed well in heuristic testing.

[0077] For example, video encoder 200 and video decoder may use one or more NN- based filters for existing filters, such as deblocking filters, sample adaptive offset (SAO), and / or adaptive loop filtering (ALF). NN-based filters can also be applied exclusively, where NN-based filters are designed to replace all of the existing filters. Additionally or alternatively, NN-based filters may be designed to supplement, enhance, or replace any or all of the other filters.

[0078] In some examples, an NN-based filter may be a convolutional neural network (CNN)-based filter with multiple layers. An NN-based filtering process may take reconstructed samples as inputs, and may add the intermediate outputs back to the inputs to refine the input samples. The NN-based filter may use all color components (e.g., Y, U, and V, or Y, Cb, and Cr) as inputs to exploit cross-component correlations. Different color components may share the same filters (including network structure and model parameters) or each component may have its own specific filters.

[0079] The filtering process can also be generalized as follows:7?'(bj) = R(i,j) + NN_filter_residual_output R')Here, R(i, j) represents a reconstructed sample at position (i, j) in the picture, R’(i, j) represents the filtered version of the reconstructed sample, and NN filter residual output(R) represents the intermediate samples discussed above that are calculated by the NN filter. The model structure and model parameters of NN-based filter(s) can be pre-defined and be stored at video encoder 200 and video decoder 300. The filters can also be signaled in the bitstream.1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 21

[0080] In some examples, an NN-based filter may include a series of feature extraction layers, followed by an output convolution. The feature extraction layers may include a 3x3 convolution (conv) layer followed by a parametric rectified linear unit (PReLU) layer. The convolutional layer applies a convolution operation to the input data, which involves a filter or kernel processing the input data (e.g., the reconstruction samples) in a sliding window fashion and computing dot products at each position. The convolution operation essentially captures local patterns within the input data. For example, in the context of image processing, these patterns could be edges, textures, or other visual features. The filter or kernel is a small matrix of weights that gets updated during the training process. By sliding this filter across the input data (or feature map from a previous layer) and computing the dot product at each position, the convolutional layer creates a feature map that encodes spatial hierarchies and patterns detected in the input. The output of a convolutional layer is a set of feature maps, each corresponding to one filter, capturing different aspects of the input data. This layer helps the neural network to learn increasingly complex and abstract features as the data passes through deeper layers of the network.

[0081] The PReLU layer is an activation function used in neural networks, and is a variant of the ReLU (Rectified Linear Unit) activation function. As described above, the convolution layer outputs feature maps, each corresponding to one filter, representing detected features in the input. Following the convolution layer, the PReLU layer applies the PReLU activation function to each element of the feature maps produced by the convolution layer. For positive values, the PReLU layer acts like a standard ReLU, passing the value through. For negative values, instead of setting them to zero (e.g., as ReLU does), the PReLU layer allows a small, linear, negative output. This keeps neurons of the NN active and maintains the gradient flow, which can be beneficial for learning in deep networks.

[0082] When NN-based filtering is applied in video coding, the whole video signal (pixel data) may be split into multiple processing units (e.g., 2D blocks), and each processing unit can be processed separately or be combined with other information associated with this block of pixels. For example, a processing unit may be a frame, a slice / tile, a CTU, or any pre-defined or signaled shapes and sizes. Typically, NN-based filtering is performed on reconstructed blocks of video data. Here, reconstructed blocks and samples may refer to both decoded blocks produced by video decoder 300, as well blocks reconstructed in a reconstruction loop of video encoder 200.1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 22

[0083] To further improve the performance of NN-based filtering, different types of input data can be processed jointly to produce the filtered output. Input data may include, but is not limited to, reconstruction pixels / samples, prediction pixels / samples, pixels / samples after the loop filter(s), partitioning structure information, deblocking parameters (e.g., boundary strength (BS)), quantization parameter (QP) values, slice or picture types, or a filters applicability or coding modes map. Input data can be provided at different granularities. Luma reconstruction and prediction samples may be provided at the original resolution, whereas chroma samples may be provided at lower resolution, e.g., for 4:2:0 representation, or can be up-sampled to the Luma resolution to achieve per-pixel representation. Similarly, QP, BS, partitioning, or coding mode information can be provided at lower resolution, including cases with a single value per frame, slice or processing block (e.g., QP). In other examples, QP, BS, partitioning, or coding mode information can be expanded (e.g., replicated) to achieve per-pixel / sample representation.

[0084] To further improve the performance of NN-based filtering, multi-mode solutions can be used. For example, for each processing unit, video encoder 200 may select a mode from a set of modes based on rate-distortion optimization and signal the selected mode in the bit-stream. The different modes may include different NN models, different values that may be used as the input information of the NN models, etc. In one example, video encoder 200 and video decoder 300 may use an NN-based filtering solution with multiple modes based on a single NN model by using different QP values as input to the NN model for different modes.

[0085] This disclosure may generally refer to “signaling” certain information, such as syntax elements. The term “signaling” may generally refer to the communication of values for syntax elements and / or other data used to decode encoded video data. That is, video encoder 200 may signal values for syntax elements in the bitstream. In general, signaling refers to generating a value in the bitstream. As noted above, source device 102 may transport the bitstream to destination device 116 substantially in real time, or not in real time, such as might occur when storing syntax elements to storage device 112 for later retrieval by destination device 116.

[0086] Video encoder 200 and video decoder 300 may be configured to perform MTS with intra coding. In enhanced compression model (ECM), MTS is realized using separable transforms, i.e., with a pair of vertical and horizontal transform pairs. MTS in ECM is implemented in two distinct ways: explicitly and implicitly. In explicit MTS, there are multiple choices (i.e., multiple transform pairs) for transform selection, and the1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 23 choices are signaled in the bitstream. The choices are transform block shape and intraprediction mode dependent. The number of choices depends on the sum of absolute level of coefficients, and the value of number of choices can be 1, 4 or 6. The implicit MTS uses an implicit process for determining a transform without signaling, i.e., only a single choice of a transform pair is defined for a given coding block, and the choice is dependent on a transform block shape and an intra prediction mode.

[0087] The transform kernels for horizontal and vertical transforms are chosen from seven distinct transforms: DCT2, DCT8, DST7, DCT5, DST4, DST1, and an identity transform (IDTR). In ECM, MTS is used for all block sizes, and thus, these kernels are defined for all block sizes (block size 2, 4, 8, 16, 32, 64, 128, 256).

[0088] In ECM, in a template-based intra mode derivation (TIMD)-merge process, the intra-coding related information is inherited from the merge candidate. Here, the transform pairs may also be inherited from the merge candidate.

[0089] In ECM, the kernels being defined for all block sizes leads to significant ROM requirements for storing those kernels. According to the techniques of this disclosure, MTS usage is constrained in order to reduce the ROM requirements. The following techniques may be implemented independently or in a combined way.

[0090] In one example, explicit MTS may be only allowed for smaller block sizes, e.g., for blocks having width and / or height less or equal than a specified threshold. For other (larger) blocks, only a specific transform kernel (e.g., DCT2) is allowed both in horizontal and vertical direction. In such examples, other kernels do not need to be defined for larger block sizes, hence requiring reduced ROM storage. Accordingly, signaling for MTS for larger block sizes may be omitted. In some examples, a high-level syntax such as an SPS level flag (or alternatively a PPS, slice level, etc., flag) may be signaled to indicate the specified threshold. In some examples, such thresholds may be a power of 2, and only a finite number of thresholds may be allowed to limit the signaling overhead. In some examples, the allowable threshold may be 32, 64, 128 and 256. The signaling of such threshold may be done in fixed length (in this case, signaling could be done in fixed 2 bits) or alternatively, the signaling may be done in variable-length coding.

[0091] In some examples, a high layer syntax element such as an SPS level flag may be signaled to indicate if any additional kernel other than DCT2, DCT8 and DST7, e.g., kernels other than those existed in VVC, are to be used for coding. For example, if the flag is 0, no additional kernels other than DCT2, DCT8 and DST7 are to be used for the coding. As another example, video encoder 200 may set the flag to 0 when generating a1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 24 bitstream and, in response, restrict transform selection during encoding to only kernels from the set of DCT2, DCT8, and DST7. Video decoder 300 may receive the bitstream, parse the flag from a high-level syntax structure, and in response to the flag being 0, select inverse transforms only from the set of DCT2, DCT8, and DST7 for decoding the video data.

[0092] In one example, a reduced set of transform kernels are used for larger block sizes (where either width and / or height larger than some threshold). For example, only DCT2 and DST7 may be used as transforms. As an illustration, video encoder 200 may determine a block size exceeds the threshold and, in response, select a forward transform only from the reduced set of DCT2 and DST7 for encoding. Correspondingly, video decoder 300 may determine that the block size exceeds the threshold and, in response, select an inverse transform only from the reduced set of DCT2 and DST7 to reconstruct the block.

[0093] In one example, MTS may be still used for larger block sizes, but with a reduced number of kernels. For example, only DCT2, DST7, and DCT8 may be allowed for larger block sizes for MTS. For instance, when encoding a block determined to be larger than a threshold, video encoder 200 may perform transform selection by evaluating only transform pairs derived from a reduced set of kernels (e.g., DCT2, DST7, DCT8). Correspondingly, video decoder 300, after determining the block size exceeds the threshold, may also apply an inverse transform selected from only the reduced set to reconstruct the residual block.

[0094] In one example, for TIMD-merge, when the transform pairs are inherited from a merge candidate, the transform pair may be modified to use a reduced set if the current block’s height and / or width is higher than some threshold. In one example, the transform pair may be modified to DCT2 if the size is higher than some threshold. For instance, video decoder 300 may determine that a current block uses TIMD-merge mode and that the size of the current block exceeds the threshold. Video decoder 300 may inherit a transform pair, such as DST7, from the merge candidate. In response to the size exceeding the threshold, video decoder 300 modifies the inherited transform pair to a transform pair from the reduced set, such as DCT2, and applies the inverse DCT2 transform. Video encoder 200 performs a corresponding operation, modifying an inherited transform pair to DCT2 when encoding a large block using TIMD-merge mode.

[0095] In one example, for implicit MTS, if the block size width and / or height is larger than some threshold, similarly a reduced set may be used (for example, only DCT2 or a1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 25 combination of DCT2 and DST7). For instance, video encoder 200 may determine that a current block uses implicit MTS and that the size of the current block exceeds the threshold. In response, video encoder 200 applies a forward transform from the reduced set, such as DCT2, even if a default implicit MTS rule would otherwise indicate a different transform. Similarly, video decoder 300 determines that the current block uses implicit MTS and that the size exceeds the threshold, and in response, video decoder 300 is constrained to select an inverse transform from the same reduced set, such as an inverse DCT2, to reconstruct the residual block.

[0096] In one example, lower number of MTS candidates (with reduced number of kernels) may be defined when the block width and / or height is larger than some threshold. For example, when encoding a block larger than the threshold, video encoder 200 may evaluate only two MTS candidates selected from a reduced set of kernels, instead of a full set of six MTS candidates. Video encoder 200 then signals an index indicating the selection from those two candidates. Correspondingly, video decoder 300 determines the block size exceeds the threshold and parses the index, using the index to select the corresponding inverse transform from the same reduced list of two MTS candidates.

[0097] In one example, the degree of block size restriction on MTS may also be dependent on the sequence resolution. For example, for lower resolution sequences, MTS may be constrained more. For instance, video encoder 200 may determine that a video sequence has a low resolution and, in response, set the MTS threshold to a smaller value, such as 16, constraining non-DCT2 transforms to blocks of size 16x16 or smaller. Video decoder 300 also determines the low resolution for the sequence and applies the same smaller threshold of 16 when decoding, selecting inverse transforms from the reduced set for blocks larger than 16x16.

[0098] In one example, particular types of kernels may be constrained to certain block sizes, for example, IDTR may be restricted up to block size N (e.g., N = 16). For instance, video encoder 200, when performing transform selection for a block, may only evaluate the IDTR kernel as a candidate if a size of the block is 16x16 or smaller. For blocks larger than 16x16, video encoder 200 excludes IDTR from the transform selection process. Correspondingly, video decoder 300 determines that the IDTR kernel is not an available option for the inverse transform when decoding a block larger than 16x16, and only applies an inverse IDTR kernel if the block size is 16x16 or smaller.

[0099] The constraints may also be applied for intra and inter coded blocks, if applicable. For example, video encoder 200, after determining a block's size exceeds the threshold,1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 26 selects a forward transform from the reduced set for the block's residual data, applying this constraint whether the block is intra-predicted or inter-predicted. Similarly, video decoder 300 determines the block's size exceeds the threshold and applies the corresponding inverse transform from the reduced set, regardless of whether the block is an intra-coded block or an inter-coded block.

[0100] As a sub-block transform (SBT) also uses non-DCT2 kernels, in some examples, the constraint on the usage of non-DCT2 kernels may be also applied to SBT. When constrained, SBT may only choose DCT2 kernels. The constraint may be applied when either height or width is higher than threshold, or in some examples, the constraint may be applied independently for each dimension (height, width), e.g., the dimension larger than threshold uses DCT2, while dimension smaller or equal can still use non-DCT2. For example, when applying an independent dimension constraint to a rectangular SBT block, video encoder 200 may determine that a height of the SBT block exceeds the threshold while a width of the SBT block does not. In response, video encoder 200 applies a DCT2 forward transform for the vertical dimension (height) and remains free to select a non- DCT2 forward transform for the horizontal dimension (width). Correspondingly, video decoder 300 determines the same dimensional constraints for the SBT block and applies an inverse DCT2 transform for the vertical dimension and the corresponding inverse non- DCT2 transform for the horizontal dimension.

[0101] FIG. 2 is a block diagram illustrating an example video encoder 200 that may perform the techniques of this disclosure. FIG. 2 is provided for purposes of explanation and should not be considered limiting of the techniques as broadly exemplified and described in this disclosure. For purposes of explanation, this disclosure describes video encoder 200 according to the techniques of VVC and HEVC. However, the techniques of this disclosure may be performed by video encoding devices that are configured to other video coding standards and video coding formats, such as AVI and successors to the AVI video coding format.

[0102] In the example of FIG. 2, video encoder 200 includes video data memory 230, mode selection unit 202, residual generation unit 204, transform processing unit 206, quantization unit 208, inverse quantization unit 210, inverse transform processing unit 212, reconstruction unit 214, filter unit 216, decoded picture buffer (DPB) 218, and entropy encoding unit 220. Any or all of video data memory 230, mode selection unit 202, residual generation unit 204, transform processing unit 206, quantization unit 208, inverse quantization unit 210, inverse transform processing unit 212, reconstruction unit1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 27214, filter unit 216, DPB 218, and entropy encoding unit 220 may be implemented in one or more processors or in processing circuitry. For instance, the units of video encoder 200 may be implemented as one or more circuits or logic elements as part of hardware circuitry, or as part of a processor, ASIC, or FPGA. Moreover, video encoder 200 may include additional or alternative processors or processing circuitry to perform these and other functions.

[0103] Video data memory 230 is an example of a memory system that may store video data to be encoded by the components of video encoder 200. Video encoder 200 may receive the video data stored in video data memory 230 from, for example, video source 104 (FIG. 1). DPB 218 is an example of a memory system that may act as a reference picture memory that stores reference video data for use in prediction of subsequent video data by video encoder 200. Video data memory 230 and DPB 218 may each be formed by any of a variety of one or more memory devices or memory units, such as dynamic random access memory (DRAM), including synchronous DRAM (SDRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM), or other types of memory devices. Video data memory 230 and DPB 218 may be provided by the same memory device or separate memory devices. In various examples, video data memory 230 may be on-chip with other components of video encoder 200, as illustrated, or off-chip relative to those components.

[0104] In this disclosure, reference to video data memory 230 should not be interpreted as being limited to memory internal to video encoder 200, unless specifically described as such, or memory external to video encoder 200, unless specifically described as such. Rather, reference to video data memory 230 should be understood as reference memory that stores video data that video encoder 200 receives for encoding (e.g., video data for a current block that is to be encoded). Memory 106 of FIG. 1 may also provide temporary storage of outputs from the various units of video encoder 200.

[0105] The various units of FIG. 2 are illustrated to assist with understanding the operations performed by video encoder 200. The units may be implemented as fixed- function circuits, programmable circuits, or a combination thereof. Fixed-function circuits refer to circuits that provide particular functionality, and are preset on the operations that can be performed. Programmable circuits refer to circuits that can be programmed to perform various tasks, and provide flexible functionality in the operations that can be performed. For instance, programmable circuits may execute software or firmware that cause the programmable circuits to operate in the manner defined by1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 28 instructions of the software or firmware. Fixed-function circuits may execute software instructions (e.g., to receive parameters or output parameters), but the types of operations that the fixed-function circuits perform are generally immutable. In some examples, one or more of the units may be distinct circuit blocks (fixed-function or programmable), and in some examples, one or more of the units may be integrated circuits.

[0106] Video encoder 200 may include arithmetic logic units (ALUs), elementary function units (EFUs), digital circuits, analog circuits, and / or programmable cores, formed from programmable circuits. In examples where the operations of video encoder 200 are performed using software executed by the programmable circuits, memory 106 (FIG. 1) may store the instructions (e.g., object code) of the software that video encoder 200 receives and executes, or another memory within video encoder 200 (not shown) may store such instructions.

[0107] Video data memory 230 is configured to store received video data. Video encoder 200 may retrieve a picture of the video data from video data memory 230 and provide the video data to residual generation unit 204 and mode selection unit 202. Video data in video data memory 230 may be raw video data that is to be encoded.

[0108] Mode selection unit 202 includes a motion estimation unit 222, a motion compensation unit 224, and an intra-prediction unit 226. Mode selection unit 202 may include additional functional units to perform video prediction in accordance with other prediction modes. As examples, mode selection unit 202 may include a palette unit, an intra-block copy unit (which may be part of motion estimation unit 222 and / or motion compensation unit 224), an affine unit, a linear model (LM) unit, or the like.

[0109] Mode selection unit 202 generally coordinates multiple encoding passes to test combinations of encoding parameters and resulting rate-distortion values for such combinations. The encoding parameters may include partitioning of CTUs into CUs, prediction modes for the CUs, transform types for residual data of the CUs, quantization parameters for residual data of the CUs, and so on. Mode selection unit 202 may ultimately select the combination of encoding parameters having rate-distortion values that are better than the other tested combinations.

[0110] Video encoder 200 may partition a picture retrieved from video data memory 230 into a series of CTUs, and encapsulate one or more CTUs within a slice. Mode selection unit 202 may partition a CTU of the picture in accordance with a tree structure, such as the MTT structure, QTBT structure, superblock structure, or the quad-tree structure described above. As described above, video encoder 200 may form one or more CUs1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 29 from partitioning a CTU according to the tree structure. Such a CU may also be referred to generally as a “video block” or “block.”[OHl] In general, mode selection unit 202 also controls the components thereof (e.g., motion estimation unit 222, motion compensation unit 224, and intra-prediction unit 226) to generate a prediction block for a current block (e.g., a current CU, or in HEVC, the overlapping portion of a PU and a TU). For inter-prediction of a current block, motion estimation unit 222 may perform a motion search to identify one or more closely matching reference blocks in one or more reference pictures (e.g., one or more previously coded pictures stored in DPB 218). In particular, motion estimation unit 222 may calculate a value representative of how similar a potential reference block is to the current block, e.g., according to sum of absolute difference (SAD), sum of squared differences (SSD), mean absolute difference (MAD), mean squared differences (MSD), or the like. Motion estimation unit 222 may generally perform these calculations using sample-by-sample differences between the current block and the reference block being considered. Motion estimation unit 222 may identify a reference block having a lowest value resulting from these calculations, indicating a reference block that most closely matches the current block.

[0112] Motion estimation unit 222 may form one or more motion vectors (MVs) that defines the positions of the reference blocks in the reference pictures relative to the position of the current block in a current picture. Motion estimation unit 222 may then provide the motion vectors to motion compensation unit 224. For example, for unidirectional inter-prediction, motion estimation unit 222 may provide a single motion vector, whereas for bi-directional inter-prediction, motion estimation unit 222 may provide two motion vectors. Motion compensation unit 224 may then generate a prediction block using the motion vectors. For example, motion compensation unit 224 may retrieve data of the reference block using the motion vector. As another example, if the motion vector has fractional sample precision, motion compensation unit 224 may interpolate values for the prediction block according to one or more interpolation filters. Moreover, for bi-directional inter-prediction, motion compensation unit 224 may retrieve data for two reference blocks identified by respective motion vectors and combine the retrieved data, e.g., through sample-by-sample averaging or weighted averaging.

[0113] When operating according to the AVI video coding format, motion estimation unit 222 and motion compensation unit 224 may be configured to encode coding blocks of video data (e.g., both luma and chroma coding blocks) using translational motion1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 30 compensation, affine motion compensation, overlapped block motion compensation (OBMC), and / or compound inter-intra prediction.

[0114] As another example, for intra-prediction, or intra-prediction coding, intraprediction unit 226 may generate the prediction block from samples neighboring the current block. For example, for directional modes, intra-prediction unit 226 may generally mathematically combine values of neighboring samples and populate these calculated values in the defined direction across the current block to produce the prediction block. As another example, for DC mode, intra-prediction unit 226 may calculate an average of the neighboring samples to the current block and generate the prediction block to include this resulting average for each sample of the prediction block.

[0115] When operating according to the AVI video coding format, intra-prediction unit 226 may be configured to encode coding blocks of video data (e.g., both luma and chroma coding blocks) using directional intra prediction, non-directional intra prediction, recursive filter intra prediction, chroma-from-luma (CFL) prediction, intra block copy (IBC), and / or color palette mode. Mode selection unit 202 may include additional functional units to perform video prediction in accordance with other prediction modes.

[0116] Mode selection unit 202 provides the prediction block to residual generation unit 204. Residual generation unit 204 receives a raw, unencoded version of the current block from video data memory 230 and the prediction block from mode selection unit 202. Residual generation unit 204 calculates sample-by-sample differences between the current block and the prediction block. The resulting sample-by-sample differences define a residual block for the current block. In some examples, residual generation unit 204 may also determine differences between sample values in the residual block to generate a residual block using residual differential pulse code modulation (RDPCM). In some examples, residual generation unit 204 may be formed using one or more subtractor circuits that perform binary subtraction.

[0117] In examples where mode selection unit 202 partitions CUs into PUs, each PU may be associated with a luma prediction unit and corresponding chroma prediction units. Video encoder 200 and video decoder 300 may support PUs having various sizes. As indicated above, the size of a CU may refer to the size of the luma coding block of the CU and the size of a PU may refer to the size of a luma prediction unit of the PU. Assuming that the size of a particular CU is 2Nx2N, video encoder 200 may support PU sizes of 2Nx2N or NxN for intra prediction, and symmetric PU sizes of 2Nx2N, 2NxN, Nx2N, NxN, or similar for inter prediction. Video encoder 200 and video decoder 3001616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 31 may also support asymmetric partitioning for PU sizes of 2NxnU, 2NxnD, nLx2N, and nRx2N for inter prediction.

[0118] In examples where mode selection unit 202 does not further partition a CU into PUs, each CU may be associated with a luma coding block and corresponding chroma coding blocks. As above, the size of a CU may refer to the size of the luma coding block of the CU. The video encoder 200 and video decoder 300 may support CU sizes of 2Nx2N, 2NxN, or Nx2N.

[0119] For other video coding techniques such as an intra-block copy mode coding, an affine-mode coding, and linear model (LM) mode coding, as some examples, mode selection unit 202, via respective units associated with the coding techniques, generates a prediction block for the current block being encoded. In some examples, such as palette mode coding, mode selection unit 202 may not generate a prediction block, and instead generate syntax elements that indicate the manner in which to reconstruct the block based on a selected palette. In such modes, mode selection unit 202 may provide these syntax elements to entropy encoding unit 220 to be encoded.

[0120] As described above, residual generation unit 204 receives the video data for the current block and the corresponding prediction block. Residual generation unit 204 then generates a residual block for the current block. To generate the residual block, residual generation unit 204 calculates sample-by-sample differences between the prediction block and the current block.

[0121] Transform processing unit 206 applies one or more transforms to the residual block to generate a block of transform coefficients (referred to herein as a “transform coefficient block”). Transform processing unit 206 may apply various transforms to a residual block to form the transform coefficient block. For example, transform processing unit 206 may apply a DCT, a directional transform, a KLT, or a conceptually similar transform to a residual block. In some examples, transform processing unit 206 may perform multiple transforms to a residual block, e.g., a primary transform and a secondary transform, such as a rotational transform. In some examples, transform processing unit 206 does not apply transforms to a residual block.

[0122] When operating according to AVI, transform processing unit 206 may apply one or more transforms to the residual block to generate a block of transform coefficients (referred to herein as a “transform coefficient block”). Transform processing unit 206 may apply various transforms to a residual block to form the transform coefficient block. For example, transform processing unit 206 may apply a horizontal / vertical transform1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 32 combination that may include a DCT, an asymmetric discrete sine transform (ADST), a flipped ADST (e.g., an ADST in reverse order), and an IDTR. When using an identity transform, the transform is skipped in one of the vertical or horizontal directions. In some examples, transform processing may be skipped.

[0123] In accordance with the techniques of this disclosure, transform processing unit 206 may be configured to determine if a transform for a block is to be explicitly signaled in the bitstream or is to be derived, and select a transform for the block accordingly.

[0124] Quantization unit 208 may quantize the transform coefficients in a transform coefficient block, to produce a quantized transform coefficient block. Quantization unit 208 may quantize transform coefficients of a transform coefficient block according to a quantization parameter (QP) value associated with the current block. Video encoder 200 (e.g., via mode selection unit 202) may adjust the degree of quantization applied to the transform coefficient blocks associated with the current block by adjusting the QP value associated with the CU. Quantization may introduce loss of information, and thus, quantized transform coefficients may have lower precision than the original transform coefficients produced by transform processing unit 206.

[0125] Inverse quantization unit 210 and inverse transform processing unit 212 may apply inverse quantization and inverse transforms to a quantized transform coefficient block, respectively, to reconstruct a residual block from the transform coefficient block. Reconstruction unit 214 may produce a reconstructed block corresponding to the current block (albeit potentially with some degree of distortion) based on the reconstructed residual block and a prediction block generated by mode selection unit 202. For example, reconstruction unit 214 may add samples of the reconstructed residual block to corresponding samples from the prediction block generated by mode selection unit 202 to produce the reconstructed block.

[0126] Filter unit 216 may perform one or more filter operations on reconstructed blocks. For example, filter unit 216 may perform deblocking operations to reduce blockiness artifacts along edges of CUs. Operations of filter unit 216 may be skipped, in some examples.

[0127] When operating according to AVI, filter unit 216 may perform one or more filter operations on reconstructed blocks. For example, filter unit 216 may perform deblocking operations to reduce blockiness artifacts along edges of CUs. In other examples, filter unit 216 may apply a constrained directional enhancement filter (CDEF), which may be applied after deblocking, and may include the application of non-separable, non-linear,1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 33 low-pass directional filters based on estimated edge directions. Filter unit 216 may also include a loop restoration filter, which is applied after CDEF, and may include a separable symmetric normalized Wiener filter or a dual self-guided filter.

[0128] Video encoder 200 stores reconstructed blocks in DPB 218. For instance, in examples where operations of filter unit 216 are not performed, reconstruction unit 214 may store reconstructed blocks to DPB 218. In examples where operations of filter unit 216 are performed, filter unit 216 may store the filtered reconstructed blocks to DPB 218. Motion estimation unit 222 and motion compensation unit 224 may retrieve a reference picture from DPB 218, formed from the reconstructed (and potentially filtered) blocks, to inter-predict blocks of subsequently encoded pictures. In addition, intra-prediction unit 226 may use reconstructed blocks in DPB 218 of a current picture to intra-predict other blocks in the current picture.

[0129] In general, entropy encoding unit 220 may entropy encode syntax elements received from other functional components of video encoder 200. For example, entropy encoding unit 220 may entropy encode quantized transform coefficient blocks from quantization unit 208. As another example, entropy encoding unit 220 may entropy encode prediction syntax elements (e.g., motion information for inter-prediction or intramode information for intra-prediction) from mode selection unit 202. Entropy encoding unit 220 may perform one or more entropy encoding operations on the syntax elements, which are another example of video data, to generate entropy-encoded data. For example, entropy encoding unit 220 may perform a context-adaptive variable length coding (CAVLC) operation, a CABAC operation, a variable-to-variable (V2V) length coding operation, a syntax-based context-adaptive binary arithmetic coding (SB AC) operation, a Probability Interval Partitioning Entropy (PIPE) coding operation, an Exponential- Golomb encoding operation, or another type of entropy encoding operation on the data. In some examples, entropy encoding unit 220 may operate in bypass mode where syntax elements are not entropy encoded.

[0130] Video encoder 200 may output a bitstream that includes the entropy encoded syntax elements needed to reconstruct blocks of a slice or picture. In particular, entropy encoding unit 220 may output the bitstream.

[0131] In accordance with AVI, entropy encoding unit 220 may be configured as a symbol -to- symbol adaptive multi-symbol arithmetic coder. A syntax element in AVI includes an alphabet of N elements, and a context (e.g., probability model) includes a set of N probabilities. Entropy encoding unit 220 may store the probabilities as n-bit (e.g.,1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 3415-bit) cumulative distribution functions (CDFs). Entropy encoding unit 220 may perform recursive scaling, with an update factor based on the alphabet size, to update the contexts.

[0132] The operations described above are described with respect to a block. Such description should be understood as being operations for a luma coding block and / or chroma coding blocks. As described above, in some examples, the luma coding block and chroma coding blocks are luma and chroma components of a CU. In some examples, the luma coding block and the chroma coding blocks are luma and chroma components of a PU.

[0133] In some examples, operations performed with respect to a luma coding block need not be repeated for the chroma coding blocks. As one example, operations to identify a motion vector (MV) and reference picture for a luma coding block need not be repeated for identifying a MV and reference picture for the chroma blocks. Rather, the MV for the luma coding block may be scaled to determine the MV for the chroma blocks, and the reference picture may be the same. As another example, the intra-prediction process may be the same for the luma coding block and the chroma coding blocks.

[0134] Video encoder 200 represents an example of a device configured to encode video data including a memory configured to store video data, and one or more processing units implemented in circuitry and configured to determine a size for a block of the encoded video data and based on the size, determine whether a transform for the block is explicitly signaled in the bitstream or is derived. Video encoder 200 also represents an example of a device configured to encode video data including a memory configured to store video data, and one or more processing units implemented in circuitry and configured to determine a size for a block of the encoded video data and based on the size, determine a set of transforms for the block.

[0135] Video encoder 200 represents an example of a device configured to encode video data including a memory configured to determine a size of a block of the encoded video data; determine that the size of the block exceeds a threshold; in response to the size for the block of video data being greater than the threshold, select a reduced set of transform pairs from the set of transform pairs, wherein the reduced set of transform pairs includes fewer than all transform pairs of the set of transform pairs; select a transform pair from the reduced set of transform pairs; inverse transform transform coefficients based on the selected transform pair to determine a residual block for the block of video data; determine a decoded representation of the block of the encoded video data using the1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 35 residual block; and output the decoded representation of the block of the encoded video data.

[0136] FIG. 3 is a block diagram illustrating an example video decoder 300 that may perform the techniques of this disclosure. FIG. 3 is provided for purposes of explanation and is not limiting on the techniques as broadly exemplified and described in this disclosure. For purposes of explanation, this disclosure describes video decoder 300 according to the techniques of VVC and HEVC. However, the techniques of this disclosure may be performed by video coding devices that are configured to other video coding standards.

[0137] In the example of FIG. 3, video decoder 300 includes coded picture buffer (CPB) memory 320, entropy decoding unit 302, prediction processing unit 304, inverse quantization unit 306, inverse transform processing unit 308, reconstruction unit 310, filter unit 312, and DPB 314. Any or all of CPB memory 320, entropy decoding unit 302, prediction processing unit 304, inverse quantization unit 306, inverse transform processing unit 308, reconstruction unit 310, filter unit 312, and DPB 314 may be implemented in one or more processors or in processing circuitry. For instance, the units of video decoder 300 may be implemented as one or more circuits or logic elements as part of hardware circuitry, or as part of a processor, ASIC, or FPGA. Moreover, video decoder 300 may include additional or alternative processors or processing circuitry to perform these and other functions.

[0138] Prediction processing unit 304 includes motion compensation unit 316 and intraprediction unit 318. Prediction processing unit 304 may include additional units to perform prediction in accordance with other prediction modes. As examples, prediction processing unit 304 may include a palette unit, an intra-block copy unit (which may form part of motion compensation unit 316), an affine unit, a linear model (LM) unit, or the like. In other examples, video decoder 300 may include more, fewer, or different functional components.

[0139] When operating according to AVI, motion compensation unit 316 may be configured to decode coding blocks of video data (e.g., both luma and chroma coding blocks) using translational motion compensation, affine motion compensation, OBMC, and / or compound inter-intra prediction, as described above. Intra-prediction unit 318 may be configured to decode coding blocks of video data (e.g., both luma and chroma coding blocks) using directional intra prediction, non-directional intra prediction, recursive filter intra prediction, CFL, IBC, and / or color palette mode, as described above.1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 36

[0140] CPB memory 320 is an example of a memory system that may store video data, such as an encoded video bitstream, to be decoded by the components of video decoder 300. The video data stored in CPB memory 320 may be obtained, for example, from computer-readable medium 110 (FIG. 1). CPB memory 320 may include a CPB that stores encoded video data (e.g., syntax elements) from an encoded video bitstream. Also, CPB memory 320 may store video data other than syntax elements of a coded picture, such as temporary data representing outputs from the various units of video decoder 300. DPB 314 is an example of a memory system that generally stores decoded pictures, which video decoder 300 may output and / or use as reference video data when decoding subsequent data or pictures of the encoded video bitstream. CPB memory 320 and DPB 314 may each be formed by any of a variety of memory devices or memory units, such as DRAM, including SDRAM, MRAM, RRAM, or other types of memory devices. CPB memory 320 and DPB 314 may be provided by the same memory device or separate memory devices. In various examples, CPB memory 320 may be on-chip with other components of video decoder 300, or off-chip relative to those components.

[0141] Additionally or alternatively, in some examples, video decoder 300 may retrieve coded video data from memory 120 (FIG. 1). That is, memory 120 may store data as discussed above with CPB memory 320. Likewise, memory 120 may store instructions to be executed by video decoder 300, when some or all of the functionality of video decoder 300 is implemented in software to be executed by processing circuitry of video decoder 300.

[0142] The various units shown in FIG. 3 are illustrated to assist with understanding the operations performed by video decoder 300. The units may be implemented as fixed- function circuits, programmable circuits, or a combination thereof. Similar to FIG. 2, fixed-function circuits refer to circuits that provide particular functionality, and are preset on the operations that can be performed. Programmable circuits refer to circuits that can be programmed to perform various tasks, and provide flexible functionality in the operations that can be performed. For instance, programmable circuits may execute software or firmware that cause the programmable circuits to operate in the manner defined by instructions of the software or firmware. Fixed-function circuits may execute software instructions (e.g., to receive parameters or output parameters), but the types of operations that the fixed-function circuits perform are generally immutable. In some examples, one or more of the units may be distinct circuit blocks (fixed-function or1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 37 programmable), and in some examples, one or more of the units may be integrated circuits.

[0143] Video decoder 300 may include ALUs, EFUs, digital circuits, analog circuits, and / or programmable cores formed from programmable circuits. In examples where the operations of video decoder 300 are performed by software executing on the programmable circuits, on-chip or off-chip memory may store instructions (e.g., object code) of the software that video decoder 300 receives and executes.

[0144] Entropy decoding unit 302 may receive encoded video data from the CPB and entropy decode the video data to reproduce syntax elements. Prediction processing unit 304, inverse quantization unit 306, inverse transform processing unit 308, reconstruction unit 310, and filter unit 312 may generate decoded video data based on the syntax elements extracted from the bitstream.

[0145] In general, video decoder 300 reconstructs a picture on a block-by-block basis. Video decoder 300 may perform a reconstruction operation on each block individually (where the block currently being reconstructed, i.e., decoded, may be referred to as a “current block”).

[0146] Entropy decoding unit 302 may entropy decode syntax elements defining quantized transform coefficients of a quantized transform coefficient block, as well as transform information, such as a quantization parameter (QP) and / or transform mode indication(s). Inverse quantization unit 306 may use the QP associated with the quantized transform coefficient block to determine a degree of quantization and, likewise, a degree of inverse quantization for inverse quantization unit 306 to apply. Inverse quantization unit 306 may, for example, perform a bitwise left-shift operation to inverse quantize the quantized transform coefficients. Inverse quantization unit 306 may thereby form a transform coefficient block including transform coefficients.

[0147] After inverse quantization unit 306 forms the transform coefficient block, inverse transform processing unit 308 may apply one or more inverse transforms to the transform coefficient block to generate a residual block associated with the current block. For example, inverse transform processing unit 308 may apply an inverse DCT, an inverse integer transform, an inverse KLT, an inverse rotational transform, an inverse directional transform, or another inverse transform to the transform coefficient block.

[0148] In accordance with the techniques of this disclosure, transform processing unit 308 may be configured to determine if a transform for a block is to be explicitly signaled in the bitstream or is to be derived, and select the transform for the block accordingly.1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 38

[0149] Furthermore, prediction processing unit 304 generates a prediction block according to prediction information syntax elements that were entropy decoded by entropy decoding unit 302. For example, if the prediction information syntax elements indicate that the current block is inter-predicted, motion compensation unit 316 may generate the prediction block. In this case, the prediction information syntax elements may indicate a reference picture in DPB 314 from which to retrieve a reference block, as well as a motion vector identifying a location of the reference block in the reference picture relative to the location of the current block in the current picture. Motion compensation unit 316 may generally perform the inter-prediction process in a manner that is substantially similar to that described with respect to motion compensation unit 224 (FIG. 2).

[0150] As another example, if the prediction information syntax elements indicate that the current block is intra-predicted, intra-prediction unit 318 may generate the prediction block according to an intra-prediction mode indicated by the prediction information syntax elements. Again, intra-prediction unit 318 may generally perform the intraprediction process in a manner that is substantially similar to that described with respect to intra-prediction unit 226 (FIG. 2). Intra-prediction unit 318 may retrieve data of neighboring samples to the current block from DPB 314.

[0151] Reconstruction unit 310 may reconstruct the current block using the prediction block and the residual block. For example, reconstruction unit 310 may add samples of the residual block to corresponding samples of the prediction block to reconstruct the current block.

[0152] Filter unit 312 may perform one or more filter operations on reconstructed blocks. For example, filter unit 312 may perform deblocking operations to reduce blockiness artifacts along edges of the reconstructed blocks. Operations of filter unit 312 are not necessarily performed in all examples.

[0153] Video decoder 300 may store the reconstructed blocks in DPB 314. For instance, in examples where operations of filter unit 312 are not performed, reconstruction unit 310 may store reconstructed blocks to DPB 314. In examples where operations of filter unit 312 are performed, filter unit 312 may store the filtered reconstructed blocks to DPB 314. As discussed above, DPB 314 may provide reference information, such as samples of a current picture for intra-prediction and previously decoded pictures for subsequent motion compensation, to prediction processing unit 304. Moreover, video decoder 3001616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 39 may output decoded pictures (e.g., decoded video) from DPB 314 for subsequent presentation on a display device, such as display device 118 of FIG. 1.

[0154] Video decoder 300 represents an example of a device configured to decode video data including a memory configured to store video data, and one or more processing units implemented in circuitry and configured to determine a size for a block of the encoded video data and based on the size, determine whether a transform for the block is explicitly signaled in the bitstream or is derived. Video decoder 300 also represents an example of a device configured to encode video data including a memory configured to store video data, and one or more processing units implemented in circuitry and configured to determine a size for a block of the encoded video data and based on the size, determine a set of transforms for the block.

[0155] Video decoder 300 represents an example of a device configured to decode video data including a memory configured to store video data, and one or more processing units implemented in circuitry and configured to determine a size of a block of the encoded video data; determine that the size of the block exceeds a threshold; in response to the size for the block of video data being greater than the threshold, select a reduced set of transform pairs from the set of transform pairs, wherein the reduced set of transform pairs includes fewer than all transform pairs of the set of transform pairs; select a transform pair from the reduced set of transform pairs; inverse transform transform coefficients based on the selected transform pair to determine a residual block for the block of video data; determine a decoded representation of the block of the encoded video data using the residual block; and output the decoded representation of the block of the encoded video data.

[0156] FIG. 4 is a flowchart illustrating an example process for encoding a current block in accordance with the techniques of this disclosure. The current block may be or include a current CU. Although described with respect to video encoder 200 (FIGS. 1 and 2), it should be understood that other devices may be configured to perform a process similar to that of FIG. 4.

[0157] In this example, video encoder 200 initially predicts the current block (400). For example, video encoder 200 may form a prediction block for the current block. Video encoder 200 may then calculate a residual block for the current block (402). To calculate the residual block, video encoder 200 may calculate a difference between the original, unencoded block and the prediction block for the current block. Video encoder 200 may then transform the residual block and quantize transform coefficients of the residual block1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 40(404). Next, video encoder 200 may scan the quantized transform coefficients of the residual block (406). During the scan, or following the scan, video encoder 200 may entropy encode the transform coefficients (408). For example, video encoder 200 may encode the transform coefficients using CAVLC or CAB AC. Video encoder 200 may then output the entropy encoded data of the block (410).

[0158] FIG. 5 is a flowchart illustrating an example process for decoding a current block of video data in accordance with the techniques of this disclosure. The current block may be or include a current CU. Although described with respect to video decoder 300 (FIGS. 1 and 3), it should be understood that other devices may be configured to perform a process similar to that of FIG. 5.

[0159] Video decoder 300 may receive entropy encoded data for the current block, such as entropy encoded prediction information and entropy encoded data for transform coefficients of a residual block corresponding to the current block (500). Video decoder 300 may entropy decode the entropy encoded data to determine prediction information for the current block and to reproduce transform coefficients of the residual block (502). Video decoder 300 may predict the current block (504), e.g., using an intra- or interprediction mode as indicated by the prediction information for the current block, to calculate a prediction block for the current block. Video decoder 300 may then inverse scan the reproduced transform coefficients (506), to create a block of quantized transform coefficients. Video decoder 300 may then inverse quantize the transform coefficients and apply an inverse transform to the transform coefficients to produce a residual block (508). Video decoder 300 may ultimately decode the current block by combining the prediction block and the residual block (510).

[0160] FIG. 6 is a flowchart illustrating an example process for decoding a current block of video data in accordance with the techniques of this disclosure. The current block may be or include a current CU. Although described with respect to video decoder 300 (FIGS. 1 and 3), it should be understood that other devices may be configured to perform a process similar to that of FIG. 6.

[0161] In the example of FIG. 6, video decoder 300 determines a size for a block of the encoded video data (600). Video decoder 300 then determines if this size exceeds a threshold (602). To determine if the size of the block exceeds the threshold, video decoder 300 may be configured to determine that a width of the block exceeds a width threshold or that a height of the block exceeds a height threshold. In some examples, video decoder 300 may receive a syntax element indicating the threshold, for example, in a high-level1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 41 syntax structure such as an SPS. The threshold may be one of a group of pre-defined values, such as 32, 64, 128, or 256.

[0162] In response to the size of the block being greater than the threshold (604, YES), video decoder 300 selects a reduced set of transform pairs from a full set of transform pairs (606). The reduced set of transform pairs includes fewer than all transform pairs of the full set of transform pairs. In some examples, the reduced set of transform pairs includes only one transform pair, such as a transform pair that specifies a DCT2 for both a horizontal and a vertical transform. Video decoder 300 then selects a transform pair from the reduced set of transform pairs (608). In some examples, video decoder 300 may be configured to perform this selection implicitly, for example, based on an intraprediction mode of the block, without receiving a syntax element that explicitly identifies the transform pair to be used.

[0163] In response to the size of the block not being greater than the threshold (e.g., being less than or equal to the threshold) (604, NO), video decoder 300 may operate using an explicit transform selection process. In this case, video decoder 300 receives explicit signaling that indicates which transform pair to select from the full set of available transform pairs (616).

[0164] After a transform pair is selected, either from the reduced set or from the full set, video decoder 300 inverse transforms transform coefficients based on the selected transform pair to determine a residual block for the block of video data (610). Video decoder 300 then determines a decoded representation of the block of the encoded video data using the residual block (612), for instance by summing the residual block with a predictive block. Finally, video decoder 300 outputs the decoded representation of the block of the encoded video data (614).

[0165] The following numbered clauses illustrate one or more aspects of the devices and techniques described in this disclosure.

[0166] Clause 1A: A method of decoding a bitstream of encoded video data, the method comprising: determining a size for a block of the encoded video data; based on the size, determining whether a transform for the block is explicitly signaled in the bitstream or is derived.

[0167] Clause 2 A: The method of clause 1 A, wherein determining whether the transform for the block is explicitly signaled in the bitstream or is derived comprises: in response to the size being less than a threshold, determining that the transform is signaled.1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 42

[0168] Clause 3 A: The method of clause 1 A, wherein determining whether the transform for the block is explicitly signaled in the bitstream or is derived comprises: in response to the size being greater than a threshold, determining that the transform is derived.

[0169] Clause 4 A: The method of clause 1 A, the transform being derived comprises the block having only a single available transform.

[0170] Clause 5 A: A method of decoding a bitstream of encoded video data, the method comprising: determining a size for a block of the encoded video data; based on the size, determining a set of transforms for the block.

[0171] Clause 6A: The method of clause 5A, wherein determining the set of transforms for the block comprises: in response to the size being less than a threshold, determining that the set corresponds to a first set selected from a group that includes the first set and a second set, wherein the first set includes more transforms than the second set.

[0172] Clause 7A: The method of clause 5A, wherein determining the set of transforms for the block comprises: in response to the size being greater than a threshold, determining that the set corresponds to a second set selected from a group that includes a first set and the second set, wherein the first set includes more transforms than the second set.

[0173] Clause 8 A: The method of any of clauses 1 A-7A, wherein the method of decoding is performed as part of a video encoding process.

[0174] Clause 9A: A device for coding video data, the device comprising one or more means for performing the method of any of clauses 1 A-8A.

[0175] Clause 10A: The device of clause 9A, wherein the one or more means comprise one or more processors implemented in circuitry.

[0176] Clause 11 A: The device of any of clauses 9A and 10A, further comprising a memory to store the video data.

[0177] Clause 12A: The device of any of clauses 9A-11A, further comprising a display configured to display decoded video data.

[0178] Clause 13A: The device of any of clauses 9A-12A, wherein the device comprises one or more of a camera, a computer, a mobile device, a broadcast receiver device, or a set-top box.

[0179] Clause 14A: The device of any of clauses 9A-13A, wherein the device comprises a video decoder.

[0180] Clause 15 A: The device of any of clauses 9A-13A, wherein the device comprises a video encoder.1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 43

[0181] Clause 16 A: A computer-readable storage medium having stored thereon instructions that, when executed, cause one or more processors to perform the method of any of clauses 1A-8A.

[0182] Clause IB: A method of decoding a bitstream of encoded video data, the method comprising: determining a size of a block of the encoded video data; determining that the size of the block exceeds a threshold; in response to the size of the block being greater than the threshold, selecting a reduced set of transform pairs from a set of transform pairs, wherein the reduced set of transform pairs includes fewer than all transform pairs of the set of transform pairs; selecting a transform pair from the reduced set of transform pairs; inverse transforming transform coefficients based on the selected transform pair to determine a residual block for the block of video data; determining a decoded representation of the block using the residual block; and outputting the decoded representation of the block.

[0183] Clause 2B: The method of clause IB, wherein the reduced set of transform pairs includes only one transform pair.

[0184] Clause 3B: The method of clause IB or 2B, further comprising: receiving information indicating the threshold in one of a sequence parameter set, a picture parameter set, or a slice header.

[0185] Clause 4B: The method of any of clauses 1B-3B, wherein determining that the size of the block exceeds the threshold comprises determining that a width of the block exceeds a width threshold.

[0186] Clause 5B: The method of any of clauses 1B-4B, wherein determining that the size of the block exceeds the threshold comprises determining that a height of the block exceeds a height threshold.

[0187] Clause 6B: The method of any of clauses 1B-5B, wherein selecting the transform pair from the reduced set of transform pairs comprises selecting the transform pair based on an intra prediction mode of the block.

[0188] Clause 7B: The method of any of clauses 1B-6B, wherein selecting the transform pair from the reduced set of transform pairs comprises implicitly selecting the transform pair.

[0189] Clause 8B: The method of clause 7B, wherein implicitly selecting the transform pair comprises selecting the transform pair without receiving a syntax element that identifies the transform pair.1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 44

[0190] Clause 9B: The method of any of clauses 1B-8B, wherein selecting the transform pair from the reduced set of transform pairs comprises: determining that the block is encoded with a template-based intra mode derivation (TIMD) merge mode; including a candidate transform pair from a merge candidate for the TIMD merge mode in the reduced set of transform pairs.

[0191] Clause 10B: The method of any of clauses 1B-9B, further comprising: receiving a variable-length syntax element indicating the threshold.

[0192] Clause 11B: The method of any of clauses 1B-10B, further comprising: in response to determining that the block comprises a sub-block to which a sub-block transform (SBT) is applied, determining that the reduced set of transform pairs includes only a discrete cosine transform of type 2 (DCT2) transform pair.

[0193] Clause 12B: A device for decoding a bitstream of encoded video data, the device comprising: at least one memory configured to store a set of transform pairs; and processing circuitry communicatively coupled to the at least one memory, the processing circuitry configured to: determine a size of a block of the encoded video data; determine that the size of the block exceeds a threshold; in response to the size of the block being greater than the threshold, select a reduced set of transform pairs from the set of transform pairs, wherein the reduced set of transform pairs includes fewer than all transform pairs of the set of transform pairs; select a transform pair from the reduced set of transform pairs; inverse transform transform coefficients based on the selected transform pair to determine a residual block for the block of video data; determine a decoded representation of the block using the residual block; and output the decoded representation of the block.

[0194] Clause 13B: The device of clause 12B, wherein the reduced set of transform pairs includes only one transform pair.

[0195] Clause 14B: The device of clause 12B or 13B, wherein to determine that the size of the block exceeds the threshold, the processing circuitry is further configured to determine that a width of the block exceeds a width threshold.

[0196] Clause 15B: The device of any of clauses 12B-14B, wherein to determine that the size of the block exceeds the threshold, the processing circuitry is further configured to determine that a height of the block exceeds a height threshold.

[0197] Clause 16B: The device of any of clauses 12B-15B, wherein to select the transform pair from the reduced set of transform pairs, the processing circuitry is further configured to select the transform pair based on an intra prediction mode of the block.1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 45

[0198] Clause 17B: The device of any of clauses 12B-16B, wherein to select the transform pair from the reduced set of transform pairs, the processing circuitry is further configured to implicitly select the transform pair.

[0199] Clause 18B: The device of clause 17B, wherein to implicitly select the transform pair, the processing circuitry is further configured to select the transform pair without receiving a syntax element that identifies the transform pair.

[0200] Clause 19B: The device of any of clauses 12B-18B, wherein to select the transform pair from the reduced set of transform pairs, the processing circuitry is further configured to: determine that the block is encoded with a template-based intra mode derivation (TIMD) merge mode; and include a candidate transform pair from a merge candidate for the TIMD merge mode in the reduced set of transform pairs.

[0201] Clause 20B: The device of any of clauses 12B-19B, wherein the processing circuitry is further configured to: in response to determining that the block comprises a sub-block to which a sub-block transform (SBT) is applied, determine that the reduced set of transform pairs includes only a discrete cosine transform of type 2 (DCT2) transform pair.

[0202] It is to be recognized that depending on the example, certain acts or events of any of the techniques described herein can be performed in a different sequence, may be added, merged, or left out altogether (e.g., not all described acts or events are necessary for the practice of the techniques). Moreover, in certain examples, acts or events may be performed concurrently, e.g., through multi-threaded processing, interrupt processing, or multiple processors, rather than sequentially.

[0203] In one or more examples, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium and executed by a hardware-based processing unit. Computer-readable media may include computer-readable storage media, which corresponds to a tangible medium such as data storage media, or communication media including any medium that facilitates transfer of a computer program from one place to another, e.g., according to a communication protocol. In this manner, computer-readable media generally may correspond to (1) tangible computer-readable storage media which is non-transitory or (2) a communication medium such as a signal or carrier wave. Data storage media may be any available media that can be accessed by one or more computers or one or more processors to retrieve instructions, code and / or data structures for1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 46 implementation of the techniques described in this disclosure. A computer program product may include a computer-readable medium.

[0204] By way of example, and not limitation, such computer-readable storage media may include one or more of RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage, or other magnetic storage devices, flash memory, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium. For example, if instructions are transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. It should be understood, however, that computer-readable storage media and data storage media do not include connections, carrier waves, signals, or other transitory media, but are instead directed to non-transitory, tangible storage media. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0205] Instructions may be executed by one or more processors, such as one or more DSPs, general purpose microprocessors, ASICs, FPGAs, or other equivalent integrated or discrete logic circuitry. Accordingly, the terms “processor” and “processing circuitry,” as used herein may refer to any of the foregoing structures or any other structure suitable for implementation of the techniques described herein. In addition, in some aspects, the functionality described herein may be provided within dedicated hardware and / or software modules configured for encoding and decoding, or incorporated in a combined codec. Also, the techniques could be fully implemented in one or more circuits or logic elements.

[0206] The techniques of this disclosure may be implemented in a wide variety of devices or apparatuses, including a wireless handset, an integrated circuit (IC) or a set of ICs (e.g., a chip set). Various components, modules, or units are described in this disclosure to emphasize functional aspects of devices configured to perform the disclosed techniques, but do not necessarily require realization by different hardware units. Rather, as described above, various units may be combined in a codec hardware unit or provided by a1616-599WO01PCT / US25 / 58822 09 December 2025 (09.12.2025)Qualcomm Ref. No.: 2501430WO 47 collection of interoperative hardware units, including one or more processors as described above, in conjunction with suitable software and / or firmware.

[0207] Various examples have been described. These and other examples are within the scope of the following claims.1616-599WO01

Claims

Qualcomm Ref. No.: 2501430WO 48WHAT IS CLAIMED IS:

1. A method of decoding a bitstream of encoded video data, the method comprising: determining a size of a block of the encoded video data; determining that the size of the block exceeds a threshold; in response to the size of the block being greater than the threshold, selecting a reduced set of transform pairs from a set of transform pairs, wherein the reduced set of transform pairs includes fewer than all transform pairs of the set of transform pairs; selecting a transform pair from the reduced set of transform pairs; inverse transforming transform coefficients based on the selected transform pair to determine a residual block for the block of video data; determining a decoded representation of the block using the residual block; and outputting the decoded representation of the block.

2. The method of claim 1, wherein the reduced set of transform pairs includes only one transform pair.

3. The method of claim 1, further comprising: receiving information indicating the threshold in one of a sequence parameter set, a picture parameter set, or a slice header.

4. The method of claim 1, wherein determining that the size of the block exceeds the threshold comprises determining that a width of the block exceeds a width threshold.

5. The method of claim 1, wherein determining that the size of the block exceeds the threshold comprises determining that a height of the block exceeds a height threshold.

6. The method of claim 1, wherein selecting the transform pair from the reduced set of transform pairs comprises selecting the transform pair based on an intra prediction mode of the block.

7. The method of claim 1, wherein selecting the transform pair from the reduced set of transform pairs comprises implicitly selecting the transform pair.1616-599WO01Qualcomm Ref. No.: 2501430WO 498. The method of claim 7, wherein implicitly selecting the transform pair comprises selecting the transform pair without receiving a syntax element that identifies the transform pair.

9. The method of claim 1, wherein selecting the transform pair from the reduced set of transform pairs comprises: determining that the block is encoded with a template-based intra mode derivation (TIMD) merge mode; including a candidate transform pair from a merge candidate for the TIMD merge mode in the reduced set of transform pairs.

10. The method of claim 1, further comprising: receiving a variable-length syntax element indicating the threshold.

11. The method of claim 1, further comprising: in response to determining that the block comprises a sub-block to which a subblock transform (SBT) is applied, determining that the reduced set of transform pairs includes only a discrete cosine transform of type 2 (DCT2) transform pair.

12. A device for decoding a bitstream of encoded video data, the device comprising: at least one memory configured to store a set of transform pairs; and processing circuitry communicatively coupled to the at least one memory, the processing circuitry configured to: determine a size of a block of the encoded video data; determine that the size of the block exceeds a threshold; in response to the size of the block being greater than the threshold, select a reduced set of transform pairs from the set of transform pairs, wherein the reduced set of transform pairs includes fewer than all transform pairs of the set of transform pairs; select a transform pair from the reduced set of transform pairs; inverse transform transform coefficients based on the selected transform pair to determine a residual block for the block of video data;1616-599WO01Qualcomm Ref. No.: 2501430WO 50 determine a decoded representation of the block using the residual block; and output the decoded representation of the block.

13. The device of claim 12, wherein the reduced set of transform pairs includes only one transform pair.

14. The device of claim 12, wherein to determine that the size of the block exceeds the threshold, the processing circuitry is further configured to determine that a width of the block exceeds a width threshold.

15. The device of claim 12, wherein to determine that the size of the block exceeds the threshold, the processing circuitry is further configured to determine that a height of the block exceeds a height threshold.

16. The device of claim 12, wherein to select the transform pair from the reduced set of transform pairs, the processing circuitry is further configured to select the transform pair based on an intra prediction mode of the block.

17. The device of claim 12, wherein to select the transform pair from the reduced set of transform pairs, the processing circuitry is further configured to implicitly select the transform pair.

18. The device of claim 17, wherein to implicitly select the transform pair, the processing circuitry is further configured to select the transform pair without receiving a syntax element that identifies the transform pair.

19. The device of claim 12, wherein to select the transform pair from the reduced set of transform pairs, the processing circuitry is further configured to: determine that the block is encoded with a template-based intra mode derivation (TIMD) merge mode; and include a candidate transform pair from a merge candidate for the TIMD merge mode in the reduced set of transform pairs.1616-599WO01Qualcomm Ref. No.: 2501430WO 5120. The device of claim 12, wherein the processing circuitry is further configured to: in response to determining that the block comprises a sub-block to which a subblock transform (SBT) is applied, determine that the reduced set of transform pairs includes only a discrete cosine transform of type 2 (DCT2) transform pair.1616-599WO01

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