Photovoltaic devices with charge transport buffers and methods for forming the same

Abstract

According to the embodiments provided herein, a second semiconductor layer can be positioned over the polycrystalline absorber layer of a photovoltaic device. A charge transport buffer can be positioned between the surface of the polycrystalline absorber layer and the second semiconductor layer. A majority of the surface of the polycrystalline absorber layer can be offset from the second semiconductor layer by less than or equal to 5 nm.

Description

PHOTOVOLTAIC DEVICES WITH CHARGE TRANSPORT BUFFERS AND METHODS FOR FORMING THE SAMEBACKGROUND

[0001] The present specification generally relates to efficient photovoltaic devices and methods for forming the same and, more specifically, to photovoltaic devices with charge transport buffers and methods for forming the same.

[0002] A photovoltaic device generates electrical power by converting light into electricity using semiconductor materials that exhibit the photovoltaic effect. Unfortunately, the manufacturing processes necessary to efficiently produce the photovoltaic device can exacerbate undesirable properties of the photovoltaic device. For example, semiconductor layers are sometimes subjected to chloride heat treatment (CHT), which is an annealing process in a chlorine and oxygen containing atmosphere. The CHT can improve the crystalline quality of the semiconductor layer. For example, the grain (crystallite) size can be increased. Also, defects in the lattice structure can be cured including, for example, defects located at grain boundary areas. Defects in the lattice structure can be sources of carrier recombination, which reduces photovoltaic efficiency. While CHT can improve grain boundary passivation and device efficiency, further improvements in passivation and efficiency are desired.

[0003] Accordingly, a need exists for alternative photovoltaic devices having grain boundary passivation, and alternative methods for forming the same.SUMMARY

[0004] The embodiments provided herein relate to photovoltaic devices having charge transport buffers, as well as methods for forming the same. These and additional features provided by the embodiments described herein will be more fully understood in view of the following detailed description, in conjunction with the drawings.BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The embodiments set forth in the drawings are illustrative and exemplary in nature and not intended to limit the subject matter defined by the claims. The following detailed description of the illustrative embodiments can be understood when read in conjunction with the following drawings, where like structure is indicated with like reference numerals.

[0006] FIG. 1 schematically depicts a photovoltaic device according to one or more embodiments shown and described herein.

[0007] FIG. 2 schematically depicts a substrate according to one or more embodiments shown and described herein.

[0008] FIG. 3 schematically depicts an enlarged view of a charge transport buffer of the photovoltaic device of FIG. 1.

[0009] FIGS. 4 and 5 schematically depict partially formed photovoltaic devices according to one or more embodiments shown and described herein.

[0010] FIG. 6 schematically depicts a method for forming photovoltaic devices with charge transport buffers according to one or more embodiments shown and described herein.

[0011] FIG. 7 shows a scanning electron micrograph (SEM) image of a portion of an absorber back surface with a grain boundary sealing buffer layer comprising the charge transport buffer.

[0012] FIGS. 8A-8C: 8(A) Cross-sectional SEM showing the charge transport buffer which appears darker, 8(B) Plan view scanning electron micrograph of back surface with the charge transport buffer (grain boundary sealing buffer layer) which appears darker, 8(C) Box and whisker plot illustrating the improvement in open circuit voltage through the implementation of the grain boundary sealing buffer layer.

[0013] FIGS. 9A-9F: P-doped & As-doped cells (Red = As-doped; Blue = P-doped), 9(A) Light and dark current-density vs voltage (JV) curves, 9(B) External quantum efficiency (EQE), 9(C) Simplified depiction of P-doped record cell’s device architecture, 9(D) Net acceptor vs depletion width from capacitance-voltage (CV) sweeps for three sweeps of the same device with the filled points being individual sweeps, the open points the zero bias points, and the solid lines interpolated averages, 9(E) Fill factor analysis of the different cell generations with the As- and P-doped cells from the other parts of this figure highlighted in red (left box) and blue (right box), 9(F) Certified results of P-doped cell.

[0014] FIGS. 10A-10C: 10(A) PLemission spectra for undoped, As-, P-, and Cu-doped devices at 298 K. Excitation at 632.8 nm with 2xl021photons / (m2s) fluence (equivalent to 1 Sun). Photoluminescence emission quantum yields are: PLQY = 3xl0-5(undoped), 2xl0-4(Cu- doping), IxlO-4(As-doping) and 2xl0-4(P-doping). Inset: absorptance for the same samples calculated using Generalized Planck’s law. Urbach energies are Eu= 13.2 mV (undoped), 16.4 meV (Cu-doping), 18.5 meV (P-doping) and 28.5 meV (As-doping). Bandgaps from absorptance spectra (using derivative method) are Eg= 1.38 ±0.01 eV for all devices, 10(B) Time-resolved photoluminescence decays for As- and P-doped devices. Excitation fluenceIxlO12photons / (cm2pulse), decays were measured at 1.35 eV. Inset: injection-dependent TRPL tail lifetimes, 10(C) Voc loss attribution for representative As- and P-doped devices. As-doped devices have greater bandtail losses whereas P-doped devices have greater recombinative losses.

[0015] FIG. 11: Urbach energy, Eu, and Voc, ideal vary with the amount of incorporated arsenic, with high doses having high Eu and low Voc, ideal.

[0016] FIGS. 12A-12B: (12A) PL emission spectra at low temperature for As-doped device (12B) and P-doped device. Excitation fluence was varied as indicated in the legends. Data was normalized at the maxima (1.134 - 1.172 eV) in (12A) and at 1.1 eV in (12B). Data indicates electrostatic potential fluctuations in (12A) and defect emission in (12B).

[0017] FIGS. 13A-13C: Microscopy of the Cd(Se,Te) side of the TCO-Cd(Se,Te) interface of a delaminated phosphorus-doped Cd(Se,Te) cell. (13 A) Scanning electron micrograph, (13B) Scanning spreading resistance micrograph with an example of representative line individual line scan below it, (13C) Se concentration from Auger electron spectroscopy. Se concentration from Auger electron spectroscopy. Group V activation is more difficult with increasing Se content. The SSRM data (under negative bias) has low resistance regions that correlate with higher Se content. This indicates regions with increased Se can exhibit more n-type behavior and ineffective doping.

[0018] FIGS. 14A-14B: XPS spectra of the TCO side of LN2-delaminated devices. In (14A), the arsenic 2ps / 2 region of the arsenic-doped device and in (14B) the phosphorus 2s region of the phosphorus-doped device. Group V elements were only detectable (XPS detection limits -0.1%) on the TCO side of the TCO-Cd(Se,Te) interface. The peak positions for both arsenic (As 2p3 / 2: 1326.4 eV) and phosphorus (P 2s: 191.52 eV) indicate that the dopant atoms are in oxidized, cationic chemical states rather than in the desired anionic acceptor form. Localization of oxidized dopant atoms on the TCO is consistent with oxidative segregation observed in CdTe and other materials. To compare the extent of oxidative segregation for the two dopants, Group V and oxygen species were quantified, finding that [As] / [0]=0.008 and that [P] / [0]=0.04.

[0019] FIGS. 15A-15D: D-SIMS compositional depth profiles for (15A) the arsenic doped device and (15B) the phosphorus doped device, in addition to direct comparisons between devices for (15C) As and P and (15D) O, Cl, and Se. The depth of all of the profiles from the arsenic doped device were shifted by 200nm to align the front interface Sn signal.

[0020] FIG. 16: Activation (CCCV / SIMS) depth profiles overlayed with the Sn signal identifying the front TCO interface.

[0021] FIGS. 17A-17D: (17A) Urbach energy extraction from QE curves, (17B)-(17D) Voc analysis for bandgap Eg, Urbach energy Eu, ideal Voc, ERE, implied Voc, measured Voc, and contact selectivity for As vs P doping.

[0022] FIGS. 18A-18C: Temperature dependent current voltage (JV(T)) of sister cell of champion P-doped Cd(Se,Te) device. The data indicate a forward bias barrier at ~0.2 eV.

[0023] FIGS. 19A-19G: Cathodoluminescence imaging from cross-section showing intensity (19A) and representative CL spectra (19B)-(19D), as well as spectrally derived bandgaps (19E). Front interface CL intensity (19F) and bandgaps (19G).

[0024] FIGS. 20A-20P: (20A)-(20F) potential images taken on cross-sections of (20A) (20B) (20C) the P-doped device and (20D) (20E) (20F) the As-doped device, showing enhanced nonuniformity in the marked areas 1 and 2. (20G)-(20J) show line profiles averaged from the whole images of the P-doped device: (20G) AFM surface morphology, (20H) potential with the various bias voltage Vb applied to the device, (201) Vb-induced potential changes by subtracting the profile at Vb=0 from that of the various Vb, (20J) Vb-induced electric field by taking the first derivative of the potentials in panel (20H). (20K) is the Vb-induced electric field averaged in area 1 of the potential images, showing enhanced electric field nonuniformity with a pronounced peak at ~ 1.4 mm from the front interface that indicates the local n-p junction. (20L)-(200) are the respective line profiles averaged from the whole images taken on the As- doped device, like (20G)-(20J) on the P-doped device. (20P) is the Vb-induced electric field averaged in Area 2 of the As-doped device, showing a shoulder at -300 nm from the interface that indicates the local n-i-p junction. The potential analysis shows the device junction at the front interface with significant potential and junction nonuniformities.

[0025] FIGS. 21A-21E: (21A)-(21C) SSRM resistance images taken on delaminated front interface of the As-doped device with (21A) sample bias voltage Vs=+10 V, (2 IB) Vs=- 10V, and (21C) with both Vs=+10 V and -10 V. (2 ID) is average resistances from 3 SSRM images at each Vs. (21D)-(21E) show example line profiles along the lines in (21A)-(21C). The overall resistance value under positive Vs = +10 V (Figs. 21A, 21C, 21D, 21E, 21G) is smaller than that of negative Vs = -10V (Figures 21B, 21C, 21D, 21F, 21G), illustrating overall p-type doing of the film. The large resistance values indicate low carrier concentrations near the front interface. The resistance fluctuates more than one order of magnitude (Figs. 21 A, 2 IE), indicating similar carrier nonuniformity.DETAILED DESCRIPTION

[0026] Embodiments of a photovoltaic device for generating electrical power from light are described herein. The photovoltaic device generally includes a polycrystalline absorber layer formed from a semiconductor material. The polycrystalline absorber layer can be subjected to one or more processing steps configured to reduce defects and improve passivation. Various embodiments of the charge transport buffer and methods for passivating the polycrystalline absorber layer of the photovoltaic device will be described in more detail herein.

[0027] Referring now to FIG. 1, an embodiment of a photovoltaic device 100 is schematically depicted. The photovoltaic device 100 can be configured to receive light and transform light into electrical signals, e.g., photons can be absorbed from the light and transformed into electrical signals via the photovoltaic effect. Accordingly, the photovoltaic device 100 can define an energy side 102 configured to be exposed to a light source such as, for example, the sun. The photovoltaic device 100 can also define an opposing side 104 offset from the energy side 102. It is noted that the term “light” refers to visible light and can also include various wavelengths of the electromagnetic spectrum such as, but not limited to, wavelengths in the ultraviolet (UV) and infrared (IR) portions of the electromagnetic spectrum. The photovoltaic device 100 can include a plurality of layers disposed between the energy side 102 and the opposing side 104. As used herein, the term “layer” refers to a thickness of material provided upon a surface. Each layer can cover all or a portion of the surface.

[0028] The photovoltaic device 100 can include a substrate 110 configured to facilitate the transmission of light into the photovoltaic device 100. The substrate 110 can be disposed at the energy side 102 of the photovoltaic device 100. Referring collectively to FIGS. 1 and 2, the substrate 110 can have a first surface 112 substantially facing the energy side 102 of the photovoltaic device 100 and a second surface 114 substantially facing the opposing side 104 of the photovoltaic device 100. One or more layers of material can be disposed between the first surface 112 and the second surface 114 of the substrate 110.

[0029] The substrate 110 can include a transparent layer 120 having a first surface 122 substantially facing the energy side 102 of the photovoltaic device 100 and a second surface 124 substantially facing the opposing side 104 of the photovoltaic device 100. In some embodiments, the second surface 124 of the transparent layer 120 can form the second surface 114 of the substrate 110. The transparent layer 120 can be formed from a substantially transparent material such as, for example, glass. Suitable glass can include soda-lime glass, ora glass with reduced iron content. The transparent layer 120 can have a transmittance, including about 450 nm to about 800 nm in some embodiments. The transparent layer 120 may also have a transmission percentage, including, for example, more than about 50% in one embodiment, more than about 60% in another embodiment, more than about 70% in yet another embodiment, more than about 80% in a further embodiment, or more than about 85% in still a further embodiment. In one embodiment, transparent layer 120 can be formed from a glass with about 90% transmittance. Optionally, the substrate 110 can include a coating 126 applied to the first surface 122 of the transparent layer 120. The coating 126 can be configured to interact with light or to improve durability of the substrate 110 such as, but not limited to, an antireflective coating, an antisoiling coating, or a combination thereof.

[0030] Referring again to FIG. 1, the photovoltaic device 100 can include a barrier layer 130 configured to mitigate diffusion of contaminants (e.g. sodium) from the substrate 110, which could result in degradation or delamination. The barrier layer 130 can have a first surface 132 substantially facing the energy side 102 of the photovoltaic device 100 and a second surface 134 substantially facing the opposing side 104 of the photovoltaic device 100. In some embodiments, the barrier layer 130 can be provided adjacent to the substrate 110. For example, the first surface 132 of the barrier layer 130 can be provided upon the second surface 114 of the substrate 110. The phrase "adjacent to," as used herein, means that two layers are disposed contiguously and without any intervening materials between at least a portion of the layers.

[0031] Generally, the barrier layer 130 can be substantially transparent, thermally stable, with a reduced number of pin holes and having high s odium-blocking capability, and good adhesive properties. Alternatively or additionally, the barrier layer 130 can be configured to apply color suppression to light. The barrier layer 130 can include one or more layers of material, including, but not limited to, tin oxide, silicon dioxide, aluminum-doped silicon oxide, silicon oxide, silicon nitride, or aluminum oxide. The barrier layer 130 can have a thickness bounded by the first surface 132 and the second surface 134, including, for example, more than about 500 A in one embodiment, more than about 750 A in another embodiment, or less than about 1200 A in a further embodiment.

[0032] Referring still to FIG. 1, the photovoltaic device 100 can include a transparent conductive oxide (TCO) layer 140 configured to provide electrical contact to transport charge carriers generated by the photovoltaic device 100. The TCO layer 140 can have a first surface 142 substantially facing the energy side 102 of the photovoltaic device 100 and a second surface 144 substantially facing the opposing side 104 of the photovoltaic device 100. In someembodiments, the TCO layer 140 can be provided adjacent to the barrier layer 130. For example, the first surface 142 of the TCO layer 140 can be provided upon the second surface 134 of the barrier layer 130. Generally, the TCO layer 140 can be formed from one or more layers of n-type semiconductor material that is substantially transparent and has a wide band gap. Specifically, the wide band gap can have a larger energy value compared to the energy of the photons of the light, which can mitigate undesired absorption of light. The TCO layer 140 can include one or more layers of material, including, but not limited to, tin dioxide, doped tin dioxide (e.g., F-SnO2), indium tin oxide, or cadmium stannate.

[0033] The photovoltaic device 100 can include a buffer layer 150 configured to provide an insulating layer between the TCO layer 140 and any adjacent semiconductor layers. The buffer layer 150 can have a first surface 152 substantially facing the energy side 102 of the photovoltaic device 100 and a second surface 154 substantially facing the opposing side 104 of the photovoltaic device 100. In some embodiments, the buffer layer 150 can be provided adjacent to the TCO layer 140. For example, the first surface 152 of the buffer layer 150 can be provided upon the second surface 144 of the TCO layer 140. The buffer layer 150 may include material having higher resistivity than the TCO later 140, including, but not limited to, intrinsic tin dioxide, zinc magnesium oxide (e.g., Zm-xMgxO), silicon dioxide (SnO2), aluminum oxide (AI2O3), aluminum nitride (AIN), zinc tin oxide, zinc oxide, tin silicon oxide, or any combination thereof. In some embodiments, the material of the buffer layer 140 can be configured to substantially match the band gap of an adjacent semiconductor layer (e.g., an absorber). The buffer layer 150 can have a thickness between the first surface 152 and the second surface 154, including, for example, more than about 100 A in one embodiment, between about 100 A and about 800 A in another embodiment, or between about 150 A and about 600 A in a further embodiment.

[0034] Referring again to FIG. 1, the photovoltaic device 100 can include a polycrystalline absorber layer 160 configured to cooperate with another layer and form a p-n junction within the photovoltaic device 100. Accordingly, absorbed photons of the light can free electron-hole pairs and generate carrier flow, which can yield electrical power. The absorber layer 160 can comprise a polycrystalline, p-type thin film. The polycrystalline absorber layer 160 can have a first surface 162 substantially facing the energy side 102 of the photovoltaic device 100 and a second surface 164 substantially facing the opposing side 104 of the photovoltaic device 100. A thickness of the polycrystalline absorber layer 160 can be defined between the first surface 162 and the second surface 164. The thickness of the polycrystalline absorber layer 160 can be between about 0.5 pm to about 10 pm. In someexamples, the absorber layer thickness is equal to or greater than: 600nm, 700nm, 800nm, 900nm, 950nm, lOOOnm, llOOnm, 1200nm, or 1500nm. In some examples, the absorber layer thickness is less than or equal to: 4000nm, 3000nm, 2500nm, 2000nm, 1800nm, or 1500nm.

[0035] The polycrystalline absorber layer 160 can include a front interface region that can include controlled concentrations of dopants to improve device operation. The front interface region can be at the first surface 162 of the absorber layer 160. In some embodiments, the front interface region can be bounded by the first surface 162 of the absorber layer 160 and extend into the absorber layer 160 towards a central or bulk region of the absorber layer 160. The front interface region can comprise between 1% to 25% of the thickness of the absorber layer. In some examples, the front interface region comprises about 15% of the thickness of the absorber layer. In some examples, the interface region comprises at least 2%, 5%, 7%, 10%, 12%, 15%, or 20% of the thickness of the absorber layer. In some examples, the interface region comprises no more than 20%, 18%, 16% 15%, 12%, 10% or 7% of the thickness of the absorber layer.

[0036] The polycrystalline absorber layer 160 can include a central or bulk region. The bulk region can be defined as the middle 50% of the thickness of the absorber layer. The bulk region of the absorber layer 160 can be positioned between the front interface region of the absorber layer 160 and the second surface 164 of the absorber layer 160. Optionally, the bulk region of the absorber layer 160 can be adjacent to the front interface region of the absorber layer.

[0037] Referring still to FIG. 1, the polycrystalline absorber layer 160 can be formed from a p-type semiconductor material having an excess of positive charge carriers, i.e., holes or acceptors. The polycrystalline absorber layer 160 can include a p-type semiconductor material such as group II- VI semiconductors. Specific examples include, but are not limited to, semiconductor materials including cadmium, tellurium, selenium, or any combination thereof. Suitable examples include, but are not limited to, cadmium telluride, ternaries of cadmium, selenium and tellurium (e.g., CdSexTei-x,), or quaternaries comprising cadmium, selenium and tellurium. In embodiments where the polycrystalline absorber layer 160 comprises selenium and cadmium, the atomic percent of the selenium can be greater than about 0 atomic percent and less than about 20 atomic percent. In embodiments where the polycrystalline absorber layer 160 comprises tellurium and cadmium, the atomic percent of the tellurium can be greater than about 30 atomic percent and less than about 50 atomic percent. It is noted that the atomic percent described herein is representative of the entirety of the polycrystalline absorber layer 160, the atomic percentage of material at a particular locationwithin the polycrystalline absorber layer 160 can vary with thickness compared to the overall composition of the polycrystalline absorber layer 160. It is noted that the concentration of tellurium, selenium, or both can vary through the thickness of the polycrystalline absorber layer 160. For example, when the polycrystalline absorber layer 160 comprises a ternary of cadmium, selenium, and tellurium (CdSexTei-x), x can vary in the polycrystalline absorber layer 160 with distance from the first surface 162 of the polycrystalline absorber layer 160. In some embodiments, the value of x can decrease in the polycrystalline absorber layer 160 with distance from the first surface 162 of the polycrystalline absorber layer 160.

[0038] According to the embodiments provided herein, the polycrystalline absorber layer 160 can be doped with a group V dopant such as, for example, nitrogen (N), phosphorous (P), arsenic (As), antimony (Sb), bismuth (Bi), Moscovium (Me) or a combination thereof. The total dosage of the dopant within the polycrystalline absorber layer 160 can be controlled. In some embodiments, an atomic concentration of Group V dopant in the polycrystalline absorber layer 160 can be greater than about lxl017cm-3such as, for example, between about lxl017cm’3and about 5xl020cm’3in one embodiment, between about 3xlO17cm-3and about 5xl019cm’3in another embodiment.

[0039] Alternatively or additionally, the atomic concentration profile of the group V dopant can vary through the depth of the polycrystalline absorber layer 160. Specifically, the atomic concentration of the group V dopant can vary with distance from the first surface 162 of the polycrystalline absorber layer 160. It is noted that the phrase “average atomic concentration,” as used herein, can mean the average of the atomic concentration profile over a given region or thickness.

[0040] Referring still to FIG. 1, the p-n junction can be formed by providing the polycrystalline absorber layer 160 sufficiently close to a portion of the photovoltaic device 100 having an excess of negative charge carriers, i.e., electrons or donors. In some embodiments, the polycrystalline absorber layer 160 can be provided adjacent to n-type semiconductor material. Alternatively, one or more intervening layers can be provided between the polycrystalline absorber layer 160 and n-type semiconductor material. In some embodiments, the polycrystalline absorber layer 160 can be provided adjacent to the buffer layer 150. For example, the first surface 162 of the polycrystalline absorber layer 160 can be provided upon the second surface 154 of the buffer layer 150.

[0041] Referring collectively to FIGS. 1 and 3, the polycrystalline absorber layer 160 can be substantially polycrystalline, i.e., the polycrystalline absorber layer 160 can include a plurality of semiconductor grains 165 each separated by grain boundaries 166. Thesemiconductor grains 165 and grain boundaries 166 can be observed from visual detection techniques. Suitable visual detection techniques include scanning electron microscope (SEM) imaging and transmission electron microscopy (TEM), each of which may be performed by cross-sectional analysis or by removing intervening layers for top down imaging. Cross- sectional TEM can be used to obtain high-resolution nanoscale images of the cross-sections of photovoltaic devices 100, and constituent layers thereof. Each semiconductor grain 165 can have a distinct crystallographic orientation with respect to a neighboring semiconductor grain 165. Accordingly, the semiconductor grains 165 can be visible within TEM or SEM images, and image analysis can be performed to quantify the details of the semiconductor grains 165.

[0042] The semiconductor grains 165 can be positioned along the grain boundaries 166 within the polycrystalline absorber layer 160. Specifically, an outer face 167 of semiconductor grains 165 can demarcate the grain boundaries 166 throughout the poly crystalline absorber layer 160. The boundary portion 168 of the outer face 167 can be the part of the outer face 167 of the semiconductor grains 165 that is within the interior of the polycrystalline absorber layer 160. Accordingly, for semiconductor grains 165 positioned completely within the interior of the polycrystalline absorber layer 160, all of the outer face 167 can be a boundary portion 168. As used herein, the interior of the polycrystalline absorber layer 160 can be a component of the polycrystalline absorber layer 160 exclusive of the first surface 162 and the second surface 164 of the polycrystalline absorber layer 160. That is, the interior of the polycrystalline absorber layer 160 is disposed between the first surface 162 and the second surface 164 of the polycrystalline absorber layer 160.

[0043] According to the embodiments provided herein, a subset of the semiconductor grains 165 can be positioned at the first surface 162 of the polycrystalline absorber layer 160. Likewise, another subset of the semiconductor grains 165 can be positioned at the second surface 164 of the polycrystalline absorber layer 160. For such subsets of the semiconductor grains 165, the outer face 167 can be a segmented into multiple sections, i.e., a boundary portion 168 and a surface layer portion 169. For semiconductor grains 165 positioned at the second surface 164 of the polycrystalline absorber layer 160, the surface layer 169 portion of the outer face 167 can form a section of the second surface 164 of the polycrystalline absorber layer 160. The boundary portion 168 of the outer face 167 of each of the semiconductor grains 165 positioned at the second surface 164 can demarcate the grain boundaries 166 with neighboring semiconductor grains 165 in the interior of the polycrystalline absorber layer 160.

[0044] Referring collectively to FIGS. 1, and 3, the photovoltaic device 100 can include a charge transport buffer 170 configured to selectively passivate the polycrystalline absorberlayer 160. For example, the charge transport buffer 170 can restrict transport of elements or charge carriers along grain boundaries 166 of the polycrystalline absorber layer 160 into other layers. Accordingly, the charge transport buffer 170 can be provided over the second surface 164 of the polycrystalline absorber layer 160. In some embodiments, the charge transport buffer 170 can be disposed adjacent to the second surface 164 of the polycrystalline absorber layer 160. Specifically, the charge transport buffer 170 can directly contact surface layer portion 169 of the outer surface 167 of the semiconductor grains 165 at the second surface 164 of the polycrystalline absorber layer 160. Alternatively or additionally, the charge transport buffer 170 can obstruct or fill the grain boundaries 166 that extend to the second surface 164 of the polycrystalline absorber layer 160.

[0045] According to the embodiments provided herein, the charge transport buffer 170 can have a plurality of non-blocking regions 172 and a plurality of passivating regions 174. The non-blocking regions 172 and passivating regions 174 of the charge transport buffer 170 can be interwoven to correspond to the topology of the polycrystalline absorber layer 160. The thickness of the non-blocking regions 172 and passivating regions 174 of the charge transport buffer 170 can be measured along a normal of a surface to the polycrystalline absorber layer 160. In embodiments where the charge transport buffer 170 is applied to the second surface 164 of the polycrystalline absorber layer 160, the thickness of the non-blocking regions 172, measured along a normal of the second surface 164 of the polycrystalline absorber layer 160, can be less than or equal to about 5 nm. In some embodiments, passages can be formed through the non-blocking regions 172 of the charge transport buffer 170, i.e., the thickness can be 0 nm in some sections of the non-blocking regions 172.

[0046] As provided herein, the average thickness of the passivating regions 174, measured along a normal of the second surface 164 of the polycrystalline absorber layer 160, can be having an average thickness greater than about 5 nm and less than about 100 nm such as, for example, greater than about 5 nm and less than about 60 nm in one embodiment, greater than about 5 nm and less than about 45 nm in one embodiment, or greater than about 5 nm and less than about 25 nm in a further embodiment. The average thickness of the passivating regions 174 of the charge transport buffer 170 can be determined via SEM or TEM (optionally via cross-sectional analysis), i.e., thicknesses of the passivating regions 174 can be measured along each pixel of the second surface 164 of the polycrystalline absorber layer 160 and averaged together.

[0047] According to the embodiments provided herein, a majority of the charge transport buffer 170 can be formed from non-blocking regions 172. In an example, thepassivating regions 174 of the charge transport buffer 170 can cover between about 1% to 50%. For example, the passivating regions 174 of the charge transport buffer 170 can cover less than 50% of the second surface 164 polycrystalline absorber layer 160 such as, for example, less than 45%, less than about 40% in one embodiment, or between about 2% and about 35%, or between 5% and 30% in another embodiment. The percentage of coverage can be determined via SEM or cross-sectional TEM, i.e., the percent coverage taken along the cross-section is indicative of and correlated with the surface coverage percentage. In some embodiments, the passivating regions 174 of the charge transport buffer 170 can be provided directly over a majority of the grain boundaries 166 that extend to second surface 164 of the poly crystalline absorber layer 160. That is, the passivating regions 174 of the charge transport buffer 170 can cover or plug a majority of the grain boundaries 166 that exposed at the second surface 164 of the polycrystalline absorber layer 160.

[0048] In some embodiments, the charge transport buffer 170 can comprise a charge transport material. For example, the charge transport material can be a p-type material capable of being dissolved in a solvent such as, for example, a polymer, a small molecule, or an inorganic compound. Suitable polymeric semiconductor materials include Poly[bis(4- phenyl)(2,4,6-trimethylphenyl)amine] or poly[bis(4-phenyl)(2,4-dimethylphenyl)amine (PTAA), Poly(3-hexylthiophene-2,5-diyl) (P3HT), or Poly(3,4-ethylenedioxythiophene)- poly(styrenesulfonate) (PEDOT:PSS). In some embodiments, the charge transport buffer 170 consists essentially of PTAA. In some embodiments, the charge transport material comprises a small molecule selected from N2,N2,N2',N2',N7,N7,N7',N7'-octakis(4-methoxyphenyl)- 9,9'-spirobi[9H-fluorene]-2,2',7,7'-tetramine (Spiro-OMeTAD), N2,N2,N2',N2',N7,N7,N7', N7'-octakis(4-methoxyphenyl)-10-phenyl-10H-spiro[acridine-9,9'-fluorene]-2,2',7,7'- tetraamine (SAF-OMe), OMeTPA-FA, SGT-407, Fused-F, or tetrathiafulvalene (TTF-1). In some embodiments, the charge transport material comprises a material selected from: alpha- NPD, 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene), PCPDTBT, PCDTBT, graphene oxide, and quinolizino acridine. In some embodiments, the charge transport material comprises [2-(9H-carbazol-9yl)ethyl] phosphonic acid (2PACz), [2-(3,6-dimethoxy-9H- carbazol-9-yl)ethyl] phosphonic acid (MeO-2PACz), or [4-(3,6-dimethyl-9H-carbazol-9- yljbutyl] phosphonic acid (Me-4PACz). In some embodiments, the charge transport material comprises cis-di(thiocyanato)bis(2,2-bipyridyl4,4-dicarboxylate)ruthenium(II) (N719). In some embodiments, the charge transport material comprises A4,A4,A4",A4"-tetrakis([l,l'- biphenyl]-4-yl)-[l,r:4',l"-terphenyl]-4,4"-diamine) (TaTm). In some embodiments, the charge transport material comprises 2,2'-(perfluoronaphthalene-2,6-diylidene) dimalononitrile (Fe-TCNNQ). In some embodiments, the charge transport material comprises a polymer. In some embodiments, the charge transport material comprises a carbazole. In some embodiments, the charge transport material comprises a carbazole phosphonic acid (PACz), such as, Me-2PACz, Me-4PACz, MeO-2PACz, and can include a polymerizing carbazole phosphonic acid small molecule, such as poly-4PACz. In some embodiments, the charge transport material comprises Spiro[fluorene-9,9'-xanthene]. In some embodiments, the charge transport material comprises 2,7-carbazole. In some embodiments, the charge transport material comprises indolo[3,2- b]carbazole. In some embodiments, the charge transport material comprises 4-fluorothiophenol (4-FTP). In some embodiments, the charge transport material comprises 4- trifluoromethylbenzyl mercaptan (4-TFMBM). In some embodiments, the charge transport material comprises cysteamine, also known as 2-aminoethanethiol (AET). In some embodiments, the charge transport material comprises 1-octanethiol (OT). In some embodiments, the charge transport material comprises an inorganic compound selected from nickel oxide (NiOx), cuprous thiocyanate (CuSCN), or copper oxide (CU2O).

[0049] Referring still to FIG. 1, the photovoltaic device 100 can include a back contact layer 180 configured to mitigate undesired alteration of dopant levels, including an absorber layer dopant and / or a charge transport buffer layer dopant, and configured to provide electrical contact to the polycrystalline absorber layer 160. The back contact layer 180 can have a first surface 182 substantially facing the energy side 102 of the photovoltaic device 100 and a second surface 184 substantially facing the opposing side 104 of the photovoltaic device 100. A thickness of the back contact layer 180 can be defined between the first surface 182 and the second surface 184. The thickness of the back contact layer 180 can be between about 5 nm to about 200 nm such as, for example, between about 10 nm to about 50 nm in one embodiment.

[0050] In some embodiments, the back contact layer 180 can be provided adjacent to the charge transport buffer 170. For example, the first surface 182 of the back contact layer 180 can be provided upon the charge transport buffer 170. In some embodiments, a majority of the second surface 164 of the polycrystalline absorber layer 160, taken along a cross-section, can be offset from the first surface 182 of the back contact layer 180 by less than or equal to about 5 nm. Alternatively or additionally, the first surface 182 of the back contact layer 180 can be adjacent to both the passivating regions 174 of the charge transport buffer 170 and the second surface 164 of the polycrystalline absorber layer 160. For example, the first surface 182 of the back contact layer 180 can extend through passages in the non-blocking regions 172 of the charge transport buffer 170. Accordingly, crystal lattices of the polycrystalline absorberlayer 160 and the back contact layer 180 can be aligned at the non-blocking regions 172 of the charge transport buffer 170.

[0051] In some embodiments, the back contact layer 180 can include a chemical compound of materials from groups I, II, VI, such as for example, one or more layers containing zinc, copper, cadmium, and tellurium in various compositions in one embodiment, or binary or ternary combinations of materials from groups I, II, VI. Further exemplary materials include, but are not limited to, zinc telluride doped with nitrogen, zinc telluride doped with copper telluride, or zinc telluride alloyed with copper telluride.

[0052] In some embodiments, the charge transport buffer 170 and / or the back contact layer 180 comprise one or more layers comprising a polymer, small molecule, or inorganic compound. These materials can be doped to alter their electrical and optical properties. The compositions of the charge transport buffer 170 and / or the back contact layer 180 may be doped. For example, p-type dopants for small molecule compositions can include but are not limited to: 2,3,5,6-Tetrafluoro-7,7,8,8-tetracyanoquinodimethane (F4-TCNQ), trityl tetrakis pentafluorophenyl borate (TrTPFB), transition metal oxides such as molybdenum tri-oxide (M0O3), vanadium pent-oxide (V2O5) or tungsten tri-oxide (WO3), and molybdenum tris[l ,2- bis(trifhioromethyl-)ethane-l,2-dithiolene] (Mo(tfd)3). Other p-type dopants can include tris- pentafluorophenyl-borane (BCF) and its derivatives, such as, lithium-tetrakis- pentafluorophenyl- borate-ethyl ether complex (Li-BCF), triphenylmethylium tetrakis- pentafluorophenyl-borate (C-BCF), V,V-dimethylanilinium tetrakis-pentafluorophenyl-borate (N-BCF), or 4-isopropyl-4'-methyldiphenyliodonium tetrakis-pentafluorophenyl-borate (I- BCF).

[0053] The photovoltaic device 100 can include a transparent conducting layer 190 configured to provide electrical contact with the back contact layer 180, the polycrystalline absorber layer 160, or both. The transparent conducting layer 190 can have a first surface 192 substantially facing the energy side 102 of the photovoltaic device 100 and a second surface 194 substantially facing the opposing side 104 of the photovoltaic device 100. In some embodiments, the transparent conducting layer 190 can be provided adjacent to the back contact layer 180 or the polycrystalline absorber layer 160. For example, the first surface 192 of the transparent conducting layer 190 can be provided upon the second surface 184 of the back contact layer 180 or the second surface 164 of the polycrystalline absorber layer 160. A thickness of the transparent conducting layer 190 can be defined between the first surface 192 and the second surface 194. The thickness of the transparent conducting layer 190 can be lessthan about 500 nm such as, for example, between about 40 nm and about 400 nm in one embodiment, or between about 60 nm and about 350 nm.

[0054] According to the embodiments provided herein, the transparent conducting layer 190 can include one or more functional layers of material. The transparent conducting layer 190 can include a diffusion barrier layer operable to limit diffusion of metal species into the polycrystalline absorber layer 160. Materials suitable for use in the diffusion barrier include transparent conductive oxides such as, for example, tin oxide (SnCh) zinc oxide (ZnO), indiumtin oxide (In(2-x)SnxO3), cadmium oxide (CdO), and cadmium stannate (Cd2SnO4). These transparent conductive oxides can be doped with impurities such as F, Al, In, Ga, Ti, and others to alter their electrical and optical properties.

[0055] The transparent conducting layer 190 can include a high conductivity layer disposed over the diffusion barrier layer and configured to provide low device series resistance. The high conductivity layer can include a degeneratively doped transparent conductive oxide. In some embodiments, the high conductivity layer can be doped n-i— I- intrinsically or with an oxide dopant. Suitable oxide dopants include, but are not limited to, ImCh, Ga2Ch, TiO2, Dy20s, SnO2, Y2O3, AI2O3, or a combination thereof. In some embodiments, high conductivity layer can include cadmium oxide (CdO) such as, for example, indium oxide doped cadmium oxide (CdO:In2O3) or gallium oxide doped cadmium oxide (CdO:Ga2O3).

[0056] The transparent conducting layer 190 can further include a capping layer operable to mitigate corrosion of the high conductivity layer in hot and humid environments. Accordingly, the transparent conducting layer 190 can include a diffusion barrier layer / high conductivity layer / capping layer stack of layers. The capping layer can include a transparent conductive oxide, such as, but not limited to, cadmium stannate.

[0057] The photovoltaic device 100 can include a back support 196 configured to cooperate with the substrate 110 to form a housing for the photovoltaic device 100. The back support 196 can be disposed at the opposing side 104 of the photovoltaic device 100. For example, the back support 196 can be formed adjacent to the transparent conducting layer 190. The back support 196 can include a supporting material, including, for example, glass (e.g., soda- lime glass).

[0058] Referring still to FIG. 1, manufacturing of a photovoltaic device 100 generally includes sequentially disposing functional layers or layer precursors in a “stack” of layers through one or more processes, including, but not limited to, sputtering, spray, evaporation, molecular beam deposition, pyrolysis, closed space sublimation (CSS), pulse laser deposition (PLD), chemical vapor deposition (CVD), electrochemical deposition (ECD), atomic layerdeposition (ALD), or vapor transport deposition (VTD). Once a layer is formed it may be desirable to modify the physical characteristics of the layer through subsequent treatment processes.

[0059] Referring collectively to FIGS. 4 and 5, a layer of a partially formed device can be processed. In some embodiments, a partially formed photovoltaic device 202 can comprise the polycrystalline absorber layer 160 adjacent to a layer stack 204. The layer stack 204 can include one or more of the layers of the photovoltaic device 100 (FIG. 1) disposed between the polycrystalline absorber layer 160 and the energy side 102. Alternatively, a partially formed photovoltaic device 206 can comprise the polycrystalline absorber layer 160 adjacent to a layer stack 208. The layer stack 208 can include one or more of the layers of the photovoltaic device 100 (FIG. 1) between the polycrystalline absorber layer 160 and the opposing side 104.

[0060] Referring now to FIG. 6, a method 210 for forming photovoltaic devices with charge transport buffers is schematically depicted. In some embodiments, the method 210 can be performed after subjecting the polycrystalline absorber layer 160 to a chloride heat treatment (CHT). CHT is an annealing process that can be performed within a chlorine, oxygen, and hydrogen containing atmosphere. CHT can alter and, in part passivate, defects by the CHT process. The charge transport buffers 170, described herein, can enhance or improve upon defect passivation achieved by the CHT process.

[0061] Referring collectively to FIGS. 3, 4, 5, and 6, the method 210 can include a process 212 for contacting the polycrystalline absorber layer 160 with a charge transport precursor 214. In some embodiments, the charge transport precursor 214 can be applied to the first surface 162 or the second surface 164 of the polycrystalline absorber layer 160 as a suspension or solution in a solvent. For example, the charge transport precursor 214 can be sprayed, spin coated, or roll coated upon the polycrystalline absorber layer 160. Alternatively or additionally, the charge transport precursor 214 can be supplied as a vapor.

[0062] The composition of the charge transport precursor 214 is controlled such that a desired percentage surface area of the polycrystalline absorber layer 160 is covered. The semiconductor material for the charge transport buffer 170 can be dissolved within an organic solvent. Suitable organic solvents include chlorobenzene, toluene, tetralin, or another aromatic liquid organic solvent. Generally, the charge transport material can be provided as , ions, small molecules, or polymers that lack strong intermolecular attractions. Accordingly, the charge transport material can be distributed substantially evenly throughout the organic solvent at the desired composition. The charge transport material can be controlled at a mass of charge transport material to volume of organic solution ratio of less than about 10 mg of chargetransport material per mL of organic solvent such as, for example, between about 0.01 mg and about 8 mg of charge transport material per mL of organic solvent in one embodiment, between about 0.05 mg and about 6 mg of charge transport material per mL of organic solvent in another embodiment or between about 0.1 mg and about 3 mg of charge transport material per mL of organic solvent in a further embodiment.

[0063] The method 210 for forming photovoltaic devices with charge transport buffers can include a process 216 for removing the solvent from the charge transport precursor 214. For example, the organic solvent can be evaporated from the charge transport precursor 214. Specifically, the charge transport precursor 214 can be processed at a temperature between about 50° C and about 250° C for less than about 5 minutes such as, for example, at a temperature in a range of about 75° C to about 200° C for a duration of less than about 1 minute. Evaporation of the organic solvent can cause the charge transport material to reach its solubility limit and begin precipitating out of charge transport precursor 214. Accordingly, the charge transport buffer 170 can be selectively deposited in valleys and low-points of a surface of the polycrystalline absorber layer 160.

[0064] Examples

[0065] Table 1

[0066] Table 1 provides a summary of various experimental embodiments according to the present disclosure. The Comparative Example and Examples 1-4 were all prepared from the same stack of materials. Specifically, a glass substrate was coated with a front contact material, which included a layer of fluorine doped tin oxide. The front contact material was coated with a buffer layer of zinc magnesium oxide. The front contact was coated with a CdSeTe absorber layer. The absorber layer was further processed with post deposition treatments including CHT processing. After CHT processing, a charge transport solution having the specified concentration of PTAAin chlorobenzene was spin coated upon the CdSeTeabsorber layer. A back contact layer of nitrogen doped zinc telluride was deposited over the PTAA charge transport buffer and a conducting layer was deposited over the back contact layer.

[0067] The application of PTAA was imaged using a scanning electron microscope (SEM) after deposition of the PTAA, and prior to deposition of any additional layers. The images were processed using MIPAR image analysis software by MIPAR of Columbus, OH, USA. With reference to FIG. 7, FIG. 8 A and FIG. 8B, which depicts an SEM image of Example 3, PTAA is visible as darkened regions. The PTAA can be seen as selectively coating the grain boundaries at the surface of the absorber layer, and local minima of semiconductor grains at the surface of the absorber layer. The coverage amount can be determined by calculating the proportion of pixels with PTAA divided by the total number of pixels corresponding to the surface of the absorber layer.

[0068] Generally, coverage increases with concentration. Significant gains in efficiency were observed with Examples 1 and 2 relative to the Comparative Example. Although efficiency decreased in Examples 3 and 4 with increased coverage, long term reliability (LTR) improves with the increased coverage of Examples 1-4 relative to the Comparative Example.

[0069] Table 2

[0070] Table 2 provides a summary of various experimental embodiments. The Comparative Example 2 and Examples 5-9 were all prepared in substantially the same manner as the examples detailed in Table 1, except different equipment was used and the organic solvent was replaced with toluene. Although coverage was not specifically collected for Examples 5-9, coverage corresponded to the coverage of Table 1. Significant gains in efficiency were observed with Examples 5-8 relative to the Comparative Example 2. LTR improvements are expected in all of Examples 1-9.

[0071] Group V doping in cadmium telluride solar cells has ushered in a resurgence of improving device performance beyond the plateau of traditional copper doping. A certified -1% absolute benefit over the best reported copper-doped devices is demonstrated. This progress came from reducing recombination via a dielectric buffer at absorber grain boundaries at the back interface and introducing a transparent back contact with optical reflector. Detailed electrical, optical, and compositional characterization of -23% efficient devices is presented allowing direct comparison of As- and P-doped cells, with notable differences in bandtails and recombination between the two. Pathways for further improvement are presented along with preliminary data on how to achieve them. These include enhanced dopant activation, reduced potential fluctuations, and identification / mitigation of non-radiative recombination centers.

[0072] As utility-scale solar photovoltaics (PV) have become cost-competitive with mainstream energy sources, its manufacture and deployment over the past decade has reached levels that demonstrate the ability to realistically impact the energy economy. While global installed PV capacity breached the terawatt (TW) threshold, forecasts project a massive increase to 75 TW by 2050. The majority of this deployment has been led by silicon (Si) photovoltaics. Most of the balance is cadmium telluride (CdTe) photovoltaics, which is the largest deployed thin-film PV technology with ~5% global market share and ~25% share of cumulative US utility-scale PV. Annual manufacturing capacity of CdTe modules has been exponentially growing at almost 40% for the better part of a decade reaching -20 GW. CdTe PV serves as an existence proof that a non-Si PV technology can be manufactured at meaningful scale and be cost-competitive. This in part comes from material and energy consumption advantages of CdTe relative to silicon and are related to the rapid, direct deposition of the thin-film semiconductor absorber on a glass substrate versus the slow, production of free- stranding single crystal wafers. At the same module nameplate wattage, CdTe competes with Si favorably in energy yield, due to its lower temperature coefficient (- 0.28% / C), lower warranted long-term degradation rate (0.3% / year), insensitivity to infrared absorption in humid climate, as well as lower embodied energy (~3x) and carbon (~2-4x). Although CdTe has achieved success in the marketplace, it has headroom to improve performance based on the detailed balance limit, with a record cell efficiency of 23% compared to -33% theoretically possible, leaving it at -70% of its entitlement.

[0073] State-of-the-art CdTe-based PV is now alloyed with Se in a graded fashion such that it is more accurately described as Cd(Se,Te). This alloying improves the carrier lifetime and radiative efficiency resulting in little voltage penalty with the lowering of its bandgap to -1.4 eV. The detailed balanced limit for a 1.4 eV bandgap semiconductor has a maximumachievable short circuit density (Jsc) of 32.88 mA / cm2, open circuit voltage Voc) of 1.122V, and fill factor of 89.3%, resulting in a Voc.FF product of 1.002V. When examining the properties of record and notable cells (Table 1), J sc is -95% of the theoretical entitlement. J sc is generally driven by increased carrier diffusion length as evident in long wavelength QE curves, by eliminating absorptive losses (e.g., by improving the transmission of the transparent contact and glass) and reflective losses (through an anti-reflective coating or ARC). Almost all remaining improvements must come from the Voc.FF product - improvement of both Voc and FF are driven by scientific understanding.

[0074] The rise of Cd(Se,Te) record devices have been improvements in the contact layers and through understanding and controlling a new doping defect chemistry, where a group V dopant (As or P) sits on the anion (Se or Te) site, in place of the historical defect chemistry where a Cu dopant sits on the cation (Cd) site. Unlike with some emerging technologies where the most efficient devices are not always the most stable, the improved efficiency has come with a much lower diffusion constant of dopants and reduced the energetic favorability of complexing with Cl which leads to improved stability with group V doping relative to a Cu defect chemistry. The present disclosure provides a detailed view of the optoelectronic properties of devices using two different group V dopants, P and As, which both achieve -23% efficiency in manufacturable architectures, but have different losses from recombination and electronic disorder.

[0075] Table 3: Cu-doping & Group V doping

[0076] Table 3 compares an optimized Cu-doped cell to recent group-V doped cells. It may appear in NREL’s record solar cell efficiency charts that until recently CdTe-based PV hadstalled. This was because all previous records with intentional doping used Cu as a dopant on the Cd site. Copper’s multivalency and high diffusivity in CdTe leads to a compensating defect chemistry limiting doping, efficiency, and stability. Use of bulk single crystals demonstrated a path to improved Voc using an alternate chemistry to dope with a group V (GrV) element on the anion (Te) site. Reductions in recombination that lead to improved voltage also improve fill factor. Good efficiency was also demonstrated for a manufacturable Cd(Se,Te):As device with a two order of magnitude increase in carrier concentration without impairing carrier lifetime. The Voc was lower than the record Cu-doped device, at least in part due to the collapse of the space charge region from increased carrier concentration making it more sensitive to recombination near the front interface. The higher carrier concentration increased susceptibility to potential fluctuations that can reduce radiative voltage.

[0077] A 22.6% record cell showed marked improvement in the voltage (and photoluminescence intensity) with the introduction of a grain boundary sealing layer, also referred to as a charge transport buffer, at the back contact. SEM images of an example sealing layer are shown in Fig. 7, Fig. 8A, and Fig 8B. Sealing the grain boundaries with a largely insulating dielectric reduces recombination at the hole contact interface, resulting in a Voc gain in the device. Reducing the losses introduced by the back contacting process provides a synergistic benefit with a GrV-doped absorber. Combining these features with a transparent back contact having an optical reflector, together with absorber thickness and Se depth concentration profile adjustments, produces devices with optimal efficiency, uniformity, stability, and manufacturability. Example devices with this architecture demonstrate measured efficiency at or above 23% efficient devices. An example P-doped cell was certified at 23.1% as shown in Fig. 9F. These improvements have led to an increase in Voc.FF product of ~5% from the last Cu-doped record cell. Devices utilizing two different GrV dopants, phosphorus and arsenic, have achieved similarly high performance (Fig. 9). This analysis provides two different routes to 23% using sister samples.

[0078] Doping Impact on Optimization for Cd(Se,Te)

[0079] While efficiency is very similar for the highest performing P- and As-doped devices, a systematic and detailed analysis reveals differences. At the highest level, the P- doped sample has notably higher FF as well as slightly higher Voc, but slightly lower current (Table 3, Fig 9). Absorber property characterization explains these differences. The bandgaps derived from the effects of Se-alloying are virtually the same, as revealed by examination of the compositional profiles combined with extracted values derived from quantum efficiency (QE) (Fig 12). The QE’s flatter red response indicates a longer diffusion length in the As-doped sample, which is consistent with the longer lifetimes observed by time-resolved photoluminescence (TRPL) that may stem from unintended differences in the Se profile. The carrier concentration in the P-doped sample is lower at 6el5 cm'3compared to 9el5 cm'3; this corresponds to a larger depletion width. In comparing the TRPL responses (Fig. 10), the P- doped sample has higher recombination. Its wider depletion width should reduce sensitivity when the recombination occurs at the front interface. The activation (ratio of electrically active net carriers to chemically incorporated dopants) for both is low, ~1% for As and 0.3% for P, with dynamic secondary ion mass spectrometry (D-SIMS, Fig 13) indicating average incorporation of ~lel8 cm'3(As) and ~2.5el8 cm'3(P) throughout most of the absorber bulk. D-SIMS indicates overall low oxygen levels in both samples with lower oxygen than the dopant through most of the bulk. This is true except near the front interface, where there is a higher concentration of both oxygen and dopant suggesting lower activation there (Figures 14-16). For example Figs. 15A-15B show very high oxygen concentrations near the front interface. Group-V dopants in oxidized form have been observed to segregate at the front interface, and in these devices, phosphorus appears to accumulate at the front more significantly than arsenic, perhaps due to higher P diffusivity related to its smaller size. This increased concentration may also be related to the higher interface recombination observed in P-doped devices.

[0080] The photoluminescence shows a higher absolute external radiative efficiency (ERE) in the As-doped sample, but also higher bandtails resulting in higher Urbach energy (Eu) derived from QE. The estimated voltage losses from these two pathways (ERE relates to non- radiative recombination losses, Eu relates to an effective reduction in the bandgap) appear to largely balance one another between the P-doped and As-doped samples (Fig 10). For multiple lots of similarly prepared high performance samples, the mean Eu was 24.9 meV (ranging from 19.9-31.9 meV) for As-doped samples and 22.3 meV (ranging from 15.5-26.6 meV). In the champion cells, Eu was 25.6 and 22.7 meV, for As- and P-doped samples, respectively. This reduced the QE derived Voc, ideal by 81 and 43 mV, for As- and P-doped samples respectively. Consistent with its lower lifetimes, there appears to be higher non-radiative recombination in the P-doped samples. This is captured in the mean external radiative efficiency of 0.073% (ranging from 0.055-176%), with the champion having 0.059% ERE. The As-doped samples had higher ERE, with a mean of 0.201% (ranging from 0.099-0.305%), with the champion having 0.219% . Looking at the champion samples, this converts implied Voc losses of 185 mV and 152 mV losses, for P- and As-doped samples respectively. While the higher Euin As- doped samples is generally deleterious, it provides a compensating benefit through its slight boost to Jsc. The last piece of the Voc loss analysis, referred to as selectivity is indicative ofpoor carrier transport and may relate to contact barriers, poor mobility, and / or other transport deficiencies. The selectivity losses here are small, but slightly better in the As-doped sample, leaving the actual open-circuit voltage for the two sample types within 1% of one another. In summary, recombination losses have the largest impact, voltage losses due to electronic disorder (bandtails) are reduced from 35% (As-doping) to 18% (P-doping) but are still significant, and selectivity losses are small, <1% (As-doping) and 2% (P-doping).

[0081] The present application discusses synergistic advances to improve the device architecture of II- VI thin-film photovoltaic technology, CdTe (including CdSexTei-xand alloys).

[0082] Device modeling has long indicated that the front interface and absorber have major opportunities for improvement. While the challenging shift in defect chemistry from Cu-doping to As- and P-doping improved the absorber, the two most recent improvements in efficiency stemmed from changes targeting the back interface, including grain boundary sealing and transparent back contact with reflector. It has been noted previously that process changes nominally targeting the back contact can also impact the bulk and even front interface, making everything intertwined. Better models which can distinguish loss pathways more readily to inform experimental work would help the community. Prior modeling of JV(T) data from record samples has been inconclusive as to band alignment at the front interface; previous modeling indicates tuning this alignment to achieve a spike in the bands of ~0.2 eV would mitigate sensitivity to high front interface recombination velocity. Low dopant activation ratios may also be contributing to Voc(T) trends. While optical absorption is not a problem as evidenced by the consistently high JSC (and should support absorbers down to 1-1.5 pm without photon recycling), decreasing thickness of devices in today’s state of the art reduces VOC and FF as the highly recombinative back interface is “seen” more easily by the front interface. This indicates more room for improvement at the back. The device architecture can be modified to optimize for band alignment, Fermi level pinning, recombination / passivation, and material compatibility. Improvements at the back not only improve absolute efficiency, but when coupled with a transparent back contact can provide higher bifaciality (ratio of backside to front-side efficiency).

[0083] Other recent work indicates that mobilities of polycrystalline Cd(Se,Te) samples are significantly lower than values often used in models. This has been generally overlooked and may be impairing diffusion length and hence fill factor in devices. Presently, polycrystalline samples rarely have mobilities measured, with little control over the factorsinfluencing it, such as grain boundaries (single crystals have much higher values making it not an intrinsic limitation).

[0084] Electronic disorder in the absorbers is another place for improvement. Photoluminescence shows bandtails (Fig. 11) that can stem from several microscopic sources including low activation resulting in potential fluctuations, and disorder from impurities / traps. One of the challenges is to identify their relative contributions and / or which dominate. Preliminary microscopic measurements using scanning spreading resistance microscopy (SSRM), Kelvin probe force microscopy (KPFM), cathodoluminescence, and Auger electron microscopy (AEM) (Fig. 13) of cross-sections and delaminated samples to reveal nonuniformities, but further analysis is to understand how they are linked and their impact is still required. For instance, SSRM shows more than one order of magnitude variation in resistance, which should directly correlate to carrier concentration, and there is weak correlation between Se concentration and resistance, but the details of the carrier uniformity and their correlation with Se content are different in the P- and As-doped samples (SI). Near the front interface are regions of low and nonuniform carrier concentration, which is consistent with KPFM.

[0085] Further work on As-doped devices has found a strong correlation between As dosage (chemical incorporation) and Eu. Varying the As dosage from 2xl017to IxlO19cm'3enabled a series of samples all with carrier concentration in the range of l-2xl016cm'3. High dosages resulted in a significant increase in bandtails with Eu> 30 meV while lowering dopant incorporation reduced Eu to ~20 meV [for reference Eu,23% As-doPed~25.6 meV, Eu,23% p-doPed~22.7 meV]. In parallel, it has been found that activation can be increased much above the ~1% in the recent 23% record cells, with up to -20% attainable for maximum 10% Se, and 7% activation for 30% Se. These last two improvements indicate that careful process control can drive down sources of electronic disorder, however, translation to improved device performance requires reoptimization with the rest of the device. Passing the 23% efficiency mark is an important milestone for CdTe photovoltaic s. It is especially notable having done this with a group- V defect chemistry facilitating synergistic improvements. Using GaAs with its similar bandgap as a reference point, practical (compared to theoretical) limits indicate >28% is achievable for CdTe-based devices.

[0086] Device Fabrication

[0087] CdSeTe absorbers with a graded Se profile are deposited using vapor transport deposition (VTD) on a substrate consisting of soda lime glass coated with fluorine-doped tin oxide (FTO) as the transparent conductive oxide (TCO) layer and a buffer layer. The doped absorbers, with either As or P doping, undergo a chlorine heat treatment (CHT) to promotegrain growth, dopant activation, chlorination of grain boundaries, and diffusion of Se to form the final graded profile. After the CHT process, a proprietary back contact passivation treatment is carried out, followed by sputter deposition of the p-type zinc telluride back contact. This is followed by a sputtered transparent back contact electrode with an added Au layer for added reflectivity. The front of the glass substrate is treated with an anti-reflective coating for record devices.

[0088] Solar simulation

[0089] A four-point probe measurement is used in JV (current- voltage) characterization to minimize the influence of contact resistance. A solar cell under 1 sun (AM 1.5) illumination in superstate configuration is measured by a class ABB Oriel Soil A solar simulator. The JV sweep was performed from -1.2 V to 1.2 V bias in steps of 6.5 mV, with a dwell time of 1 ms.

[0090] Solar Capacitance- Voltage (CV)

[0091] CV measurements were used to determine the curve of depletion width (W) versus carrier concentration (Na). The measurement by an Agilent E4980A LCR meter is from 0.5 V to -2.0 V in steps of 0.05 V with a dwell time of 20 ms at a frequency of 40 kHz.

[0092] Solar External Quantum Efficiency (EQE)

[0093] An incident photon to electron conversion efficiency was measured by scanning from 320 nm to 960 nm with 10 nm steps using a chopped monochromator and lock-in amplifier detection. It was calibrated using a spectral response of a Si reference cell (Hamamatsu, Si photodiodes S1337-66BR). EQE was used for determination of bandgap (Eg) and the Urbach energy (Eu).

[0094] External Radiative Efficiency (ERE)

[0095] ERE measurements were performed. Sample excitation occurs from a Thorlabs LDM 670 Laser module 670 nm, chopped at a frequency of 105-110 Hz using a SR540 optical chopper, in parallel with a 1 -sun-equivalent white light-emitting-diode bias (Thorlabs Solis-3C high power White LED). Sample emission is detected using a silicon photodetector (Thorlabs DET100A2 Silicon photodetector) connected to a lock-in amplifier (SR830) modulated by the optical chopper, with a 785nm long-pass filter inserted along the detection pathway. Spectralon 1” 2% and 99% reflectance standards were used for ERE calibration.

[0096] Scanning electron microscopy (SEM)

[0097] A plan view and a cross-sectional SEM was prepared by FEI Helios Nanolab 600i scanning electron microscope / focused ion beam (SEM / FIB). A 10 kV beam was used to contrast hole transport material (HTM) with CdTe. For a cross-sectional SEM, a layer of gold (Au) was deposited on the sample to prevent damage from the electron beam.

[0098] Cathodoluminescence (CL)

[0099] CL spectral mapping was carried out using a Gatan Monarc CL detector in the FEI SEM, in both top-down and cross-sectional mode, where the former was performed on CdSeTe films and the latter was performed on FIB-polished device cross-sections. Electron beams were accelerated to a beam voltage of 5kV using a beam current of 5.5 nA. CL spectra were collected with a spectral resolution (step size) of 7.8nm. Bandgap maps generated by spectral peak fitting.

[0100] Photoluminescence (PL) spectroscopy

[0101] PL emission spectra were measured with HRS300 spectrograph equipped with Si (Pixis Fl 00) and InGaAs (PyLoN 1024) detectors (all Princeton Instruments). Spectral response was calibrated by placing manufacturer provided VIS and NIR QTH calibration sources in the sample position. Absolute photon numbers were determined using reflectance standards (LabSphere). Excitation was with HeNe laser (Thorlabs) and excitation beam diameter was determined with a CCD camera beam profiler. Absolute PL emission spectra were measured at 298 K. Closed loop helium cryostat was used to measure PL emission spectra at low temperature.

[0102] Time-resolved photoluminescence (TRPL) was measured using excitation at 640 nm and 275 kHz repetition rate (300 fs laser pulses, Pharos / Orpheus, Light Conversion). Si APD detector (Micro Photon Devices) and time-correlated photon counting (Picoharp 300, Picoquant) was used. Bandpass filters were used to select emission wavelengths.

[0103] X-ray Photoemission Spectroscopy (XPS)

[0104] XPS was performed in a Physical Electronics VersaProbe III using monochromatic Al Ka X-rays and at near-normal photoelectron take-off angle. Wide range “survey” spectra were taken using a pass energy of 280 eV; narrow range spectra were acquired with 27 eV pass energy. The spectrometer binding energy scale was calibrated at high and low kinetic energy using the Fermi edge feature of clean gold foil taken with X-rays and He I light (21.22 eV). The front transparent conducting oxide-Cd(Se,Te) interface was accessed using thermomechanical delamination in a nitrogen-filled glovebox. A conductive silver epoxy (EPO-TEK H20E) was used in delaminations to ensure good electrical contact to the Cd(Se,Te) sides. Cleaved interface halves were transferred to the XPS system without exposure to air using a Physical Electronics Model 07- 11 IK sample transfer vessel. Data were analyzed using Wavemetrics Igor 9 and Physical Electronics MultiPak v9.9.1.1 with its built-in elemental sensitivity factors.

[0105] Auger Electron Spectroscopy (AES)

[0106] Auger electron spectroscopy and microscopy were performed in a Physical Electronics 710 system using a 10 kV, 10 nA primary beam. Selenium, tellurium, and cadmium AES sensitivity factors were derived as described previously using an ungraded Cd(Se,Te) standard film that had been characterized with X-ray fluorescence. Data were analyzed using Wavemetrics Igor 9 and Physical Electronics MultiPak v9.9.1.1. Samples were prepared via thermomechanical delamination and transferred to the Auger system in the same manner as XPS.

[0107] Scanning spreading resistance microscopy (SSRM)

[0108] SSRM is based on the contact mode of an atomic force microscope (AFM, Bruker Dimension Icon and Nanoscope V) and set in an Ar-glovebox with a logarithm-scale amplifier (Bruker SSRM module) to measure a wide range of resistance (103-1014 W). The probe (Bruker DDESP-V2) is highly doped (r=10-4 Wcm) diamond-coated Si tip. SSRM is a two terminal resistance measurement with a bias voltage applied to the sample (Vs) and the probe is floating-grounded. Back contact resistance along the current route, Rb, is very small (102-103 W) compared to sample’s spreading resistance Rsp, neglectable. Front probe / sample contact resistance Rc is minimized to a degree much smaller than Rsp by pressing the probe into sample in ~1 mN contact force to create local dangling and strained bonds and by applying a large forward Vs (8-10 V). The measured resistance is thus dominated by Rsp, and Rsp is further dominated by resistance beneath the probe in -50 nm sizes both laterally and vertically. For sample preparation, the front interface was delaminated by thermomechanical stressing in liquid nitrogen. The absorber film was further beveled into the bulk using Ar ion-milling (JEOL CP) at a glancing angle to make the film with mm depth appearing in wide mm lateral distance. The beveling depth was estimated based on a measurement using optical profilometer (Veeco WYKO NT1100).

[0109] Kelvin probe force microscopy (KPFM)

[0110] The state of the art KPFM potential imaging is based on a non-contact mode AFM (Veeco Dimension 3100 and Nanoscope V controller) and is made using the second harmonic oscillation of cantilever to enhance voltage sensitivity in -10 mV and to isolate from artifact of surface morphology. A Ptlr-coated Si probe (Nanosenser PPP-EFM) with the resonant oscillation frequency of -60 kHz was used. The first harmonic oscillation is used for AFM imaging. The transparent conducting oxide (TCO) is grounded and a bias voltage (Vb) is applied to the back contact to vary voltage drop across the device. The device was mechanically cleaved to expose cross-sections, and the cross-section was polished by Ar ion milling (JEOE CP). The sample was further annealed in a low vacuum oven at 250°C for 5minutes to passivate the cross-sectional surface in some degrees. As KPFM measures surface potential that is dominated by electrical charges trapped at the cross-sectional surface states, an external bias Vb is applied to the device, and the change in surface potential was measured. The potential change in the device bulk is approximately identical to the measured Vb-induced surface potential change, as the surface charges are localized, do not drift with a small Vb < 2 V. In this way, the effect of surface charges is avoided, however, only the Vb-induced changes in potential and electric field could be obtained instead of the absolute built-in potential / across the device.

[0111] Dynamic Secondary Ion Mass spectroscopy (Eurofins EAG Laboratories)

[0112] PL and Voc loss

[0113] A loss partitioning analysis can be carried out for Voc on the devices. The ideal Voc is determined by the bandgap (Eg) and the sharpness of band-edge absorption, which can be obtained either from optical absorption measurements or from external quantum efficiency (EQE) measurements, where this approach uses the latter. In particular, the bandgap (Eg) is defined as the maximum of the derivative of the EQE measurement, and the Urbach energy as the inverse slope of ln(-ln(l-QE)) in the range of Eg to Eg-lOOmV, namely the band edge. The ideal Voc is considered the radiative limit of Voc. The Voc losses from non-radiative recombination are then accounted for using external radiation efficiency (ERE) measurements, which define the deficit from Voc, ideal by kT / qln(ERE), which leads to the implied Voc or “iVoc”, namely the quasi-fermi level separation and best achievable Voc considering both radiative and non-radiative recombination losses, but with perfectly selective contacts. The ratio of iVoc / Voc captures any losses due to imperfect contact selectivity.

[0114] Using this framework, the Voc partitioning for P and As doped record devices can be compared with Voc -900 mV for both cases. The lower Urbach energy for P doping leads to higher ideal Voc, but the lower ERE for P offsets this Urbach energy benefit, leading to similar iVoc for the two dopants. The close matching between iVoc and measured Voc indicates good contact selectivity for both dopants.

[0115] Composition and Activation

[0116] D-SIMS for the two record devices was carried out by Eurofins EAG Laboratories (Fig. 14). Measurements were carried out from the back surface of the device stack through the Au metallization, TBC, back contact buffer, Cd(Se,Te) absorber, front buffer, and finally the tin oxide TCO. Quantification for As, P, Cl, and O was done assuming a Cd(Se,Te) matrix, so the profiles are shown primarily for the Cd(Se,Te) absorber (after the Au / TBC stack and up to the tin oxide TCO). Signals outside the Cd(Se,Te) absorber and withinlOOnm of the interfaces are likely erroneous. The profiles from the arsenic doped device were shifted by 200nm to align the front interface TCO Sn signal between the P and As doped devices. Cl, O and Se (raw) are similar between the two devices, but there are some differences in the dopant signals. The As device exhibits shows a flat As incorporation profile at ~ lei 8 cm'3throughout the depth of the absorber with a slight increase near the front interface to -2E18 cm'3. The P signal in the P device is not as flat, starting around lel9 cm'3near the back interface, decreasing to lel8 at total depth of about 4um before increasing sharply again to Mel 9 cm'3near the front interface. The background As level in the P doped device seems below lel7 cm'3for most of the absorber, though this signal also increases near the front interface. The oxygen signal is very high both devices within 0.5- 1pm of the front interface. Oxidative segregation may be partially responsible for this increase, but the difference between As and P profiles in this high photo-generation region of the device may be important.

[0117] To help make this point, the CV derived carrier concentration (CCCV) at 0-bias is used in conjunction with the SIMS incorporation profile to create a dopant activation depth profile (Fig 15). This assumes the same CC everywhere in the absorber and that only the intended dopant in contributing to CC. Nevertheless, the As doped device shows flat activation profile of ~1% dropping to 0.5% near the front interface. This is contrasted with the P doped device where the increase from 0.1% near the back of the device to a peak of -0.6% before dropping to less than 0.1% near the front interface. Low dopant activation ratios have been shown as a potentially large Voc loss mechanism and right now the lowest activation ratios seem correlated with the highest photogeneration region of the device.

[0118] It should now be understood that the embodiments provided herein, relate to the use of charge transport buffers to improve photovoltaic device efficiency and long term reliability. Specifically, charge transport buffers can preferentially passivate grain boundaries at the surface of polycrystalline absorbers to further reduce defects. Additionally, the charge transport buffers provided herein can restrict various form of transport along blocked grain boundaries.

[0119] According to the embodiments provided herein, a photovoltaic device can include a polycrystalline absorber layer, a second semiconductor layer, and a charge transport buffer. The polycrystalline absorber layer can include semiconductor grains arranged along grain boundaries within the polycrystalline absorber layer. Each of the semiconductor grains can include cadmium and tellurium and have an outer face. A surface layer portion of the outer face of each of the semiconductor grains can form a section of a surface of the polycrystalline absorber layer. The second semiconductor layer can be positioned over the polycrystallineabsorber layer. The charge transport buffer can be positioned between the surface of the polycrystalline absorber layer and the second semiconductor layer. A majority of the surface of the polycrystalline absorber layer can be offset from the second semiconductor layer by less than or equal to 5 nm.

[0120] According to the embodiments of the present disclosure, a method for forming a photovoltaic device can include contacting a surface of a polycrystalline absorber layer with a charge transport precursor. The polycrystalline absorber layer can include cadmium and tellurium. The charge transport precursor can include an organic solvent and a charge transport material. The charge transport precursor can include less than 10 grams of the charge transport material per liter of the organic solvent. The organic solvent can be removed from the charge transport precursor. The charge transport precursor can be deposited upon the surface of the polycrystalline absorber layer as a charge transport buffer.

[0121] In certain embodiments, the photovoltaic device has an efficiency equal to or greater than 23.1%. In some examples, the photovoltaic device has an efficiency in a range from 23% to 29.0%.

[0122] In some embodiments, a photovoltaic device can include a II- VI, thin film, polycrystalline absorber layer. The absorber layer can include cadmium, tellurium, and selenium. The absorber layer can have a front-side or first surface and a back or second surface. The absorber layer can include a front interface region at the first surface of the absorber layer. A thickness of the front interface region can comprise between 5% to 20% of the thickness of the absorber layer. The front interface region can have a thickness of between 10 nm to 450 nm. The absorber layer can be doped with at least one Group V dopant and a halogen. In an example, the halogen dopant can include chlorine and can optionally include one or more of: fluorine, bromine, or iodine. In some embodiments, the polycrystalline absorber layer is doped with phosphorus and arsenic. A dopant concentration in the front interface region can greater than in a bulk region of the absorber. In some embodiments, a dopant concentration is between about lxl016cm’3and about lxl022cm’3. The absorber layer can be p-type. In some embodiments, the polycrystalline absorber layer is doped with phosphorus and arsenic, and a ratio of phosphorus to arsenic in a bulk region of the absorber layer is greater than 1:10 and less than 10:1. In some examples, the ratio of phosphorus to arsenic in the bulk region is greater than 2:1, 3:1, or greater than 4:1.

[0123] In some embodiments, an average area density of the charge transport buffer over the absorber layer back surface is between 10 ng / cm and 2000 ng / cm. In some embodiments, the area density of the charge transport buffer is less than 1200 ng / cm, 1000ng / cm, 700 ng / cm, 500 ng / cm, 400 ng / cm, 300 ng / cm, 250 ng / cm, 200 ng / cm, or less than 180 ng / cm. In some embodiments, the charge transport buffer comprises a plurality of passivating regions; and the passivating regions have an average thickness greater than 4 nm and less than 100 nm. In some embodiments, the passivating regions have an average thickness less than 70nm, 60nm, 50nm, 40nm, 30nm, 25nm, 20nm, 15nm, or less than lOnm.

[0124] In some embodiments, a back contact layer is formed over the absorber layer and over the charge transport buffer. In some embodiments, the absorber layer is a first semiconductor layer and the back contact layer is a second semiconductor layer. In some embodiments, the charge transport buffer is noncontiguous and the back contact layer is adjacent to portions of the absorber layer back surface and to the charge transport buffer. In some embodiments, the passivating regions of the charge transport buffer cover less than 50% of the surface of the polycrystalline absorber layer. In some embodiments the passivating regions of the charge transport buffer cover between 10% to 40% of the absorber layer back surface. In some embodiments, the back contact layer comprises one or more of: zinc, cadmium, tellurium, nitrogen, or oxygen. In some embodiments, the back contact layer is transparent.

[0125] It is noted that the terms "substantially" and "about" may be utilized herein to represent the inherent degree of uncertainty that may be attributed to any quantitative comparison, value, measurement, or other representation. These terms are also utilized herein to represent the degree by which a quantitative representation may vary from a stated reference without resulting in a change in the basic function of the subject matter at issue.

[0126] While particular embodiments have been illustrated and described herein, it should be understood that various other changes and modifications may be made without departing from the spirit and scope of the claimed subject matter. Moreover, although various aspects of the claimed subject matter have been described herein, such aspects need not be utilized in combination. It is therefore intended that the appended claims cover all such changes and modifications that are within the scope of the claimed subject matter.

Claims

CLAIMSWhat is claimed is:

1. A photovoltaic device comprising a polycrystalline absorber layer, a second semiconductor layer, and a charge transport buffer, wherein: the polycrystalline absorber layer comprises semiconductor grains arranged along grain boundaries within the polycrystalline absorber layer; each of the semiconductor grains comprises cadmium and tellurium; each of the semiconductor grains has an outer face; a surface layer portion of the outer face of each of the semiconductor grains forms a section of a surface of the polycrystalline absorber layer; the second semiconductor layer is positioned over the polycrystalline absorber layer; the charge transport buffer positioned between the surface of the polycrystalline absorber layer and the second semiconductor layer; and a majority of the surface of the polycrystalline absorber layer, taken along a cross-section, is offset from the second semiconductor layer by less than or equal to 5 nm.

2. The photovoltaic device of claim 1, wherein: the charge transport buffer comprises a plurality of passivating regions; and the passivating regions have an average thickness greater than 5 nm and less than 100 nm.

3. The photovoltaic device of claim 2, wherein the passivating regions of the charge transport buffer can be provided directly over a majority of the grain boundaries that extend to the surface of the polycrystalline absorber layer.

4. The photovoltaic device of claim 3, wherein the passivating regions of the charge transport buffer plug the majority of the grain boundaries that extend to the surface of the polycrystalline absorber layer.

5. The photovoltaic device of claim 2, wherein the passivating regions of the charge transport buffer are adjacent to both the surface of the polycrystalline absorber layer and the second semiconductor layer.

6. The photovoltaic device of claim 2, wherein the passivating regions of the charge transport buffer cover less than 45% of the surface of the poly crystalline absorber layer.

7. The photovoltaic device of claim 1, wherein: the charge transport buffer comprises a plurality of non-blocking; and the non-blocking regions have a thickness less than 5nm.

8. The photovoltaic device of claim 7, wherein passages are formed through the nonblocking regions of the charge transport buffer.

9. The photovoltaic device of claim 7, wherein crystal lattices of the polycrystalline absorber layer and the second semiconductor layer are aligned at the non-blocking regions of the charge transport buffer.

10. The photovoltaic device of claim 1, wherein the charge transport buffer is p-type and is formed from a p-type material capable of being dissolved in a solvent.

11. The photovoltaic device of claim 10, wherein the p-type material is a polymer, a small molecule, or an inorganic compound.

12. The photovoltaic device of claim 11, wherein the p-type material is PTAA, P3HT, or PEDOT:PSS.

13. The photovoltaic device of claim 1, wherein the charge transport buffer consists essentially of p-type PTAA.

14. The photovoltaic device of claim 1, wherein the second semiconductor layer is a back contact layer comprising a chemical compound of materials from groups I, II, and / or VI.

15. The photovoltaic device of claim 14, wherein the back contact layer comprises zinc telluride doped with nitrogen.

16. The photovoltaic device of claim 14, comprising a transparent conducting layer overthe back contact layer.

17. The photovoltaic device of claim 1, wherein the polycrystalline absorber layer comprises cadmium and tellurium.

18. The photovoltaic device of claim 17, wherein the polycrystalline absorber layer comprises selenium.

19. The photovoltaic device of claim 17, wherein the polycrystalline absorber layer comprises a Group V dopant with an atomic concentration of greater than lxlO17cm-3.

20. The photovoltaic device of claim 18, wherein the polycrystalline absorber layer comprises at least two Group V dopants, and wherein the Group V dopants include phosphorus and arsenic.

21. The photovoltaic device of claim 20, wherein the polycrystalline absorber layer comprises a halogen dopant.

22. A method for forming a photovoltaic device, comprising: contacting a surface of a polycrystalline absorber layer with a charge transport precursor, wherein: the polycrystalline absorber layer comprises cadmium and tellurium; the charge transport precursor comprises an organic solvent and a charge transport material; and the charge transport precursor comprises less than 10 mg of the charge transport material per mL of the organic solvent; and removing the organic solvent from the charge transport precursor, whereby the charge transport precursor is deposited upon the surface of the polycrystalline absorber layer as a charge transport buffer.

23. The method of claim 22, wherein: the charge transport buffer the charge transport buffer comprises a plurality of passivating regions and a plurality of non-blocking regions; the passivating regions have an average thickness greater than 5nm and less than 100 nm;the non-blocking regions have a thickness of less than 5nm; and the passivating regions of the charge transport buffer cover less than 45% of the surface of the polycrystalline absorber layer.

24. The method of claim 22, comprising: subjecting the polycrystalline absorber layer to a chloride heat treatment before the surface of the polycrystalline absorber layer is contacted with the charge transport precursor.

25. The method of claim 22, wherein the surface of the polycrystalline absorber layer is contacted with the charge transport precursor via roll coating or spray coating.

26. The method of claim 22, wherein the organic solvent is removed from the charge transport precursor by processing the charge transport precursor at a temperature between 50° C and 250° C for less than 5 minutes.

27. The method of claim 22, wherein the organic solvent comprises an aromatic liquid organic solvent.

28. The method of claim 22, wherein the charge transport material is provided in the charge transport precursor as a suspension or a solution dissolved in the organic solvent of the charge transport precursor.

29. The method of claim 22, wherein the charge transport material is p-type and is a polymer, a small molecule, or an inorganic compound.

30. The method of claim 29, wherein the p-type material is PTAA, P3HT, or PEDOT:PSS.

31. The method of claim 22, wherein the charge transport buffer consists essentially of p- type PTAA.

32. The method of claim 22, comprising: depositing a back contact layer over the charge transport buffer , wherein the back contact layer comprises a chemical compound of materials from groups I, II, or VI.

33. The method of claim 32, wherein the back contact layer comprises zinc telluride doped with nitrogen.

34. The method of claim 22 or claim 23, comprising: subjecting the polycrystalline absorber layer to a chloride heat treatment before the surface of the polycrystalline absorber layer is contacted with the charge transport precursor.

35. The method of any one of claims 22, 23, or 34, wherein the surface of the polycrystalline absorber layer is contacted with the charge transport precursor via roll coating or spray coating.

36. The method of any one of claims 22, 23, or 34-35, wherein the organic solvent is removed from the charge transport precursor by processing the charge transport precursor at a temperature between 50° C and 250° C for less than 5 minutes.

37. The method of any one of claims 22, 23, or 34-36, wherein the organic solvent comprises an aromatic liquid organic solvent.

38. The method of any one of claims 22, 23, or 34-37, wherein the charge transport material is provided in the charge transport precursor as a suspension or a solution dissolved in the organic solvent of the charge transport precursor.

39. The method of any one of claims 22, 23, or 34-38, wherein the charge transport material is p-type and is a polymer, a small molecule, or an inorganic compound.

40. The method of claim 39, wherein the p-type material is PTAA, P3HT, or PEDOT:PSS.

41. The method of any one of claims 22, 23, or 34-38, wherein the charge transport buffer consists essentially of p-type PTAA.

42. The method of any one of claims 22, 23, or 34-41, comprising: depositing a back contact layer over the charge transport buffer, wherein the back contact layer comprises a chemical compound of materials from groups I, II, or VI.

43. The method of claim 42, wherein the back contact layer comprises zinc telluride doped with nitrogen.

44. The method of any one of claims 22, 23, or 34-43, wherein the charge transport precursor comprises between 0.01 mg and 8 mg of the charge transport material per mL of the organic solvent.

45. The method of any one of claims 22, 23, or 34-43, wherein the charge transport precursor comprises between 0.05 mg and 6 mg of the charge transport material per mL of the organic solvent.

46. The method of any one of claims 22, 23, or 34-43, wherein the charge transport precursor comprises between 0.1 mg and 3 mg of the charge transport material per mL of the organic solvent.

47. A photovoltaic device comprising a polycrystalline absorber layer, a second semiconductor layer, and a charge transport buffer, wherein: the polycrystalline absorber layer comprises semiconductor grains arranged along grain boundaries within the polycrystalline absorber layer; each of the semiconductor grains comprises cadmium and tellurium; each of the semiconductor grains has an outer face; a surface layer portion of the outer face of each of the semiconductor grains forms a section of a surface of the polycrystalline absorber layer; the second semiconductor layer is positioned over the polycrystalline absorber layer; the charge transport buffer positioned between the surface of the polycrystalline absorber layer and the second semiconductor layer; and a majority of the surface of the polycrystalline absorber layer is offset from the second semiconductor layer by less than or equal to 5 nm.

48. The photovoltaic device of claim 47, wherein the offset is measured along a crosssection.

49. The photovoltaic device of claim 47 or 48, wherein: the charge transport buffer comprises a plurality of passivating regions; andthe passivating regions have an average thickness greater than 5nm and less than 100 nm.

50. The photovoltaic device of claim 47, or method of any one of claims 22, 23, or 34-43, wherein the passivating regions have an average thickness greater than 5nm and less than 60 nm.

51. The photovoltaic device of claim 47, or method of any one of claims 21, or 32 to 41, wherein the passivating regions have an average thickness greater than 5nm and less than 45 nm.

52. The photovoltaic device of claim 47, or method of any one of claims 21, or 32 to 41, wherein the passivating regions have an average thickness greater than 5nm and less than 25 nm.

53. The photovoltaic device of any one of claims 45 to 50, or method of any one of claims 21, 32 to 41, or 48 to 51, wherein the passivating regions of the charge transport buffer can be provided directly over a majority of the grain boundaries that extend to the surface of the polycrystalline absorber layer.

54. The photovoltaic device or method of claim 51, wherein the passivating regions of the charge transport buffer plug the majority of the grain boundaries that extend to the surface of the polycrystalline absorber layer.

55. The photovoltaic device of any one of claims 47 to 54, wherein the passivating regions of the charge transport buffer are adjacent to both the surface of the polycrystalline absorber layer and the second semiconductor layer.

56. The photovoltaic device of any one of claims 47 to 55, or the method of any one of claims 21, 32 to 41, or 48 to 51, wherein the passivating regions of the charge transport buffer cover less than 45% of the surface of the polycrystalline absorber layer.

57. The photovoltaic device of any one of claims 47 to 54, or method of any one of claims 21, 32 to 41, or 48 to 51, wherein the passivating regions of the charge transport buffer cover less than 40% of the surface of the polycrystalline absorber layer.

58. The photovoltaic device of any one of claims 47 to 54 or method of any one of claims 21, 32 to 41, or 48 to 51, wherein the passivating regions of the charge transport buffer cover between 2% and 35% of the surface of the polycrystalline absorber layer.

59. The photovoltaic device of any one of claims 47 to 58, wherein: the charge transport buffer comprises a plurality of non-blocking; and the non-blocking regions have a thickness less than 5nm.

60. The photovoltaic device of claim 59, wherein passages are formed through the nonblocking regions of the charge transport buffer.

61. The photovoltaic device of claim 59 or 60, wherein crystal lattices of the polycrystalline absorber layer and the second semiconductor layer are aligned at the non-blocking regions of the charge transport buffer.

62. The photovoltaic device of any one of claims 47 to 61, wherein the charge transport buffer is p-type and is formed from a p-type material capable of being dissolved in a solvent.

63. The photovoltaic device of claim 62, wherein the p-type material is a polymer, a small molecule, or an inorganic compound.

64. The photovoltaic device of claim 63, wherein the p-type material is PTAA, P3HT, or PEDOT:PSS.

65. The photovoltaic device of any one of claims 47 to 64, wherein the charge transport buffer consists essentially of p-type PTAA.

66. The photovoltaic device of any one of claims 47 to 65, wherein the second semiconductor layer is a back contact layer comprising a chemical compound of materials from groups I, II, or VI.

67. The photovoltaic device of claim 66, wherein the back contact layer comprises zinc telluride doped with nitrogen.

68. The photovoltaic device of any one of claims 66 to 67, comprising a transparent conducting layer over the back contact layer.

69. The photovoltaic device of any one of claims 47 to 68, wherein the polycrystalline absorber layer comprises cadmium and tellurium.

70. The photovoltaic device of any one of claims 47 to 69, wherein the polycrystalline absorber layer comprises selenium.

71. The photovoltaic device of any one of claims 47 to 70, wherein the polycrystalline absorber layer comprises a Group V dopant with an atomic concentration of greater than lxlO17cm-3in a bulk region of the absorber layer72. The photovoltaic device of any one of claims 47 to 71, wherein the polycrystalline absorber layer comprises at least two Group V dopants, and wherein the Group V dopants include phosphorus and arsenic.

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