Gate-bonded transistors and methods of forming gate-bonded transistors
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- MONDE WIRELESS INC
- Filing Date
- 2025-12-12
- Publication Date
- 2026-06-18
AI Technical Summary
III-V semiconductor devices face thermal management challenges due to high power densities, leading to elevated operating temperatures and performance degradation, especially when using substrates like sapphire with lower thermal conductivity.
A semiconductor device configuration where a lateral transistor is bonded to a base substrate with integrated thermal management features, including compliant thermal interface materials and dual-sided gate structures, enhancing heat dissipation through thermocompression bonding and heat sinks.
Improves thermal conductivity and mechanical robustness, reducing self-heating effects and maintaining electrical performance, while minimizing parasitic impedances and costs associated with conventional III-V integrated circuits.
Smart Images

Figure US2025059412_18062026_PF_FP_ABST