Gate-bonded transistors and methods of forming gate-bonded transistors

WO2026128818A2PCT designated stage Publication Date: 2026-06-18MONDE WIRELESS INC

Patent Information

Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
MONDE WIRELESS INC
Filing Date
2025-12-12
Publication Date
2026-06-18

AI Technical Summary

Technical Problem

III-V semiconductor devices face thermal management challenges due to high power densities, leading to elevated operating temperatures and performance degradation, especially when using substrates like sapphire with lower thermal conductivity.

Method used

A semiconductor device configuration where a lateral transistor is bonded to a base substrate with integrated thermal management features, including compliant thermal interface materials and dual-sided gate structures, enhancing heat dissipation through thermocompression bonding and heat sinks.

🎯Benefits of technology

Improves thermal conductivity and mechanical robustness, reducing self-heating effects and maintaining electrical performance, while minimizing parasitic impedances and costs associated with conventional III-V integrated circuits.

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Abstract

High power semiconductor devices generate power dissipation, which may cause overheating that ultimately degrade the device. Mitigating the heat at the packaging level can allow for more reliable applications of fast switching devices. Increasing thermal routes of power dissipated energy protects the active device region from damage. In addition, the packaging configuration disclosed herein may improve mechanical, electrical, and thermal robustness for high-frequency devices comprising a III-N material. These favorable properties may result from structures related to heat convection in a given device. Flip chip configurations in accordance with the present disclosure may also improve the manufacturing process of III-N device structures. The devices and systems may enable generated thermal energy to escape efficiently.
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