Back-contact cell with specific passivated light-receiving surface, and preparation method therefor and use thereof

Abstract

The present disclosure belongs to the technical field of back-contact cells, and particularly relates to a back-contact cell with a specific passivated light-receiving surface, and a preparation method therefor and the use thereof. The back-contact cell comprises a substrate, and the substrate is provided with a shady surface and a light-receiving surface. The light-receiving surface of the substrate is sequentially provided with a first tunneling oxide layer, a doped amorphous silicon layer and a silicon medium anti-reflection layer, wherein the thickness of the first tunneling oxide layer is 0.2-1.5 nm, the doped amorphous silicon layer is doped with oxygen and hydrogen, and the first tunneling oxide layer is doped with hydrogen, with the hydrogen content of the side of the first tunneling oxide layer close to the doped amorphous silicon layer being greater than that of the side thereof close to the substrate. The present disclosure can balance a relatively good passivation effect and optical loss, and has the function of enhanced passivation, thereby improving the passivation effect and current of a cell, such that the cell efficiency is increased, and the equipment cost is low.

Description

A back contact battery with passivated light-receiving surface, its preparation method and application

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 2024118661286, filed on December 18, 2024, entitled “A Back Contact Battery with Passivated Specific Light-Receiving Surface and Its Preparation Method and Application”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure belongs to the field of back contact battery technology, specifically relating to a back contact battery with a passivated light-receiving surface, its preparation method, and its application. Background Technology

[0004] Existing back-contact solar cells include a first semiconductor layer and a second semiconductor layer alternately disposed on the back side of a silicon substrate, and a light-receiving passivation layer and an anti-reflection layer sequentially disposed on the light-receiving surface of the silicon substrate. The light-receiving passivation layer is generally an amorphous silicon passivation layer, a tunneling polycrystalline passivation layer, or a stacked passivation layer of aluminum oxide and silicon nitride. In the fabrication process, the first semiconductor layer and the second semiconductor layer are first formed sequentially on the back side, and then the light-receiving passivation layer and the anti-reflection layer are formed on the light-receiving surface.

[0005] However, the existing composition of the passivation layer on the light-receiving surface in the aforementioned back contact battery has the following drawbacks:

[0006] ① When the passivation layer on the light-receiving surface is an amorphous silicon passivation layer, intrinsic amorphous silicon is required as the passivation contact layer, in conjunction with N-type amorphous silicon, to meet the passivation performance requirements. Furthermore, it is formed using plate-type PECVD, which is expensive, significantly increasing equipment costs. Additionally, the intrinsic amorphous silicon and N-type doped amorphous silicon layers have relatively small band gaps, resulting in high light absorption and thus severely impacting the battery's short-circuit current.

[0007] ② When the passivation layer of the light-receiving surface is a tunneling polycrystalline passivation layer, the preparation process of the polycrystalline silicon layer is relatively complicated. It needs to be deposited and then diffused through high-temperature annealing. Moreover, polycrystalline silicon has a large absorption capacity. When used as a passivation layer of the light-receiving surface, it affects the absorption of sunlight, thereby affecting the battery current.

[0008] ③ When the passivation layer of the light-receiving surface is a stacked passivation layer of aluminum oxide and silicon nitride, aluminum oxide and silicon nitride need to be coated by two separate machines, which increases the equipment cost.

[0009] In existing bifacial heterojunction solar cells, the two semiconductors and their two electrodes are respectively positioned as the light-receiving side and the back side of the cell. The light-receiving side utilizes a doped amorphous silicon layer. However, in this bifacial structure, the passivation film on the light-receiving side needs to consider the conductivity, light transmittance, and carrier extraction performance of the light-receiving side. Bifacial heterojunction solar cells and back-contact solar cells belong to two different battery systems. In back-contact solar cells, the passivation film on the light-receiving side does not need to consider conductivity or carrier extraction performance; it requires higher light transmittance and better passivation performance. In other words, different battery systems have different requirements for the passivation film on the light-receiving side and face different problems. Moreover, in bifacial heterojunction solar cells, ITO is used as a conductivity-antireflection layer on the light-receiving side, serving only a conductivity-antireflection function. In contrast, existing technologies using a simple N-type doped amorphous silicon layer (i.e., only phosphorus doped) on the light-receiving side of back-contact solar cells lead to a significant decrease in passivation, requiring further improvement.

[0010] It should be noted that this part of the disclosure only provides background technology related to this disclosure, and does not necessarily constitute prior art or publicly known technology. Summary of the Invention

[0011] The purpose of this disclosure is to overcome the shortcomings of low short-circuit current and high equipment cost of the passivation layer on the light-receiving surface of the existing back contact battery. It provides a back contact battery with specific passivation on the light-receiving surface, its preparation method and application, which can balance good passivation effect and optical loss, play a role in enhancing passivation, thereby improving the passivation effect and current of the battery, and thus improving the battery efficiency, while having low equipment cost.

[0012] To achieve the above objectives, in a first aspect, this disclosure provides a back contact battery with a specific passivated light-receiving surface, including a substrate. The substrate has a back light-receiving surface and a light-receiving surface. The light-receiving surface of the substrate is sequentially provided with a first tunneling oxide layer, a doped amorphous silicon layer, and a silicon dielectric antireflection layer. The thickness of the first tunneling oxide layer is 0.2-1.5 nm. The doped amorphous silicon layer is doped with oxygen and hydrogen. The first tunneling oxide layer is doped with hydrogen. The hydrogen content in the first tunneling oxide layer near the doped amorphous silicon layer is greater than the hydrogen content near the substrate.

[0013] Optionally, the hydrogen content of the doped amorphous silicon layer is greater than the arithmetic average of the hydrogen content in the first tunneling oxide layer.

[0014] Optionally, the oxygen content of the doped amorphous silicon layer is 5-60 at.% based on the total amount of doped amorphous silicon.

[0015] Optionally, the hydrogen content of the doped amorphous silicon layer is 1-35 at.% based on the total amount of doped amorphous silicon.

[0016] Optionally, the first tunneling oxide layer has a hydrogen content of 1-20 at.% based on the total elemental content of the first tunneling oxide layer.

[0017] Optionally, the oxygen content of the first tunneling oxide layer near the doped amorphous silicon side is less than the oxygen content near the substrate side.

[0018] Optionally, the oxygen content in the first tunneling oxide layer is 55-68 at.%.

[0019] Optionally, the silicon dielectric antireflection layer is doped with hydrogen.

[0020] Optionally, the hydrogen content of the silicon dielectric antireflection layer is less than or equal to the hydrogen content of the doped amorphous silicon layer.

[0021] Optionally, the hydrogen content of the silicon dielectric antireflection layer is greater than or equal to the arithmetic mean of the hydrogen content in the first tunneling oxide layer.

[0022] Optionally, the silicon dielectric antireflection layer has a hydrogen content of 1-25 at.% based on the total elemental composition of the silicon dielectric antireflection layer.

[0023] Optionally, the doped amorphous silicon layer also contains phosphorus and / or carbon elements, with the carbon content being 0-20 at.% and the phosphorus content being 0-0.5 at.% based on the total amount of the doped amorphous silicon layer.

[0024] Optionally, the phosphorus content in the doped amorphous silicon layer is 0.1-0.3 at.%.

[0025] Optionally, the bandgap of the doped amorphous silicon layer is between 1.9 and 6 eV, and the refractive index of the doped amorphous silicon layer at a wavelength of 600 nm is between 2 and 3.7.

[0026] Optionally, the atomic percentage ratio R of silicon and oxygen in the doped amorphous silicon layer satisfies: 1 < R ≤ 2.2.

[0027] Alternatively, 1.5 ≤ R ≤ 2.2.

[0028] Optionally, the substrate is a monocrystalline silicon substrate.

[0029] Optionally, the doped amorphous silicon layer is a single-layer structure.

[0030] Optionally, the doped amorphous silicon layer is a single-layer or multi-layer structure, and in the case of a multi-layer structure, the corresponding bandgap width gradually increases in a gradient in the thickness direction from the light-receiving surface outward.

[0031] Optionally, in the multilayer structure, the ratio of the bandgap width of any layer to the adjacent layer that is relatively far from the light-receiving surface is 1:1.02-5 and the ratio of their thicknesses is 1:0.2-10, preferably the ratio of the bandgap width is 1:1.1-5 and the ratio of their thicknesses is 1:0.5-10.

[0032] Optionally, the thickness of the doped amorphous silicon layer is 3-40 nm.

[0033] Optionally, the silicon dielectric antireflection layer is at least one of silicon nitride, silicon oxynitride, and silicon oxide.

[0034] Optionally, the thickness of the silicon dielectric antireflection layer is 50-120 nm.

[0035] Optionally, the backlight surface is provided with a film layer including a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is a stack including a second tunneling oxide layer and a first doped polysilicon layer or a stack including a first intrinsic silicon layer and a first doped silicon layer. The second semiconductor layer includes a second intrinsic silicon layer and a second doped silicon layer.

[0036] Optionally, the first semiconductor layer includes a second tunneling oxide layer and a first doped polycrystalline silicon layer, the second semiconductor layer includes a second intrinsic silicon layer and a second doped silicon layer, and the thickness ratio of the doped amorphous silicon layer to the second tunneling oxide layer is 2-30:1.

[0037] Optionally, the first semiconductor layer includes a second tunneling oxide layer and a first doped polycrystalline silicon layer, wherein the thickness ratio of the first tunneling oxide layer, the doped amorphous silicon layer and the second tunneling oxide layer is 0.1-1:2-30:1.

[0038] Optionally, the two ends of the second semiconductor layer extend outward to cover the back side of the adjacent first semiconductor layer, and a second opening region that does not cover the second semiconductor layer is formed on the back side of the first semiconductor layer. A first opening region is formed between adjacent first semiconductor layers. The first opening region and the second opening region are arranged alternately, and the area between them is a gap region. In the gap region, a mask layer is provided between the first semiconductor layer and the second semiconductor layer or no mask layer is provided. The back contact battery also includes a metal electrode and a conductive film layer laid on the outer surface of the first semiconductor layer and the second semiconductor layer. An isolation groove is formed on the portion of the conductive film layer located in the gap region. The metal electrode is disposed on the outer surface of the corresponding conductive film layer of the first opening region and the second opening region.

[0039] Secondly, this disclosure provides a method for preparing a back contact battery with a specific passivated light-receiving surface, comprising the following steps:

[0040] A substrate is provided, the substrate having a backlight side and a light-receiving side;

[0041] A first tunneling oxide layer, a doped amorphous silicon layer, and a silicon dielectric antireflection layer are sequentially formed on the light-receiving surface of the substrate. The doped amorphous silicon layer is doped with oxygen and hydrogen, and the first tunneling oxide layer is doped with hydrogen. The hydrogen content in the first tunneling oxide layer near the doped amorphous silicon layer is greater than the hydrogen content near the substrate.

[0042] Optionally, the first tunneling oxide layer, the doped amorphous silicon layer, and the silicon dielectric antireflection layer are deposited in one step using tubular PECVD at a deposition temperature of 350-600℃.

[0043] Optionally, the fabrication method further includes forming a first semiconductor layer and a second semiconductor layer on the back surface of a silicon substrate.

[0044] Optionally, the first semiconductor layer is obtained by deposition followed by annealing at a temperature of 800-950°C.

[0045] Optionally, the deposition temperature of the second semiconductor layer is 150-250°C.

[0046] Optionally, the preparation method specifically includes the following steps:

[0047] S101 provides a double-sided polished silicon substrate;

[0048] S102, A first semiconductor layer and a mask layer are sequentially formed on the back side of a silicon substrate;

[0049] S103. The first etching opening is performed on the back side obtained in S102 to form the first opening area;

[0050] S104. Then, texturing and cleaning are performed to form a textured surface on the light-receiving surface of the silicon substrate and the first opening area. After that, it is optional to perform a step of cleaning to remove the mask layer outside the first opening area on the back side of the silicon substrate.

[0051] S105. A first tunneling oxide layer, a doped amorphous silicon layer, and a silicon dielectric antireflection layer are sequentially deposited on the light-receiving surface of a silicon substrate. The thickness of the first tunneling oxide layer is 0.2-1.5 nm. The first tunneling oxide layer is doped with hydrogen, and the hydrogen content in the first tunneling oxide layer near the doped amorphous silicon layer is controlled to be greater than the hydrogen content near the substrate. The doped amorphous silicon layer is doped with oxygen and hydrogen.

[0052] S106. Deposit a second semiconductor layer on the back side obtained in S105.

[0053] Optionally, the formation conditions of the first tunneling oxide layer include: introducing an oxygen-containing gas at a pressure of 0.5e2Pa-1e5Pa, and maintaining the temperature at a set process temperature for 1-30 minutes.

[0054] Optionally, the deposition conditions of the doped amorphous silicon layer include: a process pressure of 100-500 Pa, a power of 2-15 kW, and the introduction of a process gas containing silane and the required dopant element.

[0055] Optionally, the deposition conditions of the silicon dielectric antireflection layer include: a process pressure of 100-500 Pa and a power of 5-20 kW.

[0056] Optionally, the hydrogen content in the first tunneling oxide layer near the doped amorphous silicon layer is controlled to be greater than the hydrogen content near the substrate, which can be achieved by at least one of the following methods:

[0057] Method 1: During the deposition of the doped amorphous silicon layer, hydrogen gas is introduced at a flow rate of 0.5-30 slm.

[0058] Method 2, the preparation method also includes: after depositing the doped amorphous silicon layer, hydrogen treatment is performed. The conditions for hydrogen treatment include: hydrogen gas is introduced, the hydrogen flow rate is 0.5-30 slm, the treatment temperature is 350-600℃, and the treatment time is 1-15 min.

[0059] Method 3: During the deposition of the silicon dielectric antireflection layer, hydrogen gas is introduced at a flow rate of 0.5-30 slm.

[0060] Optionally, the method for fabricating the back contact battery with the specific light-receiving surface passivated further includes:

[0061] S107. A second etch opening is made on a portion of the second semiconductor layer on the back side of the silicon substrate to form a second opening region that is spaced apart from the first opening region.

[0062] S108. Deposit a conductive film layer on the back side obtained in S107;

[0063] S109. A third etching opening is performed on a portion of the conductive film layer located between the second opening region and the first opening region to form an isolation trench.

[0064] S110, metal electrodes are formed on the outer surfaces of the corresponding conductive film layers in the regions where the second opening region and the first opening region are located, respectively.

[0065] Thirdly, this disclosure provides a back contact battery with a specific light-receiving surface passivation, which is prepared by the method for preparing a back contact battery with a specific light-receiving surface passivation described in the second aspect.

[0066] Fourthly, this disclosure provides a photovoltaic module, which includes a back contact cell with a specific light-receiving surface passivated as described in the first aspect, or a back contact cell with a specific light-receiving surface passivated as described in the third aspect. Beneficial effects:

[0067] This disclosure, through the aforementioned technical solution, particularly the use of a first tunneling oxide layer, a doped amorphous silicon layer, and a silicon dielectric antireflection layer with appropriate doping amounts on the light-receiving surface, allows for the adjustment and control of the doped amorphous silicon layer to have a suitable high bandgap, resulting in low light absorption and improved short-circuit current. Furthermore, the appropriate amount of hydrogen doping enhances the passivation effect. The simultaneous and appropriate doping of oxygen and hydrogen synergistically adjusts the refractive index of the doped amorphous silicon layer within a suitable range, achieving a good passivation effect and minimizing optical loss. The silicon dielectric antireflection layer further enhances passivation. Additionally, controlling the hydrogen content in the first tunneling oxide layer to be greater near the doped amorphous silicon layer than near the substrate better passivates dangling bonds in the amorphous silicon, reducing defects in the amorphous silicon layer and thus improving the battery passivation effect and current, ultimately increasing battery efficiency.

[0068] Furthermore, the doped amorphous silicon layer and silicon dielectric antireflection layer can be deposited in a single high-temperature process using tubular PECVD (deposition temperature 350-550℃), replacing the low-temperature (approximately 200℃) deposition of amorphous silicon and antireflection layers using plate-type PECVD. This significantly reduces equipment costs. Additionally, the doped amorphous silicon layer can increase its bandgap by doping with oxygen and hydrogen, thereby reducing light absorption. In contrast, conventional HBC cells, when formed at low temperatures, have a bandgap of only about 1.7 eV for amorphous silicon, resulting in high light absorption and hindering the improvement of short-circuit current.

[0069] In the preferred embodiment of this disclosure, a light-receiving surface passivation structure containing a doped amorphous silicon layer is adopted in the joint passivation structure. Since the back-side joint passivation structure does not require high-temperature sintering (in conventional HBC cells, the first semiconductor on the back side will fail severely after deposition of the front film layer at 350-550℃; in TBC cells, high-temperature sintering at 800℃ is required when forming the metal electrode), and the light transmittance of the specific film layer on the light-receiving surface is higher, the doped amorphous silicon layer does not need to be doped with a high concentration of phosphorus (i.e., the phosphorus content in the doped amorphous silicon layer is 0-0.5 at.%), better passivation effect and higher short-circuit current can be obtained. Moreover, when configured as a joint passivation structure, the formation temperatures of the first semiconductor layer (maximum annealing temperature 800-950℃), the light-receiving surface film layer (deposition temperature 350-550℃), and the second semiconductor layer (deposition temperature 150-250℃) show a step-decreasing trend, which is more conducive to passivation retention. The formation temperatures of the second semiconductor layer and the passivation layer (amorphous silicon layer deposited at low temperature (approximately 200°C) by plate-type PECVD) in conventional joint passivation are relatively close. However, the formation temperature of the antireflection layer in the light-receiving film layer is higher than that of the second semiconductor layer and the passivation layer in the light-receiving film layer (generally 20-50°C higher). Furthermore, the antireflection layer needs to be formed after the passivation layer in the second semiconductor layer and the light-receiving film layer. Therefore, the passivation effect of the second semiconductor layer and the light-receiving film layer will be destroyed when the passivation layer in the light-receiving film layer is formed. Attached Figure Description

[0070] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this disclosure and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0071] Figure 1 is a schematic diagram of the structure of the double-sided polished silicon substrate of Embodiment 1 of this disclosure;

[0072] Figure 2 is a schematic diagram of the structure of the first semiconductor layer and mask layer formed on the back side in Embodiment 1 of this disclosure;

[0073] Figure 3 is a schematic diagram of the structure of the first opening area formed on the back side of Embodiment 1 of this disclosure;

[0074] Figure 4 is a schematic diagram of the structure after the back opening area and the light-receiving surface of Embodiment 1 of this disclosure are textured and the mask layer is removed.

[0075] Figure 5 is a schematic diagram of the structure of the first tunneling oxide layer, the doped amorphous silicon layer and the antireflection layer deposited on the light-receiving surface in Embodiment 1 of this disclosure.

[0076] Figure 6 is a schematic diagram of the structure in Embodiment 1 of this disclosure where a second semiconductor layer is formed on the back side;

[0077] Figure 7 is a schematic diagram of the structure of the second opening area formed on the back side in Embodiment 1 of this disclosure;

[0078] Figure 8 is a schematic diagram of the structure of the transparent conductive film layer deposited on the back side in Embodiment 1 of this disclosure;

[0079] Figure 9 is a schematic diagram of the structure of the isolation groove formed on the back side in Embodiment 1 of this disclosure;

[0080] Figure 10 is a schematic diagram of the structure of the back-printed metal electrode of Embodiment 1 of this disclosure.

[0081] Figure 11 shows the variation spectrum of each film layer on the light-receiving surface of the silicon substrate in Embodiment 1 of this disclosure, obtained by time-of-flight secondary ion mass spectrometry analysis at different film layer thicknesses. The horizontal axis represents the film layer thickness (nm) on the light-receiving surface towards the silicon wafer, and the left vertical axis represents the absolute doping concentration, in cm. -3 The right vertical axis represents the relative doping concentration in c / s, and each vertical axis represents the doping concentration in Log10. The films corresponding to layers A to D are, in order, a silicon substrate, a first tunneling oxide layer, a doped amorphous silicon layer, and an antireflection layer.

[0082] The attached figures are labeled as follows: 1. Silicon substrate; 2. Second tunneling oxide layer; 3. First doped polycrystalline silicon layer; 4. Mask layer; 5. First opening region W1; 6. Second opening region W2; 7. First tunneling oxide layer; 8. Doped amorphous silicon layer; 9. Anti-reflection layer; 10. Intrinsic amorphous silicon layer; 11. Second doped amorphous silicon layer; 2. Transparent conductive film layer; 3. Isolation trench W3; 4. Metal electrode. Detailed Implementation

[0083] In this disclosure, unless otherwise stated, directional terms such as "up," "down," "left," and "right" are generally used to refer to the orientation as shown in the accompanying drawings and in practical applications.

[0084] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise expressly specified.

[0085] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0086] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges. For numerical ranges, the endpoint values ​​of the ranges, the endpoint values ​​of the ranges and individual point values, and individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein. The terms "optional" and "discretionary" mean that they may or may not be included (or may or may not be present).

[0087] In this disclosure, the area closer to the silicon substrate is defined as the inside, and the area farther from the silicon substrate is defined as the outside.

[0088] To achieve the above objectives, in a first aspect, this disclosure provides a back contact battery with a specific passivated light-receiving surface, including a substrate. The substrate has a back light-receiving surface and a light-receiving surface. The light-receiving surface of the substrate is sequentially provided with a first tunneling oxide layer, a doped amorphous silicon layer, and a silicon dielectric antireflection layer. The thickness of the first tunneling oxide layer is 0.2-1.5 nm. The doped amorphous silicon layer is doped with oxygen and hydrogen. The first tunneling oxide layer is doped with hydrogen. The hydrogen content in the first tunneling oxide layer near the doped amorphous silicon layer is greater than the hydrogen content near the substrate.

[0089] The thickness of the first tunneling oxide layer is 0.2-1.5 nm, specifically 0.2 nm, 0.3 nm, 0.5 nm, 0.8 nm, 0.9 nm, 1.0 nm, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, etc., or any range between two values, preferably 0.3-1.5 nm. Using a thinner first tunneling oxide layer is beneficial for improving battery current.

[0090] Optionally, the hydrogen content of the doped amorphous silicon layer is greater than the arithmetic average of the hydrogen content in the first tunneling oxide layer, which is more conducive to improving the passivation effect of the substrate's light-receiving surface.

[0091] In this disclosure, the arithmetic mean of hydrogen content in the first tunneling oxide layer refers to the arithmetic mean of the maximum and minimum hydrogen content in the first tunneling oxide layer, which is equal to 1 / 2 of the maximum and minimum hydrogen content in the first tunneling oxide layer.

[0092] Optionally, the oxygen content of the doped amorphous silicon layer is 5-60 at.% based on the total amount of doped amorphous silicon. Doping the amorphous silicon layer with an appropriate amount of oxygen is more conducive to reducing light absorption on the light-receiving surface of the battery, thereby increasing the battery current.

[0093] Optionally, the hydrogen content of the doped amorphous silicon layer is 1-35 at.% based on the total amount of doped amorphous silicon. Doping the amorphous silicon layer with an appropriate amount of hydrogen is more conducive to improving the passivation effect of the light-receiving surface of the substrate.

[0094] Optionally, the first tunneling oxide layer has a hydrogen content of 1-20 at.%, more preferably 1-15 at.%, based on the total elemental content of the first tunneling oxide layer. Doping the first tunneling oxide layer with an appropriate amount of hydrogen is more conducive to improving the passivation effect of the light-receiving surface of the substrate.

[0095] In this disclosure, the atomic percentage content of each element in the corresponding membrane layer is obtained by SIMS (time-of-flight secondary ion mass spectrometry).

[0096] Optionally, the oxygen content of the first tunneling oxide layer near the doped amorphous silicon side is lower than the oxygen content near the substrate side. This preferred embodiment reduces defects in the first tunneling oxide layer and amorphous silicon, thus improving the passivation effect on the light-receiving surface of the substrate.

[0097] Optionally, the oxygen content in the first tunneling oxide layer is 55-68 at.%.

[0098] Optionally, the silicon dielectric antireflection layer is doped with hydrogen, which further improves the passivation effect of the substrate's light-receiving surface.

[0099] Optionally, the hydrogen content of the silicon dielectric antireflection layer is less than or equal to the hydrogen content of the doped amorphous silicon layer, which is more conducive to improving the passivation effect of the substrate's light-receiving surface.

[0100] Optionally, the hydrogen content of the silicon dielectric antireflection layer is greater than or equal to the arithmetic mean of the hydrogen content in the first tunneling oxide layer, which is more conducive to improving the passivation effect of the substrate light-receiving surface.

[0101] Optionally, the silicon dielectric antireflection layer has a hydrogen content of 1-25 at.%, based on the total amount of elements in the silicon dielectric antireflection layer, which is more conducive to improving the passivation effect of the substrate's light-receiving surface.

[0102] Optionally, the doped amorphous silicon layer further comprises phosphorus and / or carbon. More preferably, the carbon content is 0-20 at.% and the phosphorus content is 0-0.5 at.% based on the total amount of the doped amorphous silicon layer.

[0103] The phosphorus content is 0-0.5 at.%, specifically 0, 0.05 at.%, 0.1 at.%, 0.15 at.%, 0.2 at.%, 0.25 at.%, 0.3 at.%, 0.35 at.%, 0.4 at.%, 0.45 at.%, 0.5 at.%, etc., as well as the range between any two point values.

[0104] Optionally, the phosphorus content in the doped amorphous silicon layer is 0.1-0.5 at.%, more preferably 0.1-0.3 at.%, which is more conducive to improving the field passivation of the substrate.

[0105] In some preferred embodiments of this disclosure, the doped amorphous silicon layer is not doped with phosphorus, which is beneficial for increasing the bandgap of amorphous silicon and thus for increasing battery current.

[0106] Optionally, the bandgap of the doped amorphous silicon layer is 1.9-6 eV, preferably 3.0-6 eV, and the refractive index of the doped amorphous silicon layer at a wavelength of 600 nm is between 2 and 3.7. The doped amorphous silicon layer has suitable bandgap and refractive index, which is more conducive to reducing light absorption and improving anti-reflection and anti-reflection effects, thereby further improving the battery current.

[0107] The bandgap of the doped amorphous silicon layer is between 1.9 and 6 eV, specifically 1.9 eV, 2.0 eV, 2.1 eV, 2.2 eV, 2.3 eV, 2.5 eV, 2.8 eV, 3.0 eV, 3.3 eV, 3.5 eV, 3.7 eV, 4.0 eV, 4.2 eV, 4.5 eV, 4.8 eV, 5.0 eV, 5.2 eV, 5.5 eV, 5.7 eV, 6.0 eV, and any range between any two values.

[0108] The refractive index of the doped amorphous silicon layer at a wavelength of 600 nm is between 2 and 3.7. For example, the refractive index at a wavelength of 600 nm can be 2.0, 2.2, 2.5, 2.7, 2.9, 3.0, 3.3, 3.5, 3.6, 3.7, etc., as well as any range between two points.

[0109] Optionally, the atomic percentage ratio R of silicon and oxygen in the doped amorphous silicon layer satisfies: 1 < R ≤ 2.2. This preferred scheme enables the formation of silicon suboxide, which is more conducive to increasing the bandgap of the doped amorphous silicon layer, reducing the absorption of amorphous silicon, and thus increasing the battery current.

[0110] Optionally, 1.5≤R≤2.2 is more conducive to increasing the bandgap of the doped amorphous silicon layer, reducing the absorption of amorphous silicon, and thus increasing the battery current.

[0111] Optionally, the substrate is a silicon substrate. The silicon substrate can be N-type or P-type.

[0112] Optionally, the substrate is a monocrystalline silicon substrate, which is more conducive to improving battery efficiency than a polycrystalline silicon substrate.

[0113] Optionally, the doped amorphous silicon layer is a single-layer structure.

[0114] Optionally, the doped amorphous silicon layer is a multilayer structure with two or more layers, which is more conducive to improving the passivation effect and short-circuit current of the battery.

[0115] Optionally, in the multilayer structure, the corresponding bandgap gradually increases in a gradient along the thickness direction from the light-receiving surface outwards. Using a multilayer structure with a gradually increasing bandgap as the doped amorphous silicon layer is more conducive to optical matching and improves battery current.

[0116] Optionally, the ratio of the bandgap width of any layer in the multilayer structure to that of the adjacent layer that is relatively far from the light-receiving surface is 1:1-5, which is more conducive to optical matching and improves battery current.

[0117] Optionally, the thickness ratio of any layer in the multilayer structure to the thickness of the adjacent layer that is relatively far from the light-receiving surface is 1:0.5-10, preferably 1:1.5-10, and even more preferably 1:2.0-10, which is more conducive to optical matching and improves battery current.

[0118] Optionally, the thickness of the doped amorphous silicon layer is 3-40 nm, specifically 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 10 nm, 12 nm, 15 nm, 17 nm, 20 nm, 23 nm, 25 nm, 27 nm, 30 nm, 32 nm, 35 nm, 38 nm, 40 nm, etc., as well as any range between two point values.

[0119] Optionally, the backlight surface is provided with a film layer including a first semiconductor layer and a second semiconductor layer.

[0120] Optionally, the first semiconductor layer is a stack comprising a second tunneling oxide layer and a first doped polycrystalline silicon layer, or a stack comprising a first intrinsic silicon layer and a first doped silicon layer, and the second semiconductor layer comprises a second intrinsic silicon layer and a second doped silicon layer. The second doped silicon layer may be, for example, second doped amorphous silicon or second doped microcrystalline silicon. The second intrinsic silicon layer is preferably intrinsic amorphous silicon.

[0121] Optionally, the first semiconductor layer includes a second tunneling oxide layer and a first doped polycrystalline silicon layer. By employing a combined passivation structure, in conjunction with a light-receiving surface passivation structure, the doped amorphous silicon layer does not require high concentrations of phosphorus doping to achieve better passivation performance. Furthermore, when configured as a combined passivation structure, the formation temperatures of the first semiconductor layer (maximum annealing temperature 800-950℃), the light-receiving surface layer (deposition temperature 350-550℃), and the second semiconductor layer (deposition temperature 150-250℃) exhibit a stepped decreasing trend, which is more conducive to maintaining passivation.

[0122] Optionally, the second semiconductor layer includes a second intrinsic silicon layer and a second doped silicon layer, wherein the thickness ratio of the doped amorphous silicon layer to the second tunneling oxide layer is 2-30:1, which is more conducive to improving the passivation effect and short-circuit current of the battery.

[0123] As will be understood in this disclosure, one of the first doped polysilicon layer and the second doped silicon layer is N-type and the other is P-type.

[0124] Optionally, when the first semiconductor layer includes a second tunneling oxide layer and a first doped polycrystalline silicon layer, the thickness ratio of the first tunneling oxide layer, the doped amorphous silicon layer and the second tunneling oxide layer is 0.1-1:2-30:1, and more preferably 0.2-0.8:2-20:1, which is more conducive to improving the passivation effect and short-circuit current of the battery.

[0125] Optionally, the thickness of the second tunneling oxide layer is 1-2 nm, and the thickness of the first doped polysilicon layer is 50-200 nm, with a corresponding dopant element content of 0.1-2 at.%.

[0126] Optionally, the thickness of the second intrinsic silicon layer is 4-12 nm, and the thickness of the second doped silicon layer is 7-14 nm, with a corresponding dopant element content of 0.05-1 at.%.

[0127] It is understandable that the corresponding doping elements mentioned above are phosphorus or boron.

[0128] Optionally, the silicon dielectric antireflection layer is at least one of silicon nitride, silicon oxynitride, and silicon oxide.

[0129] Optionally, the thickness of the silicon dielectric antireflection layer is 50-120 nm.

[0130] Optionally, the two ends of the second semiconductor layer extend outward to cover the back side of the adjacent first semiconductor layer, and a second opening region that does not cover the second semiconductor layer is opened on the back side of the first semiconductor layer. A first opening region is formed between adjacent first semiconductor layers. The first opening region and the second opening region are arranged alternately, and the area between them is a gap region.

[0131] Optionally, a mask layer may be provided or not provided between the first semiconductor layer and the second semiconductor layer within the spacing region.

[0132] Optionally, the back contact battery further includes a metal electrode and a conductive film layer deposited on the outer surfaces of the first semiconductor layer and the second semiconductor layer, wherein an isolation groove is formed on the portion of the conductive film layer located within the spacer region; the metal electrode is disposed on the outer surface of the corresponding conductive film layer in the first opening region and the second opening region.

[0133] Optionally, in this disclosure, a portion of the silicon substrate located at the first opening region is a textured surface, and a portion of the silicon substrate at the position corresponding to the first semiconductor layer is a polished surface.

[0134] Secondly, this disclosure provides a method for preparing a back contact battery with a specific passivated light-receiving surface, comprising the following steps:

[0135] A substrate is provided, the substrate having a backlight side and a light-receiving side;

[0136] A first tunneling oxide layer, a doped amorphous silicon layer, and a silicon dielectric antireflection layer are sequentially formed on the light-receiving surface of the substrate. The doped amorphous silicon layer is doped with oxygen and hydrogen, and the first tunneling oxide layer is doped with hydrogen. The hydrogen content in the first tunneling oxide layer near the doped amorphous silicon layer is greater than the hydrogen content near the substrate.

[0137] Optionally, the first tunneling oxide layer, the doped amorphous silicon layer, and the silicon dielectric antireflection layer are deposited in one step using tubular PECVD at a deposition temperature of 350-600℃.

[0138] Optionally, the fabrication method further includes forming a first semiconductor layer and a second semiconductor layer on the back surface of a silicon substrate.

[0139] Optionally, the first semiconductor layer is obtained by deposition followed by annealing at a temperature of 800-950°C.

[0140] Optionally, the deposition temperature of the second semiconductor layer is 150-250°C.

[0141] Optionally, the preparation method specifically includes the following steps:

[0142] S101 provides a double-sided polished silicon substrate;

[0143] S102, A first semiconductor layer and a mask layer are sequentially formed on the back side of a silicon substrate;

[0144] S103. The first etching opening is performed on the back side obtained in S102 to form the first opening area;

[0145] S104. Then, texturing and cleaning are performed to form a textured surface on the light-receiving surface of the silicon substrate and the first opening area. After that, it is optional to perform a step of cleaning to remove the mask layer outside the first opening area on the back side of the silicon substrate.

[0146] S105. A first tunneling oxide layer, a doped amorphous silicon layer, and a silicon dielectric antireflection layer are sequentially deposited on the light-receiving surface of a silicon substrate. The thickness of the first tunneling oxide layer is 0.2-1.5 nm. The first tunneling oxide layer is doped with hydrogen, and the hydrogen content in the first tunneling oxide layer near the doped amorphous silicon layer is controlled to be greater than the hydrogen content near the substrate. The doped amorphous silicon layer is doped with oxygen and hydrogen.

[0147] S106. Deposit a second semiconductor layer on the back side obtained in S105.

[0148] Optionally, the formation conditions of the first tunneling oxide layer include: introducing an oxygen-containing gas at a pressure of 0.5e2Pa-1e5Pa, and maintaining the temperature at a set process temperature for 1-30 minutes. The oxygen-containing gas may include, for example, oxygen, nitrous oxide, etc.

[0149] Optionally, the deposition conditions for the doped amorphous silicon layer include: a process pressure of 100-500 Pa, a power of 2-15 kW, and the introduction of a process gas containing silane and the desired dopant element. Using appropriate process pressure and power is more conducive to improving the film quality of the doped amorphous silicon, thereby improving the passivation effect of the battery.

[0150] During the deposition of the doped amorphous silicon layer, a process gas containing silane and the required dopant element gas source is introduced. The required dopant element gas source refers to an oxygen-doped gas source (such as oxygen, nitrous oxide, etc.), a carbon-doped gas source (such as methane, carbon dioxide, etc.), a phosphorus-doped gas source (such as phosphine, etc.), or a hydrogen-doped gas source (such as hydrogen, etc.). The corresponding dopant element gas source can be selected according to the required dopant element.

[0151] This disclosure discloses hydrogen doping of amorphous silicon layers via the following methods: ① silane decomposition; ② hydrogen implantation during subsequent film deposition; ③ adding a hydrogen treatment step after depositing the doped amorphous silicon layer; ④ introducing hydrogen gas simultaneously with silane. In this disclosure, at least one of the above methods can be selected to achieve the desired hydrogen doping concentration, as long as the target doping concentration can be obtained.

[0152] In this disclosure, the flow rate of the corresponding dopant gas source can be adjusted according to the target doping amount required. Optionally, the flow rate of silane is 1-10 slm, the flow rate of nitrous oxide is 1-10 slm, and the flow rate of methane is 2-30 slm. More preferably, phosphine is introduced in the form of a hydrogen-diluted mixed gas, with the flow rate of the hydrogen-diluted phosphine (hydrogen flow rate ratio of 90%-99%) being 1-10 slm. The deposition time is until the target film thickness is achieved.

[0153] Optionally, the deposition conditions of the silicon dielectric antireflection layer include: a process pressure of 100-500 Pa and a power of 5-20 kW. During the deposition of the silicon dielectric antireflection layer, a desired target gas can be introduced, as long as the target film layer can be obtained. For example, a process gas containing silane, ammonia, hydrogen, or nitrous oxide can be introduced.

[0154] Optionally, in this disclosure, controlling the hydrogen content in the first tunneling oxide layer to be greater on the side near the doped amorphous silicon layer than on the side near the substrate can be achieved through at least one of the following methods:

[0155] Method 1: Hydrogen gas is introduced during the deposition of a doped amorphous silicon layer, and the hydrogen flow rate is 0.5-30 slm, more preferably 2-30 slm;

[0156] Method 2, the preparation method also includes: after depositing the doped amorphous silicon layer, hydrogen treatment is performed. The conditions for hydrogen treatment include: hydrogen gas is introduced, the hydrogen flow rate is 0.5-30 slm, the treatment temperature is 350-600℃, and the treatment time is 1-15 min.

[0157] Method 3: During the deposition of the silicon dielectric antireflection layer, hydrogen gas is introduced at a flow rate of 0.5-30 slm. Correspondingly, controlling the oxygen content of the first tunneling oxide layer near the doped amorphous silicon side to be lower than the oxygen content near the substrate side can also be achieved by at least one of the above three methods, that is, by controlling the oxygen content to regulate the hydrogen content.

[0158] The formation of the first semiconductor layer, mask layer, and second semiconductor layer in this disclosure can refer to existing methods, as long as the required thickness and doping amount of the corresponding film layer can be obtained. For example, the corresponding doped silicon layer in the first semiconductor layer can be formed by in-situ doping deposition and annealing using tubular PECVD, LPCVD, or PVD, preferably by sequential deposition and high-temperature annealing in a tubular polycrystalline silicon deposition furnace; as long as the annealing temperature in these methods meets the range of this disclosure, they can be configured to achieve the effects of this disclosure, and will not be elaborated further here.

[0159] In this disclosure, the first tunneling oxide layer and the second tunneling oxide layer can be formed using any other existing method, such as LPCVD, tubular PECVD, or wet processing. Preferably, the first tunneling oxide layer, the doped amorphous silicon layer, and the silicon dielectric antireflection layer are all formed in a single step using a tubular PECVD apparatus.

[0160] The thickness of the mask layer can be, for example, 30-90 nm. The type of mask layer can be, for example, at least one of silicon nitride, silicon oxynitride, and silicon oxide.

[0161] In S104 of this disclosure, it is necessary to select whether to perform a step of cleaning and removing the mask layer outside the first opening area on the back side of the silicon substrate, for example, the mask layer can be completely removed or partially retained.

[0162] Optionally, the method for fabricating the back contact battery with the specific light-receiving surface passivated further includes:

[0163] S107. A second etch opening is made on a portion of the second semiconductor layer on the back side of the silicon substrate to form a second opening region that is spaced apart from the first opening region.

[0164] S108. Deposit a conductive film layer on the back side obtained in S107;

[0165] S109. A third etching opening is performed on a portion of the conductive film layer located between the second opening region and the first opening region to form an isolation trench.

[0166] S110, metal electrodes are formed on the outer surfaces of the corresponding conductive film layers in the regions where the second opening region and the first opening region are located, respectively.

[0167] Thirdly, this disclosure provides a back contact battery with a specific passivated light-receiving surface, which is prepared by the method for preparing a back contact battery with a specific passivated light-receiving surface described in the second aspect. The structure and performance of the back contact battery of the third aspect are the same as those of the back contact battery of the first aspect, and will not be repeated here.

[0168] Fourthly, this disclosure provides a photovoltaic module, which includes a back contact cell with a specific light-receiving surface passivated as described in the first aspect, or a back contact cell with a specific light-receiving surface passivated as described in the third aspect.

[0169] The embodiments of this disclosure described below are exemplary and are only used to explain this disclosure, and should not be construed as limiting this disclosure.

[0170] Example 1

[0171] The fabrication method of a back contact battery with a specific passivated light-receiving surface is as follows:

[0172] S101. As shown in Figure 1, a silicon substrate 1 (monocrystalline silicon) is provided, and the silicon substrate 1 is polished and cleaned in sequence.

[0173] S102, as shown in Figure 2, a first semiconductor layer and a mask layer 4 are sequentially formed on the back side of the silicon substrate 1. The first semiconductor layer includes a second tunneling oxide layer 2 and an N-type first doped polysilicon layer 3 sequentially formed on the back side. The thickness of the second tunneling oxide layer 2 is 1.5 nm, the thickness of the first doped polysilicon layer 3 is 100 nm, and the phosphorus content is 0.2 at.%. The first semiconductor layer is formed by LPCVD deposition followed by high-temperature diffusion annealing. The mask layer 4 is formed by tubular PECVD deposition furnace. The high-temperature diffusion annealing temperature is in the range of 800-880℃, and the highest high-temperature diffusion annealing temperature is 880℃. The thickness of the mask layer is 70 nm, and the mask layer is silicon nitride.

[0174] S103, as shown in Figure 3, the first semiconductor layer and its corresponding mask layer are etched open on the back side obtained in S102 to form a first opening region W1 with spaced distribution.

[0175] S104. As shown in Figure 4, a texturing surface is formed in the first opening area W1 on the back side and the light-receiving surface through texturing and cleaning, and then the mask layer 4 is completely removed.

[0176] S105, as shown in Figure 5, a first tunneling oxide layer 5, a doped amorphous silicon layer 6, and an antireflection layer 7 are sequentially formed on the light-receiving surface. The thickness of the first tunneling oxide layer 5 is 1 nm. The first tunneling oxide layer 5, the doped amorphous silicon layer 6, and the antireflection layer 7 are formed in one step using tubular PECVD at a deposition temperature of 460°C. The antireflection layer 7 is a silicon dielectric film silicon nitride with a thickness of 80 nm.

[0177] During the deposition of the doped amorphous silicon layer 6, the process pressure was 200 Pa, the power was 6 kW, the silane flow rate was 5 slm, the silane to nitrous oxide flow rate ratio was 3:2, and the hydrogen flow rate was 0.5 slm. This resulted in a 10 nm thick oxygen-doped amorphous silicon layer with a bandgap of 2.50 eV and a refractive index of 2.5 at a wavelength of 600 nm. The total oxygen content was 28 at.% and the hydrogen content was 22 at.%. The atomic percentage ratio of silicon to oxygen in the oxygen-doped amorphous silicon layer was R = 2.

[0178] The formation conditions of the first tunneling oxide layer 5 are as follows: oxygen is introduced at a flow rate of 2 slm and a pressure of 0.5e2Pa, and the temperature is kept constant for 10 minutes under the set process temperature conditions.

[0179] Deposition conditions for antireflection layer 7: 2 slm of silane, 14 slm of ammonia, and 5 slm of hydrogen were introduced; the process pressure was 200 Pa; the power was 10 kW; and the hydrogen content in antireflection layer 7 was 15 at.%.

[0180] S106, as shown in Figure 6, a second semiconductor layer is formed on the back side obtained in S105. The second semiconductor layer includes an intrinsic amorphous silicon layer 8 and a P-type second doped amorphous silicon layer 9 formed sequentially on the back side. The thickness of the intrinsic amorphous silicon layer 8 is 7 nm, the thickness of the second doped amorphous silicon layer 9 is 10 nm, and the boron content is 0.1 at.%. The second semiconductor layer is deposited using plate-type PECVD technology at a deposition temperature of 200 °C.

[0181] S107. As shown in Figure 7, a second etching opening is then made in the polished area on the back side obtained in S106 (i.e., the spacer area where the first semiconductor layer and the second semiconductor are superimposed) to expose the first semiconductor layer and form a second opening area W2 that is spaced apart from the first opening area W1.

[0182] S108. As shown in Figure 8, a transparent conductive film layer 10 is formed on the back side, covering the entire surface.

[0183] S109. As shown in Figure 9, a third etching opening is made in the transparent conductive film layer 10 on the back side, located between the second opening area W2 and the first opening area W1, to form an isolation trench W3.

[0184] S110, as shown in Figure 10, metal electrodes 11 are formed on the outer surfaces of the corresponding areas of the second opening region W2 and the first opening region W1 on the back side.

[0185] The obtained back-contact battery's silicon substrate light-receiving surface layers were analyzed by time-of-flight secondary ion mass spectrometry (TOF-MS / MS), and the spectra are shown in Figure 11. Figure 11 shows that the hydrogen content in the first tunneling oxide layer 5 near the doped amorphous silicon layer 6 is greater than the hydrogen content near the silicon substrate 1, and the oxygen content in the first tunneling oxide layer 5 near the doped amorphous silicon layer 6 is less than the oxygen content near the silicon substrate 1. The hydrogen content in the first tunneling oxide layer 5 is 5-15 at.% (corresponding to its minimum and maximum values, and the same applies to others), and the oxygen content is 55-66 at.%.

[0186] Example 2

[0187] The method described in Example 1 is followed, except that in S105, two oxygen-doped amorphous silicon layers with different bandgap widths are deposited. The silane flow rate remains constant. During the deposition of the first layer, the silane to nitrous oxide ratio is controlled to be 3:1. The first oxygen-doped amorphous silicon layer has a bandgap of 2.2 eV, a thickness of 3 nm, and a refractive index of 3.7 at a wavelength of 600 nm. During the deposition of the second layer, the silane to nitrous oxide ratio is 1:1. The second oxygen-doped amorphous silicon layer has a bandgap of 3.5 eV, a thickness of 7 nm, and a refractive index of 2.3 at a wavelength of 600 nm. The total oxygen content is 31 at.% and the hydrogen content is 21 at.%. Calculations show that the bandgap ratio of the first to the second oxygen-doped amorphous silicon layer is 1:1.59, and the thickness ratio is 1:2.3. The atomic percentages R of silicon and oxygen in the first and second layers of the oxygen-doped amorphous silicon layer are 2.2 and 1.8, respectively.

[0188] Example 3

[0189] The method of Example 2 is followed, except that the thickness of the second layer of the oxygen-doped amorphous silicon layer is adjusted to be the same as that of the first layer, but their respective band gaps remain unchanged, that is, the thickness ratio of the first layer to the second layer is 1:1. To meet this condition, the deposition time of the second amorphous layer is adjusted to a thickness of 3nm.

[0190] Example 4

[0191] The method is the same as in Example 2, except that no first oxygen-doped amorphous silicon layer is deposited in S105. That is, the doped amorphous silicon layer in S105 is a single layer: the second oxygen-doped amorphous silicon layer in Example 2 has a bandgap of 3.5 eV, a thickness of 10 nm, and a refractive index of 2.3 at a wavelength of 600 nm. To meet this condition, the deposition process parameters need to be adjusted as follows: the deposition time of the second amorphous layer is adjusted to a thickness of 10 nm.

[0192] Example 5

[0193] The method was carried out according to Example 1, except that the doped amorphous silicon layer in S105 was also doped with phosphorus. Correspondingly, hydrogen-diluted phosphine (98% hydrogen flow rate) was introduced during the deposition process, with a flow rate such that the ratio of silane:nitrous oxide:hydrogen-diluted phosphine mixed gas flow rate was 3:2:1. The resulting doped amorphous silicon layer had a band gap of 2.45 eV, a thickness of 10 nm, and a refractive index of 2.6 at a wavelength of 600 nm. The total oxygen content was 24 at.%, the hydrogen content was 26 at.%, and the phosphorus content was 0.2 at.%. The atomic percentage ratio of silicon to oxygen in the doped amorphous silicon layer was R = 1.9.

[0194] Example 6

[0195] The method was carried out according to Example 1, except that the doped amorphous silicon layer in S105 was also doped with carbon, and methane was introduced during the deposition process, with the methane flow rate such that the silane:methane flow rate ratio was 1:3. The resulting doped amorphous silicon layer had a band gap of 2.3 eV, a thickness of 10 nm, and a refractive index of 3.2 at a wavelength of 600 nm. The total oxygen content was 20 at.%, the hydrogen content was 20 at.%, and the carbon content was 10 at.%.

[0196] Example 7

[0197] The method was carried out according to Example 6, except that in S105, two carbon-doped amorphous silicon layers with different bandgap widths were deposited. Specifically, a second layer of doped amorphous silicon was deposited on the outer surface of the doped amorphous silicon layer in Example 6. During the deposition of the second layer, the methane flow rate was controlled so that the silane:methane flow rate ratio was 1:6. The resulting second layer of doped amorphous silicon had a bandgap width of 2.4 eV, a thickness of 2 nm, and a refractive index of 2.8 at a wavelength of 600 nm. The total amount of hydrogen in the two layers of doped amorphous silicon was 20 at.%, carbon 11 at.%, and oxygen 19 at.%. Calculations showed that the bandgap ratio of the first to the second layer of doped amorphous silicon was 1:1.04, and the thickness ratio was 1:0.2.

[0198] Example 8

[0199] The method is carried out in accordance with Example 7, except that the thickness of the second layer of the doped amorphous silicon layer is adjusted to be the same as the thickness of the first layer and the band gap remains unchanged, that is, the thickness ratio of the first layer to the second layer is 1:1. To meet this condition, the deposition time of the first and second amorphous layers needs to be adjusted so that the thickness of each layer is 5nm.

[0200] Example 9

[0201] The method is carried out in accordance with Example 1, except that in S105, the silicon content is adjusted so that the ratio of silicon to oxygen in the doped amorphous silicon layer in terms of atomic percentage R = 1.2. To meet this condition, the following adjustments are made during the deposition process: the silane flow rate is adjusted so that the ratio of silane to nitrous oxide is adjusted to 1:1.

[0202] Example 10

[0203] The method described in Example 1 was followed, except that the thickness of the first tunneling oxide layer was 1.5 nm, and the calculated thickness ratio of the first tunneling oxide layer to the second tunneling oxide layer was 1:1. To meet this condition, the process parameters to be adjusted were: oxygen was introduced at a pressure of 5e2 Pa, and correspondingly, the first tunneling oxide layer, based on the total elemental composition, had a hydrogen content of 7-20 at.% and an oxygen content of 57-68 at.%.

[0204] Example 11

[0205] The method was followed as in Example 1, except that hydrogen gas was not introduced during the deposition of the doped amorphous silicon layer. The resulting doped amorphous silicon layer had a bandgap of 2.45 eV and a refractive index of 2.7 at a wavelength of 600 nm. The atomic percentage ratio of silicon to oxygen in the doped amorphous silicon layer was R = 2.1. Accordingly, the hydrogen content near the doped amorphous silicon layer in the first tunneling oxide layer was greater than that near the silicon substrate, and the oxygen content near the doped amorphous silicon layer was less than that near the silicon substrate. The hydrogen content in the first tunneling oxide layer was 3-13 at.%, and the oxygen content was 57-67 at.%.

[0206] Example 12

[0207] The method was carried out according to Example 1, except that hydrogen gas was not introduced during the deposition of the doped amorphous silicon layer. Instead, hydrogen treatment was performed after the deposition of the doped amorphous silicon layer. The hydrogen treatment process was as follows: the hydrogen flow rate was 10 slm, the treatment temperature was 460°C, and the treatment time was 10 min. The oxygen-doped amorphous silicon layer had a band gap of 2.6 eV, constant thickness, and a refractive index of 2.45 at a wavelength of 600 nm. The total oxygen content was 29 at.% and the hydrogen content was 21 at.%.

[0208] The same test results show that the hydrogen content in the first tunneling oxide layer near the doped amorphous silicon layer is greater than that near the silicon substrate, and the oxygen content in the first tunneling oxide layer near the doped amorphous silicon layer is less than that near the silicon substrate.

[0209] Comparative Example 1

[0210] The method described in Example 1 is followed, except that the doped amorphous silicon layer is replaced with a conventional amorphous silicon film. Specifically, the conventional amorphous silicon film consists of: intrinsic amorphous silicon, N-type doped amorphous silicon (phosphorus-doped only, no oxygen-doped) deposited sequentially on the light-receiving surface, and no first tunneling oxide layer deposited. The thickness of the intrinsic amorphous silicon is 6 nm, the thickness of the N-type doped amorphous silicon is 10 nm, and the phosphorus content is 0.2 at.%. The band gap of the conventional amorphous silicon film is 1.75 eV, and the refractive index at a wavelength of 600 nm is 3.9.

[0211] Comparative Example 2

[0212] The method is the same as in Example 1, except that the doped amorphous silicon layer is replaced with a conventional light-receiving surface passivation film. Specifically, the conventional light-receiving surface passivation film is as follows: a first tunneling silicon oxide layer (same as in Example 1) and an N-type doped polycrystalline silicon layer (phosphorus-doped only, no oxygen-doped) are deposited sequentially on the light-receiving surface. The thickness of the N-type doped polycrystalline silicon is 5 nm, the phosphorus content is 0.2 at.%, the band gap of the N-type doped polycrystalline silicon is 1.25 eV, and the refractive index at a wavelength of 600 nm is 4.2.

[0213] Comparative Example 3

[0214] The method was carried out according to Example 1, except that the doped amorphous silicon layer was not doped with oxygen, but only with hydrogen (the hydrogen content was the same as in Example 1). The band gap of the doped amorphous silicon layer was 1.6 eV, and the refractive index at a wavelength of 600 nm was 4.1. To meet the condition of not being doped with oxygen, the following adjustments were made during the deposition process: the nitrous oxide flow rate was set to 0 during the deposition of amorphous silicon.

[0215] Comparative Example 4

[0216] The method was carried out according to Example 1, except that the hydrogen content in the first tunneling oxide layer near the doped amorphous silicon layer was equal to the hydrogen content near the substrate, while the oxygen content remained unchanged. To meet this condition, adjustments were made during the deposition process: no hydrogen gas was introduced during the deposition of the antireflection layer 7.

[0217] Test case

[0218] The back contact batteries obtained in the above embodiments and comparative examples were subjected to performance tests, and the results are shown in Table 1.

[0219] Table 1

[0220] The results above show that, compared with the comparative example, the embodiment of this disclosure can achieve a better passivation effect and optical loss, thereby enhancing the passivation effect, improving the battery passivation effect and current, and thus improving battery efficiency.

[0221] Furthermore, as can be seen from Embodiments 1 and 2-12, the preferred battery structure of this disclosure is more conducive to improving the passivation effect and current of the battery, thereby improving the battery efficiency.

[0222] The preferred embodiments of this disclosure have been described in detail above; however, this disclosure is not limited thereto. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, including combining the various technical features in any other suitable manner. These simple modifications and combinations should also be considered as the content disclosed in this disclosure and are all within the protection scope of this disclosure. Industrial applicability

[0223] This disclosure, through the aforementioned technical solution, particularly the use of a first tunneling oxide layer, a doped amorphous silicon layer, and a silicon dielectric antireflection layer with appropriate doping amounts on the light-receiving surface, allows for the adjustment and control of the doped amorphous silicon layer to have a suitable high bandgap, resulting in low light absorption and improved short-circuit current. Furthermore, the appropriate amount of hydrogen doping enhances the passivation effect. The simultaneous and appropriate doping of oxygen and hydrogen synergistically adjusts the refractive index of the doped amorphous silicon layer within a suitable range, achieving a good passivation effect and minimizing optical loss. The silicon dielectric antireflection layer further enhances passivation. Additionally, controlling the hydrogen content in the first tunneling oxide layer to be greater near the doped amorphous silicon layer than near the substrate better passivates dangling bonds in the amorphous silicon, reducing defects in the amorphous silicon layer and thus improving the battery passivation effect and current, ultimately increasing battery efficiency.

Claims

1. A back-contact battery with a specific passivated light-receiving surface, comprising a substrate having a back-light surface and a light-receiving surface, characterized in that, The light-receiving surface of the substrate is sequentially provided with a first tunneling oxide layer, a doped amorphous silicon layer, and a silicon dielectric antireflection layer. The thickness of the first tunneling oxide layer is 0.2-1.5 nm. The doped amorphous silicon layer is doped with oxygen and hydrogen elements, and the first tunneling oxide layer is doped with hydrogen elements. The hydrogen content in the first tunneling oxide layer near the doped amorphous silicon layer is greater than the hydrogen content near the substrate.

2. The back contact battery with passivated light-receiving surface according to claim 1, characterized in that, The hydrogen content of the doped amorphous silicon layer is greater than the arithmetic average of the hydrogen content in the first tunneling oxide layer.

3. The back contact battery with passivated light-receiving surface according to claim 1, characterized in that, The doped amorphous silicon layer has an oxygen content of 5-60 at.% based on the total amount of doped amorphous silicon.

4. The back contact battery with passivated light-receiving surface according to claim 1, characterized in that, The doped amorphous silicon layer has a hydrogen content of 1-35 at.% based on the total amount of doped amorphous silicon.

5. The back contact battery with passivated light-receiving surface according to claim 1, characterized in that, The first tunneling oxide layer has a hydrogen content of 1-20 at.% based on the total elemental composition of the first tunneling oxide layer.

6. The back contact battery with passivated light-receiving surface according to claim 1, characterized in that, The oxygen content of the first tunneling oxide layer near the doped amorphous silicon side is less than the oxygen content near the substrate side, and / or the oxygen content in the first tunneling oxide layer is between 55-68 at.%.

7. The back contact battery with passivated light-receiving surface according to claim 1, characterized in that, The silicon dielectric antireflection layer is doped with hydrogen.

8. The back contact battery with passivated light-receiving surface according to claim 7, characterized in that, The hydrogen content of the silicon dielectric antireflection layer is less than or equal to the hydrogen content of the doped amorphous silicon layer.

9. The back contact battery with passivated light-receiving surface according to claim 7, characterized in that, The hydrogen content of the silicon dielectric antireflection layer is greater than or equal to the arithmetic mean of the hydrogen content in the first tunneling oxide layer.

10. The back contact battery with passivated light-receiving surface according to claim 7, characterized in that, The silicon dielectric antireflection layer has a hydrogen content of 1-25 at.% based on the total elemental composition of the silicon dielectric antireflection layer.

11. The back contact battery with passivated light-receiving surface according to claim 1, characterized in that, The doped amorphous silicon layer also contains phosphorus and / or carbon elements, with the carbon content being 0-20 at.% and the phosphorus content being 0-0.5 at.% based on the total amount of the doped amorphous silicon layer.

12. The back contact battery with passivated light-receiving surface according to claim 11, characterized in that, The phosphorus content in the doped amorphous silicon layer is 0.1-0.3 at.%.

13. The back contact battery with passivated light-receiving surface according to any one of claims 1-12, characterized in that, The bandgap of the doped amorphous silicon layer is 1.9-6 eV, and the refractive index of the doped amorphous silicon layer at a wavelength of 600 nm is between 2 and 3.

7.

14. The back contact battery with passivated light-receiving surface according to any one of claims 1-12, characterized in that, The atomic percentage ratio R of silicon and oxygen in the doped amorphous silicon layer satisfies: 1 < R ≤ 2.

2.

15. The back contact battery with passivated light-receiving surface according to claim 14, characterized in that, 1.5≤R≤2.2。 16. The back contact battery with passivated light-receiving surface according to any one of claims 1-12, characterized in that, The substrate is a monocrystalline silicon substrate.

17. The back contact battery with passivated light-receiving surface according to any one of claims 1-12, characterized in that, The doped amorphous silicon layer is a single-layer structure.

18. The back contact battery with passivated light-receiving surface according to any one of claims 1-12, characterized in that, The doped amorphous silicon layer can be a single layer or a multilayer structure. In the case of a multilayer structure, the corresponding bandgap width gradually increases in a gradient from the light-receiving surface outwards in the thickness direction.

19. The back contact battery with passivated light-receiving surface according to claim 18, characterized in that, In a multilayer structure, the ratio of the bandgap width of any layer to the adjacent layer that is relatively far from the light-receiving surface is 1:1.1-5, and the ratio of their thicknesses is 1:0.5-10.

20. The back contact battery with passivated light-receiving surface according to any one of claims 1-12, characterized in that, The thickness of the doped amorphous silicon layer is 3-40 nm; and / or, The silicon dielectric antireflection layer is at least one of silicon nitride, silicon oxynitride, and silicon oxide, and the thickness of the silicon dielectric antireflection layer is 50-120 nm.

21. The back contact battery with passivated light-receiving surface according to any one of claims 1-12, characterized in that, The backlight surface is provided with a film layer including a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is a stack containing a second tunneling oxide layer and a first doped polysilicon layer or a stack containing a first intrinsic silicon layer and a first doped silicon layer. The second semiconductor layer includes a second intrinsic silicon layer and a second doped silicon layer.

22. The back contact battery with passivated light-receiving surface according to claim 21, characterized in that, The first semiconductor layer includes a second tunneling oxide layer and a first doped polycrystalline silicon layer, and the second semiconductor layer includes a second intrinsic silicon layer and a second doped silicon layer. The thickness ratio of the doped amorphous silicon layer to the second tunneling oxide layer is 2-30:

1.

23. The back contact battery with passivated light-receiving surface according to claim 21, characterized in that, The first semiconductor layer includes a second tunneling oxide layer and a first doped polycrystalline silicon layer, wherein the thickness ratio of the first tunneling oxide layer, the doped amorphous silicon layer and the second tunneling oxide layer is 0.1-1:2-30:

1.

24. The back contact battery with passivated light-receiving surface according to claim 21, characterized in that, The two ends of the second semiconductor layer extend outward to cover the back side of the adjacent first semiconductor layer, and a second opening region that does not cover the second semiconductor layer is formed on the back side of the first semiconductor layer. A first opening region is formed between adjacent first semiconductor layers. The first opening region and the second opening region are arranged alternately, and the area between them is a gap region. In the gap region, a mask layer is provided between the first semiconductor layer and the second semiconductor layer or no mask layer is provided. The back contact battery also includes a metal electrode and a conductive film layer laid on the outer surface of the first semiconductor layer and the second semiconductor layer. An isolation groove is formed on the portion of the conductive film layer located in the gap region. The metal electrode is disposed on the outer surface of the corresponding conductive film layer of the first opening region and the second opening region.

25. A method for preparing a back contact battery with passivated light-receiving surface, characterized in that, Includes the following steps: A substrate is provided, the substrate having a backlight side and a light-receiving side; A first tunneling oxide layer, a doped amorphous silicon layer, and a silicon dielectric antireflection layer are sequentially formed on the light-receiving surface of the substrate. The doped amorphous silicon layer is doped with oxygen and hydrogen, and the first tunneling oxide layer is doped with hydrogen. The hydrogen content in the first tunneling oxide layer near the doped amorphous silicon layer is greater than the hydrogen content near the substrate.

26. The method for preparing a back contact battery with passivated specific light-receiving surfaces as described in claim 25, characterized in that, The first tunneling oxide layer, the doped amorphous silicon layer, and the silicon dielectric antireflection layer are deposited in one step using tubular PECVD at a deposition temperature of 350-600℃.

27. The method for preparing a back contact battery with passivated specific light-receiving surfaces as described in claim 25, characterized in that, The fabrication method also includes forming a first semiconductor layer and a second semiconductor layer on the back surface of a silicon substrate.

28. The method for preparing a back contact battery with passivated specific light-receiving surfaces as described in claim 27, characterized in that, The first semiconductor layer is obtained by deposition followed by annealing at a temperature of 800-950℃.

29. The method for preparing a back contact battery with passivated specific light-receiving surfaces as described in claim 27, characterized in that, The deposition temperature of the second semiconductor layer is 150-250℃.

30. The method for preparing a back contact battery with passivated specific light-receiving surfaces as described in claim 27, characterized in that, The preparation method specifically includes the following steps: S101 provides a double-sided polished silicon substrate; S102, A first semiconductor layer and a mask layer are sequentially formed on the back side of a silicon substrate; S103. The first etching opening is performed on the back side obtained in S102 to form the first opening area; S104. Then, texturing and cleaning are performed to form a textured surface on the light-receiving surface of the silicon substrate and the first opening area. After that, it is optional to perform a step of cleaning to remove the mask layer outside the first opening area on the back side of the silicon substrate. S105. A first tunneling oxide layer, a doped amorphous silicon layer, and a silicon dielectric antireflection layer are sequentially deposited on the light-receiving surface of a silicon substrate. The thickness of the first tunneling oxide layer is 0.2-1.5 nm. The first tunneling oxide layer is doped with hydrogen, and the hydrogen content in the first tunneling oxide layer near the doped amorphous silicon layer is controlled to be greater than the hydrogen content near the substrate. The doped amorphous silicon layer is doped with oxygen and hydrogen. S106. Deposit a second semiconductor layer on the back side obtained in S105.

31. The method for preparing a back contact battery with passivated specific light-receiving surfaces according to claim 25 or 30, characterized in that, The formation conditions of the first tunneling oxide layer include: introducing an oxygen-containing gas at a pressure of 0.5e2Pa-1e5Pa, and maintaining the temperature at a set process temperature for 1-30 minutes; The deposition conditions for the doped amorphous silicon layer include: a process pressure of 100-500 Pa, a power of 2-15 kW, and the introduction of a process gas containing silane and the required dopant element. The deposition conditions for the silicon dielectric antireflection layer include: a process pressure of 100-500 Pa and a power of 5-20 kW.

32. The method for preparing a back contact battery with passivated specific light-receiving surfaces according to claim 25, characterized in that, The hydrogen content in the first tunneling oxide layer near the doped amorphous silicon layer is controlled to be greater than the hydrogen content near the substrate, which is achieved by at least one of the following methods: Method 1: During the deposition of the doped amorphous silicon layer, hydrogen gas is introduced at a flow rate of 0.5-30 slm. Method 2, the preparation method also includes: after depositing the doped amorphous silicon layer, hydrogen treatment is performed. The conditions for hydrogen treatment include: hydrogen gas is introduced, the hydrogen flow rate is 0.5-30 slm, the treatment temperature is 350-600℃, and the treatment time is 1-15 min. Method 3: During the deposition of the silicon dielectric antireflection layer, hydrogen gas is introduced at a flow rate of 0.5-30 slm.

33. The method for preparing a back contact battery with passivated specific light-receiving surfaces according to claim 30, characterized in that, The method for preparing the back contact battery with passivated specific light-receiving surfaces further includes: S107. A second etch opening is made on a portion of the second semiconductor layer on the back side of the silicon substrate to form a second opening region that is spaced apart from the first opening region. S108. Deposit a conductive film layer on the back side obtained in S107; S109. A third etching opening is made on a portion of the conductive film layer located between the second opening region and the first opening region to form an isolation trench. S110, metal electrodes are formed on the outer surfaces of the corresponding conductive film layers in the regions where the second opening region and the first opening region are located, respectively.

34. A back contact battery with a specific passivated light-receiving surface, characterized in that, It is prepared by the method of back contact battery with passivated light-receiving surface as described in any one of claims 25-33.

35. A photovoltaic module, characterized in that, It includes a back contact battery with a specific light-receiving surface passivated as described in any one of claims 1-24, or a back contact battery with a specific light-receiving surface passivated as described in claim 34.

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