Graphics processing method and system, computing device, and storage medium

Abstract

The present disclosure provides a graphics processing method and system, a computing device, and a storage medium. The system comprises at least two enabled graphics processing cores, and each graphics processing core comprises a vertex splitting module, a vertex processing pipeline module, a primitive processing pipeline module, and a pixel processing pipeline module. A vertex splitting module of a target graphics processing core is configured to determine, from vertex index data, a primitive packet to be processed by the target graphics processing core; a vertex processing pipeline module is configured to perform shading processing on a vertex corresponding to an index in the primitive packet to obtain a shading processing result; a primitive processing pipeline module is configured to acquire primitive composition information and perform geometry processing on the shading processing result on the basis of the primitive composition information to obtain a geometry processing result; and a pixel processing pipeline module is configured to process the geometry processing result to obtain a visual graph.

Description

Graphics processing methods and systems, computing devices and storage media

[0001] This application claims priority to Chinese Patent Application No. 202411885411.3, filed on December 19, 2024, entitled "Graphics Processing Method and System, Computing Device and Storage Medium", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of computer technology, and in particular to a graphics processing method and system, a computing device and storage medium, and a computer program product. Background Technology

[0003] In the field of computer science, graphics processing units (GPUs) are used to process various types of graphics data. The rendering pipeline is a key concept in computer graphics processing; it's a stage within the GPU responsible for processing and transforming graphics data. The main task of the rendering pipeline is to convert the geometric primitives (such as points, lines, and triangles) included in the input graphics data into pixels visible on the screen, thereby achieving the rendering of the graphics. Summary of the Invention

[0004] In view of this, the present disclosure provides a graphics processing method and system, a computing device and storage medium, and a computer program product.

[0005] According to a first aspect of this disclosure, a graphics processing system is provided, the graphics processing system comprising at least two enabled graphics processing cores, and each of the at least two enabled graphics processing cores comprising a vertex splitting module, a vertex processing pipeline module, a primitive processing pipeline module, and a pixel processing pipeline module; wherein the at least two enabled graphics processing cores include a target graphics processing core, and wherein the vertex splitting module of the target graphics processing core is configured to determine a primitive package to be processed by the target graphics processing core from vertex index data; the vertex processing pipeline module of the target graphics processing core is configured to process the primitives to be processed by the target graphics processing core. The vertices corresponding to the indices in the primitive package are shading processed to obtain the shading result. The primitive processing pipeline module of the target graphics processing core is configured to acquire primitive composition information and perform geometric processing on the shading result based on the primitive composition information to obtain the geometric processing result. The primitive composition information represents the primitive information of the vertices corresponding to the indices included in the primitive package. The primitive composition information is obtained by the vertex splitting module or the primitive processing pipeline module at least based on the primitive package to be processed by the target graphics processing core. The pixel processing pipeline module of the target graphics processing core is configured to process the geometric processing result to obtain the visualization graphics.

[0006] In some embodiments, the primitive package includes vertex index fragments and suffix vertex indices, wherein the vertex index data includes indices of vertices of a graph of a specified topology to be drawn, and the suffix vertex indices are indices that are consecutively located after the vertex index fragments in the vertex index data. The vertex index fragments included in the primitive package to be processed by the at least two enabled graphics processing cores all include the same predetermined number of vertex indices, and the number of suffix vertex indices depends on the specified topology.

[0007] In some embodiments, the vertex splitting module is further configured to parse the primitive packets to be processed by the target graphics processing core to obtain the primitive composition information, and transmit the primitive composition information to the primitive processing pipeline module.

[0008] In some embodiments, the vertex splitting module is further configured to parse the primitive packet to be processed by the target graphics processing core and the primitive packet consisting of vertex index data preceding the primitive packet to be processed by the target graphics processing core, in order to obtain the primitive composition information, and to transmit the primitive composition information to the primitive processing pipeline module.

[0009] In some embodiments, the vertex splitting module is further configured to transmit the primitive packet to be processed by the target graphics processing core to the primitive processing pipeline module, and the primitive processing pipeline module is configured to parse the primitive packet to be processed by the target graphics processing core to obtain the primitive composition information.

[0010] In some embodiments, the vertex splitting module is further configured to transmit a primitive packet to be processed by the target graphics processing core, and a primitive packet consisting of vertex index data preceding the primitive packet to be processed by the target graphics processing core, to a primitive processing pipeline module, and the primitive processing pipeline module is configured to parse the transmitted primitive packet to obtain the primitive composition information.

[0011] In some embodiments, the number of indices in the vertex index fragment is aligned with the bandwidth of the access interface of the memory where the geometry processing results are to be stored.

[0012] In some embodiments, the vertex splitting module of the target graphics processing core is further configured to: obtain a graphics drawing command, the graphics drawing command indicating that a graphics with a specified topology type should be drawn, the graphics drawing command including indication information for indicating that the graphics to be drawn do not have reset points; determine the number sequence corresponding to the indexes of a predetermined number of vertices to be processed by the target graphics processing core; and obtain vertex index fragments and suffix vertex indices to be processed by the target graphics processing core from the vertex index data according to the number sequence, so as to determine the primitive package to be processed by the target graphics processing core.

[0013] In some embodiments, the vertex splitting module of the target graphics processing core is further configured to: obtain a graphics drawing command, the graphics drawing command indicating that a graphics with a specified topology type should be drawn, the graphics drawing command including indication information for indicating that the graphics to be drawn have reset points; determine the number sequence corresponding to the indexes of a predetermined number of vertices to be processed by the target graphics processing core; obtain all vertex index data required for drawing the graphics; and determine the vertex index fragments and suffix vertex indices to be processed by the target graphics processing core from the obtained vertex index data according to the number sequence, so as to determine the primitive package to be processed by the target graphics processing core.

[0014] In some embodiments, the vertex splitting module of the target graphics processing core is further configured to: divide consecutive numbers into number sequences based on the number of vertex index segments, and number the obtained number sequences sequentially; determine the sequence number of the target graphics processing core among the at least two enabled graphics processing cores during the current graphics processing; and, in response to the remainder obtained by dividing the number of the obtained target number sequence by the number of the at least two enabled graphics processing cores being the same as the sequence number of the target graphics processing core, determine the target number sequence as the number sequence corresponding to the index of a predetermined number of vertices to be processed by the target graphics processing core.

[0015] In some embodiments, the vertex index data is pre-generated by the application that issues the graphics drawing command or generated by the vertex splitting module itself.

[0016] In some embodiments, the vertex splitting module of the target graphics processing core is further configured to determine the number of suffix vertex indices in the following ways: In response to the specified topology type being a point list, the number of suffix vertex indices is zero; in response to the specified topology type being a line list, loop line, or line strip, the number of suffix vertex indices is one; in response to the specified topology type being a triangle list, triangle strip, or triangle fan, the number of suffix vertex indices is two; in response to the specified topology type being a line list with adjacency information or a line strip with adjacency information, the number of suffix vertex indices is three; in response to the specified topology type being a triangle list with adjacency information, the number of suffix vertex indices is five; in response to the specified topology type being a triangle strip with adjacency information, the number of suffix vertex indices is seven; in response to the specified topology type being a control packet list with K points, the number of suffix vertex indices is K-1, where K is a positive integer.

[0017] According to a second aspect of this disclosure, a graphics processing method is provided, the method being executed by a target graphics processing core, the target graphics processing core being one of at least two enabled graphics processing cores included in a graphics processing system, each of the at least two enabled graphics processing cores including a vertex splitting module, a vertex processing pipeline module, a primitive processing pipeline module, and a pixel processing pipeline module; and the method comprising: using the vertex splitting module of the target graphics processing core to determine a primitive package to be processed by the target graphics processing core from vertex index data; and using the vertex processing pipeline module of the target graphics processing core to process the vertex indices in the primitive package to be processed by the target graphics processing core. The corresponding vertices are shading processed to obtain the shading result. Using the primitive processing pipeline module of the target graphics processing core, primitive composition information is obtained, and geometric processing is performed on the shading result based on the primitive composition information to obtain the geometric processing result. The primitive composition information represents the information of the vertex constituent primitives corresponding to the indices included in the primitive package to be processed by the target graphics processing core. The primitive composition information is obtained by the vertex splitting module or the primitive processing pipeline module at least based on the primitive package to be processed by the target graphics processing core through parsing. The pixel processing pipeline module of the target graphics processing core is then used to process the geometric processing result to obtain a visual graphic.

[0018] According to a third aspect of this disclosure, a computing device is provided, including a processor; and a memory configured to store computer-executable instructions thereon, which, when executed by the processor, perform any of the methods described above.

[0019] According to a fourth aspect of this disclosure, a computer-readable storage medium is provided that stores computer-executable instructions that, when executed, perform any of the methods described above.

[0020] According to a fifth aspect of this disclosure, a computer program product is provided, including computer-readable code or a non-volatile computer-readable storage medium carrying the computer-readable code, wherein when the computer-readable code is run in a processor of an electronic device, the processor in the electronic device performs any of the methods described above.

[0021] The graphics processing method and system claimed in this disclosure employ a decentralized parallel geometry processing pipeline, where vertex processing and primitive assembly can be processed in parallel, significantly expanding the data processing throughput of the geometry stage, improving the processing speed of the graphics processing system, achieving high-quality and high-resolution rendering in real time, and possessing good scalability. Users can easily add or remove (or dynamically configure as needed) the corresponding GPU units (e.g., enabled graphics processing cores) according to the usage scenario to meet the performance and power consumption requirements of different scenarios.

[0022] These and other advantages of this disclosure will become clear from the embodiments described below, and will be illustrated with reference to the embodiments described below. Attached Figure Description

[0023] Embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings, in which:

[0024] Figure 1 illustrates an exemplary architecture diagram of a graphics processing system according to an embodiment of the present disclosure;

[0025] Figure 2 shows an exemplary flowchart of a graphics processing method according to an embodiment of the present disclosure;

[0026] Figure 3 illustrates an exemplary flowchart of a method for determining a primitive package to be processed by a target graphics processing core based on vertex index data according to a specified topology type, according to an embodiment of the present disclosure.

[0027] Figure 4 illustrates an exemplary process for partitioning primitive packets according to an embodiment of the present disclosure;

[0028] Figures 5A, 5B, 5C, and 5D illustrate exemplary schematic diagrams of a partitioned primitive package according to an embodiment of the present disclosure;

[0029] Figure 6 illustrates an example system, which includes an example computing device representing one or more systems and / or devices that can implement the various technologies described herein. Detailed Implementation

[0030] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0031] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0032] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0033] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0034] It should be understood that while the terms first, second, third, etc., may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another. Therefore, the first component discussed below may be referred to as the second component without departing from the teachings of this disclosure. As used herein, the terms "and / or" and similar terms include all combinations of any, multiple, and all of the associated listed items.

[0035] Those skilled in the art will understand that the accompanying drawings are merely schematic diagrams of exemplary embodiments, and the modules or processes in the drawings are not necessarily necessary for implementing this disclosure, and therefore cannot be used to limit the scope of protection of this disclosure.

[0036] Before detailing the embodiments of this disclosure, some related concepts will be explained for clarity.

[0037] Geometric primitives, also known as graphic primitives, refer to the basic geometric shapes that make up a graphic, including points, lines, triangles, etc. For example, a graphic drawn by an application can be represented in the computer by a large number of triangles. After breaking down graphic data into corresponding basic geometric shapes, these basic geometric shapes can be used to determine the pixels of the drawn graphic.

[0038] Topology types: also known as primitive topology types, typically include point lists, line lists, triangle lists, line bands, triangle bands, line lists with adjacency information, triangle lists with adjacency information, line bands with adjacency information, triangle bands with adjacency information, loop lines, etc. The definitions of these topologies are the same as those in Microsoft DirectX 11.3.

[0039] As mentioned earlier, the GPU rendering pipeline is a key concept in computer graphics. It's a stage within the graphics processing unit (GPU) responsible for processing and transforming graphics data for rendering. The primary task of the rendering pipeline is to convert input geometric primitives (such as points, lines, triangles, etc.) into pixels visible on the screen. The goal of the rendering pipeline is to process graphics efficiently and generate the final image. Through parallel processing and specialized hardware support, the GPU can perform these calculations rapidly to achieve real-time graphics rendering.

[0040] In related technologies, the rendering pipeline can generally be divided into two parts: the geometry processing part (also known as the geometry pipeline) and the pixel processing part (also known as the fragment pipeline).

[0041] The geometry processing section includes the vertex input stage, vertex shading stage, primitive assembly stage, geometry shading stage, clipping stage, and screen mapping stage. The geometry pipeline primarily focuses on the processing and transformation of geometric data. It receives input geometric primitives (such as points, lines, triangles, etc.) and, after a series of stages, transforms them into geometric processing results mapped to pixel coordinates in screen space. The geometry processing section is responsible for performing geometric calculations such as model transformation, view transformation, and projection transformation, as well as generating new geometric primitives and changing their shape, size, and position.

[0042] The pixel processing section generally includes the rasterization stage, the fragment shading stage, and the pixel manipulation stage. The fragment pipeline focuses on pixel-level processing. It receives the pixels on the screen generated by the rasterization stage and processes each pixel through a series of stages. The pixel processing section is responsible for performing pixel-level lighting calculations, texture sampling, depth testing, and other operations to determine the final color and attributes of each pixel.

[0043] Specifically, the vertex input phase passes vertex data from the application to the geometry pipeline. Vertex data includes attributes such as position, color, and normals. In the vertex shading phase, the vertex shader calculates for each input vertex and can perform various transformations and operations, such as model transformations, view transformations, and projection transformations. It can also calculate vertex lighting and texture coordinates. In the primitive assembly phase, the primitive assembler converts vertices into complete geometric primitives, such as points, line segments, and triangles. In the geometry shading phase, the geometry shader can manipulate and generate geometric primitives. It can create new primitives and change their shape, size, and position. In the clipping phase, the clipper compares primitives to the screen boundary and discards portions outside the view volume. The screen mapping phase maps the clipped primitives to pixel coordinates in screen space. The rasterization phase converts the transformed geometry into pixels on the screen and determines the position, color, and other attributes of each pixel. In the fragment shading phase, the fragment shader calculates for each rasterized pixel, performing pixel-level lighting calculations, texture sampling, depth testing, and other operations. Pixel operations are used to perform final pixel processing, such as blending, dithering, and anti-aliasing.

[0044] It should be noted that these two pipelines are consecutive stages in the rendering pipeline; they are interdependent and work closely together to ultimately generate a visualized image. The geometry pipeline transforms geometric data into geometric processing results corresponding to pixel coordinates, while the fragment pipeline performs final processing and computation on the geometric processing results and the corresponding pixel data. Through parallel processing and dedicated hardware support, the GPU can efficiently execute these pipeline stages to achieve real-time graphics rendering.

[0045] With the development of GPUs, there is an urgent need to improve GPU throughput to increase processing speed and achieve high-quality, high-resolution rendering in real time. However, this poses a significant challenge to the data processing capabilities of current conventional GPUs. This disclosure proposes a graphics processing method and system for deferred primitive assembly, enabling parallel processing of vertex processing and primitive assembly, significantly expanding the data processing throughput of the geometry stage, thereby improving GPU speed. The following sections will illustrate in detail how to implement this graphics processing method and system using several embodiments.

[0046] Figure 1 illustrates an exemplary architecture diagram of a graphics processing system 100 according to an embodiment of the present disclosure. As shown in Figure 1, the graphics processing system includes multiple graphics processing cores, of which three are shown: 110, 120, and 130. Two or more of the multiple graphics processing cores can be enabled as needed; for example, graphics processing cores 110 and 120 can be enabled while 130 is disabled. Here, "enable" means "start" or "activate". Each graphics processing core may include a vertex splitting module, a vertex processing pipeline module, a primitive processing pipeline module, and a pixel processing pipeline module. As shown in Figure 1, graphics processing core 110 includes a vertex splitting module 111, a vertex processing pipeline module 112, a primitive processing pipeline module 113, and a pixel processing pipeline module 114. Graphics processing core 120 includes a vertex splitting module 121, a vertex processing pipeline module 122, a primitive processing pipeline module 123, and a pixel processing pipeline module 124. The graphics processing core 130 includes a vertex splitting module 131, a vertex processing pipeline module 132, a primitive processing pipeline module 133, and a pixel processing pipeline module 134.

[0047] For each enabled graphics processing core, taking graphics processing core 110 as an example, the vertex splitting module 111 can be configured to determine the primitive package to be processed by the target graphics processing core from the vertex index data; the vertex processing pipeline module 112 can be configured to perform coloring processing on the vertices corresponding to the indices in the primitive package to be processed by the target graphics processing core to obtain the coloring processing result; the primitive processing pipeline module 113 can be configured to acquire primitive composition information and perform geometric processing on the coloring processing result based on the primitive composition information to obtain the geometric processing result, wherein the primitive composition information represents the information of the vertex constituent primitives corresponding to the indices included in the primitive package to be processed by the target graphics processing core, wherein the primitive composition information is obtained by the vertex splitting module or the primitive processing pipeline module at least based on the primitive package to be processed by the target graphics processing core; the pixel processing pipeline module 114 can be configured to process the geometric processing result to obtain the visualization graphics.

[0048] In this way, the graphics processing core 110 achieves parallel processing of vertex processing and primitive processing, which can make full use of the parallelism of vertex shading and primitive assembly in graphics processing, reduce processing time, and improve the system's geometric processing throughput.

[0049] The primitive package described herein may include vertex index fragments and suffix vertex indices, wherein the vertex index data includes indices of vertices of a graph of a specified topology to be drawn, and the suffix vertex indices are indices that are consecutively located after the vertex index fragments in the vertex index data. The vertex index fragments included in the primitive package to be processed by the at least two enabled graphics processing cores all include the same predetermined number of vertex indices, and the number of suffix vertex indices depends on the specified topology.

[0050] Optionally, the graphics processing system 100 may further include a system configuration module 140, which can be configured to generate configuration information and send the configuration information to the vertex splitting module of each graphics processing core for configuration. The configuration information may include the number of vertex indices included in each vertex index fragment, information indicating at least two enabled graphics processing cores among the plurality of graphics processing cores included in the graphics processing system, and the sequence numbers of the at least two enabled graphics processing cores in the current graphics processing process.

[0051] Optionally, the graphics processing system 100 may further include a system bus 150 and a storage unit 160. The graphics processing core can obtain the required data from the storage unit via the system bus, or store the generated data into the storage unit via the system bus. The system bus can be an on-chip bus or an on-chip bus. The storage unit can be SRAM (Static Random-Access Memory), DRAM (Dynamic Random-Access Memory), etc., and is not limited here. In some embodiments, the system bus 150 and the storage unit 160 may not be included in the graphics processing system and exist as independent components outside the graphics processing system.

[0052] In embodiments of this disclosure, the graphics processing system 100 can be implemented as a complete GPU system (i.e., GPU) as a chip module. Each graphics processing core can be implemented as a smaller module or chip unit as a GPU unit. A GPU system may have only one GPU unit, suitable for applications with low performance and low power consumption requirements, such as PDAs (Personal Digital Assistants) and automotive chips. A GPU system may also include multiple GPU units to provide solutions for high-performance applications. This disclosure does not limit the number of GPU units.

[0053] Chip modules are a novel integrated circuit design approach that breaks down a complex chip into multiple smaller modules or chip units, which are then combined to form a complete system-on-a-chip (SoC). Each smaller module typically contains a specific function or subsystem and can be designed, tested, and manufactured independently. These modules can be implemented using different manufacturing processes, technologies, or suppliers. Finally, these modules can be assembled in a single package to form a fully functional SoC.

[0054] As can be seen from the above, the graphics processing system disclosed herein adopts a decentralized parallel geometry processing pipeline, in which vertex processing and primitive assembly can be processed in parallel, which fully expands the data processing throughput of the geometry stage, improves the processing speed of the graphics processing system, realizes high-quality and high-resolution rendering in real time, and has good scalability. Users can easily add or reduce (or dynamically configure as needed) the corresponding GPU units (e.g., enabled graphics processing cores) according to the usage scenario to meet the performance and power consumption requirements of different scenarios.

[0055] To facilitate understanding of this solution, the technical details will be described in detail below using the enabled graphics processing core 110 as an example of the target graphics processing core. It should be noted that any enabled graphics processing core can serve as the target graphics processing core.

[0056] As described above, the vertex splitting module 111 can be configured to determine the primitive package to be processed by the target graphics processing core from the vertex index data. The vertex index data includes indexes of the vertices of the graphic to be drawn. The vertices described herein are represented by the vertex data as described above; therefore, the vertex index data can also be understood as an index of the vertex data. The vertex index data can be in the form of numbers or letters, for example, without limitation. Numerical numbers are, for example, 0, 1, 2, etc., and letter numbers are, for example, A, B, C, etc. In some embodiments, the vertex index data required for drawing the graphic can be obtained from an index buffer memory, or the vertex index data required for drawing the graphic can be automatically generated.

[0057] In some embodiments, the primitive package includes vertex index fragments and suffix vertex indices, wherein the vertex index data includes indices of vertices of a graph of a specified topology to be drawn, and the suffix vertex indices are indices that are consecutively located after the vertex index fragments in the vertex index data. The vertex index fragments included in the primitive package to be processed by the at least two enabled graphics processing cores all include the same predetermined number of vertex indices, and the number of suffix vertex indices depends on the specified topology. In this embodiment, each primitive comprises two parts: a vertex index fragment and a suffix vertex index. The number of vertex indices included in the vertex index fragment of each primitive is the same and can be pre-specified.

[0058] As described above, the number of vertex indices included in each vertex index fragment (e.g., Z, where Z is a positive integer) can be pre-specified or configured by the system configuration module. That is, each vertex index fragment includes a fixed number of Z vertex indices, and these vertex index fragments are non-repeating and have no gaps (i.e., no skipped vertex indices). The number Z can optionally be aligned with the bandwidth of the access interface of the memory where the geometry processing results are to be stored. Vertex index fragments may not be sufficient to represent complete primitives; therefore, the vertex splitting module needs to add a certain number of suffix vertex indices to each vertex index fragment according to the topology type specified by the drawing instructions, so that the vertex index fragments, after adding the suffix vertex indices, can represent complete primitive information.

[0059] The number of suffix vertex indices depends on the specified topology type. In some embodiments, the vertex splitting module is further configured to determine the number of suffix vertex indices as follows: zero suffix vertex indices in response to the specified topology type being a point list; one suffix vertex indices in response to the specified topology type being a line list, loop line, or line strip; two suffix vertex indices in response to the specified topology type being a triangle list, triangle strip, or triangle fan; three suffix vertex indices in response to the specified topology type being a line list with adjacency information or a line strip with adjacency information; five suffix vertex indices in response to the specified topology type being a triangle list with adjacency information; seven suffix vertex indices in response to the specified topology type being a triangle strip with adjacency information; and K-1 suffix vertex indices in response to the specified topology type being a control packet list with K points, where K is a positive integer.

[0060] It should be noted that the graphic to be drawn may or may not have a reset point, which can be explicitly specified in the drawing command. A reset point is a point where there are no common vertices between the geometric primitive containing the vertex before the reset point and the geometric primitive containing the vertex after the reset point. For example, in the vertex index data A, B, C, (CT), D, E, F of a triangle band, ABC constitutes the first triangle primitive, and DEF constitutes the second triangle primitive. CT represents a reset point, indicating that there are no common vertices between the first and second triangle primitives, that is, A, B, C, D, E, F are divided into two primitives, while B, C, and D do not constitute a triangle primitive.

[0061] In some embodiments, the graphic to be drawn does not have a reset point. In this case, the vertex splitting module 111 can be configured to first obtain a graphics drawing command, which indicates that a graphic with a specified topology type is to be drawn, and the graphics drawing command includes indication information indicating that the graphic to be drawn does not have a reset point; then, determine the number sequence corresponding to the indices of a predetermined number of vertices to be processed by the target graphics processing core; finally, obtain the vertex index fragments and suffix vertex indices to be processed by the target graphics processing core from the vertex index data according to the number sequence, so as to determine the primitive package to be processed by the target graphics processing core. When the graphic to be drawn does not have a reset point, the vertex splitting module of the graphics processing core can skip vertex indices that do not belong to its processing, and can only obtain the vertex index fragments and suffix vertex indices that the target graphics processing core needs to process, thereby reducing the access bandwidth to storage and reducing system power consumption. For example, if the numbering sequence is (0,1,2,3,4,5), then the vertex index fragments to be processed by the target graphics processing core are obtained from the vertex index data based on the numbering sequence (which includes, for example, the vertex indices 0,1,2,3,4,5, which is not limited) and suffix vertex indices (indices 6,7, which depend on the specified topology type). Typically, the numbering sequence and the indices in the vertex index data can have a one-to-one correspondence, and the corresponding vertex index can be obtained based on the numbering sequence.

[0062] In some embodiments, the graph to be drawn has a reset point. In this case, the vertex splitting module 111 can be configured to first obtain a graph drawing command indicating that a graph with a specified topology type is to be drawn, the graph drawing command including indication information indicating that the graph to be drawn has a reset point; then, determine the number sequence corresponding to the indices of a predetermined number of vertices to be processed by the target graphics processing core; finally, obtain all vertex index data required for drawing the graph, and determine the vertex index fragments and suffix vertex indices to be processed by the target graphics processing core from the obtained vertex index data according to the number sequence, so as to determine the primitive package to be processed by the target graphics processing core. When the graph to be drawn has a reset point, the vertex splitting module of the graphics processing core needs to access the complete vertex index data to perform vertex splitting.

[0063] It should be noted that the vertex index data mentioned above can be pre-generated by the application issuing the graphics drawing command and, for example, stored in an index buffer. The vertex splitting module can obtain the vertex index fragments and suffix vertex indices to be processed by the target graphics processing core from the vertex index data in the index buffer, or the vertex index data can be generated by the vertex index data itself; there is no limitation here. Optionally, after determining the primitive packets to be processed by the target graphics processing core, a corresponding synchronization marker can be inserted after each primitive packet, wherein the synchronization marker is used to mark the complete primitive packet. Inserting a corresponding synchronization marker into each primitive packet can clearly indicate the boundary of each primitive packet. These primitive packets and the synchronization markers are sent downstream for processing, which helps the subsequent pixel processing pipeline module to correctly recover these primitive packets and their order.

[0064] The process by which the vertex splitting module 111 determines the number sequence corresponding to the indexes of a predetermined number of vertices to be processed by the target graphics processing core can be understood as a process of splitting vertex index data, because the resulting number sequence can be used to determine the vertex index segments and suffix vertex indices to be processed by the target graphics processing core from the vertex index data. The vertex splitting module 111 can be configured to execute various vertex splitting methods to determine the number sequence corresponding to the indexes of a predetermined number of vertices to be processed by the target graphics processing core. In some embodiments, the vertex splitting module 111 can be configured to first divide consecutive numbers in units of the number of vertex index segments to obtain a number sequence, and then number the resulting number sequence sequentially; then, determine the sequence number of the target graphics processing core among the at least two enabled graphics processing cores in this graphics processing process; finally, in response to the remainder obtained by dividing the number of the divided target number sequence by the number of the at least two enabled graphics processing cores being the same as the sequence number of the target graphics processing core, the target number sequence is determined as the number sequence corresponding to the indexes of the predetermined number of vertices to be processed by the target graphics processing core. The number of consecutive numbers here can be the same as the number of all vertex index data.

[0065] As an example, the numbering sequence obtained by dividing consecutive numbers based on the number of vertex index segments can start from 0, for example, by dividing the consecutive numbers in the order they were divided to obtain numbering sequence 0, numbering sequence 1, numbering sequence 2, etc. The serial number of the graphics processing core is different from the physical number of the graphics processing core. The physical number is usually assigned to the graphics processing core at the physical level and is fixed, while the serial number is variable and can be dynamically assigned each time it is used. For example, the physical numbers of the two enabled graphics processing cores 110 and 120 described with reference to FIG1 are fixed as 0 and 1, respectively, while the physical number of the disabled graphics processing core 130 is fixed as 3. However, the serial numbers of graphics processing cores 110 and 120 can be 0 and 1, or 1 and 0, respectively, while the disabled graphics processing core 130 may not be assigned or have a serial number (representing NULL), which enhances the flexibility of processing. For graphics processing systems (GPUs) with a fixed number of graphics processing cores, users (applications, drivers, or operating systems) can dynamically adjust the number of enabled GPUs as needed to meet performance requirements and power consumption constraints in different application scenarios. Furthermore, for GPUs with multiple GPUs, if some GPUs are defective and unusable during tape-out, these defective GPUs can be disabled, for example, through system configuration modules. This allows the partially defective chip to still be used, reducing losses due to yield issues. This mechanism also applies to virtualization scenarios.

[0066] As an example, assuming the target graphics processing core's sequence number is 0, if the partitioned numbering sequence is 2, then the remainder obtained by dividing it by the number of at least two enabled graphics processing cores is 0, which is the same as the target graphics processing core's sequence number. Therefore, numbering sequence 2 is determined as the numbering sequence corresponding to the indexes of the predetermined number of vertices to be processed by the target graphics processing core. Then, based on numbering sequence 2, the corresponding vertex index fragments and suffix vertex indices can be obtained from the vertex index data as primitive package 2, and primitive package 2 is determined as the primitive package to be processed by the target graphics processing core, with optional insertion of corresponding synchronization markers.

[0067] As mentioned above, primitive composition information represents the information about how the vertices corresponding to the indices included in the primitive package constitute primitives. In other words, primitive composition information represents how the vertices corresponding to the indices included in the primitive package constitute primitives or the specific manner in which they constitute primitives. As an example, it may include the starting primitive number and offset, the starting primitive orientation (i.e., the winding order of the primitives), etc., which are not limited here.

[0068] In some embodiments, the vertex splitting module 111 can parse the vertices in each primitive packet and pass the primitive composition information to the primitive processing pipeline module 113. For example, the vertex splitting module can also be configured to parse the primitive packets to be processed by the target graphics processing core to obtain the primitive composition information, and then transmit the primitive composition information to the primitive processing pipeline module. When parsing the currently processed primitive packet, it may be necessary to parse the data of the primitive packets preceding the currently processed primitive packet to obtain the primitive composition information. Therefore, the vertex splitting module can also be configured to parse the primitive packets to be processed by the target graphics processing core and the primitive packets composed of vertex index data preceding the primitive packets to be processed by the target graphics processing core, to obtain the primitive composition information, and then transmit the primitive composition information to the primitive processing pipeline module.

[0069] In some embodiments, the vertex splitting module 111 can also directly send the primitive packet to the primitive processing pipeline module 113, whereby the primitive processing pipeline module parses the vertices in the primitive packet to obtain how the vertices constitute primitives. For example, the vertex splitting module can be configured to send the primitive packet to be processed by the target graphics processing core to the primitive processing pipeline module, and the primitive processing pipeline module is configured to parse the primitive packet to be processed by the target graphics processing core to obtain the primitive composition information. When parsing the currently processed primitive packet, it may be necessary to parse the data of the primitive packets preceding the currently processed primitive packet to obtain the primitive composition information. Therefore, the vertex splitting module is also configured to send the primitive packet to be processed by the target graphics processing core and the primitive packet composed of vertex index data preceding the primitive packet to be processed by the target graphics processing core to the primitive processing pipeline module, and the primitive processing pipeline module is configured to parse the sent primitive packet to obtain the primitive composition information.

[0070] Accordingly, Figure 2 shows an exemplary flowchart of a graphics processing method 200 according to an embodiment of the present disclosure. The method 200 can be executed by a target graphics processing core, which is one of at least two enabled graphics processing cores included in a graphics processing system. Each of the at least two enabled graphics processing cores includes a vertex splitting module, a vertex processing pipeline module, a primitive processing pipeline module, and a pixel processing pipeline module. The target graphics processing core may, for example, be an enabled graphics processing core 110 as described with reference to Figure 1. The method 200 may include the following steps.

[0071] In step 210, the vertex splitting module of the target graphics processing core is used to determine the primitive package to be processed by the target graphics processing core from the vertex index data. The vertex index data includes indices of the vertices of the graph to be drawn. In some embodiments, the primitive package includes vertex index fragments and suffix vertex indices, wherein the vertex index data includes indices of the vertices of the graph to be drawn having a specified topology, and the suffix vertex indices are indices that are consecutively located after the vertex index fragments in the vertex index data. The vertex index fragments included in the primitive package to be processed by the at least two enabled graphics processing cores all include the same predetermined number of vertex indices, and the number of suffix vertex indices depends on the specified topology.

[0072] In step 220, the vertex processing pipeline module of the target graphics processing core is used to perform shading processing on the vertices corresponding to the indices in the primitive package to be processed by the target graphics processing core, so as to obtain the shading processing result. The shading processing here calculates for each vertex and can perform various transformations and operations, such as model transformation, view transformation, projection transformation, etc., and can also calculate the vertex's lighting, texture coordinates, etc.

[0073] In step 230, the primitive processing pipeline module of the target graphics processing core is used to obtain primitive composition information and perform geometric processing on the shading processing result based on the primitive composition information to obtain a geometric processing result. The primitive composition information represents the information of the vertex constituent primitives corresponding to the indices included in the primitive package to be processed by the target graphics processing core. This primitive composition information is obtained by the vertex splitting module or the primitive processing pipeline module, at least based on the primitive package to be processed by the target graphics processing core, through parsing. Here, the shading processing result is geometrically processed based on the primitive composition information, for example, assembling it into geometric primitives and performing geometric shading on the geometric primitives. After a series of processing steps, they are converted into geometric processing results mapped to pixel coordinates in screen space.

[0074] In step 240, the geometric processing results are processed using the pixel processing pipeline module of the target graphics processing core to obtain a visualized graphic. The pixel processing pipeline module primarily obtains the visualized graphic by executing the various stages of the pixel processing portion of the rendering pipeline as described above. These stages are similar to those described in related technologies and will not be described in detail here.

[0075] The graphics processing method disclosed herein enables parallel processing of vertex processing and primitive assembly, significantly expanding the data processing throughput of the geometry stage, improving the processing speed of the graphics processing system, achieving high-quality and high-resolution rendering in real time, and possessing good scalability. Users can easily add or remove (or dynamically configure as needed) the corresponding GPU units (e.g., enabled graphics processing cores) according to the usage scenario to meet the performance and power consumption requirements of different scenarios.

[0076] Figure 3 illustrates an exemplary flowchart of a method 300 for determining a primitive package to be processed by a target graphics processing kernel based on vertex index data according to a specified topology type, according to an embodiment of the present disclosure. The method 300 includes the following steps.

[0077] In step 310, the number i of the current number sequence is reset to 0.

[0078] In step 320, the consecutive numbers are divided into number sequences based on the number of vertex index segments, and the current number i is assigned to the number sequence obtained by the division.

[0079] In step 330, it is determined whether the remainder obtained by dividing number i by the number of the at least two enabled graphics processing cores is the same as the sequence number of the target graphics processing core. If they are different, in step 340, it is determined that the target number sequence is not the number sequence corresponding to the indexes of the predetermined number of vertices to be processed by the target graphics processing core. In other words, the primitive package corresponding to the current number sequence is not the primitive package to be processed by the target graphics processing core and is discarded directly. Here, the primitive package corresponding to the current number sequence includes the vertex index fragment and suffix vertex index to be processed by the target graphics processing core, determined from the acquired vertex index data based on the current number sequence. If they are the same, in step 350, it is determined that the target number sequence is the number sequence corresponding to the indexes of the predetermined number of vertices to be processed by the target graphics processing core. In other words, the primitive package corresponding to the current number sequence is the primitive package to be processed by the target graphics processing core. In step 360, the vertex index segments and suffix vertex indices to be processed by the target graphics processing core can be determined from the acquired vertex index data based on the numbering sequence, thereby determining the primitive packets to be processed by the target graphics processing core, and the primitive packets are sent to the vertex processing pipeline module. In step 370, corresponding synchronization markers are inserted into the divided primitive packets.

[0080] In step 380, it is determined whether the numbering sequence division has ended. If it has ended, the execution of this method is terminated. If it has not ended, in step 390, the value of number i is incremented by one and assigned to the current number i in the numbering sequence, and the process returns to step 320 to continue execution.

[0081] Embodiments of this disclosure provide an efficient and simple method for partitioning primitive packets, which can quickly determine the primitive packets to be processed by the target graphics processing core.

[0082] Figure 4 illustrates an exemplary process for partitioning primitive packets according to an embodiment of the present disclosure, specifically showing the partitioning of primitive packets by the vertex splitting module in the first graphics processing core (serial number 0) when three graphics processing cores are enabled. Taking graphics processing core 110 in Figure 1 as an example, as shown in Figure 4, the first partitioned primitive packet is numbered 0, the second partitioned primitive packet is numbered 1, and so on. According to the method described in Figure 3, primitive packets 0 and 3 can be determined as the primitive packets to be processed by the first graphics processing core, and corresponding synchronization markers are inserted, while primitive packets 1, 2, 4, and 5 are not the primitive packets to be processed by the first graphics processing core and should therefore be discarded.

[0083] Figures 5A, 5B, 5C, and 5D illustrate exemplary schematic diagrams of a partitioned primitive package according to an embodiment of the present disclosure, with a triangle list topology as an example. As shown in Figure 5A, all vertex index data is v0-v31, representing indices of 32 vertices, which can form 10 triangles as shown. Assume the system configuration module is configured with Z = 8 vertex indices included in each vertex index fragment. Simultaneously, the number of suffix vertex indices can be determined to be 2 based on the triangle list. In this case, these vertex index data can be split into four vertex index fragments: vertex index fragments v0-v7, vertex index fragments v8-v15, vertex index fragments v16-v23, and vertex index fragments v24-v31. The vertices corresponding to each vertex index fragment do not constitute a complete primitive; for example, vertex index fragments v0-v7 are missing v8 to form the first three triangles. As an example, the vertex splitting module can split the primitive package according to method 300 described above.

[0084] As shown in Figure 5B, the partitioned primitive package 0 contains vertex index segments v0-v7, and two suffix vertex indices v8 and v9. The vertices corresponding to these indices are sent to the downstream vertex processing pipeline module to execute the vertex shading program. The information of these vertices is also sent to the primitive processing pipeline module, allowing it to analyze how these vertices form primitives while the vertex processing pipeline module is running the vertex shading program. Specifically, v0-v1-v2 form a triangle, v3-v4-v5 form a triangle, v6-v7-v8 form a triangle, while v9 is redundant and its result can be discarded.

[0085] As shown in Figure 5C, primitive package 1 contains vertex index segments v8-v15, and two suffix vertex indices v16 and v17. The vertices corresponding to these indices are sent to the downstream vertex processing pipeline module to execute the vertex shading program. The information of these vertices is also sent to the primitive processing pipeline module, allowing it to analyze how these vertices constitute primitives while the vertex processing pipeline module is running the vertex shading program. Specifically, v9-v10-v11 form a triangle, v12-v13-v14 form a triangle, v15-v16-v17 form a triangle, and v8 is redundant and its result can be discarded. Note that when parsing primitive package 1, the primitive processing pipeline module may need data from primitive package 0 as input to determine how the primitives in primitive package 1 are constructed.

[0086] As shown in Figure 5D, primitive package 2 contains vertex index segments v16-v23, and two suffix vertex indices v24 and v25. The vertices corresponding to these indices are sent to the downstream vertex processing pipeline module to execute the vertex shading program. The information of these vertices is also sent to the primitive processing pipeline module, allowing it to analyze how these vertices constitute primitives while the vertex processing pipeline module is running the vertex shading program. Specifically, v18-v19-v20 form a triangle, v21-v22-v23 form another triangle, while v16, v17, v24, and v25 are redundant and their results can be discarded. Note that when parsing primitive package 2, the primitive processing pipeline module may need data from primitive package 0 and primitive package 1 as input to determine how the primitives in primitive package 2 are constructed.

[0087] Without violating logic, different embodiments of this application can be combined with each other. The descriptions of different embodiments have different focuses, and the parts not described in a particular focus can be referred to the descriptions of other embodiments.

[0088] In some embodiments of this disclosure, the system provided by this disclosure may have functions or include modules that can be used to execute the methods described in the above method embodiments. The specific implementation and technical effects can be referred to the description of the above method embodiments. For the sake of brevity, they will not be repeated here.

[0089] Figure 6 illustrates an example system 600, which includes an example computing device 610 representing one or more systems and / or devices that can implement the various technologies described herein. The computing device 610 may be, for example, a server of a service provider, a device associated with a server, a system-on-a-chip, and / or any other suitable computing device or computing system. The graphics processing system 100 described above with reference to Figure 1 may take the form of computing device 610. Alternatively, the graphics processing method 200 may be implemented as a computer program in the form of application 616.

[0090] The example computing device 610 shown includes a processing system 611 communicatively coupled to each other, one or more computer-readable media 612, and one or more I / O interfaces 613. Although not shown, the computing device 610 may also include a system bus or other data and command transfer system that couples the various components to each other. The system bus may include any or a combination of different bus architectures, such as a memory bus or memory controller, a peripheral bus, a universal serial bus, and / or a processor or local bus utilizing any of the various bus architectures. Various other examples, such as control and data lines, are also conceived.

[0091] Processing system 611 represents the functionality of performing one or more operations using hardware. Therefore, processing system 611 is illustrated as including hardware elements 614 that can be configured as processors, function blocks, etc. This may include other logic devices implemented in hardware as application-specific integrated circuits (ASICs) or formed using one or more semiconductors. Hardware element 614 is not limited by the materials in which it is formed or the processing mechanism employed therein. For example, a processor may consist of semiconductors and / or transistors (e.g., integrated circuits (ICs)). In such a context, processor-executable instructions may be electronically executable instructions.

[0092] Computer-readable medium 612 is illustrated as including memory / storage device 615. Memory / storage device 615 represents a memory / storage capacity associated with one or more computer-readable media. Memory / storage device 615 may include volatile media (such as random access memory (RAM)) and / or non-volatile media (such as read-only memory (ROM), flash memory, optical disk, magnetic disk, etc.). Memory / storage device 615 may include fixed media (e.g., RAM, ROM, fixed hard disk drive, etc.) and removable media (e.g., flash memory, removable hard disk drive, optical disk, etc.). Computer-readable medium 612 may be configured in various other ways as further described below.

[0093] One or more I / O interfaces 613 represent the functionality to allow users to input commands and information to computing device 610 using various input devices and optionally also to present information to the user and / or other components or devices using various output devices. Examples of input devices include keyboards, cursor control devices (e.g., mice), microphones (e.g., for voice input), scanners, touch functionality (e.g., capacitive or other sensors configured to detect physical touch), cameras (e.g., capable of detecting non-touch-related motion as gestures using visible or invisible wavelengths (such as infrared frequencies), and so on. Examples of output devices include display devices (e.g., monitors or projectors), speakers, printers, network interface cards, haptic-responsive devices, and so on. Therefore, computing device 610 can be configured in various ways, as further described below, to support user interaction.

[0094] The computing device 610 also includes an application 616. The application 616 may be, for example, a software instance of a graphics processing method, and implements the techniques described herein in combination with other elements in the computing device 610.

[0095] This document describes various technologies within the general context of software and hardware components or program modules. Generally, these modules include routines, programs, objects, elements, components, data structures, etc., that perform specific tasks or implement specific abstract data types. As used herein, the terms "module," "function," and "component" generally refer to software, firmware, hardware, or a combination thereof. The technologies described herein are characterized as platform-independent, meaning that these technologies can be implemented on a variety of computing platforms with various processors.

[0096] Implementations of the described modules and technologies may be stored on or transmitted across some form of computer-readable medium. The computer-readable medium may include various media accessible by the computing device 610. By way of example and not limitation, the computer-readable medium may include "computer-readable storage media" and "computer-readable signal media".

[0097] In contrast to simple signal transmission, carrier waves, or signals themselves, a "computer-readable storage medium" refers to a medium and / or device capable of persistently storing information, and / or a tangible storage device. Therefore, a computer-readable storage medium refers to a non-signal-bearing medium. Computer-readable storage media include hardware such as volatile and non-volatile, removable and non-removable media and / or storage devices implemented using methods or techniques suitable for storing information (such as computer-readable instructions, data structures, program modules, logic elements / circuits, or other data). Examples of computer-readable storage media may include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, DVD or other optical storage devices, hard disks, magnetic tape cassettes, magnetic tapes, disk storage devices or other magnetic storage devices, or other storage devices, tangible media, or articles of art suitable for storing desired information and accessible by a computer.

[0098] "Computer-readable signal medium" refers to a signal-bearing medium configured to transmit instructions, such as via a network, to computing device 610. A signal medium typically embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal, such as a carrier wave, data signal, or other transmission mechanism. Signal media also include any information transmission medium. The term "modulated data signal" refers to a signal in which one or more of its characteristics are set or altered to encode information. By way of example and not limitation, communication media include wired media such as wired networks or direct connections, and wireless media such as acoustic, RF, infrared, and other wireless media.

[0099] As previously described, hardware element 614 and computer-readable medium 612 represent instructions, modules, programmable device logic, and / or fixed device logic implemented in hardware, which in some embodiments can be used to implement at least some aspects of the techniques described herein. Hardware elements may include components of integrated circuits or systems-on-a-chip, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), and other implementations or other hardware devices in silicon. In this context, hardware elements can serve as processing devices for executing program tasks defined by instructions, modules, and / or logic embodied by the hardware element, and as hardware devices for storing instructions for execution, such as the previously described computer-readable storage medium.

[0100] The foregoing combinations can also be used to implement the various techniques and modules described herein. Therefore, software, hardware, or program modules and other program modules can be implemented as one or more instructions and / or logic embodied on some form of computer-readable storage medium and / or by one or more hardware elements 614. The computing device 610 can be configured to implement specific instructions and / or functions corresponding to the software and / or hardware modules. Thus, for example, by using the computer-readable storage medium and / or hardware elements 614 of a processing system, modules can be implemented at least partially in hardware as modules executable as software by the computing device 610. Instructions and / or functions can be executable / operable by one or more articles of art (e.g., one or more computing devices 610 and / or processing systems 611) to implement the techniques, modules, and examples described herein.

[0101] In various embodiments, the computing device 610 can be configured in various ways. For example, the computing device 610 can be implemented as a computer-type device, including personal computers, desktop computers, multi-screen computers, laptop computers, netbooks, etc. The computing device 610 can also be implemented as a mobile device, including mobile devices such as mobile phones, portable music players, portable gaming devices, tablet computers, multi-screen computers, etc. The computing device 610 can also be implemented as a television-type device, including devices with or connected to a generally large screen in a leisure viewing environment. These devices include televisions, set-top boxes, game consoles, etc.

[0102] The techniques described herein can be supported by these various configurations of computing device 610, and are not limited to specific examples of the techniques described herein. Functionality can also be implemented, wholly or partially, on “cloud” 620 using distributed systems, such as platform 622 as described below.

[0103] Cloud 620 includes and / or represents platform 622 for resource 624. Platform 622 abstracts the underlying functionality of the hardware (e.g., server) and software resources of cloud 620. Resource 624 may include applications and / or data that can be used when performing computer processing on a server remote from computing device 610. Resource 624 may also include services provided via the Internet and / or via subscriber networks such as cellular or Wi-Fi networks.

[0104] Platform 622 can abstract resources and functions to connect computing device 610 to other computing devices. Platform 622 can also be used to abstract resource hierarchy to provide a tiered hierarchy of the appropriate levels of demand for resource 624 implemented via platform 622. Therefore, in interconnect device embodiments, the implementation of the functions described herein can be distributed throughout system 600. For example, functions can be implemented partly on computing device 610 and partly through platform 622, which abstracts the functions of cloud 620.

[0105] This disclosure provides a computer-readable storage medium storing computer-readable instructions thereon, which, when executed, implement any of the methods described above. The computer-readable storage medium may be a volatile storage medium or a non-volatile storage medium.

[0106] This disclosure provides a computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of a computing device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computing device to perform any of the methods provided in the various alternative implementations described above.

[0107] It should be understood that, for clarity, embodiments of this disclosure have been described with reference to different functional units. However, it will be apparent that, without departing from this disclosure, the functionality of each functional unit may be implemented in a single unit, in multiple units, or as part of other functional units. For example, functionality described as being performed by a single unit may be performed by multiple different units. Therefore, references to a particular functional unit are considered merely as references to the appropriate unit used to provide the described functionality, and not as indicating a strict logical or physical structure or organization. Thus, this disclosure may be implemented in a single unit, or may be physically and functionally distributed among different units and circuits.

[0108] It will be understood that although the terms first, second, third, etc., may be used herein to describe various devices, elements, components, or parts, these devices, elements, components, or parts should not be limited by these terms. These terms are used only to distinguish one device, element, component, or part from another device, element, component, or part.

[0109] Although this disclosure has been described in conjunction with some embodiments, it is not intended to be limited to the specific forms set forth herein. Rather, the scope of this disclosure is limited only by the appended claims. Additionally, although individual features may be included in different claims, these may be advantageously combined, and inclusion in different claims does not imply that such a combination of features is not feasible and / or advantageous. The order of features in the claims does not imply that the features must be in any particular order of their operation. Furthermore, in the claims, the word "comprising" does not exclude other elements, and the terms "a" or "an" do not exclude a plurality. Reference numerals in the claims are provided only by way of explicit example and should not be construed as limiting the scope of the claims in any way.

Claims

1. A graphics processing system, the graphics processing system comprising at least two enabled graphics processing cores, and each of the at least two enabled graphics processing cores comprising a vertex split module, a vertex processing pipeline module, a primitive processing pipeline module, and a pixel processing pipeline module; wherein, The at least two enabled graphics processing cores include a target graphics processing core, and wherein, The vertex splitting module of the target graphics processing core is configured to determine the primitive package to be processed by the target graphics processing core from the vertex index data. The vertex processing pipeline module of the target graphics processing core is configured to perform color processing on the vertices corresponding to the indices in the primitive package to be processed by the target graphics processing core, so as to obtain the color processing result. The primitive processing pipeline module of the target graphics processing core is configured to acquire primitive composition information and perform geometric processing on the shading processing result based on the primitive composition information to obtain a geometric processing result. The primitive composition information represents the information of the vertex composition primitives corresponding to the index included in the primitive package. The primitive composition information is obtained by the vertex splitting module or the primitive processing pipeline module at least based on the primitive package to be processed by the target graphics processing core. The pixel processing pipeline module of the target graphics processing core is configured to process the geometric processing results to obtain a visual graphic.

2. The graphics processing system of claim 1, wherein, The primitive package includes vertex index fragments and suffix vertex indices, wherein the vertex index data includes indices of vertices of a graph of a specified topology to be drawn, and the suffix vertex indices are indices that are consecutively located after the vertex index fragments in the index order of the vertex index data. The vertex index fragments included in the primitive package to be processed by the at least two enabled graphics processing cores all include the same predetermined number of vertex indices, and the number of suffix vertex indices depends on the specified topology.

3. The graphics processing system of claim 1 or 2, wherein, The vertex splitting module is also configured to parse the primitive packets to be processed by the target graphics processing core to obtain the primitive composition information, and transmit the primitive composition information to the primitive processing pipeline module.

4. The graphics processing system according to claim 1 or 2, wherein, The vertex splitting module is further configured to parse the primitive packet to be processed by the target graphics processing core and the primitive packet consisting of vertex index data preceding the primitive packet to be processed by the target graphics processing core, in order to obtain the primitive composition information, and transmit the primitive composition information to the primitive processing pipeline module.

5. The graphics processing system of claim 1 or 2, wherein, The vertex splitting module is also configured to transmit the primitive packet to be processed by the target graphics processing core to the primitive processing pipeline module, and the primitive processing pipeline module is configured to parse the primitive packet to be processed by the target graphics processing core to obtain the primitive composition information.

6. The graphics processing system of claim 1, wherein, The vertex splitting module is further configured to transmit the primitive packet to be processed by the target graphics processing core, as well as the primitive packet consisting of vertex index data preceding the primitive packet to be processed by the target graphics processing core, to the primitive processing pipeline module, and the primitive processing pipeline module is configured to parse the transmitted primitive packet to obtain the primitive composition information.

7. The graphics processing system of claim 2, wherein, The number of indices in the vertex index fragment is aligned with the bandwidth of the access interface of the memory where the geometry processing results are to be stored.

8. The graphics processing system of claim 2, wherein, The vertex splitting module of the target graphics processing core is also configured to: Obtain a drawing command, the drawing command indicating that a graph with a specified topology type should be drawn, the drawing command including indication information for indicating that the graph to be drawn does not have a reset point; Determine the number sequence corresponding to the index of the predetermined number of vertices to be processed by the target graphics processing core; Based on the numbering sequence, obtain the vertex index fragments and suffix vertex indices to be processed by the target graphics processing core from the vertex index data to determine the primitive package to be processed by the target graphics processing core.

9. The graphics processing system of claim 2, wherein, The vertex splitting module of the target graphics processing core is also configured to: Obtain a drawing command, which indicates that a graph with a specified topology type should be drawn, and the drawing command includes indication information for indicating that the graph to be drawn has a reset point; Determine the number sequence corresponding to the index of the predetermined number of vertices to be processed by the target graphics processing core; Obtain all vertex index data required to draw the graphic; Based on the numbering sequence, determine the vertex index fragments and suffix vertex indices to be processed by the target graphics processing core from all the acquired vertex index data, so as to determine the primitive package to be processed by the target graphics processing core.

10. The graphics processing system of claim 8 or 9, wherein, The vertex splitting module of the target graphics processing core is also configured to: The consecutive numbers are divided into number sequences based on the number of vertex index segments, and the resulting number sequences are numbered sequentially. Determine the sequence number of the target graphics processing core among the at least two enabled graphics processing cores during this graphics processing process; If the remainder obtained by dividing the number of the target number sequence obtained by partitioning by the number of the at least two enabled graphics processing cores is the same as the sequence number of the target graphics processing core, then the target number sequence is determined as the number sequence corresponding to the index of the predetermined number of vertices to be processed by the target graphics processing core.

11. The graphics processing system of claim 8 or 9, wherein, The vertex index data is either pre-generated by the application that issues the graphics drawing command or generated by the vertex splitting module itself.

12. The graphics processing system of any one of claims 2, 8 or 9, wherein, The vertex splitting module of the target graphics processing core is also configured to determine the number of suffix vertex indices in the following manner: In response to the specified topology type being a point list, the number of suffix vertex indices is zero; In response to the specified topology type being a line list, a circular line, or a line strip, the number of suffix vertex indices is one; In response to the specified topology type being a triangle list, triangle strip, or triangle fan, the number of suffix vertex indices is two; In response to the specified topology type being a line list with adjacency information or a line strip with adjacency information, the number of suffix vertex indices is three; In response to the specified topology being a triangle list with adjacency information, the number of suffix vertex indices is five; In response to the specified topology type being a triangle strip with adjacency information, the number of suffix vertex indices is seven; In response to the specified topology being a control packet list with K points, the number of suffix vertex indices is K-1, where K is a positive integer.

13. A graphics processing method, the method being performed by a target graphics processing core, the target graphics processing core being one of at least two enabled graphics processing cores included in a graphics processing system, each of the at least two enabled graphics processing cores including a vertex split module, a vertex processing pipeline module, a primitive processing pipeline module, and a pixel processing pipeline module; Furthermore, the method includes: Using the vertex splitting module of the target graphics processing core, the primitive package to be processed by the target graphics processing core is determined from the vertex index data; Using the vertex processing pipeline module of the target graphics processing core, the vertices corresponding to the indices in the primitive package to be processed by the target graphics processing core are colored to obtain the coloring result. Using the primitive processing pipeline module of the target graphics processing core, primitive composition information is obtained and geometric processing is performed on the shading processing result based on the primitive composition information to obtain a geometric processing result. The primitive composition information represents the information of the vertex composition primitives corresponding to the indexes included in the primitive package to be processed by the target graphics processing core. The primitive composition information is obtained by the vertex splitting module or the primitive processing pipeline module at least based on the primitive package to be processed by the target graphics processing core. The pixel processing pipeline module of the target graphics processing core is used to process the geometric processing results to obtain a visual graphic.

14. A computing device, the computing device comprising: Memory, which is configured to store computer-executable instructions; A processor configured to perform the method of claim 13 when the computer-executable instructions are executed by the processor.

15. A computer-readable storage medium storing computer-executable instructions that, when executed, perform the method of claim 13.

16. A computer program product comprising computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code, wherein when the computer-readable code is executed in a processor of an electronic device, the processor in the electronic device performs an action to implement the method of claim 13.

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