Anode system with separate anode chamber and ion collimator

Abstract

Metal may be electroplated on a substrate in an electroplating apparatus having a micro regulated virtual anode array and an anisotropic ion collimator positioned proximate to the substrate. The micro-regulated virtual anode array includes a plurality of micro-regulated anode elements that are independently controllable. Current applied to the micro-regulated virtual anode elements provides a current distribution in the array that may be based at least in part on a die layout or other pattern in the substrate or based at least in part on within-wafer and / or within-die or device corrections. The current distribution may achieve uniform plating thickness even with a non-uniform distribution of features in the die of the semiconductor substrate. In some implementations, electroplating apparatus may include a micro-regulated virtual anode array, an anisotropic ion collimator, and a separate anode region.

Description

Docket No. LAM1P056WOANODE SYSTEM WITH SEPARATE ANODE CHAMBER AND ION COLLIMATORINCORPORATION BY REFERENCE

[0001] A PCT Request Form is filed concurrently with this specification as part of the present application. Each application that the present application claims benefit of or priority to as identified in the concurrently filed PCT Request Form is incorporated by reference herein in its entirety and for all purposes.FIELD

[0002] Implementations herein relate to methods and apparatus for electroplating metal on a semiconductor wafer. More particularly, the methods and apparatuses described herein relate to an electroplating apparatus employing an array of small anodes.BACKGROUND

[0003] In semiconductor device manufacturing, a conductive material, such as copper, is often deposited by electroplating onto a seed layer of metal to fill one or more recessed features on a semiconductor wafer. Electroplating is a method of choice for depositing metal into the vias and trenches of the wafer during damascene processing and is also used in through-mask plating in wafer level packaging (WLP) applications to form pillars and lines of metal. Another application of electroplating is filling through-silicon vias (TSVs), which are relatively large vertical electrical connections used in 3D integrated circuits and 3D packages.

[0004] The background provided herein is for the purposes of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent that it is described in this background, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.SUMMARY

[0005] Provided herein is a method and apparatus for electroplating metal on a substrate.

[0006] One general aspect includes a system for electroplating employing micro-regulated virtual anode (MRVA). The system includes a substrate holder configured to hold a substrate during electroplating onto the substrate; a micro-regulated variable anode (MRVA) array having a plurality of independently electrically addressable inert anodes; and an anisotropicDocket No. LAM1P056WO ion collimator (AIC) located between the substrate holder and the MRVA. The AIC includes a solid insulating body with a plurality of channels having axes oriented in a direction between the substrate and the MRVA. The AIC may be configured to (a) transfer current from a first anode of the MRVA through one or more first channels of the plurality of channels proximate to the first anode and to a first location on the substrate, and (b) transfer current from a second anode of the MRVA through one or more second channels of the plurality of channels proximate to the second anode and to a second location on the substrate.

[0007] One general aspect includes a system for electroplating employing an anode. The system includes a substrate holder configured to hold a substrate during electroplating onto the substrate; the anode array having a plurality of independently electrically addressable inert anodes; and an ion collimator located between the substrate holder and the anode array. The ion collimator includes an insulating body with a plurality of channels having axes oriented in a direction between the substrate and the anode array. The ion collimator may be configured to (a) transfer current from a first anode of the anode array through one or more first channels of the plurality of channels proximate to the first anode and to a first location on the substrate, and (b) transfer current from a second anode of the anode array through one or more second channels of the plurality of channels proximate to the second anode and to a second location on the substrate.

[0008] Implementations may include one or more of the following features. The substrate holder of the system may include a cup having a substantial ring shape and configured to contact an outer edge of the substrate while a cone pushes against the backside of the substrate, which is not substantially electroplated. In some embodiments, the substrate holder is configured to rotate with respect to the AIC during electroplating onto the substrate.

[0009] In some embodiments, the MRVA array may include at least about 100 of the inert anodes. Each of the inert anodes may be or include a noble metal, a semi-noble metal, a mixed metal oxide, or any combination thereof. In some embodiments, each of the inert anodes may include platinum, iridium, gold, niobium, or any combination thereof. In some embodiments, each of the inert anodes may include titanium oxide, ruthenium oxide, iridium oxide, platinum oxide, or any combination thereof.

[0010] In some embodiments, each inert anode may have a surface facing the AIC, and where the surface of at least one of the inert anodes has a principal dimension of about 5 mm or less or about 500 pm or less.

[0011] In some embodiments, the inert anodes have a pitch defined between adjacent inert anodes in the MRVA of about 500 pm or less.Docket No. LAM1P056WO

[0012] In some embodiments, the system may further include a MRVA controller, configured to independently electrically access the inert anodes and to generate a non-uniform current distribution over an area of the MRVA array. The non-uniform current distribution corresponds to a pattern to be electroplated on the substrate. In some embodiments, the MRVA controller is further configured to activate a subset of the inert anodes in a manner corresponding to a die layout on the substrate. The non-uniform current distribution is based, at least in part, on global within- wafer (WIW) corrections and / or local within-die corrections.

[0013] In some embodiments, a system includes software or other logic that (a) analyzes a die layout on a substrate to be processed using a MRVA array as described herein and (b) generates an array image for activating a subset of the MRVA array’s inert anodes to electroplate a pattern corresponding to the die layout.

[0014] In some embodiments, the system may further include an ionically conductive membrane. The ionically conductive membrane is configured to fluidically separate, during electroplating onto the substrate, a catholyte in contact with the substrate and an anolyte in contact with the MRVA array.

[0015] In some embodiments, the anisotropic ion collimator (AIC) is located between the substrate holder and the ionically conductive membrane.

[0016] In some embodiments, the ionically conductive membrane may include a cationically conductive ionomer. In some embodiments, the ionically conductive membrane may include a hydrogen ion conductive polymer. In some embodiments, the ionically conductive membrane may include an ionomer having an average pore size of about 10 nm or less, and a molecular weight of about 250 daltons or less.

[0017] In some embodiments, the AIC has a solid insulating body that may include glass, plastic, ceramic, or any combinations thereof.

[0018] In some embodiments, AIC has a porosity of at least about 20% or at least about 50%. The thickness of AIC may be about 10 mm or less.

[0019] In some embodiments, the AIC has a raised top surface and an overall plateau shape coincident with the position of the substrate when held in a substrate holder.

[0020] In some embodiments, each of the plurality of channels in AIC independently has a diameter of about 1.5 mm or less. In some embodiments, each of the plurality of channels independently has a diameter of about 0.5 mm or less. In some embodiments, each of the plurality of channels has an anisotropic orientation, and each anisotropic channel having a thin wall may include a dielectric material where the thin walls are non-reacting and nonconducting. In some embodiments, each of the plurality of channels independently has a depthDocket No. LAM1P056WO of about 5mm or more. In some embodiments, each of the plurality of channels independently has a depth of about 10mm or more. The center-to-center spacing between adjacent channels in the plurality of channels is about 2 mm or less. In some embodiments, the spacing between adjacent channels in the plurality of channels is about 1 mm or less. The AIC may include about 30,000 to 500,000 or more channels.

[0021] In some embodiments, the AIC and the MRVA are separated by a gap of about 1 mm or less.

[0022] In some embodiments, the system is configured to provide, during electroplating, a gap between the AIC surface and the substrate of at most about 4 mm.

[0023] In some embodiments, the system may further include an anolyte flow loop configured to flow the anolyte in the gap between the MRVA array and the ionically conductive membrane. The anolyte flow loop may include: an anolyte outlet stream, where the anolyte outlet stream may include hydrogen ions; an anolyte inlet stream may include metal ions; and a plating solution reservoir may include a metal oxide, where the plating solution reservoir is configured to receive the anolyte outlet stream and provide the anolyte to the anolyte inlet stream in the anolyte flow loop; and where, during operation, the metal oxide and the hydrogen ions react to form the metal ions in the plating solution reservoir. In some embodiments, the metal oxide is a copper(II) oxide and / or a copper(II) hydroxide and the metal ions are Cu(II) ions. In some embodiments, the anolyte has a resistivity that is at least about 20 times greater than a resistivity of the catholyte.

[0024] In some embodiments, the system further includes an anolyte inlet and / or an anolyte manifold configured to flow the anolyte in a gap between the MRVA array and the AIC. In some embodiments, the anolyte inlet and / or the anolyte manifold is configured to flow the anolyte substantially uniformly across the gap between the MRVA array and the AIC

[0025] In some embodiments, the system may include a catholyte flow loop configured to flow the catholyte adjacent to the substrate and the AIC. In some embodiments, the system may include a cross-flow injection manifold configured to flow the catholyte in a gap between the AIC and the substrate. In some embodiments, the system may further include an inlet and an outlet configured to cause the catholyte to flow across the face of the substrate during electroplating. In some embodiments, the second inlet and the second outlet may be present and are configured to cause the catholyte to purge the plurality channels of the AIC and / or a region between the AIC and the ionically conductive membrane.

[0026] Another general aspect includes a method of electroplating metal features on a substrate. The method includes receiving a substrate in a cathode region of an electroplatingDocket No. LAM1P056WO chamber, where the cathode region may include a substrate holder and an anisotropic ion collimator (AIC). The AIC may include a solid insulating body with a plurality of channels having axes oriented in a direction between the substrate and a micro-regulated virtual anode (MRVA) array. The method further includes flowing catholyte over the substrate in the cathode region; flowing anolyte over the MRVA array where MRVA array may include a plurality of inert anodes in an anode region of the electroplating chamber, and the anode region is separated from the cathode region by an ionically conductive membrane. The method also includes applying current to two or more inert anodes of the (MRVA) array to provide a non-uniform current distribution over an area of the substrate to electroplate the metal features on the substrate. The AIC (a) transfers current from a first anode of the MRVA through one or more first channels of the plurality of channels proximate to the first anode and to a first location on the substrate, and (b) transfers current from a second anode of the MRVA through one or more second channels of the plurality of channels proximate to the second anode and to a second location on the substrate.

[0027] The method may further includes: flowing the anolyte from the anode region to a plating solution reservoir via an anolyte outlet stream, where the anolyte outlet stream may include hydrogen ions and the plating solution reservoir may include a metal oxide; reacting the metal oxide and the hydrogen ions to form metal ions. The method includes flowing the anolyte from the plating solution reservoir to the anode regions via an anolyte inlet stream that may include the metal ions. The metal oxide is a copper (II) oxide and or copper (II) hydroxide and the metal ions are Cu(II) ions.

[0028] Implementations may include one or more of the following features. The substrate holder may include a cup having a substantial ring shape and configured to contact an outer edge of the substrate while a cone pushes against the backside of the substrate, wherein the backside which is not substantially electroplated. In some embodiments, the substrate holder is configured to rotate with respect to the AIC during electroplating onto the substrate.

[0029] In some embodiments, the MRVA array may include at least about 100 of the inert anodes. Each of the inert anodes may be or include a noble metal, a semi-noble metal, a mixed metal oxide, or any combination thereof. In some embodiments, each of the inert anodes may include platinum, iridium, gold, niobium, titanium, or any combination thereof. In some embodiments, each of the inert anodes may include titanium oxide, ruthenium oxide, iridium oxide, platinum oxide, or any combination thereof.Docket No. LAM1P056WO

[0030] In some embodiments, each inert anode may have a surface facing the AIC, and where the surface of at least one of the inert anodes has a principal dimension of about 5 mm or less or about 500 pm or less.

[0031] In some embodiments, the inert anodes have a pitch defined between adjacent inert anodes in the MRVA of about 500 pm or less.

[0032] In some embodiments, the method may further involve a MRVA controller, configured to independently electrically access the inert anodes and to generate a non-uniform current distribution over an area of the MRVA array. The non-uniform current distribution corresponds to a pattern to be electroplated on the substrate. In some embodiments, the MRVA controller is further configured to activate a subset of the inert anodes in a manner corresponding to a die layout on the substrate. The non-uniform current distribution is based, at least in part, on global within- wafer (WIW) corrections and / or local within-die corrections.

[0033] In some embodiments, the method may further include an ionically conductive membrane. The ionically conductive membrane is configured to fluidically separate, during electroplating onto the substrate, a catholyte in contact with the substrate and an anolyte in contact with the MRVA array.

[0034] In some embodiments, the anisotropic ion collimator (AIC) is located between the substrate holder and the ionically conductive membrane.

[0035] In some embodiments, the ionically conductive membrane may include a cationically conductive ionomer. In some embodiments, the ionically conductive membrane may include a hydrogen ion conductive polymer. In some embodiments, the ionically conductive membrane may include an ionomer having an average pore size of about 10 nm or less, and a molecular weight of about 250 daltons or less.

[0036] In some embodiments, the AIC has a solid insulating body that may include glass, plastic, ceramic, or any combinations thereof.

[0037] In some embodiments, AIC has a porosity of at least about 20% or at least about 50%. The thickness of AIC may be about 10 mm or less.

[0038] In some embodiments, the AIC has a raised top surface and an overall plateau shape coincident with the position of the substrate when held in a substrate holder.

[0039] In some embodiments, each of the plurality of channels in AIC independently has a diameter of about 1 mm or less. In some embodiments, each of the plurality of channels independently has a diameter of about 0.5 mm or less. In some embodiments, each of the plurality of channels has an anisotropic orientation, and each anisotropic channel having a thin wall may include a dielectric material where the thin walls are non-reacting and nonDocket No. LAM1P056WO conducting. In some embodiments, each of the plurality of channels independently has a depth of about 5mm or more. In some embodiments, each of the plurality of channels independently has a depth of about 10mm or more. The spacing between adjacent channels in the plurality of channels is about 2 mm or less. In some embodiments, the spacing between adjacent channels in the plurality of channels is about 1.5 mm or less. The AIC may include about 50,000 to 500,000 or more channels.

[0040] In some embodiments, the AIC and the MRVA are separated by a gap of about 1 mm or less.

[0041] In some embodiments, the method further includes flowing anolyte, where an anolyte inlet and / or an anolyte manifold configured to flow the anolyte in a gap between the MRVA array and the AIC. In some embodiments, the anolyte inlet and / or the anolyte manifold is configured to flow the anolyte substantially uniformly across the gap between the MRVA array and the AIC

[0042] In some embodiments, the method may include flowing catholyte, where the catholyte flows adjacent to the substrate and the AIC. In some embodiments, flowing catholyte may include a cross-flow injection manifold configured to flow the catholyte in a gap between the AIC and the substrate. In some embodiments, flowing catholyte may involve an inlet and an outlet configured to cause the catholyte to flow across the face of the substrate during electroplating. In some embodiments, the second inlet and the second outlet may be used to purge the catholyte from the plurality channels of the AIC and / or a region between the AIC and the ionically conductive membrane.BRIEF DESCRIPTION OF DRAWINGS

[0043] Figure 1 illustrates a flow diagram of an example method of electroplating metal features on a substrate using a micro-regulated anode array according to some implementations

[0044] Figure 2 illustrates a simplified diagram of an example electroplating apparatus including multiple inert anode array plating stations according to some implementations.

[0045] Figure 3A depicts a perspective view of an example schematic micro-regulated virtual anode array according to some implementations.

[0046] Figure 3B depicts a top view of the example schematic micro-regulated virtual anode array of Figure 3A.

[0047] Figure 4 shows different shapes and arrangements of inert anodes in a micro-regulated virtual anode array according to some implementations.

[0048] Figure 5 illustrates a circuit diagram of example micro-regulated virtual anode arrayDocket No. LAM1P056WO elements with active matrix control circuitry according to some implementations.

[0049] Figure 6 depicts a top-down view of a schematic illustration of an example microregulated virtual anode array for processing a circular semiconductor substrate according to some implementations.

[0050] Figure 7 illustrates a schematic diagram of an electroplating cell.

[0051] Figures 8 A, 8B, and 8C depict schematic diagrams of an example electroplating cell in combination with an anisotropic ion collimator module using a single electroplating solution according to some implementations.

[0052] Figure 9 presents an equivalent circuit representation of an electroplating cell according to some implementations.

[0053] Figure 10 depicts a top view of the anisotropic ion collimator according to various embodiments.

[0054] Figure 11 illustrates a schematic diagram of an example inert anode array electroplating cell in combination with general electroplating cell fluidic and plating controls according to some implementations.

[0055] Figure 12 illustrates a schematic diagram of an example inert anode array electroplating cell in combination with a metal oxide dose control unit according to some implementations.

[0056] Figure 13 illustrates a schematic diagram of an example inert anode array electroplating cell in combination with a redox couple according to some implementations.

[0057] Figure 14 illustrates a cross-sectional schematic view of an example micro-regulated virtual anode array positioned relative to a semiconductor substrate according to some implementations.

[0058] Figure 15 depicts a simplified view of a multi-tool electroplating apparatus according to some implementations.

[0059] Figure 16 depicts a simplified view of an example electroplating apparatus with different electroplating cells and modules according to some implementations.DETAILED DESCRIPTIONIntroduction and Context

[0060] In this application, the terms “semiconductor wafer,” “wafer,” “substrate,” “wafer substrate,” and “partially fabricated integrated circuit” may be used interchangeably. One of ordinary skill in the art would understand that the term “partially fabricated integrated circuit” can refer to a silicon wafer during any of many stages of integrated circuit fabrication thereon. A wafer or substrate used in the semiconductor device industry typically has a diameter of atDocket No. LAM1P056WO least 200 mm, or at least 300 mm, or at least 450 mm. In some cases, the substrate may be a rectangular or square panel. A rectangular or square panel can have dimensions of at least 300 mm by 300 nm, at least 500 mm by 500 mm, or at least 600 mm by 600 mm, but are not limited to such dimensions. Further, the terms “electrolyte,” “plating bath,” “bath,” and “plating solution” are used interchangeably. The following detailed description assumes the embodiments are implemented on a wafer. However, the embodiments are not so limited. The work piece may be of various shapes, sizes, and materials. In addition to semiconductor wafers, other work pieces that may take advantage of the disclosed embodiments include various articles such as glass panels, printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, micro-mechanical devices and the like. Work pieces in the disclosed embodiments may include substrates with seed layers and masked surfaces, which can include semiconductor wafers, printed circuit boards, panels, and the like.

[0061] While the methods and apparatus described herein have many applications, some of which are described below, one example application pertains to forming features on dies of a substrate. In such applications, multiple integrated circuits or other electronic devices are formed on the substrate, where a pattern associated with the electronic devices typically repeats over a certain size scale and shape, e.g., the pattern repeats over multiple dies. After fabricating structures corresponding to features on the electronic devices, the substrate is typically sliced (“diced”) into functionally identical entities (referred to as “die”) before undergoing further packaging operations which may involve other substrates and / or die. It will be understood that the die on the substrate need not be functionally identical entities.

[0062] This disclosure presents systems and methods employing micro-anode array technology for electroplating copper and / or other metals on electronic devices and related structures. Conventionally, electroplating tools for such applications have employed a single anode, and may include one or more additional secondary electrodes, such as few additional secondary electrodes. Additional secondary electrodes may be used to modify the current distribution applied to the entire substrate (e.g., to modify the current directed at a wafer edge to make the entire distribution more uniform). By contrast, a micro-anode array employs a large array of small individual inert anodes, which in some contexts may be considered “pixels,” to direct and control the current distribution in a sub-die size programmable spatial pattern. That pattern can be varied and tuned without hardware modifications for radial and azimuthal and within die or within device current control. The pattern can be modified and adapted to direct current spatially and can be further modified at the local level over the time of an electroplating process. In some implementations, the micro-anode array apparatus rotatesDocket No. LAM1P056WO the substrate in an electrolyte cross-flow field.

[0063] Disclosed herein is a version of micro-anode array electroplating that employs an ionically conductive membrane separator. The membrane separates the transport of oxidation sensitive organic additives (sometimes referred to as “plating additives”) from reaching the oxidizing anode and inhibits the transport of protons and / or oxygen gas or bubbles from reaching the substrate surface.

[0064] As mentioned, conventional electroplating tools often have a single anode source, which may be an active metal such as copper, or in some case an inert anode that oxidizes water. Such tools sometimes employ elements to control the tendency of metal to plate at the edge of the substrates relative to the center due to the limited conductivity of a metal seed layer on the substrate surface. For example, electroplating tools may use a high resistance virtual anode (HRVA) located in close proximity to the substrate surface; the large ionic current resistance added by the HRVA to the overall system resistance made the relative resistance for various path of current to various location on the substrate all very similar and is able to eliminate the bias towards the edge (the “terminal effect”). In some cases, electroplating tools use a HRVA-like element that confines fluid, injected into the side of a gap between the substrate and the top surface of the HRVA, to flow across and parallel to the substrate surface. The shape of the HRVA in some electroplating tools is raised and non-planar, to shape the flow around a substrate holder and seal and create a small (e.g., about 1-2 mm) gap to create high sheer flow. For through-mask patterned substrate plating, intense parallel flow is necessary to create circulatory eddies of flow and associated convection inside recessed cavities.

[0065] Some electroplating cells have a fluid flow separation system including an ionically conductive membrane and membrane support structure located between the anode and the HRVA bottom surface. The membrane prevents fluid that is exposed to the substrate and contains low (e.g., ppm) levels of organic additives in the electrolyte from being exposed to the oxidizing conditions of the anode surface. The organic additives are useful for facilitating bottom-up fill of recesses, for controlling the shape of the bump, and for other properties. The membrane divides the electroplating apparatus into one portion containing a catholyte and the substrate and a second portion containing an anolyte and the anode. The anolyte and catholyte are electrolytes having different compositions.

[0066] The inventors have previously observed that micro-anode array electroplating systems have formed dissolved oxygen gas and may form oxygen bubbles at the anode. Bubbles can create defects by blocking the current from the anode needed at the substrate surface for electroplating. Further, the inventors have observed that some chemical additives in theDocket No. LAM1P056WO electroplating bath were rapidly degraded by exposure to oxygen or exposure to an electrode at the potentials associated with oxygen formation.

[0067] Conceptually, these issues could be removed by introducing a separated anode chamber membrane between the substrate and the anode. Unfortunately, micro-anode array systems cannot simply implement a membrane technology to avoid these problems

[0068] The scale of lateral control of the current is proportional and approximately equal to the separation between the anode source plane and the substrate. Not until the source micro-anode is approximately the size of the gap between the anode and the substrate do individual source anodes provide sufficient resolution control. To be useful in producing die-level features, the gap between the array anode surface and the substrate surface may be smaller than the size of the die, and approximately the same size as the transition between die feature size, densities and pitches. From a practical perspective, that implies a gap of about 1-4 mm is appropriate. This size is also appropriate for producing high speed sheer flow.

[0069] In some embodiments, the issue may be addressed by employing a current-carrying element in conjunction with an ionically conductive membrane. The current carrying element may be configured to transfer a majority of the spatially distinct current produced by microanodes (pixel or combination of pixels sourcing current at one location) to the substrate surface without significant dispersion along the substrate surface. The current carrying element may be an anisotropic ion collimator (AIC). In some embodiments, the AIC has a plurality of channels or pores configured to direct current from the micro-anodes to corresponding locations on the substrate surface.

[0070] An AIC shape, channel configuration, porosity, and other properties may allow the electroplating system to project current from source current locations on a micro-anode array to corresponding locations on the substrate surface. Such AIC, together with an ionically conductive membrane (which inhibits transport of chemicals and bulk liquid), allows the electroplating system to employ two electrolytes and associated regions. The first is a separated anolyte and anode region (sometimes referred to as a separated anode chamber (SAC)) where anolyte is exposed to the micro-anode array and bottom surface of the membrane. The second is a catholyte region, exposed to the substrate surface, the channels in the AIC, and the top surface or the membrane.

[0071] Such electroplating system may have two small gaps substantially or approximately coplanar with the substrate surface and / or the MRVA. A first gap is between the substrate electroplating surface and one side of the AIC and a second gap is between the other side of the AIC, opposite the substrate surface, and a surface of the micro-anode array containing theDocket No. LAM1P056WO exposed anode micro array pixels. The membrane may be adjacent to the AIC surface at the second gap.

[0072] The AIC may be made of a non-electrically conducting material such as glass, plastic, or ceramic. It may contain continuous channels or pores that start at the second gap (for convenience referred to as the bottom of the AIC) and end at the first gap. In some embodiments, the channels or pores within the AIC are completely separated from each another. In some implementations, the ionic resistance in a major axis (parallel to the substrate surface) is greater by about ten times or more than the ionic resistance across a minor axis. In some implementations, the total ionic resistance of the system from the AIC is about 10% or less of the total ionic current resistance between the anode array and the substrate surface. This can be accomplished in part by having the specific conductivity of the catholyte about ten times or greater than the conductivity of the anolyte solution and having a porosity of the AIC of about 20% or greater. The pores at their openings may be small and numerous with a separation distance smaller than a targeted lateral control resolution (e.g., about 0.25 mm diameter and having a spacing of about 1 mm).

[0073] The AIC allows a micro-anode array to be operated at a remote location from the substrate onto which a programmed control distribution of current is directed. This spatial separation between the substrate and the micro-anode array, for instance, allows the shape and surface of the AIC to be tailored to follow the combined substrate and substrate holder contour, to direct current from the anode array across and into edge regions of the substrate and plating area and allow for the location of the source of directed current to be remote and even noncoaxial to the target location. For example, as shown in Figures 8 A and 8B, the AIC may have a planar outer portion 243, a sloped middle portion 245 (that may be with or without channels running through), and a planar or plateau inner portion 247, to direct current across the surface of the wafer as desired, including at the outer edge regions of the wafer. The AIC also allows the electroplating system to have two separate flow loops, one exposed to only the substrate and the other exposed to only the anodes. The membrane can both prevent the mixing and exposure of organic additives in the catholyte from being exposed to the oxidizing surface of the anodes and prevent dissolved oxygen and oxygen bubbles from reaching the catholyte or substrate surface.Electroplating with Micro-Regulated Virtual Anode (MRVA) Arrays

[0074] The present disclosure relates to electroplating metal features on a substrate using a micro-regulated virtual anode (MRVA) array. Electroplating with a micro-regulated virtual anode array provides a high level of control over the spatial distribution of plating thicknesses.Docket No. LAM1P056WOThe micro-regulated virtual anode array can be used to improve plating uniformity on a die level for multiple die layouts on a substrate. The micro-regulated virtual anode array manipulates or otherwise controls an amount of current going to each of a plurality of microregulated virtual anode array elements in the micro -regulated virtual anode array. This creates a pattern in current distribution that can be used to modify plating rates by driving more or less current to regions that require more or less current (e.g., due to variability in local feature density). When the micro-regulated virtual anode array is placed in close proximity to a substrate surface, the electric fields in the electrolyte can be programmed or controlled locally rather than globally as is typical for standard anodes. This control may be based in part on a through-resist pattern of a particular surface layout or die layout. Thus, using the die layout on a substrate, the current distribution in the micro-regulated virtual anode array can be determined. Additionally, the current distribution in the micro -regulated virtual anode array may be adjusted in real-time during electroplating. For example, adjustments in current distribution may be made based at least in part on an angular position and rotational path of a rotating substrate. Additionally, as metal is electroplated within the features, the current applied to the various micro anodes in the array and to the regions of high density versus lower density may be changed over time during the plating process to obtain a more uniform end result. Control over current distribution in the micro-regulated virtual anode array addresses various plating uniformity challenges such as WID non-uniformity.

[0075] Figure 1 illustrates a flow diagram of an example method of electroplating metal features on a semiconductor substrate using a micro-regulated virtual anode array according to some implementations. The operations in a process shown in Figure 1 may be performed in different orders and / or with different, fewer, or additional operations.

[0076] At block 100, a semiconductor substrate is loaded. By way of an example as shown in Figure 2, the semiconductor substrate may be loaded in a substrate load / unload station 230. The semiconductor substrate may be received in an electroplating apparatus with one or more plating stations. In some embodiments, the semiconductor substrate may be loaded in one or more pods or front opening unified pods (FOUPs). In some embodiments, the semiconductor substrate may have a conductive seed layer such as a copper seed layer. The conductive seed layer may be disposed on a material layer such as a dielectric layer. In some embodiments, the substrate may be patterned. The patterned substrate may be patterned with a patterned non- conductive mask layer or patterned photoresist that resides on the conductive seed layer. The patterned substrate may have a plurality of recessed features such that the conductive seed layer is exposed at bottom portions of the recessed features. The semiconductor substrate may be aDocket No. LAM1P056WO partially fabricated semiconductor substrate comprising one or more dice having a distribution of features.

[0077] At block 110, the substrate type and layouts are identified. The semiconductor substrate may contain multiple die. Each die may have the same or different layout of features relative to adjacent dice. In some embodiments, each die may have significant variability in feature density, such as dense regions of features and regions of largely isolated features. Some die may have features having a range of different widths. Some die may have features of different depths including deep features and shallow features. This variability in feature density, depth, width, etc. generally leads to variability in metal thickness distribution after electroplating due to variability of ionic resistance and the resulting current distribution during electroplating.

[0078] WLP interconnects, namely solder bumps, pillars typically capped with solder, and / or redistribution lines (RDLs), are typically formed by through-mask plating. However, depending on the die layout and variations across the die, through-mask plating is generally not uniform and conforms to the die design layout. Variations in die design layout may stem from design rules and chip performance. Some die regions may include features (e.g., bumps) tightly packed together (smaller pitch). Some die regions may include smaller diameter features to further increase feature count. In addition, some die regions may include die streets (non-plateable empty spacing between die) that present themselves as lower area density from a plating perspective; hence it is often typical to observe die edge regions plate locally thicker (i.e., “hot areas”). It is desired in the present disclosure to produce a current distribution sufficiently near the substrate to account for die design layout and compensate for feature variations (e.g., variation in local feature density), thereby producing a desired final metallization thickness uniformity at a die level throughout the entire semiconductor substrate. Though the present disclosure is mainly described in context with and may be implemented in through-mask electroplating applications, it will be understood that the present disclosure is not limited to such applications. For instance, the present disclosure may be applied in non- WLP applications such as damascene or TSV feature filling applications.

[0079] At block 120, the semiconductor substrate may optionally undergo substrate pretreatment. Pre-treatment of the semiconductor substrate may reduce oxides or remove impurities such as organic impurities. In addition, the pre-treatment may involve vacuum surface pre-wetting. By way of an example shown in Figure 2, the semiconductor substrate may be transferred from a substrate load / unload station 230 to a substrate pre-treatment station 210 via robot 250. In some cases, the substrate pre-treatment station 210 is configured as a vacuum backfill station. In some cases, the substrate pre-treatment station 210 is configuredDocket No. LAM1P056WO as an acid pre-wetting station.

[0080] At block 130, the semiconductor substrate is immersed in electrolyte in an anode array plating station (e.g., a station including a MRVA and an AIC as discussed herein). The plating station may also be referred to as an electroplating vessel, electroplating cell, or plating chamber. The plating chamber is configured to contain an electrolyte and one or more anodes while electroplating metal onto the substrate. By way of an example shown in Figure 2, the semiconductor substrate may be transferred from the substrate pre-treatment station 210 to the anode array plating station 220a via robot 250. The anode array plating station 220a may perform electroplating on the semiconductor substrate using a micro-regulated virtual anode array as described below. Electroplating operations may be performed in one or more anode array plating stations 220a, 220b, 220c, and 220d. It will be understood that any of the one or more anode array plating stations 220a, 220b, 220c, and 220d may be replaced by a plating station without a micro-regulated virtual anode array. In turn, some of the plating stations 220a, 220b, 220c, and 220d may include micro-regulated virtual anode arrays and some of the plating stations 220a, 220b, 220c, and 220d may omit micro-regulated virtual anode arrays.

[0081] The semiconductor substrate is cathodically biased via electrical contacts made to the conductive seed layer, and the substrate surface is immersed in the electrolyte containing ions of the metal to be plated. For example, the electrolyte may contain copper ions from a copper salt such as copper sulfate, copper methane sulfonate, copper pyrophosphate, copper propane sulfonate, etc. The electrolyte may include an acid increasing the electrolyte conductivity. Example acids include but are not limited to sulfuric acid and methane sulfonic acid. In some embodiments, the electrolyte includes plating additives. Plating additives modify the surface reaction kinetics and often are useful in improving the current distribution (feature shape and thickness distribution) relative to that which occurs in their absence (improved relative to the primary or electrolyte-resistance-driven current distribution). In the presence of a mask layer, the ionic current distribution is primarily governed by the distribution of the exposed portions of the conductive seed layer on the substrate surface. As a result of non-uniform ionic current distribution, recessed features will be filled differently.

[0082] In some implementations, the electrolyte includes plating additives such as accelerators, suppressors, and levelers. Other plating additives may include carriers and / or ductilizers. In some embodiments, an accelerator may include an alkane chain with at least one mercapto- and one sulfonic acid group or acid-salt. For example, the accelerator may include mercaptopropane sulfonic acid or mercaptoethane sulfonic acid. In some embodiments, the suppressor may include derivatives of polyethylene- and polypropylene-glycols and oxides. InDocket No. LAM1P056WO these or other cases, the suppressor may include at least one material selected from the group consisting of: polyethylene oxide, polypropylene oxide, polyethylene glycol, polypropylene glycol, polyethylene with at least one S- and / or N-containing functional group, and polypropylene oxide with at least one S- and / or N- containing functional group. The composition of additives in the electrolyte may be optimized for use with a micro-regulated virtual anode array in an electroplating process.

[0083] The plating chamber may be designed with an electrolyte injection flow system designed to produce flow parallel to the semiconductor substrate. The flow of electrolyte across the surface of the semiconductor substrate may occur at high velocities. Further, the electrolyte injection flow system is designed so that the flow of electrolyte is parallel to the micro-regulated virtual anode array. The micro-regulated virtual anode array may be positioned in the plating chamber so that there is a thin gap between the micro-regulated virtual anode array and the semiconductor substrate.

[0084] The plating chamber may include a cross-flow manifold to promote cross-flowing of electrolyte across the substrate surface. The cross-flow manifold may be configured to contain an electrolyte flowing between a micro-regulated virtual anode array and the substrate surface. The cross-flow manifold may also be referred to as a flow injection manifold. The flow injection manifold may be a cavity with a series of exit holes around its periphery and under a cross-flow confinement ring. The flow injection manifold may serve to create an azimuthally uniform injection of flow into a cross-flow gap. In an alternative embodiment, spatially distributed electrolyte through holes may be placed in the micro-regulated virtual anode array, allow for the injection of fresh electrolyte to enter a gap from spaces and holes between microregulated virtual anode elements and opposite the gap from the semiconductor substrate, and exiting the gap from the general periphery.Micro-Regulated Virtual Anode (MRVA) Array Features

[0085] In some conventional semiconductor substrate plating chambers having cross-flow manifolds, plating chambers include an ionically resistive element (instead of the microregulated virtual anode array of this present disclosure), such as a channeled ionically resistive plate (CIRP) or a high resistance virtual anode (HRVA) that is placed in close proximity to the semiconductor substrate. The ionically resistive plate is typically a low porosity plate (less than 5% porosity) made of an electrically insulating material, and pores in the electrically insulating material allow for movement of ions through the porous plate towards the cathodically biased semiconductor substrate. The pores or holes in the ionically resistive element would be uniform or regularly distributed and spaced apart. The ionically resistiveDocket No. LAM1P056WO element can provide an additional resistance on the path of ionic current towards the cathodically biased semiconductor substrate.

[0086] In some embodiments, a system includes software or other logic that (a) analyzes a die layout on a substrate to be processed using a MRVA array as described herein and (b) generates an array image for activating a subset of the MRVA array’ s inert anodes to electroplate a pattern corresponding to the die layout.

[0087] Figure 3A depicts a perspective view of an example schematic micro-regulated virtual anode array according to some implementations. Figure 3B depicts a top view of the example schematic micro -regulated virtual anode array of Figure 3 A. The micro-regulated virtual anode array 700 may include a substrate 710 having microelectronic embedded elements 720 and electrical wiring 730. The substrate 710 may include any suitable substrate material such as glass, plastic, ceramic, silicon, or other dielectric material. For example, the substrate 710 can include a dielectric layer such as a polyimide dielectric layer. The microelectronic embedded elements 720 may be inert anodes or dimensionally stable anodes at a surface of the substrate 710. These inert anodes 720 may also be referred to as micro-anode electrodes, microregulated virtual anode elements (MIA elements), anode elements, or micro-anodes. The inert anodes 720 may be arranged in an array on the substrate 710. The inert anodes 720 may be physically and electrically isolated from one another. Each of the inert anodes 720 may include a material such as Pt, Ir, Au, Nb, TiCh. Rut , IrC>2, or PtCb. Current may be delivered to each of the inert anodes 720 via conductive wiring 730 (e.g., copper wiring). A power source (not shown) delivers current to one or more inert anodes 720 through the conductive wiring 730. As shown in Figures 7A and 7B, each of the inert anodes 720 may be individually connected to conductive wiring 730 for independent tunable control.

[0088] In some embodiments, the inert anodes 720 may be arranged in an M x N array of elements. For example, the M x N array of elements may be arranged as a square or rectangular pattern. In some other embodiments, the inert anodes 720 may be arranged in alternative arrangements such as hexagonal or triangular packing arrangements. Size and spacing of inert anodes 720 may be at a sub-mm scale or less than about 1 mm. Spacing between inert anodes 720 may be defined by its pitch, where a pitch of the plurality of inert anodes may be equal to or less than about 1000 pm, equal to or less than about 500 pm, equal to or less than about 300 pm, or between about 100 pm and about 400 pm. The size (e.g., diameter or principal dimension) of each inert anode 720 may be comparable to pitch. In some embodiments, a diameter or a principal dimension of an inert anode 720 in the micro-regulated virtual anode array 700 may be equal to or less than about 800 pm, equal to or less than about 500 pm, equalDocket No. LAM1P056WO to or less than about 300 |am, or between about 50 |am and about 200 |am. In some embodiments, a diameter or a principal dimension of an inert anode 720 is about 5 mm or less. Essentially, micro-sized inert anodes 720 closely packed together model approximately to an infinite number of very small anodes. This allows for finer or more precise control over current distribution in the micro-regulated virtual anode array 700. In some cases, a number of the micro-sized inert anodes 720 may be at least 100, at least 200, at least 500, at least 1000, or at least 2000.

[0089] Figure 4 shows different shapes and arrangements of inert anodes in a micro-regulated virtual anode array according to some implementations. Different shapes can include circular, square, hexagonal, or other polygonal shape. Different arrangements can include square or triangular arrangements. In some embodiments, micro-regulated virtual anode elements 820a may be circular and arranged in a square / rectangular arrangement or array. In some embodiments, micro-regulated virtual anode elements 820b may be square and arranged in a square / rectangular arrangement or array. In some embodiments, micro-regulated virtual anode elements 820c may be hexagonal and arranged in a square / rectangular arrangement or array. In some embodiments, micro-regulated virtual anode elements 820d may be hexagonal and arranged in a hexagonal arrangement or array.

[0090] The control logic or circuitry for turning on or off or otherwise regulating the current to each of the inert anodes, e.g., MRVA controller, is not shown in Figures 7A, 7B, and 8, but is advantageously physically integrated with the micro-regulated virtual anode array 700. The control components may include row and column drivers, ribbon connections, and controller board, buss power, etc.

[0091] Figure 5 illustrates a circuit diagram of example micro-regulated virtual anode array elements with active matrix control circuitry according to some implementations. In some embodiments, each of the inert anodes 920 of a micro-regulated virtual anode array 900 is connected in series to a switch device 910 that either connects or isolates a line (e.g., conductive wiring) from a common power source. Optionally, the switch device 910 may be connected in series with or replaced by a current regulator capable of varying the magnitude of the current being delivered to the anode to which it is connected. As shown in Figure 9, the switch device 910 is referred to as an “element control circuit” and the inert anode 920 is referred to as a “micro anode.” A common power source 930 to some or all of the inert anodes 920 in the micro-regulated virtual anode array 900 may include an electrical bus (labeled “power buss”). In addition to the switch device 910 or element control circuit, circuitry for monitoring and regulating an amount of current flow to each of the inert anodes 920 may be included.Docket No. LAM1P056WO

[0092] The switch device 910 or element control circuit may include one or more of a switching element and a transistor. The element control circuit may be an active matrix element, which may comprise one or more of a transistor, a diode, and a switch (e.g., MEMS or NEMS switch). The element control circuit is coupled to the inert anode 920. The element control circuit is connected to column lines that connect to a column driver 950 and row lines that connect to a row driver 940.

[0093] The switch device 910 or a MRVA controller may be configured to independently electrically access the inert anodes and to generate a non-uniform current distribution over an area of the MRVA array. In various implementations, the non-uniform current distribution may correspond to a pattern to be electroplated on the substrate. In some embodiments, the non- uniform current distribution is based at least in part on global within- wafer (WIW) correction and / or local within-die or within-device corrections.

[0094] A processor (not shown) may be configured to communicate with an array driver, where the array driver includes a column driver 950 (or column driver circuit) and a row driver 940 (or row driver circuit). The column driver 950 and the row driver 940 provide signals to the array of inert anodes 920. The row driver 940 and the column driver 950 address the particular inert anode or plurality of inert anodes 920 by an active matrix addressing scheme. The processor may or may not be physically integrated or co-located with the row and column drivers 940, 950. The processor and row and column drivers 940, 950 may be fabricated via one of several common microelectronics production methods or materials sets, including but not limited to thin film transistor (TFT) technology, silicon-based complementary metal oxide semiconductor (CMOS) technology, organic electronics, or other printed electronics fabrication technology. Current delivered to each micro-regulated virtual anode 920 may be provided continuously or pulsed. The processor and row and column drivers 940, 950 may be configured to deliver power to all pixels simultaneously, or to a subset of pixels in any instant. In some embodiments, the processor and drivers may be capable of delivering power to a fraction, for example one-sixteenth, of the micro -regulated virtual anode array 900 at any time, and power is delivered to the entire array on a time-averaged basis by sequentially powering different fractions, blocks or sub-arrays in a pulsed mode. In another embodiment, the power to the micro-regulated virtual anode array 900 may be rastered across the entire array, or the power may be rastered within one or more blocks or sub-arrays. Such pulsed or rastering implementations potentially decrease the implementation cost of the present disclosure, though in most cases a the expense of metal deposition rate.

[0095] Some or all the components for powering and controlling flow of current to each of theDocket No. LAM1P056WO inert anodes, such as the electrical bus and other power / current flow regulating devices may be located at the periphery of the array area or outside the array area. Figure 6 depicts a top-down view of a schematic illustration of an example micro-regulated virtual anode array for processing a circular semiconductor substrate according to some implementations. In some instances, the manufactured micro-regulated virtual anode array 1000 is produced in a square or rectangular area. As a result, the array area is larger than a circular workpiece or circular substrate. For example, when electroplating on a 300-mm semiconductor substrate, a microregulated virtual anode array 1000 will preferably have a region at least as large as 300 mm in diameter. In some embodiments as shown in Figure 6, the micro-regulated virtual anode array 1000 may be square in shape. Power and control inputs 1030 may be positioned along a periphery of the array area. The power and control inputs 1030, including the electrical bus and row input control 1040 and column input control 1050, are positioned in the plane of and at the periphery of the array area outside a central circular region. The peripheral coated area 1010 in Figure 10 designates the array area for the micro-regulated virtual anode array 1000. The central circular region 1020 in Figure 10 designates the array area for the micro-regulated virtual anode array 1000 that exposes the 300-mm substrate. In some cases, the peripheral coated area 1010 surrounds the central circular region 1020. In some cases, the inert anodes outside the central circular region 1020 are not used. In some embodiments, power and connections may generally pass from the edge to the center of the array. In some other embodiments, power and connections may pass from below a substrate of the micro-regulated virtual anode array 1000 with connections and bus power made from below the plane of the inert anodes. Regardless, the gap region between exposed inert anodes and the semiconductor substrate being electroplated will comprise an electrolyte containing metal ions or other acids and salts, where the electrolyte is a generally corrosive solution.Electroplating Cell Design Examples

[0096] Figure 7 depicts an electroplating cell 101 configured to electroplate copper or other metal onto and / or into features on a substrate 103. During electroplating, substrate 103 may be held by a substrate holder 105, which may, in some embodiments be implemented as a cone and cup design such as described in US Patent No. 9,512,538 issued December 6, 2016, which is incorporated herein by reference in its entirety. During electroplating, substrate 103 serves as the cathode and anodes of a MRVA array 107 serves as the anodes.

[0097] Electroplating cell 101 includes a vessel or housing 117. During electroplating, an electrolyte 109 flows in a path that includes, sequentially, an electrolyte inlet 111, a gap 115 between substrate 103 and MRVA array 109, and an electrolyte outlet 113. As illustrated, theDocket No. LAM1P056WO electroplating solution may exit vessel 117 by overflowing one edge of vessel 117, as depicted on the right side of electroplating cell 101.

[0098] In this embodiment, the electrolyte has a single composition, and it comes in contact with both the anodes of MRVA array 107 and the active surface of substrate 103. As explained elsewhere herein, this situation is known to introduce challenges such as (a) having the oxygen that evolves at the anodes potentially form bubbles that block electroplating on the substrate surface and (b) having the organic additives necessary for desired feature electroplating properties come in contact with the anodes where they oxidize into inactive and potentially detrimental products.

[0099] Figures 8A, 8B, and 8C illustrate embodiments that can address issues that arise by using a MRVA array with a single electroplating solution. These embodiments have separated anolyte and catholyte regions, with the anolyte in contact with the MRVA array but not the substrate, and the catholyte in contact with the substrate but not the MRVA array.

[0100] The examples of Figures 8A, 8B, and 8C have some differences, and in this regard, they represent distinct embodiments, but they also have many similarities, so they will be described together.

[0101] In each of Figures 8A, 8B, and 8C, a corresponding electroplating cell 201a, 201b, and 201c is depicted. In the electroplating cells, a substrate 203 is held in position by wafer holder that includes a cup 205, and a cone, not illustrated. In some embodiments, the cup has a substantially ring shape and configured to contact an outer edge of the substrate while a cone pushes against a backside of the substrate, which is not substantially electroplated. In some implementations, the substrate holder has a seal to seal the wafer at it edge and isolate electrical contacts from exposure to the electrolyte. During electroplating, the electrical contacts contact the perimeter or outer edge of the substrate and thereby apply a cathodic potential to the substrate. In some embodiments, the substrate holder is configured to rotate during electroplating onto the substrate.

[0102] Electroplating cells 201a, 201b, 201c, have a containment vessel 207, which, during electroplating, houses the electrolyte and provides various structural components of the electroplating cell. Cup 205 may contact a portion of containment vessel 207 via a sliding seal 237.

[0103] As indicated, electroplating cells 201a, 201b, and 201c are designed to use two separated electrolytes that have different compositions, an anolyte and the catholyte. An ionically conductive membrane 209 separates the anolyte from the catholyte but allows ionic communication between the anolyte and the catholyte. Details of exemplary membranes willDocket No. LAM1P056WO be discussed below.

[0104] Electroplating cells 201a, 201b, and 201c include a MRVA array 211, which may be supported by a MRVA support 213. Examples of MRVA array features and operation are provided elsewhere herein. Membrane 209 divides the electroplating cells into an anolyte region on the MRVA array side of the cells and a catholyte region on the substrate side of the cells. Some conventional electroplating cell designs employ an anolyte region that is sometimes referred to as a separated anode chamber or SAC. To the extent the term SAC is used herein, refers to a region of a cell in which the anolyte resides and the catholyte does not. As illustrated, membrane 209 may be held in place by a seal 235 that engages with structural elements of containment vessel 207. Seal 235 may be fluid tight and ensure that anolyte and catholyte do not contact one another.

[0105] An anisotropic ion collimator (AIC) 219 is provided adjacent to and, in some embodiments, in contact with membrane 209. While the AIC is described in further detail below, for purposes of this discussion, the AIC may be formed of a relatively rigid material that can hold membrane 209 substantially flat and immobile, even when exposed to high flow rates and high shear conditions. In this way, the membrane 209 maintains a thin gap of consistent dimensions between MRVA array 211 and the MRVA-facing surface of membrane 209. AIC 219 contains a plurality of channels or substantially parallel channels or pores between membrane 209 and a crossflow gap 221.

[0106] In electroplating cells 201a, 201b, and 201c, the anolyte flows in crossflow gap 229 between the MRVA array 211 and the membrane 209, while the catholyte flows in a crossflow gap 221 between the substrate surface 203 and the AIC 219. While the embodiments of electroplating cells 201a, 201b, 201c may employ different configurations for flow paths of the anolyte in the catholyte, they all provide relatively thin flow paths for crossflow gap 229 and crossflow gap 221.

[0107] In some embodiments, the substrate holder is configured to rotate the substrate with respect to the AIC during electroplating. In some such cases, the AIC is rotationally stationary, while the substrate holder rotates.

[0108] Electroplating cell 201a is a relatively simple design in which both the anolyte flow path and the catholyte flow path have no branch points. As shown in Figure 8A, the catholyte flow path includes an inlet 223, crossflow gap 221, and an outlet 225. Similarly, the anolyte has flow inlet 227, crossflow gap 229, and an anolyte flow outlet 231.

[0109] Electroplating cell 201b has a slightly more complex catholyte flow path. As shown, the catholyte flow path includes a collimator purge flow path 233.Docket No. LAM1P056WO

[0110] As shown, purge flow path 233 is fed off the main catholyte flow path. In some cases, an inlet to the collimator purge flow path 233 is located before flow restrictions (not shown) and therefore is provided at a relatively higher pressure. In other cases, the inlet of collimator purge flow path 233 is provided as a branch of flow after the flow restrictors.

[0111] Purge flow path 233 is proximate to membrane 209 and can be at least partially sealed or blocked by the membrane. When the pressure on the anolyte flow path side of membrane 209 is sufficiently greater than the pressure on the purge flow side of the membrane (e.g., the catholyte flow path side), membrane 209 can be forced upwards toward the bottom of AIC 219, restricting the flow of anolyte. By turning the anolyte flow pressure down (or turning off all flow), membrane 209 is deflected “downward” and away from the bottom of AIC 219 and allowing fluid to flow through the gap so created, and outwards and upwards through the channels in AIC 219. This allows for cleaning out the channels in AIC 219.

[0112] As depicted in the perspective illustrated in Figure 8C, electroplating cell 201c may have various anolyte and catholyte flow path features. For example, the catholyte flow path includes a catholyte supply manifold 251 and a catholyte drain 255. Further, the anolyte flow path includes an anolyte inlet 259, an anolyte return manifold 253, and an anolyte outlet 261. In the depicted embodiment, electroplating cell 201c also includes an anolyte chamber 257, which may contain a large volume of anolyte.

[0113] In certain embodiments, the system includes one or more anolyte flow components configured to flow anolyte in a gap between the MRVA array and the AIC. In some implementations, the anolyte flows between the MRVA array and a membrane on the AIC. Anolyte flowing in the gap may flow across the surface of the MRVA. This flow may have various functions including, for example, removing any bubbles such as oxygen gas bubbles that might otherwise accumulate in the gap and interfere with a desired current or potential distribution at the AIC. The components configured to induce the flow may be an anolyte inlet manifold, an anolyte outlet manifold, etc. arranged with respect to the gap to induce anolyte cross flow in the gap.

[0114] Further as depicted in Figure 8C, electroplating cell 201c may have various electrical power and communications components configured to provide power and instructions to the MRVA array and, optionally, for to control current and / or potential to substrate 203 via electrical contacts. Electroplating cell 201c includes a bus power and communication feedthrough 263 for, at least, MRVA array 211.

[0115] It should be understood that various details illustrated in Figures 8A to 8C are not necessary in all embodiments. In most cases, as long as the wafer holder, AIC, membrane, andDocket No. LAM1P056WOMRVA array are arranged in this order and thin stable gaps are provided for the anolyte and catholyte, the depicted features can be varied. For example, the particular containment vessel structure depicted in these figures is non-limiting. For example, the vessel need not have hook shape on top to engage with the cup is not necessary in some embodiments. As another example, a purge flow path as depicted in Figure 8B may be used in many different embodiments that employ a MRVA array, a membrane, and an AIC, without necessarily requiring other features of Figure 8B.

[0116] Figure 9 presents an equivalent circuit representation 301 of an electroplating cell having a MRVA array 303 (or other array of discrete or pixelated anodes), an anolyte gap 305, an ionically conductive membrane 307, an AIC 309, and a catholyte crossflow gap 311 between AIC 309 and a substrate 313. As illustrated, small regions of the anolyte, the membrane 307, and the catholyte act as discrete resistors to ionic conduction.

[0117] From the perspective of a given anode “pixel” 315, its electrical impact should be projected directly onto a corresponding region of substrate 313 without significant lateral dispersion. Assuming that anolyte gap 305 is sufficiently small, channel(s) 317 proximate to anode pixel 315 constrain the ionic current from anode pixel 315 and prevent dispersion. Without the constraining effect of the channel 317, the current from anode pixel 315 would disperse laterally compromise high-resolution electroplating from independently controlled anodes of a MRVA array. The substrate-facing sides of the isolated channels may be viewed as “virtual anodes” powered by the corresponding anode pixels in the MRVA array.

[0118] As shown in equivalent circuit 301, the channels of AIC 309, the anolyte gap 305, and the catholyte crossflow gap 311 define paths of least resistance from individual anode pixels of MRVA array 303 to substrate 313. As illustrated, a desired current path for anode pixel 315 contains resistors 321, 323, 325, and 327 but not other resistors of the equivalent circuit.

[0119] Generally, the resistance to current flow in the plane parallel to the MRVA array surface and substrate surface should be very high to prevent lateral current dispersion. The AIC and thin gaps enable the electroplating cell to programmatically reshape current density to minimize die-level and wafer-level nonuniformity. It enables application of high current where high current is needed, and low current where low current is needed. The current distribution is shaped to match die layout.

[0120] As indicated, the anolyte and catholyte regions are separate. They may each include their own flow circuit. In some embodiments, catholyte enters an injection manifold and manifold restriction from one side of the cell. Azimuthal restrictions in the direction of catholyte flow enable a uniform velocity parallel-to-the- wafer flow over the entire wafer. InDocket No. LAM1P056WO the catholyte flow, catholyte passes into a gap created between the bottom of a substrate surface, and in some designs a peripheral portion of a substrate holder (e.g., a cup). The catholyte in this gap may flow at a high shearing speed (e.g., about 1 m / s or greater). The flowing catholyte exits the gap into a port at the opposite side where it may return to a catholyte reservoir or supply tank.

[0121] A second flow gap is created in the space between a bottom surface of a flexible ion conducting membrane and the top surface of the MRVA array. This gap also supports crossflowing electrolyte, anolyte in this case. The fluid flowing in this region is part of the anolyte flow circuit and is separated and different from the catholyte flow circuit above. In certain embodiments the electrolyte ionic resistance of the anolyte is at least about 50 times greater than that of the catholyte.

[0122] Various parameters associated with the anolyte and catholyte may reduce dispersion or otherwise facilitate projection of the potential distribution of the MRVA array onto the substrate surface. For example, in some embodiments, the anolyte has a resistivity that is at least about 10 times greater than a resistivity of the catholyte, or at least about 20 times greater than a resistivity of the catholyte.

[0123] A suitably small gap between AIC and the MRVA may reduce dispersion in anolyte within the gap. See gap 229 in Figures 8 A and 8B. As an example, the AIC and the MRVA may be separated by a gap of about 1 mm or less or by a gap of about 0.5 mm or less. A suitably small gap between AIC and the substrate may similarly reduce dispersion in the catholyte within such gap. See gap 221 in Figures 8A and 8B. In certain embodiments, during electroplating, a gap between the AIC and the substrate is at most about 4 mm or at most about 3 mm.Anisotropic Ion Collimator

[0124] While Figures 8A, 8B, and 8C illustrate an AIC in cross-section, Figure 10 illustrates a portion of an AIC from a top view (e.g., a planar or plateau portion of an AIC). Sloped portion of the AIC is not shown in Figure 10. As illustrated in Figure 10, an AIC 401 includes a plurality of channels 403 that may be characterized by parameters such diameter and pitch or center-to-center separation. Note that while the channels in Figure 10 are shown with circular cross-sectional shapes, this need not be the case. For example, the shapes may be polygonal (e.g., triangular, rectangular, pentagonal, etc.), elliptical, etc.

[0125] Typically, the AIC is made of a solid, non-electrically conducting material such as glass, plastic, or ceramic. To this end, the channels may have walls made from a dielectric material, which is non-reacting (with catholyte) and non-conducting. The channels of the AIC may beDocket No. LAM1P056WO continuous across the AIC structure. In some embodiments, the channels within the AIC are completely separated from each another. The channel directions may be characterized as anisotropic.

[0126] The major axes of the plurality channels may be oriented in a direction between the substrate and the MRVA. In some cases, the major axes 250, shown in Figures 8A and 8B, are oriented substantially perpendicular to the MRVA and / or the substrate surface. In some cases, the channels have a non-perpendicular angle. For example, the channels may be angled outwards relative to major axes 250, to direct current from more centrally located MRVA array anodes / pixels to more radial regions on the substrate. In some cases, some of the channels in AIC may be substantially perpendicular, while others may be non-perpendicular. In operation, the channels may service to (a) transfer current from a first anode of the MRVA through one or more first channels of the plurality of channels proximate the first anode and to a first location on the substrate, and (b) transfer current from a second anode of the MRVA through one or more second channels of the plurality of channels proximate the second anode and to a second location on the substrate.

[0127] In some implementations, within the channels, the ionic resistance in a major axis (parallel to the wafer surface) is greater by about 10 times or more than the ionic resistance across a minor axis. In some implementations, the total ionic resistance of the electroplating system from the AIC is about 10% or less of the total ionic current resistance between the anode array and the wafer surface. This can be accomplished in part by having the specific conductivity of the catholyte be about 10 times greater or more than the conductivity of the anolyte solution. In some embodiments, the AIC has a porosity of about 20% or greater, about 30% or greater, about 40% or greater, about 50% or greater, about 60% or greater, about 70% or greater, or about 80% or greater. In some examples, the AIC has a porosity of about 20% or greater or about 50% or greater.

[0128] The channels at their openings may be small and numerous with a separation distance smaller than a targeted lateral control resolution (e.g., about 0.25 mm diameter and having a spacing of 1 mm). In some embodiments, each of the plurality of channels, independently, has a diameter of about 1 mm or less or about 0.5 mm or less. In some embodiments, the spacing between adjacent channels in the plurality of channels is about 2 mm or less or about 1 mm or less. In some embodiments, the plurality of channels, independently, has a depth about 50 mm or less, about 25mm or less, about 10 mm or less, or about 5 mm or less.

[0129] In some embodiments, the AIC has about 10,000 channels or more. In some embodiments, the AIC has about 50,000 to 500,000 channels. In some embodiments, the AICDocket No. LAM1P056WO has more 1,500,000 channels or less.

[0130] In some embodiments, the AIC may include a plurality of channels or holes positioned along the sloped portion 245, extending between the MRVA facing surface (e.g., surface opposite the MRVA) and substrate facing surface (e.g., surface opposite the substrate) of the AIC. In some embodiments, channels may not be present the sloped portion 245 of the AIC.

[0131] In some embodiments, the AIC, at its thickest portion (e.g., the inner plateau portion 247), has a thickness (in the direction of the membrane to the substrate) of about 100 mm or less, about 50 mm or less, about 25 mm or less, about 10 mm or less, or about 5 mm or less. In some embodiments, the AIC’s surface opposite and facing the MRVA has a planar profile. In some embodiments, the AIC’s surface that faces the substrate has a non-flat or non-planar profile (e.g., a sloped portion 245). For example, the surface profile may follow the contours of the substrate and its holder such as the cup portion of a cup and cone substrate holder. In some embodiments, the AIC has a planar outer portion 243, a sloped middle portion 245, that may be or without channels running through, and an inner plateau portion 247 coincident with a position of the substrate when held in substrate holder. As examples, see the top or substratefacing surface (e.g., top surface spanning portions 243, 245, and 247) of the AIC in Figures 8 A, 8B, and 8C. In some embodiments, the plateau portion 247 has a thickness that is greater than thickness of the planar outer portion 243. In some embodiments, the sloped portion 245 tapers from the outer portion 243 to the plateau portion 247. In some embodiments, the substrate-facing surface of the AIC follows the contour of the substrate holder. For instance, the sloped portion 245 slopes or extends from the outer portion 243 to the plateau portion 247, proximate the lip seal in the cup assembly. In some embodiments, the sloped portion 245 has the same or a substantially similar slope to the slope of the lip in a cup assembly. In some embodiments, the sloped portion 245 is at least partially parallel to the lip seal. In other embodiments, the sloped portion 245 is at least partially non-parallel to the lip seal. The AIC that follows the contours of the substrate and its holder may allow narrowing of the flow path at the edges of the wafer. The reduced gap is advantageous for improving the resolution and control of the spatial pattern of the current distribution, especially at or near the edges of the substrate, which is otherwise challenging in AIC with a non-contour profile.

[0132] Because of the pressure arising from the anolyte flow can cause the membrane to push upwards on the AIC in the direct towards the substrate, it is important that the AIC can withstand the exerted force and not be substantially deflected or permanently deformed. In the case of a 300mm wafer processing cell, the pressure in the anode chamber and membrane is just 1 psi, the total force on the AIC would be about 110 lbs. Therefore, the pressure within theDocket No. LAM1P056WO anolyte chamber should not be excessive to meet the needs of flowing at a high rate (to remove bubbles and dissolved oxygen) and pushing the membrane upwards against the AIC bottom surface. With the need to maintain the size of both the small anolyte and catholyte gap fixed / constant, the AIC needs to be designed so as to avoid deflection (e.g. deflection held to <0.1mm) or permanent deformation. The AIC thickness, porosity, and material of construction are variables that impact its physical resistance to bowing / deflection. Thicker plates with lower porosity composed of a material having a higher Youngs modulus are preferred. In some embodiments, an AIC composed of glass having a Youngs modulus of greater than 20 GPa. In a particular example meeting the requirement of less than 0.1mm deflection is a AIC composed of glass with a Youngs Modulus of 50 GPa, a thickness of 10 mm, and a porosity of 50%.

[0133] In some regards an AIC may superficially seem similar to a high resistance virtual anode (HRVA) used in some existing electroplating systems such as the SABRE® family of tools from Lam Research Corporation of Fremont, CA. However, unlike systems employing HRVAs, in systems employing AICs, the ionic resistance of the AIC may be low relative to the rest of the system. The porosity of a HRVA is often less than about 5%, and the resistance of the HRVA is often 80% or more of the total system resistance. In contrast, the porosity of an AIC may be greater than about 20% or greater than about 50% and create only a minor increase in the system’s total ionic resistance (less than 10%). Further, the positions of the AIC channels may, at least to some extent, align with positions of micro anodes in a MRVA with which the AIC is used.Ionically Conductive Membrane

[0134] The ionically conductive membrane may be a flexible, compliant, and highly flow restrictive membrane. As mentioned, the ionically conductive membrane may be located between the substrate holder and the MRVA array. The ionically conductive membrane may be located on the MRVA facing surface of AIC. In some embodiments, an ionically conductive membrane and AIC may be separated, i.e., having a small gap between the ionically conductive membrane and AIC. In some embodiments, an ionically conductive membrane and AIC are in contact with one another. In some embodiments, ionically conductive membrane is a unitary piece that extends between the lip seals 235 or between two points more proximate the MRVA and / or AIC. Further, the ionically conductive membrane is configured to fluidically separate, during electroplating onto the substrate, a catholyte in contact with the substrate and an anolyte in contact with the MRVA array.

[0135] In some embodiments, the ionically conductive membrane comprises a cationically conductive ionomer. In some embodiments, the ionically conductive membrane comprises aDocket No. LAM1P056WO hydrogen ion conductive ionomer such as a Nation™. In some embodiments, the ionically conductive membrane comprises a reverse osmosis membrane. In some embodiments, the ionically conductive membrane comprises an ionomer having an average pore size of about 10 nm or less. In some embodiments, the ionically conductive membrane comprises an ionomer having a molecular weight cutoff of about 250 daltons or less.

[0136] In some embodiments, the ionically conductive membrane materials have flowresistant properties, and the AIC functions are combined into one element. For example, the AIC holes can be filled with an ionomer such as a polymeric gel or other nanoporous material. In this case, the current passes through the holes that are filled with a flow resistance yet still ionically conductive materials, thereby allowing current to flow and isolating the catholyte from the anolyte fluids. In preferred embodiments, the material is an ionomer, such as a cationically selective material.Systems including Micro-Regulated Virtual Anode (MRVA) Arrays

[0137] Figure 11 illustrates a schematic diagram of an example virtual anode array electroplating cell in combination with general electroplating cell fluidic and plating controls according to some implementations. The inert anode array electroplating cell 1110 includes a cup assembly with an elastomeric seal and one or more electrical contact members. The cup assembly serves to hold the substrate at its periphery and provide electrical current to the substrate. The inert anode array electroplating cell 1110 further includes a micro-regulated virtual anode array adjacent to the substrate, where the micro-regulated virtual anode array and the substrate is separated by a small gap. A plurality of straightening fins may be positioned around the substrate (not directly under the substrate), where the plurality of straightening fins can have a height defined by the small gap. When electrolyte fluid comes up from an injection manifold, electrolyte fluid turns 90 degrees to provide a lateral flow over the surface of the substrate. This occurs with the assistance of the straightening fins.

[0138] In some embodiments, the virtual anode array electroplating cell 1110 is fluidly coupled to a plating solution reservoir 1190 by inlet and outlet plumbing lines to create a circulatory flow loop. An electroplating system 1100 includes the inert anode array electroplating cell 1110 and the plating solution reservoir 1190. The electroplating system 1100 may further include a recirculation pump 1130, a flow meter 1134, a degasser 1136, cell and reservoir level monitors such as a level sensor 1170, heat exchangers and / or immersion heaters 1160, thermocouple 1150, temperature controller 1180 coupled to the thermocouple 1150 and heat exchangers and / or immersion heaters 1160, and one or more exhaust ports (e.g., side outlets). In some embodiments, the electroplating system 1100 further includes density, pH, and / orDocket No. LAM1P056WO conductivity meters, where such meters may be utilized for bath maintenance 1140. In addition to the aforementioned hardware components, the electroplating system 1100 may further include controllers such as a flow controller 1132 for modifying and controlling the flow, temperature, chemical dosing of additives, acids, bases, etc. of the electrolyte fluid, and / or a micro-regulated virtual anode array controller 1120. A power supply may be electrically coupled to the micro-regulated virtual anode array controller 1120 for supplying current to the micro-regulated virtual anode array. A controller may be configured with instructions or programmed to control one or more of the processes described herein. Such processes may be related to flow direction, timing, substrate rotation, substrate and die layout identification, and current distribution control to the micro-regulated virtual anode array. In some embodiments, an electrochemical metal cation regeneration system is housed within or fluidly coupled to the plating solution reservoir.

[0139] As in any electrochemical cell, an oxidative electrochemical half-reaction will occur at the micro-regulated virtual anode elements. In some embodiments, this half-reaction may result in oxygen evolution, where water is broken into hydrogen ions and oxygen gas (2H2OO2 + 4H++ 4e“). In this embodiment, oxygen gas is generated, and the electrolyte becomes more acidic as hydrogen ions are generated. Metal ions (e.g. copper ions) are consumed from the solution as they are deposited onto the cathode / substrate (2Cu+2+ 4e“ — 2Cu). In some embodiments where all substrates are processed from an electrolyte of nearly the same composition, the depletion of copper ion and decrease in pH resulting from increased hydrogen ions may adversely impact metal plating on the substrate. Bubble generation from oxygen production may also adversely impact metal plating on the substrate. Bubble generation and associated defects from generated oxygen can be mitigated by high flow of a non-oxygen saturated electrolyte near the micro-regulated virtual anode array, e.g. by using a contactor / membrane degasser in the flow loop that is connected to a vacuum and removes dissolved gases from the solution. The acidification and copper depletion can be mitigated by adjusting the electrolyte concentration. This can be done in one of several approaches, of which two approaches are described below with respect to Figures 12 and 13.

[0140] Figure 12 illustrates a schematic diagram of an example inert anode array electroplating cell in combination with a metal oxide dose control unit according to some implementations. An electroplating system 1200 includes a plating cell 1210 in fluid communication with a plating solution reservoir 1270. The plating cell 1210 includes a micro -regulated virtual anode array 1220 (anode) and a semiconductor substrate or workpiece 1230 (cathode). The semiconductor substrate or workpiece 1230 may include patterned features in one or more dies.Docket No. LAM1P056WOThe micro -regulated virtual anode array 1220 may include an array of micro-sized inert anodes configured to provide a desired current distribution over an area of the semiconductor substrate or workpiece 1230. The micro-regulated virtual anode array 1220 and the workpiece 1230 may be separated by a flow gap, where the flow gap may be between about 0.5 mm and about 8 mm, or between about 0.5 mm and about 4 mm. Electrolyte may flow between the workpiece 1230 and the micro-regulated virtual anode array 1220 in a cross-flow manifold region. The electrolyte may enter the cross-flow manifold region through a cell flow inlet 1212 and exit the cross-flow manifold region through a cell flow outlet 1214. The plating cell 1210 is fluidly coupled to the plating solution reservoir 1270 by plumbing line to the cell flow inlet 1212 and plumbing lines to the cell flow outlet 1214, thereby creating a circulatory flow loop. The electrolyte may be recirculated from the plating solution reservoir 1270 to the plating cell 1210 via a recirculation pump 1240. The electroplating system 1200 may further include controllers such as a controller 1250 for modifying and controlling the flow, temperature, chemical dosing of additives, acids, bases, etc. of the electrolyte fluid, and / or a micro-regulated virtual anode array controller. A power supply may be electrically coupled to the controller 1250 for supplying current to the micro-regulated virtual anode array 1220. The controller 1250 may be configured with instructions or programmed to control one or more of the processes described herein. Such processes may be related to flow direction, timing, substrate rotation, substrate and die layout identification, and current distribution control to the micro-regulated virtual anode array 1220.

[0141] As shown in Figure 12, oxidative electrochemical half-reactions may result in decreased pH and increased oxygen generation by the breakdown of water (2H2O O2 + 4H++ 4e ) occurring at the micro-regulated virtual anode elements of the micro-regulated virtual anode array 1220. Concurrently, metal ions (e.g., copper ions) are depleted at the workpiece 1230 by reductive electrochemical half-reactions (2Cu+2+ 4e“ — 2Cu). The acidification and copper depletion may be mitigated by dosing a solution with known concentrations and volumes of electrolyte (preferably of higher copper concentration and lower acid concentration than the plating electrolyte used), and periodically removing excess solution to maintain the overall volume of the system (often referred to as a “bleed and feed” operation). In an alternative embodiment, a material can be added that reacts with the excess acid generated and releases copper ions in the process. In Figure 12, solid metal oxide such as copper oxide is dosed as part of an overall plating system bath composition control. A metal oxide dose control unit 1260 is fluidly coupled to the plating solution reservoir 1270. Using the metal oxide in the stochiometric ratio associated with the reaction leads to a balanced overall bathDocket No. LAM1P056WO composition. For instance, dosing copper oxide reacts with hydrogen ions to produce copper ions and water (4H++ 2CuO — 2Cu+2+ 2H2O). This compensates for copper depletion and acidification in the plating electrolyte. An oxide of the same oxidation state as the metal being plated (Cu+2 / CuO, Ni+2 / NiO, or Sn+2 / SnO) leads to a favorable result because the reaction with the acid generated replaces the metal ion and water consumed and oxygen removed.

[0142] It should be noted that, although not shown in Figures 11A and 12, in some implementations, the virtual anode array electroplating cell may have two electrolyte flow loops (i.e., separated anolyte and catholyte flow loops).

[0143] Figure 13 illustrates a schematic diagram of an example inert anode array electroplating cell in combination with a redox couple according to some implementations. An electroplating system 1300 includes a plating cell 1310 in fluid communication with a plating solution reservoir 1375. The plating cell 1310 includes a micro-regulated virtual anode array 1320 (anode) and a semiconductor substrate or workpiece 1330 (cathode). The workpiece 1330 may include patterned features in one or more dies. The micro-regulated virtual anode array 1320 may include an array of micro-sized inert anodes configured to provide a desired current distribution over an area of the workpiece 1330. The micro-regulated virtual anode array 1320 and the workpiece 1330 may be separated by a flow gap, where the flow gap may be between about 0.5 mm and about 8 mm, or between about 0.5 mm and about 4 mm. Electrolyte may flow between the workpiece 1330 and the micro-regulated virtual anode array 1320 in a crossflow manifold region. The electrolyte may enter the cross-flow manifold region through a cell flow inlet 1312 and exit the cross-flow manifold region through a cell flow outlet 1314. The plating cell 1310 is fluidly coupled to the plating solution reservoir 1375 by plumbing line to the cell flow inlet 1312 and plumbing lines to the cell flow outlet 1314, thereby creating a circulatory flow loop. The electrolyte may be recirculated from the plating solution reservoir 1375 to the plating cell 1310 via a recirculation pump 1340. The electroplating system 1300 may further include controllers such as a controller 1350 for modifying and controlling the flow, temperature, chemical dosing of additives, acids, bases, etc. of the electrolyte fluid, and / or a micro -regulated virtual anode array controller. A power supply may be electrically coupled to the controller 1350 for supplying current to the micro -regulated virtual anode array 1320. The controller 1350 may be configured with instructions or programmed to control one or more of the processes described herein. Such processes may be related to flow direction, timing, substrate rotation, substrate and die layout identification, and current distribution control to the micro-regulated virtual anode array 1320.

[0144] As shown in Figure 13, a soluble ion redox couple may be used. For example, ferrousDocket No. LAM1P056WO ions (Fe+2) can be oxidized to ferric ions (Fe+3) at the various micro-regulated virtual anode electrode surfaces of the micro-regulated virtual anode array 1320. In this embodiment, no gas is produced and the electrolyte pH remains unchanged as no oxygen gas or hydrogen ions are generated. However, the concentration of Fe+3ions will increase over time if means to mitigate it are not included. This can be addressed by either dosing a solution with known concentrations (“bleed and feed”) as described above, or by driving a reverse electrochemical reaction (2Fe+3+ Cu — 2Fe+2+ Cu+2) in an electrochemical cell containing the main plating electrolyte 1375. This can be done as either part of a recirculation loop as shown in Figure 13, or by removing the electrolyte to a separate apparatus and periodically or continuously returning the electrolyte to a main reservoir. As further shown in Figure 13, a membrane, such as a cationic membrane 1380, can optionally be used to separate the active metal anode 1390 (2Cu — Cu+2+ 2e“) and regenerating anode electrolyte 1395 from a regenerating system cathode 1370 (2Fe+3+ 2e“ — 2Fe+2) and main plating electrolyte 1375. This can be useful so as to prevent metal particles that may be generated at the soluble metal anode 1390 from reaching the workpiece 1330, and to avoid organic additive breakdown by exposure of them to the oxidizing surface of the active metal anode 1390.

[0145] Although Figures 12 and 13 does not show separated anolyte and catholyte sections, AIC, or ionically conductive membrane in the electroplating cells, these features would be normally present.

[0146] Returning to Figure 1, at block 140, the anodes in the micro-regulated virtual anode array are energized based at least in part on identified substrate type and layouts. A controller including one or more processors may regulate and direct current to various micro-regulated virtual anode elements of the micro-regulated virtual anode array. Each of the micro-regulated virtual anode elements may be independently controllable and tunable. As such, the microregulated virtual anode elements may be referred to as independently controllable microregulated virtual anode elements. The micro-regulated virtual anode array coupled with its drive circuitry provides a finely spatially resolved tunable array of current sources. The semiconductor substrate may have die layouts having a non-uniform distribution of features. However, it will be understood that in some embodiments, the semiconductor substrate may have die layouts having a uniform distribution of features. In some cases, the semiconductor substrate may have multiple die, where each die has a pattern of features (e.g., region of isolated features and a region of dense features). The feature patterns on each die may exhibit varying density, varying feature sizes, shapes, and depths, and the patterns appearing on one die may vary from those on adjacent die. The micro -regulated virtual anode array placed in proximityDocket No. LAM1P056WO to the semiconductor substrate can produce a current distribution such as a non-uniform current distribution over an area of the semiconductor substrate. In some embodiments, the microregulated virtual anode array placed in proximity to the semiconductor substrate can produce a current distribution such as an uniform current distribution over an area of the semiconductor substrate. Current may be applied to at least two or more micro-regulated virtual anode elements to generate the desired current distribution. In some cases, the micro-regulated virtual anode array can produce a current distribution corresponding to the die layouts having a distribution of features. Accordingly, when electrolyte flows laterally in contact with the substrate and the micro-regulated virtual anode array, the electric fields can be controlled to match a die pattern. More or less current is provided to regions that require more or less current (e.g., due to variability in local feature density), which provides a more uniform plating thickness distribution than would be otherwise possible. Quite simply, electroplating metal features on the semiconductor substrate occurs using a micro-regulated virtual anode array where the current is spatially controlled and varied improves the uniformity of plating distribution relative to having a single anode far away (e.g., more than about 8 mm away) from the substrate surface or relative to an AIC having a uniform current distribution resistance pattern. As a result, metal is plated with a substantially uniform thickness in one or more dies having a distribution of features.

[0147] Control of wafer-level current distribution can also be achieved, for example, by modifying the current from center-to-edge radially, compensating for the terminal effect or compensating for impact of a non-uniform feature thickness profiles. The current distribution can also be controlled to compensate for missing patterned areas, which may also be referred to as “missing die” areas, for example between die streets or edge-of-wafer missing die and feature regions. A particular advantage of being able to control the current to avoid “missing die” areas is that it eliminates the need of filling that space with a “dummy” die to avoid local current loading. Elimination of such dummy edge die eliminates the potential for sealing failures at the edge of the wafer in the missing die region, reduces the material consumption, and reduces the possibility of tin and tin-silver lipseal plating in the area. Thus, in some cases, the current applied to the inert anodes of the micro-regulated virtual anode array may provide a current distribution based on a non-uniform distribution of features in one or more dies. Alternatively or additionally, the current applied to the inert anodes of the micro-regulated virtual anode array may provide a current distribution based on global within- wafer corrections.

[0148] High-resolution die level current distribution control may be achieved for die patterns by controlling or determining at least (a) the pitch (distance) between micro-regulated virtualDocket No. LAM1P056WO anode elements, and (b) the gap between the semiconductor substrate and the micro-regulated virtual anode array. Smaller micro-regulated virtual anode element sizes and spacing can be used, but doing so may come with a tradeoff of increased design, manufacturing, and current distribution control complexity, and the need for small gaps between the micro-regulated virtual anode array and the substrate. Gaps may be equal to or smaller than about four times the micro-regulated virtual anode element feature size so as to lead to improved results relative to using a larger feature. By way of an example, for current control on a 0.25 mm scale, microregulated virtual anode element may have a size (e.g., diameter) and pitch of about 50 pm, and a gap between the micro-regulated virtual anode array and the semiconductor substrate may be about 200 pm. Similarly, when the AIC is part of the cell and system, the same rules for gap and spacing from the AIC surface apply. Gaps smaller than four times the individual AIC hole size are preferred.

[0149] Though the present disclosure is mainly described in context with and may be implemented in through-mask electroplating applications, it will be understood that the present disclosure is not limited to such applications. In some implementations, the present disclosure may be applied in non-WLP applications such as damascene applications or TSV applications. Damascene and TSV processes involve plating that occurs over the entire seeded and exposed surface of the substrate (no masking, but with recess metallized surfaces), and the feature patterns can still have variability in feature density that may be addressed with a microregulated virtual anode array of the present disclosure. More particularly, the micro-regulated virtual anode array and current distribution control in the micro-regulated virtual anode array may be applied in plating metal in damascene and TSV applications or similar applications where local control of the macroscopic current distribution is beneficial. Furthermore, by varying the amount of current as a function of radial position and programming a wafer level anode array current source optimized profile, one can compensate for the effects of a thin seed layer (the so-called “terminal effect”) with this new hardware and process. The process can by quite dynamic for damascene and TSV plating applications. As metal is plated over the general surface, there is a reduction in the resistance of the base layer (seed plus plated field film) over time, and thereby a reduction in the magnitude of the terminal effect correction is required. Therefore, a process with both changing currents with time to compensate for the changing terminal effects, overlaid with a process that is correcting for the local (e.g., die level) feature density effects, is envisioned. Typically, the difference in the current applied at the center versus the wafer edge will decrease over time; when the base metal layer becomes sufficiently thick (theoretically when it is infinitely thick) no correction is required, and the micro-regulatedDocket No. LAM1P056WO virtual anode array will apply a generally uniform center to edge current (with within-die or device variation still applied for within-die or device controlled behavior).

[0150] Figure 14 illustrates a cross-sectional schematic view of an example micro-regulated virtual anode array positioned relative to a semiconductor substrate according to some implementations. The micro-regulated virtual anode array 1620 includes a plurality of microregulated virtual anode elements 1625. The semiconductor substrate 1630 may be a partially fabricated semiconductor substrate having a pattern of features 1660. The pattern of features 1660 may be non-uniformly distributed in one or more dies. The pattern of features 1660 may be disposed on a conductive seed layer 1640 of the semiconductor substrate 1630. Metalcontaining electrolyte may flow between the semiconductor substrate 1630 and the microregulated virtual anode array 1620 in an electroplating cell.

[0151] A pitch between adjacent micro-regulated virtual anode elements 1625 may be defined by p. Each of the micro-regulated virtual anode elements may have a critical dimension (e.g., diameter) defined by d. A gap size between the semiconductor substrate 1630 and the microregulated virtual anode array 1620 may be defined by g. A distance between repeating substrate patterns in the pattern of features 1660 may be defined by L. Current is applied to the microregulated virtual anode elements 1625 in the micro-regulated virtual anode array 1620 to provide a particular current distribution over an area of the semiconductor substrate 1630 having the pattern of features 1660. The area may include an area of repeating layouts of patterned features or repeating substrate patterns, where the repeating substrate patterns may be separated by the distance L. For effective current distribution control, dimensions p (pitch), g (gap size), d (critical dimension), and L (distance between repeating substrate patterns) are optimized. Generally speaking, for effective current distribution control to target variable current to different regions of the semiconductor substrate 1630, p is configured to be less than L, p is configured to be less than g, and d is configured to be less than L. In some embodiments, g is also configured to be less than L. Accordingly, for the ability to effectively target variable currents into regions of different pattern density, dimensionless ratios of g / L and p / L and d / L are each less than 1. To further effectively use the micro-regulated virtual anode elements 1625 for enhanced current control, p is configured to be at least three times less than g, and d is configured to be at least three times less than g. In other words, dimensionless ratios of p / g and d / g are less than 1 / 3. At such dimensions, current distribution control prevents images of discrete anodes.

[0152] Returning to Figure 1, at block 150, electrolyte is flowed laterally across a substrate surface and the semiconductor substrate is rotated while the micro-regulated virtual anode arrayDocket No. LAM1P056WO is energized to achieve a desired spatial and temporal current distribution pattern. As discussed above, substrate rotation may be employed to achieve time average directional flow uniformity, and as a result WIF uniformity and avoid unevenly- shaped features. For instance, if flow fields occur in one direction, then non-uniform feature profiles in recessed features are produced. Even if flow fields occur in multiple directions, non-uniform feature profiles in recessed features can still result. Having the flow field change during the electroplating process can reduce the non-uniformity of feature profiles, but some non-uniformity may still be evident. One technique for achieving improved uniformity within features is to have the flow entering the gap between the semiconductor substrate and the micro-regulated virtual anode array on one side and rotating the semiconductor substrate. Thus, in the present disclosure, the electrolyte may be provided in the plating chamber such that it flows laterally substantially parallel to the plating face of the semiconductor substrate. In such embodiments, the electrolyte flows substantially in one direction entering and exiting the plating chamber at azimuthally opposite positions proximate the perimeter of the chamber. As the electrolyte flows laterally, the semiconductor substrate is rotated. However, it will be understood that alternative techniques may be employed for achieving improved uniformity within features, such as enabling the flow entering the gap between the semiconductor substrate and micro-regulated virtual anode array come from a set of or continuously different directions.

[0153] If the semiconductor substrate is rotated, the applied current to each of the microregulated virtual anode elements in the array may follow the locations of the die features. In other words, the current distribution in the micro-regulated virtual anode array can dynamically change according to the position of die features in a semiconductor substrate even as the semiconductor substrate is rotated. The array-imposed current pattern can follow a timevariable distribution of the optimized target distribution, with the rotation of the semiconductor substrate around a mechanical rotation center. Because the rotation center may move (i.e. the concentricity of the rotation of the micro-regulated virtual anode array to the wafer center may not be perfect), the magnitude and direction of the non-concentricity relative to the rotation center can be determined, and the programmed time-varying array current distribution may be modified over time. By way of an example, prior to starting the electroplating process, the relative center position of the semiconductor substrate to the micro-regulated virtual anode array can be determined and the non-concentricity magnitude and direction can also be determined. The semiconductor substrate is indexed, and rotation of the semiconductor substrate is started and followed by a computer program or controller. The semiconductor substrate is immersed into the plating solution and the plating solution fills the gap betweenDocket No. LAM1P056WO the semiconductor substrate and the micro-regulated virtual anode array. The computer program or controller is configured to turn on power at the power source knowing where the semiconductor substrate and die feature positions are at that point in time. At a set time later (e.g., after 10 ms), the semiconductor substrate shall have rotated a known amount, and the center position of the semiconductor substrate will have shifted by a known amount, allowing the controller to calculate the new die feature location relative to the micro-regulated virtual anode array. The controller can also calculate a new optimal micro-regulated virtual anode element current distribution, decreasing or increasing the various element applied current depending on the calculated requirements, and modifying the current distribution to the new current distribution. This process is repeated as the semiconductor substrate rotates and plating occurs during the entire electroplating process until the target time and / or target film thickness is achieved.

[0154] In some embodiments, the semiconductor substrate may be rotated according to a time base edge shielding, or “smart” spin technique. Such techniques are further discussed in U.S. Patent No. 9,260,793 to Mayer et al., filed September 11, 2014, and titled “ELECTROPLATING APPARATUS FOR TAILORED UNIFORMITY PROFILE,” which is herein incorporated by reference in its entirety and for all purposes. Because die layouts at the edge of a semiconductor substrate may not be uniform and because some portions of the die may have “missing dies,” at certain azimuthal locations, the semiconductor substrate may be slowed down or sped up over a shielded or missing region of an AIC, depending on the die layout or die pattern. This process is sometimes referred to as the “smart spin” technique. As the semiconductor substrate is rotated, a portion of the semiconductor substrate (e.g., missing die) may be encountered that needs to get less current or no current in such spaces. The substrate rotation may initially be slow but then quickly sped up upon encountering the portion of the semiconductor substrate that requires less or no current. Accordingly, the rotation of the semiconductor substrate may be dynamically changed in response to encountering certain die patterns during rotation. Implementations of the “smart spin” technique can be extended to micro-regulated virtual anode array plating methods and apparatuses, by having certain peripheral regions of the micro-regulated virtual anode array missing active anode elements or having them blocked or otherwise shielded. However, because micro-regulated virtual anode array elements can be turned off and / or modulated in current intensity, it will be understood that in some instances, substrate rotation according to “smart” spin techniques may be unnecessary. Specifically, the micro-regulated virtual anode array may be programmed so that missing die regions are programmed to not have inert anodes supplying current to thoseDocket No. LAM1P056WO regions. As rotation occurs, the pattern of low current in the missing die traces the angular rotation of the part. This technique has the advantage over the shielding and rotation speed modulation (“smart spin”) technique in that an inherent time-based flow direction bias associated with dwelling in one region and angular orientation and the related feature shape irregularities that can occur can be avoided.

[0155] In some embodiments, the semiconductor substrate may be rotated so as to stop and dwell at a series of fixed positions in a repeated pattern. For example, the wafer may rotate from one angular position to another quickly (e.g. in less than 0.1s) to a new position, remain at the new position for 1 or more seconds, and then repeat the process over and over until the wafer undergoes one or more full rotations. At each fixed angular position, the wafer is plated with a corresponding pattern by energizing the desired array of anode elements to a target current distribution. The target current distribution may be the same or different for each fixed angular location. The power may be turned off during the motion between fixed positions. The fixed angular positions may be an integral value such that upon executing the process the same angular position is repeated after one, two, or more wafer rotations. For example, angular movements which, when dividing 360 degrees by the movement angle in degrees, results in an integer value, will repeat itself with each rotation stopping that integral value number of time. Examples include 5, 10, 15, 20, 30, and 45 degrees), with 72, 36, 24, 18, 12 and 8 stop locations respectively. This set-of-fixed angular position process has the advantage of requiring less data and signal processing and is less sensitive to current transient that may occur while setting the pixel to a particular current, but the disadvantage of not having to have the current off some period of time while moving between positions (or having some smearing of the target distributions), and less effective averaging the flow field on the plating uniformity relative to the continuously rotating case.The features being plated may be started at a substantially deep feature depth. For example, a 20 pm diameter feature may be 20 pm or 40 pm deep. The mass transfer and ionic (ohmic) resistance to plating inside a deep feature can be significant relative to a resistance governing the distribution of current to an array of plated metal features. So as metal features are plated on the semiconductor substrate, if the anode source position and source distribution remains unchanged, the current distribution across the micro-regulated virtual anode array will also change, due to the reduction in the series resistance from the resistance of mass transfer and electrical (ionic) resistance. Larger or smaller features and features in high versus lower densities, will experience a different relative change of these resistance. Therefore, an optimal applied micro-regulated virtual anode array current distribution for a feature in a 20 pm deep condition is not likely to be the optimal applied microDocket No. LAM1P056WO regulated virtual anode array current distribution when the features are 10 |am or 5 |am deep. Therefore, during the plating process, changing parameters to maintain an instantaneously optimal profile such as changing the micro-regulated virtual anode array programmed / applied current distribution, or changing the array-to- substrate gap, can be used to obtain a desired time-integrated plating non-uniformity result.

[0156] At block 160, the semiconductor substrate may undergo substrate post-treatment. In some embodiments, the substrate post-treatment can include rinsing, drying, and / or cleaning operations in a rinse / dry / clean station. In some embodiments, the substrate post-treatment can include etching in an etching module. Etches may be performed to selectively remove patterned features or non-pattemed features. Removal of patterned features may only remove portions of the patterned features to achieve coplanarity. Thus, the process may include both plating and etching operations.Applications

[0157] The methods and apparatus disclosed herein may be used in any of many different electroplating applications. Some of these applications comprise bottom-up filling of recessed features. Regardless, examples of some applications include forming interconnects within dies (e.g., forming lines and vias via Damascene processing), through silicon via (TSV) processing, wafer level packaging (WLP) processing, panel plating, etc.

[0158] In some electroplating embodiments, a conductive seed layer is formed over the entire surface of the substrate prior to electroplating (typically in damascene and TSV processing), and metal is electroplated over the entirety of the substrate. In other electroplating embodiments, a portion of the seed layer is covered by a non-conducting mask material, such as by photoresist, while another portion of the seed layer is exposed. In such substrates with a partially masked seed layer, electroplating occurs only over the exposed portions of the seed layer while the covered portions of the seed layer are protected from being plated upon. Electroplating on a substrate having a seed layer that is coated with patterned mask material (e.g., photoresist) is referred to as mask plating and is sometimes used in WLP applications.

[0159] Some applications involve a series of steps for forming fine line interconnects and other metallic features. For example, for 3D packaging, WLP applications may involve forming a conductive seed layer on the semiconductor substrate, forming a layer of photoresist on the conductive seed layer, and exposing and developing the layer of photoresist to define a pattern therein, where the pattern typically repeats over a certain size scale and shape, e.g., the pattern repeats over multiple dies.Docket No. LAM1P056WO

[0160] Lines, pads, and pillars are typically plated to create bonds between substrates and to create interconnecting electrical connections within and between die of differing functions. It is generally desirable for electroplating to produce acceptable within-die (WID), within- wafer (WIW), and within-feature (WIF) plating non-uniformity.Electroplating Systems

[0161] The methods described herein may be performed by any suitable system / apparatus. A suitable apparatus includes hardware for accomplishing the process operations and a system controller having instructions for controlling process operations in accordance with the present embodiments. For example, in some embodiments, the hardware may include one or more process stations included in a process tool.

[0162] Figure 15 depicts a simplified view of a multi-chamber electroplating apparatus according to some implementations. The electrodeposition apparatus 1900 can include three separate electroplating modules 1902, 1904, and 1906. The electrodeposition apparatus 1900 can also include three separate modules 1912, 1914, and 1916 configured for various process operations. For example, in some embodiments, one or more of modules 1912, 1914, and 1916 may be a spin rinse drying (SRD) module. In other embodiments, one or more of the modules 1912, 1914, and 1916 may be post-electrofill modules (PEMs), each configured to perform a function, such as edge bevel removal, backside etching, and acid cleaning of substrates after they have been processed by one of the electroplating modules 1902, 1904, and 1906.

[0163] The electrodeposition apparatus 1900 includes a central electrodeposition chamber 1924. The central electrodeposition chamber 1924 is a chamber that holds the chemical solution used as the electroplating solution in the electroplating modules 1902, 1904, and 1906. The electrodeposition apparatus 1900 also includes a dosing system 1926 that may store and deliver additives for the electroplating solution. A chemical dilution module 1922 may store and mix chemicals to be used as an etchant. A filtration and pumping unit 1928 may filter the electroplating solution for the central electrodeposition chamber 1924 and pump it to the electroplating modules.

[0164] A system controller 1930 provides electronic and interface controls required to operate the electrodeposition apparatus 1900. The system controller 1930 (which may include one or more physical or logical controllers) controls some or all of the properties of the electroplating apparatus 1900.

[0165] Signals for monitoring the process may be provided by analog and / or digital input connections of the system controller 1930 from various process tool sensors. The signals for controlling the process may be output on the analog and digital output connections of theDocket No. LAM1P056WO process tool. Non-limiting examples of process tool sensors that may be monitored include mass flow controllers, pressure sensors (such as manometers), thermocouples, optical position sensors, etc. Appropriately programmed feedback and control algorithms may be used with data from these sensors to maintain process conditions.

[0166] A hand-off tool 1940 may select a substrate from a substrate cassette such as the cassette 1942 or the cassette 1944. The cassettes 1942 or 1944 may be front opening unified pods (FOUPs). A FOUP is an enclosure designed to hold substrates securely and safely in a controlled environment and to allow the substrates to be removed for processing or measurement by tools equipped with appropriate load ports and robotic handling systems. The hand-off tool 1940 may hold the substrate using a vacuum attachment or some other attaching mechanism.

[0167] The hand-off tool 1940 may interface with a wafer handling station 1932, the cassettes 1942 or 1944, a transfer station 1950, or an aligner 1948. From the transfer station 1950, a hand-off tool 1946 may gain access to the substrate. The transfer station 1950 may be a slot or a position from and to which hand-off tools 1940 and 1946 may pass substrates without going through the aligner 1948. In some embodiments, however, to ensure that a substrate is properly aligned on the hand-off tool 1946 for precision delivery to an electroplating module, the handoff tool 1946 may align the substrate with an aligner 1948. The hand-off tool 1946 may also deliver a substrate to one of the electroplating modules 1902, 1904, or 1906 or to one of the three separate modules 1912, 1914, and 1916 configured for various process operations.

[0168] An example of a process operation according to the methods described above may proceed as follows: (1) receiving a substrate in an electroplating module, where the substrate includes one or more dies having a non-uniform distribution of features; (2) contacting the substrate with an electrolyte in the electroplating module; and (3) electroplating metal on the substrate using a micro-regulated virtual anode array having a plurality of micro-regulated virtual anode elements, where current is applied to one or more micro-regulated virtual anode elements to achieve a current distribution based at least in part on feature layouts of the one or more dies. In some embodiments, a gap size defined between the substrate and the microregulated virtual anode array is equal to or greater than a pitch defined between micro-regulated virtual anode elements in the array. In some embodiments, contacting the substrate with the electrolyte includes cross-flowing the electrolyte laterally across the surface of the substrate.

[0169] An apparatus configured to allow efficient cycling of substrates through sequential plating, rinsing, drying, and PEM process operations may be useful for implementations for use in a manufacturing environment. To accomplish this, the module 1912 can be configuredDocket No. LAM1P056WO as a spin rinse dryer and an edge bevel removal chamber. With such a module 1912, the substrate would only need to be transported between the electroplating module 1904 and the module 1912 for the copper plating and EBR operations. In some embodiments the methods described herein will be implemented in a system which comprises an electroplating apparatus and a stepper.

[0170] Figure 16 depicts a simplified view of an example electroplating apparatus with different electroplating cells and modules according to some implementations. An alternative embodiment of an electrodeposition apparatus 2000 is schematically illustrated in Figure 16. In this embodiment, the electrodeposition apparatus 2000 has a set of electroplating cells 2007, each containing an electroplating bath, in a paired or multiple “duet” configuration. In addition to electroplating per se, the electrodeposition apparatus 2000 may perform a variety of other electroplating related processes and sub-steps, such as spin-rinsing, spin-drying, metal and silicon wet etching, electroless deposition, pre-wetting and pre-chemical treating, reducing, annealing, electro-etching and / or electropolishing, photoresist stripping, and surface preactivation with a pre-accelerator solution, for example. The electrodeposition apparatus 2000 is shown schematically looking top down in Figure 16, and only a single level or “floor” is revealed in the figure, but it is to be readily understood by one having ordinary skill in the art that such an apparatus, e.g., the Fam SABREO3D tool, can have two or more levels “stacked” on top of each other, each potentially having identical or different types of processing stations.

[0171] Referring once again to Figure 16, the substrates 2006 that are to be electroplated are generally fed to the electrodeposition apparatus 2000 through a front end loading FOUP 2001 and, in this example, are brought from the FOUP to the main substrate processing area of the electrodeposition apparatus 2000 via a front-end robot 2002 that can retract and move a substrate 2006 driven by a spindle 2003 in multiple dimensions from one station to another of the accessible stations — two front-end accessible stations 2004 and also two front-end accessible stations 2008 are shown in this example. The front-end accessible stations 2004 and 2008 may include, for example, pre-treatment stations, and spin rinse drying (SRD) stations. Eateral movement from side-to-side of the front-end robot 2002 is accomplished utilizing robot track 2002a. Each of the substrates 2006 may be held by a cup / cone assembly (not shown) driven by a spindle 2003 connected to a motor (not shown), and the motor may be attached to a mounting bracket 2009. Also shown in this example are the four “duets” of electroplating cells 2007, for a total of eight electroplating cells 2007. A system controller (not shown) may be coupled to the electrodeposition apparatus 2000 to control some or all of the properties of the electrodeposition apparatus 2000. The system controller may be programmed or otherwiseDocket No. LAM1P056WO configured to execute instructions according to processes described earlier herein.

[0172] In some implementations, a controller is part of a system, which may be part of the above-described examples. Such systems can comprise semiconductor processing equipment, including a processing tool or tools, chamber or chambers, a platform or platforms for processing, and / or specific processing components (a wafer pedestal, a gas flow system, etc.). These systems may be integrated with electronics for controlling their operation before, during, and after processing of a semiconductor wafer or substrate. The electronics may be referred to as the “controller,” which may control various components or subparts of the system or systems. The controller, depending on the processing requirements and / or the type of system, may be programmed to control any of the processes disclosed herein, including the delivery of processing gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positional and operation settings, wafer transfers into and out of a tool and other transfer tools and / or load locks connected to or interfaced with a specific system.

[0173] Broadly speaking, the controller may be defined as electronics having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files), defining operational parameters for carrying out a particular process on or for a semiconductor wafer or to a system. The operational parameters may, in some embodiments, be part of a recipe defined by process engineers to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0174] The controller, in some implementations, may be a part of or coupled to a computer that is integrated with, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller may be in the “cloud” or all or a part of a fab host computer system, which can allow for remote access of the wafer processing. The computer may enable remote access to the system to monitor current progress of fabrication operations, examine a history of past fabrication operations, examine trends or performanceDocket No. LAM1P056WO metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process. In some examples, a remote computer (e.g. a server) can provide process recipes to a system over a network, which may include a local network or the Internet. The remote computer may include a user interface that enables entry or programming of parameters and / or settings, which are then communicated to the system from the remote computer. In some examples, the controller receives instructions in the form of data, which specify parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the controller is configured to interface with or control. Thus as described above, the controller may be distributed, such as by comprising one or more discrete controllers that are networked together and working towards a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes would be one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) that combine to control a process on the chamber.

[0175] Without limitation, example systems may include a plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing systems that may be associated or used in the fabrication and / or manufacturing of semiconductor wafers.Examples

[0176] An example of an electroplating system employing a micro-regulated virtual anode (MRVA). The system includes a substrate holder configured to hold a substrate during electroplating onto the substrate; a micro-regulated variable anode (MRVA) array having a plurality of independently electrically addressable inert anodes; and an anisotropic ion collimator (AIC) located between the substrate holder and the MRVA. The AIC includes a solid insulating body with a plurality of channels having axes oriented in a direction between the substrate and the MRVA. The AIC may be configured to (a) transfer current from a first anode of the MRVA through one or more first channels of the plurality of channels proximate to the first anode and to a first location on the substrate, and (b) transfer current from a second anodeDocket No. LAM1P056WO of the MRVA through one or more second channels of the plurality of channels proximate to the second anode and to a second location on the substrate.

[0177] The example system may include one or more of the following features. The substrate holder of the system may include a cup having a substantial ring shape and configured to contact an outer edge of the substrate while a cone pushes against the backside of the substrate, which is not substantially electroplated. In some embodiments, the substrate holder is configured to rotate with respect to the AIC during electroplating onto the substrate.

[0178] In some example systems, the MRVA array may include at least about 100 of the inert anodes. Each of the inert anodes may be or include a noble metal, a semi-noble metal, a mixed metal oxide, or any combination thereof. In some embodiments, each of the inert anodes may include platinum, iridium, gold, niobium, or any combination thereof. In some embodiments, each of the inert anodes may include titanium oxide, ruthenium oxide, iridium oxide, platinum oxide, or any combination thereof.

[0179] In some example systems, each inert anode may have a surface facing the AIC, and where the surface of at least one of the inert anodes has a principal dimension of about 5 mm or less or about 500 pm or less. In some examples, the inert anodes have a pitch defined between adjacent inert anodes in the MRVA of about 500 pm or less.

[0180] In some example systems, the system may further include a MRVA controller, configured to independently electrically access the inert anodes and to generate a non-uniform current distribution over an area of the MRVA array. The non-uniform current distribution corresponds to a pattern to be electroplated on the substrate. In some embodiments, the MRVA controller is further configured to activate a subset of the inert anodes in a manner corresponding to a die layout on the substrate. The non-uniform current distribution is based, at least in part, on global within- wafer (WIW) corrections and / or local within-die corrections.

[0181] In some example systems, a system includes software or other logic that (a) analyzes a die layout on a substrate to be processed using a MRVA array as described herein and (b) generates an array image for activating a subset of the MRVA array’s inert anodes to electroplate a pattern corresponding to the die layout.

[0182] In some example systems, the system may further include an ionically conductive membrane. The ionically conductive membrane is configured to fluidically separate, during electroplating onto the substrate, a catholyte in contact with the substrate and an anolyte in contact with the MRVA array.

[0183] In some example systems, the anisotropic ion collimator (AIC) is located between the substrate holder and the ionically conductive membrane.Docket No. LAM1P056WO

[0184] In some example systems, the ionically conductive membrane may include a cationically conductive ionomer. In some embodiments, the ionically conductive membrane may include a hydrogen ion conductive polymer. In some embodiments, the ionically conductive membrane may include an ionomer having an average pore size of about 10 nm or less, and a molecular weight of about 250 daltons or less.

[0185] In some example systems, the AIC has a solid insulating body that may include glass, plastic, ceramic, or any combinations thereof.

[0186] In some example systems, AIC has a porosity of at least about 20% or at least about 50%. The thickness of AIC may be about 10 mm or less.

[0187] In some example systems, the AIC has a raised top surface and an overall plateau shape coincident with the position of the substrate when held in a substrate holder.

[0188] In some example systems, each of the plurality of channels in AIC independently has a diameter of about 1.5 mm or less. In some embodiments, each of the plurality of channels independently has a diameter of about 0.5 mm or less. In some embodiments, each of the plurality of channels has an anisotropic orientation, and each anisotropic channel having a thin wall may include a dielectric material where the thin walls are non-reacting and nonconducting. In some embodiments, each of the plurality of channels independently has a depth of about 5mm or more. In some embodiments, each of the plurality of channels independently has a depth of about 10mm or more. The center-to-center spacing between adjacent channels in the plurality of channels is about 2 mm or less. In some embodiments, the spacing between adjacent channels in the plurality of channels is about 1 mm or less. The AIC may include about 30,000 to 500,000 or more channels.

[0189] In some example systems, the AIC and the MRVA are separated by a gap of about 1 mm or less.

[0190] In some example systems, the system is configured to provide, during electroplating, a gap between the AIC surface and the substrate of at most about 4 mm.

[0191] In some example systems, the system may further include an anolyte flow loop configured to flow the anolyte in the gap between the MRVA array and the ionically conductive membrane. The anolyte flow loop may include: an anolyte outlet stream, where the anolyte outlet stream may include hydrogen ions; an anolyte inlet stream may include metal ions; and a plating solution reservoir may include a metal oxide, where the plating solution reservoir is configured to receive the anolyte outlet stream and provide the anolyte to the anolyte inlet stream in the anolyte flow loop; and where, during operation, the metal oxide and the hydrogen ions react to form the metal ions in the plating solution reservoir. In some embodiments, theDocket No. LAM1P056WO metal oxide is a copper(II) oxide and / or a copper(II) hydroxide and the metal ions are Cu(II) ions. In some embodiments, the anolyte has a resistivity that is at least about 20 times greater than a resistivity of the catholyte.

[0192] In some example systems, the system further includes an anolyte inlet and / or an anolyte manifold configured to flow the anolyte in a gap between the MRVA array and the AIC. In some embodiments, the anolyte inlet and / or the anolyte manifold is configured to flow the anolyte substantially uniformly across the gap between the MRVA array and the AIC

[0193] In some example systems, the system may include a catholyte flow loop configured to flow the catholyte adjacent to the substrate and the AIC. In some embodiments, the system may include a cross-flow injection manifold configured to flow the catholyte in a gap between the AIC and the substrate. In some embodiments, the system may further include an inlet and an outlet configured to cause the catholyte to flow across the face of the substrate during electroplating. In some embodiments, the second inlet and the second outlet may be present and are configured to cause the catholyte to purge the plurality channels of the AIC and / or a region between the AIC and the ionically conductive membrane.

[0194] Another example includes a method of electroplating metal features on a substrate. The method includes receiving a substrate in a cathode region of an electroplating chamber, where the cathode region may include a substrate holder and an anisotropic ion collimator (AIC). The AIC may include a solid insulating body with a plurality of channels having axes oriented in a direction between the substrate and a micro-regulated virtual anode (MRVA) array. The method further includes flowing catholyte over the substrate in the cathode region; flowing anolyte over the MRVA array where MRVA array may include a plurality of inert anodes in an anode region of the electroplating chamber, and the anode region is separated from the cathode region by an ionically conductive membrane. The method also includes applying current to two or more inert anodes of the (MRVA) array to provide a non-uniform current distribution over an area of the substrate to electroplate the metal features on the substrate. The AIC (a) transfers current from a first anode of the MRVA through one or more first channels of the plurality of channels proximate to the first anode and to a first location on the substrate, and (b) transfers current from a second anode of the MRVA through one or more second channels of the plurality of channels proximate to the second anode and to a second location on the substrate.

[0195] The example method may further includes: flowing the anolyte from the anode region to a plating solution reservoir via an anolyte outlet stream, where the anolyte outlet stream may include hydrogen ions and the plating solution reservoir may include a metal oxide; reacting the metal oxide and the hydrogen ions to form metal ions. The method includes flowing theDocket No. LAM1P056WO anolyte from the plating solution reservoir to the anode regions via an anolyte inlet stream that may include the metal ions. The metal oxide is a copper (II) oxide and or copper (II) hydroxide and the metal ions are Cu(II) ions.

[0196] The example method may include one or more of the following features. The substrate holder may include a cup having a substantial ring shape and configured to contact an outer edge of the substrate while a cone pushes against the backside of the substrate, wherein the backside which is not substantially electroplated. In some embodiments, the substrate holder is configured to rotate with respect to the AIC during electroplating onto the substrate.

[0197] In some examples of the method, the MRVA array may include at least about 100 of the inert anodes. Each of the inert anodes may be or include a noble metal, a semi-noble metal, a mixed metal oxide, or any combination thereof. In some embodiments, each of the inert anodes may include platinum, iridium, gold, niobium, titanium, or any combination thereof. In some embodiments, each of the inert anodes may include titanium oxide, ruthenium oxide, iridium oxide, platinum oxide, or any combination thereof.

[0198] In some embodiments, each inert anode may have a surface facing the AIC, and where the surface of at least one of the inert anodes has a principal dimension of about 5 mm or less or about 500 pm or less.

[0199] In some examples of the method, the inert anodes have a pitch defined between adjacent inert anodes in the MRVA of about 500 pm or less.

[0200] In some examples of the method, the method may further involve a MRVA controller, configured to independently electrically access the inert anodes and to generate a non-uniform current distribution over an area of the MRVA array. The non-uniform current distribution corresponds to a pattern to be electroplated on the substrate. In some embodiments, the MRVA controller is further configured to activate a subset of the inert anodes in a manner corresponding to a die layout on the substrate. The non-uniform current distribution is based, at least in part, on global within- wafer (WIW) corrections and / or local within-die corrections.

[0201] In some examples of the method, the method may further include an ionically conductive membrane. The ionically conductive membrane is configured to fluidically separate, during electroplating onto the substrate, a catholyte in contact with the substrate and an anolyte in contact with the MRVA array.

[0202] In some examples of the method, the anisotropic ion collimator (AIC) is located between the substrate holder and the ionically conductive membrane.

[0203] In some examples of the method, the ionically conductive membrane may include a cationically conductive ionomer. In some embodiments, the ionically conductive membraneDocket No. LAM1P056WO may include a hydrogen ion conductive polymer. In some embodiments, the ionically conductive membrane may include an ionomer having an average pore size of about 10 nm or less, and a molecular weight of about 250 daltons or less.

[0204] In some examples of the method, the AIC has a solid insulating body that may include glass, plastic, ceramic, or any combinations thereof.

[0205] In some examples of the method, AIC has a porosity of at least about 20% or at least about 50%. The thickness of AIC may be about 10 mm or less.

[0206] In some examples of the method, the AIC has a raised top surface and an overall plateau shape coincident with the position of the substrate when held in a substrate holder.

[0207] In some examples of the method, each of the plurality of channels in AIC independently has a diameter of about 1 mm or less. In some embodiments, each of the plurality of channels independently has a diameter of about 0.5 mm or less. In some embodiments, each of the plurality of channels has an anisotropic orientation, and each anisotropic channel having a thin wall may include a dielectric material where the thin walls are non-reacting and nonconducting. In some embodiments, each of the plurality of channels independently has a depth of about 5mm or more. In some embodiments, each of the plurality of channels independently has a depth of about 10mm or more. The spacing between adjacent channels in the plurality of channels is about 2 mm or less. In some embodiments, the spacing between adjacent channels in the plurality of channels is about 1.5 mm or less. The AIC may include about 50,000 to 500,000 or more channels.

[0208] In some examples of the methods, the AIC and the MRVA are separated by a gap of about 1 mm or less.

[0209] In some examples of the method, the method further includes flowing anolyte, where an anolyte inlet and / or an anolyte manifold configured to flow the anolyte in a gap between the MRVA array and the AIC. In some embodiments, the anolyte inlet and / or the anolyte manifold is configured to flow the anolyte substantially uniformly across the gap between the MRVA array and the AIC

[0210] In some examples of the method, the method may include flowing catholyte, where the catholyte flows adjacent to the substrate and the AIC. In some embodiments, flowing catholyte may include a cross-flow injection manifold configured to flow the catholyte in a gap between the AIC and the substrate. In some embodiments, flowing catholyte may involve an inlet and an outlet configured to cause the catholyte to flow across the face of the substrate during electroplating. In some embodiments, the second inlet and the second outlet may be used toDocket No. LAM1P056WO purge the catholyte from the plurality channels of the AIC and / or a region between the AIC and the ionically conductive membrane.Conclusion

[0211] In the foregoing description, numerous specific details are set forth to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail to not unnecessarily obscure the disclosed embodiments. While the disclosed embodiments are described in conjunction with the specific embodiments, it will be understood that it is not intended to limit the disclosed embodiments.

[0212] Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and apparatus of the present embodiments. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein.

Claims

Docket No. LAM1P056WOCLAIMSWhat is claimed is:

1. A system comprising: a substrate holder configured to hold a substrate during electroplating onto the substrate; a micro-regulated virtual anode (MRVA) array comprising a plurality of independently electrically addressable inert anodes; and an anisotropic ion collimator (AIC) located between the substrate holder and the MRVA, wherein the AIC comprises a solid insulating body with a plurality of channels having axes oriented in a direction between the substrate and the MRVA and configured to (a) transfer current from a first anode of the MRVA through one or more first channels of the plurality of channels proximate the first anode and to a first location on the substrate, and (b) transfer current from a second anode of the MRVA through one or more second channels of the plurality of channels proximate the second anode and to a second location on the substrate.

2. The system of claim 1, wherein the substrate holder comprises a cup having a substantially ring shape and configured to contact an outer edge of the substrate while a cone pushes against a backside of the substrate, which is not substantially electroplated.

3. The system of claim 1, wherein the substrate holder is configured to rotate relative to the AIC during electroplating onto the substrate.

4. The system of claim 1, wherein the MRVA array comprises at least about 100 of the inert anodes.

5. The system of claim 1, wherein each of the inert anodes comprises a noble metal, a semi-noble metal, a mixed metal oxide, or any combination thereof.

6. The system of claim 1, wherein the inert anodes each have a surface facing the AIC, and wherein said surface of at least one of the inert anodes has a principal dimension of about 5 mm or less.Docket No. LAM1P056WO7. The system of claim 1, wherein each of the inert anodes has a surface facing the AIC, and wherein said surface of at least one of the inert anodes has a principal dimension of about 500 pm or less.

8. The system of claim 1, wherein the inert anodes have a pitch defined between adjacent inert anodes in the MRVA of about 500 pm or less.

9. The system of claim 1, further comprising a MRVA controller configured to independently electrically access the inert anodes and to generate a non-uniform current distribution over an area of the MRVA array.

10. The system of claim 9, wherein the non-uniform current distribution corresponds to a pattern to be electroplated on the substrate.

11. The system of claim 10, wherein the MRVA controller is further configured to activate a subset of the inert anodes in a manner corresponding to a die layout on the substrate.

12. The system of claim 1, further comprising an ionically conductive membrane located between the substrate holder and the MRVA array, wherein the ionically conductive membrane is configured to fluidically separate, during electroplating onto the substrate, a catholyte in contact with the substrate and an anolyte in contact with the MRVA array.

13. The system of claim 12, wherein the anisotropic ion collimator (AIC) is located between the substrate and the ionically conductive membrane.

14. The system of claim 12, wherein the ionically conductive membrane comprises a cationically conductive ionomer.

15. The system of claim 1, wherein the solid insulating body of the AIC comprises glass, plastic, ceramic, or any combination thereof.

16. The system of claim 1, wherein AIC has a porosity of at least about 20%, or at least 50%.Docket No. LAM1P056WO17. The system of claim 1, wherein the AIC has a thickness of about 10 mm or less.

18. The system of claim 1, wherein the AIC has a raised top surface and an overall plateau shape coincident with a position of the substrate when held in substrate holder.

19. The system of claim 1, wherein each of the plurality of channels, independently, has a diameter of about 1 mm or less.

20. The system of claim 1, wherein each of the plurality of channels, independently has a depth about 5mm or more.

21. The system of claim 1, wherein the spacing between adjacent channels in the plurality of channels is about 2 mm or less.

22. The system of claim 1, wherein the AIC comprises about 50,000 to 500,000 channels.

23. The system of claim 1, wherein the AIC and the MRVA are separated by a gap of about 1 mm or less.

24. The system of claim 1, wherein the system is configured to provide, during electroplating, a gap between the AIC and the substrate of at most about 4 mm.

25. The system of claim 12, further comprises an anolyte flow loop configured to flow the anolyte in a gap between the MRVA array and the ionically conductive membrane.

26. The system of claim 1, further comprising an anolyte inlet and / or an anolyte manifold configured to flow the anolyte in a gap between the MRVA array and the AIC.

27. The system of claim 1, further comprising a catholyte flow loop configured to flow the catholyte adjacent to the substrate and the AIC.

28. The system of claim 1, further comprising a cross-flow injection manifold configured to flow a catholyte in a gap between the AIC and the substrate.Docket No. LAM1P056WO29. The system of claim 1 , further comprising an inlet to and an outlet from a region between the substrate and the AIC, wherein the inlet and outlet are configured to cause a catholyte to flow across a face of the substrate during electroplating.

30. A system comprising: a substrate holder configured to hold a substrate during electroplating onto the substrate; an anode array comprising a plurality of independently electrically addressable inert anodes; and an ion collimator located between the substrate holder and the anode array, wherein the ion collimator comprises a insulating body with a plurality channels having axes oriented in a direction between the substrate and the anode array and configured to (a) transfer current from a first anode of the anode array through one or more first channels of the plurality of channels proximate the first anode and to a first location on the substrate, and (b) transfer current from a second anode of the anode array through one or more second channels of the plurality of channels proximate the second anode and to a second location on the substrate.

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