Display panel and control method therefor, and display apparatus

Abstract

Provided are a display panel and a control method therefor, and a display apparatus, which belong to the technical field of display. The display panel comprises a substrate (10), a plurality of pixels (2), and a plurality of first gate driving lines (30). The maximum light emission angle of sub-pixels (21) in first pixels (2a) is less than the maximum light emission angle of sub-pixels (21) in second pixels (2b). A plurality of first sub-pixel groups (20a) comprise a plurality of first-type sub-pixel groups (201) and a plurality of second-type sub-pixel groups (202) alternately arranged in a first direction. All sub-pixels (21) in the first-type sub-pixel groups (201) are the sub-pixels (21) in the first pixels (2a), and all sub-pixels (21) in the second-type sub-pixel groups (202) are the sub-pixels (21) in the second pixels (2b). The power consumption of the display panel in an anti-peeping mode can be reduced.

Description

Display panel, control method thereof, and display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display panel, its control method, and a display device. Background Technology

[0002] With the continuous development of display technology, people's needs for display methods are becoming increasingly diversified. When using display devices, sometimes it is desirable to share the displayed information with others, while at other times it is desirable to keep the displayed information confidential. When confidentiality is desired, the display device needs to have a privacy protection function. Summary of the Invention

[0003] This disclosure provides a display panel, its control method, and a display device, which can reduce the power consumption of the display panel in privacy mode. The technical solution is as follows:

[0004] On one hand, a display panel is provided, comprising a substrate, a plurality of pixels, and a plurality of first gate driving lines. The plurality of pixels are arranged in an array on the substrate. Each pixel includes a plurality of sub-pixels. The plurality of pixels includes a plurality of first pixels and a plurality of second pixels. The maximum light emission angle of a sub-pixel in a first pixel is smaller than the maximum light emission angle of a sub-pixel in a second pixel. The sub-pixels included in the plurality of pixels comprise a plurality of first sub-pixel groups arranged sequentially along a first direction. Each first sub-pixel group includes a plurality of sub-pixels arranged sequentially along a second direction. The first direction and the second direction intersect. The plurality of first sub-pixel groups include a plurality of first-type sub-pixel groups and a plurality of second-type sub-pixel groups arranged alternately along the first direction. The plurality of sub-pixels in the first-type sub-pixel groups are all sub-pixels of the first pixels, and the plurality of sub-pixels in the second-type sub-pixel groups are all sub-pixels of the second pixels. The plurality of first gate driving lines are located on the substrate, and each first gate driving line extends along the second direction. Each first gate driving line is electrically connected to a plurality of sub-pixels in a first sub-pixel group.

[0005] Optionally, the first gate driving line includes at least one of a light emission control line and a scan line.

[0006] Optionally, the display panel further includes a plurality of reset control lines located on the substrate, each of which extends along the second direction; the plurality of reset control lines include a plurality of first reset control lines and a plurality of second reset control lines, each of the first reset control lines being electrically connected to a plurality of sub-pixels in a first type sub-pixel group, each of the second reset control lines being electrically connected to a plurality of sub-pixels in a second type sub-pixel group, and the waveforms of the reset control signals provided by at least one first reset control line and at least one second reset control line being identical.

[0007] Optionally, the waveforms of the reset control signals provided by each of the first reset control lines and the adjacent second reset control lines are the same.

[0008] Optionally, the sub-pixels included in the plurality of pixels include a plurality of second sub-pixel groups arranged sequentially along the second direction, each second sub-pixel group including a plurality of sub-pixels arranged sequentially along the first direction, and the second sub-pixel group including sub-pixels in a plurality of first-type sub-pixel groups and a plurality of second-type sub-pixel groups arranged alternately along the first direction; the display panel further includes a plurality of data lines located on the substrate, and each data line extending along the first direction, and each data line being electrically connected to a plurality of sub-pixels in a second sub-pixel group.

[0009] Optionally, multiple sub-pixels in the second sub-pixel group have the same color.

[0010] Optionally, the plurality of second sub-pixel groups include a plurality of third-type sub-pixel groups and a plurality of fourth-type sub-pixel groups arranged alternately along the second direction. Each third-type sub-pixel group includes a plurality of first-color sub-pixels and a plurality of third-color sub-pixels arranged alternately along the first direction. Each fourth-type sub-pixel group includes a plurality of second-color sub-pixels arranged sequentially along the first direction.

[0011] Optionally, the plurality of first pixels and the plurality of second pixels are arranged alternately in a third direction and a fourth direction, the third direction and the fourth direction intersect each other, and the third direction intersects both the first direction and the second direction, and the fourth direction intersects both the first direction and the second direction.

[0012] Optionally, each sub-pixel in the pixel includes a first color sub-pixel, two second color sub-pixels and a third color sub-pixel, and in each pixel, the first color sub-pixel, the two second color sub-pixels and the third color sub-pixel are arranged sequentially along the second direction.

[0013] Optionally, each sub-pixel includes a light-emitting unit. Each sub-pixel in each pixel includes a first color sub-pixel, two second color sub-pixels, and a third color sub-pixel. In each pixel, the line connecting the center of the orthographic projection of the light-emitting unit of the first color sub-pixel on the substrate and the center of the orthographic projection of the light-emitting unit of the third color sub-pixel on the substrate intersects the line connecting the center of the orthographic projection of the light-emitting units of the two second color sub-pixels on the substrate. The extension direction of the line connecting the center of the orthographic projection of the light-emitting unit of the first color sub-pixel on the substrate and the center of the orthographic projection of the light-emitting unit of the third color sub-pixel on the substrate is one of the first direction and the second direction. The extension direction of the line connecting the center of the orthographic projection of the light-emitting units of the two second color sub-pixels on the substrate is the other of the first direction and the second direction.

[0014] Optionally, the substrate has a plurality of pixel regions arranged in an array, the plurality of pixel regions including a plurality of first pixel regions and a plurality of second pixel regions, each first pixel being located in a first pixel region and each second pixel being located in a second pixel region; each sub-pixel includes a light-emitting unit and a color resist block stacked sequentially along a direction away from the substrate; the display panel further includes a plurality of dimming structures, each dimming structure being located in a first pixel region and between the light-emitting unit and the color resist block, the side of the dimming structure away from the substrate having a plurality of first openings; a portion of each color resist block in the first pixel region is located in one of the first openings, and the refractive index of the dimming structure is less than the refractive index of the color resist block.

[0015] On the other hand, a control method for a display panel is provided for controlling any of the aforementioned display panels. The control method includes: when the display panel is in a shared mode, controlling the light emission of sub-pixels in the first type of sub-pixel group and the second type of sub-pixel group through the first gate driving line to control the light emission of sub-pixels in the first pixel and the second pixel; and when the display panel is in a privacy mode, controlling the light emission of sub-pixels in the first type of sub-pixel group through the first gate driving line to control the light emission of sub-pixels in the first pixel.

[0016] Optionally, the light emission efficiency of the sub-pixels in the first pixel is greater than that of the sub-pixels in the second pixel; the step of controlling the light emission of sub-pixels in the first type of sub-pixel group and the second type of sub-pixel group through the first gate driving line when the display panel is in the shared mode includes: when the display panel is in the shared mode, controlling the light emission unit of the target color in the first pixel to emit light at a first brightness, and controlling the light emission unit of the target color in the second pixel to emit light at a second brightness, wherein the second brightness is greater than the first brightness.

[0017] Optionally, when the display panel is in privacy mode, controlling the light emission of sub-pixels in the first type of sub-pixel group through the first gate driving line includes: when the display panel is in privacy mode, controlling the light-emitting unit of the target color in the first pixel to emit light at a third brightness, wherein the third brightness is different from the first brightness.

[0018] In another aspect, a display device is provided, comprising any of the aforementioned display panels and a power supply, wherein the display panel is electrically connected to the power supply.

[0019] The beneficial effects of the technical solutions provided in this disclosure are:

[0020] In this embodiment, each first gate driving line is electrically connected to multiple sub-pixels in a first sub-pixel group. The multiple first sub-pixel groups include multiple first-type sub-pixel groups and multiple second-type sub-pixel groups arranged alternately along a first direction. Multiple sub-pixels in the first-type sub-pixel groups are all sub-pixels of the first pixel, and multiple sub-pixels in the second-type sub-pixel groups are all sub-pixels of the second pixel. The first gate driving line can input a GOA signal to control the on / off state of transistors, thereby controlling the light-emitting state of sub-pixels in the first-type and second-type sub-pixel groups, and enabling the display panel to switch between privacy mode and sharing mode. Furthermore, in privacy mode, since the sub-pixels in the second pixel do not emit light, the voltage of the GOA signal provided by the first gate driving line electrically connected to the multiple sub-pixels in the second-type sub-pixel group can be the off voltage. This reduces the logic power consumption caused by voltage jumps between the on and off voltages of the GOA signal provided by the first gate driving line, thus reducing the power consumption of the display panel in privacy mode. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 is a schematic diagram of the structure of a display panel provided in an embodiment of this disclosure;

[0023] Figure 2 is a schematic block diagram of a driving circuit provided in an embodiment of this disclosure;

[0024] Figure 3 is a schematic diagram of a pixel circuit provided in an embodiment of this disclosure;

[0025] Figure 4 is a circuit diagram of a pixel circuit provided in an embodiment of this disclosure;

[0026] Figure 5 is a signal timing diagram of a pixel circuit provided in an embodiment of this disclosure;

[0027] Figure 6 is a schematic diagram of another display panel provided in an embodiment of this disclosure;

[0028] Figure 7 is a schematic diagram of the structure of another display panel provided in an embodiment of this disclosure;

[0029] Figure 8 is a schematic diagram of the structure of another display panel provided in an embodiment of this disclosure;

[0030] Figure 9 is a schematic diagram of the structure of another display panel provided in an embodiment of this disclosure;

[0031] Figure 10 is a schematic diagram of the structure of another display panel provided in an embodiment of this disclosure;

[0032] Figure 11 is a schematic diagram of the structure of another display panel provided in an embodiment of this disclosure;

[0033] Figure 12 is a schematic diagram of the structure of another display panel provided in an embodiment of this disclosure;

[0034] Figure 13 is a schematic diagram of the arrangement of light-emitting units in a display panel according to an embodiment of the present disclosure;

[0035] Figure 14 is a schematic diagram of the structure of another display panel provided in an embodiment of this disclosure;

[0036] Figure 15 is a partial structural diagram of a display panel in the first pixel region according to an embodiment of the present disclosure;

[0037] Figure 16 is a partial structural schematic diagram of a display panel in the second pixel area according to an embodiment of the present disclosure;

[0038] Figure 17 is a partial structural diagram of another display panel provided in the second pixel area according to an embodiment of the present disclosure;

[0039] Figure 18 is a flowchart of a control method for a display panel provided in an embodiment of this disclosure;

[0040] Figure 19 is a structural block diagram of a control device for a display panel provided in an embodiment of this disclosure.

[0041] Legend: y, first direction x, second direction n, third direction m, fourth direction 10, substrate 10a, first pixel area 10b, second pixel area 2, pixel 2a, first pixel 2b, second pixel 20a, first sub-pixel group 20b, second sub-pixel group 201, first type sub-pixel group 202, second type sub-pixel group 203, third type sub-pixel group 204, fourth type sub-pixel group 21, sub-pixel 21a, first color sub-pixel 21b, second color sub-pixel 21c, third color sub-pixel 22, light-emitting unit 221, anode 222, light-emitting layer 223, cathode 23. Color resist block 30, first gate driving line 31, reset control line 31a, first reset control line 31b, second reset control line 32, data line 40, dimming structure 401, first opening 41, pixel definition layer 411, pixel opening 411a, second opening 411b, third opening 42, encapsulation layer 43, touch metal layer 44, black matrix 45, cover layer 46, touch protection layer 50, first driving module 51, second driving module 52, third driving module 6, pixel sub-circuit 1000, control device 1001, first control module 1002, second control module Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0043] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the element or object preceding “comprising” or “including” encompasses the element or object listed following “comprising” or “including” and its equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” “top,” and “bottom,” etc., are used only to indicate relative positional relationships, which may change accordingly when the absolute position of the described object changes. Furthermore, “A and / or B” indicates the presence of three cases: A and B, and A and B.

[0044] In related technologies, there exists a display panel with privacy protection function, which includes a substrate, multiple pixels, and multiple gate driving lines. The multiple pixel array is arranged on the substrate, each pixel includes multiple sub-pixels, and the multiple pixels include multiple first pixels and multiple second pixels. The maximum light emission angle of the sub-pixels in the first pixels is smaller than the maximum light emission angle of the sub-pixels in the second pixels.

[0045] Each sub-pixel within a plurality of pixels comprises multiple sub-pixel groups arranged sequentially along a column direction, and each sub-pixel group comprises multiple sub-pixels arranged sequentially along a row direction. Each sub-pixel group includes sub-pixels from a first pixel and sub-pixels from a second pixel. Multiple gate driving lines are located on the substrate, and each gate driving line extends along a row direction, electrically connecting to multiple sub-pixels in a sub-pixel group. Gate Driven on Array (GOA) signals are output via the gate driving lines to control the on / off state of the transistors in each connected sub-pixel, thereby controlling the light-emitting state of the sub-pixels in the first pixel and the second pixel respectively, enabling the display panel to switch between privacy mode and sharing mode.

[0046] However, in privacy mode, it is necessary to control the emission of sub-pixels in the first pixel, while the emission of sub-pixels in the second pixel is suppressed. That is, in privacy mode, only the first pixel is used to display the image, and the second pixel does not participate in the display. Each sub-pixel group includes sub-pixels in the first pixel and sub-pixels in the second pixel. Each gate drive line is electrically connected to multiple sub-pixels in a sub-pixel group. Therefore, in privacy mode, the voltage of the GOA signal on each gate drive line needs to switch between on and off voltages to drive the sub-pixels in the first pixel to display the image. This results in higher logic power consumption for the gate drive lines and higher power consumption for the display panel in privacy mode.

[0047] To this end, embodiments of this disclosure provide a display panel that can switch between a privacy mode and a sharing mode, and can reduce power consumption in privacy mode.

[0048] Figure 1 is a schematic diagram of a display panel provided in an embodiment of this disclosure. As shown in Figure 1, the display panel includes a substrate 10, a plurality of pixels 2, and a plurality of first gate driving lines 30. The plurality of pixels 2 are arrayed on the substrate 10, each pixel 2 includes a plurality of sub-pixels 21, the plurality of pixels 2 includes a plurality of first pixels 2a and a plurality of second pixels 2b, the maximum light emission angle of the sub-pixels 21 in the first pixels 2a is smaller than the maximum light emission angle of the sub-pixels 21 in the second pixels 2b, the sub-pixels 21 included in the plurality of pixels 2 include a plurality of first sub-pixel groups 20a arranged sequentially along a first direction y, each first sub-pixel group 20a includes a plurality of sub-pixels 21 arranged sequentially along a second direction x, the first direction y and the second direction x intersect. The plurality of first sub-pixel groups 20a include a plurality of first-type sub-pixel groups 201 and a plurality of second-type sub-pixel groups 202 arranged alternately along a first direction y. The sub-pixels 21 in the first-type sub-pixel groups 201 are all sub-pixels 21 in the first pixel 2a, and the sub-pixels 21 in the second-type sub-pixel groups 202 are all sub-pixels 21 in the second pixel 2b. A plurality of first gate driving lines 30 are located on the substrate 10, and each first gate driving line 30 extends along a second direction x. Each first gate driving line 30 is electrically connected to a plurality of sub-pixels 21 in a first sub-pixel group 20a. That is, all sub-pixels 21 in a first sub-pixel group 20a are electrically connected to the same first gate driving line 30, and sub-pixels 21 connected to different first gate driving lines 30 belong to different first sub-pixel groups 20a.

[0049] In this embodiment of the present disclosure, each first gate driving line 30 is electrically connected to a plurality of sub-pixels 21 in a first sub-pixel group 20a. The plurality of first sub-pixel groups 20a include a plurality of first type sub-pixel groups 201 and a plurality of second type sub-pixel groups 202 arranged alternately along the first direction y. The plurality of sub-pixels 21 in the first type sub-pixel group 201 are all sub-pixels 21 in the first pixel 2a, and the plurality of sub-pixels 21 in the second type sub-pixel group 202 are all sub-pixels 21 in the second pixel 2b. The switching on and off of the transistor can be controlled by inputting a GOA signal through the first gate driving line 30, so as to control the light emission state of the sub-pixels 21 in the first type sub-pixel group 201 and the sub-pixels 21 in the second type sub-pixel group 21, thereby realizing the switching of the display panel between the privacy mode and the sharing mode. Furthermore, in privacy mode, since the sub-pixel 21 in the second pixel 2b does not emit light, the voltage of the GOA signal provided by the first gate driving line 30, which is electrically connected to the multiple sub-pixels 21 in the second type sub-pixel group 202, can be the off voltage. This can reduce the logic power consumption caused by the voltage jump between the on and off voltages of the GOA signal provided by the first gate driving line 30, and reduce the power consumption of the display panel in privacy mode.

[0050] For example, in privacy mode, the voltage of the GOA signal provided by the first gate driving line 30, which is electrically connected to multiple sub-pixels 21 in the first type sub-pixel group 201, can switch between on and off voltages to drive the sub-pixels 21 in the first pixel 2a to display the image. The voltage of the GOA signal provided by the first gate driving line 30, which is electrically connected to multiple sub-pixels 21 in the second type sub-pixel group 202, can be kept at the off voltage so that the sub-pixels 21 in the second pixel 2b do not participate in the display. Compared to the fact that the voltage of the GOA signal provided by each first gate driving line 30 needs to switch between on and off voltages in privacy mode, the overall logic power consumption of the first gate driving line 30 can be reduced.

[0051] For example, the first direction y is perpendicular to the second direction x.

[0052] In this embodiment of the disclosure, the first direction y is the column direction, and the second direction x is the row direction. In other embodiments, the first direction y can be the row direction, and the second direction x can be the column direction.

[0053] Optionally, the first gate driving line 30 includes at least one of a light-emitting control line and a scan line. The light-emitting control line can provide a light-emitting control signal to control the on and off of the light-emitting control transistor, and the scan line can provide a scan signal to control the on and off of the data writing transistor, thereby controlling the light-emitting state of sub-pixels 21 in the first type of sub-pixel group 201 and sub-pixels 21 in the second type of sub-pixel group 202. In privacy mode, since the sub-pixels 21 in the second pixel 2b do not emit light, the voltage of the light-emitting control signal provided by the light-emitting control line electrically connected to the plurality of sub-pixels 21 in the second type of sub-pixel group 202 can be the off voltage, and the voltage of the scan signal provided by the scan line electrically connected to the plurality of sub-pixels 21 in the second type of sub-pixel group 202 can be the off voltage. This can reduce the logic power consumption caused by the voltage jump between the on and off voltages of the light-emitting signal provided by the light-emitting control line or the scan signal provided by the scan line, thereby reducing the power consumption of the display panel in privacy mode.

[0054] In this embodiment, the first gate driving line 30 may simultaneously include both light emission control lines and scan lines. In Figure 1, the first gate driving line 30 extending along the second direction x is illustrated by a single horizontal line; each horizontal line can represent both a light emission control line and a scan line. Exemplarily, multiple first gate driving lines 30 include multiple light emission control lines and multiple scan lines. Each light emission control line is electrically connected to multiple sub-pixels 21 in a first sub-pixel group 20a, and each scan line is electrically connected to multiple sub-pixels 21 in a first sub-pixel group 20a.

[0055] In other embodiments, the first gate driving line 30 may also include only one of the light emission control line and the scan line, and this disclosure does not limit this.

[0056] In other embodiments, the first gate drive line 30 may also include drive lines for providing other types of GOA signals.

[0057] Optionally, the display panel further includes multiple reset control lines 31 located on the substrate 10, each extending along a second direction x, and each reset control line 31 electrically connected to multiple sub-pixels 21 in a first sub-pixel group 20a. The multiple reset control lines 31 include multiple first reset control lines 31a and multiple second reset control lines 31b. Each first reset control line 31a is electrically connected to multiple sub-pixels 21 in a first type sub-pixel group 201, and each second reset control line 31b is electrically connected to multiple sub-pixels 21 in a second type sub-pixel group 202. The reset control signals provided by at least one first reset control line 31a and at least one second reset control line 31b have the same waveform. In Figure 1, the first gate driving line 30 and the first reset control line 31a are illustrated using only one horizontal line; each horizontal line can simultaneously represent a light-emitting control line, a scan line, and a reset control line 31.

[0058] Since each light-emitting control line and each scan line can independently control a first-type sub-pixel group 201 or a second-type sub-pixel group 202, whether a sub-pixel 21 emits light in both shared mode and privacy mode is mainly controlled by the light-emitting control line and the scan line. In privacy mode, the voltage of the light-emitting control signal and the voltage of the scan signal provided by the light-emitting control line and the scan line to multiple sub-pixels 21 in the second-type sub-pixel group 202 can both be off voltages. In this way, the reset control signal provided by the second reset control line 31b will not affect the light-emitting state of the second-type sub-pixel group 21. The waveforms of the reset control signals provided by at least one first reset control line 31a and at least one second reset control line 31b are the same. Compared with the reset control signal provided by each reset control line 31 having an independent waveform, this simplifies the control algorithm and does not affect the display function of shared mode and privacy mode.

[0059] Optionally, the waveform of the reset control signal provided by each first reset control line 31a and the adjacent second reset control line 31b is the same. That is, two adjacent rows of first sub-pixel groups 20a can share the same waveform of reset control signal, which can further simplify the control algorithm and does not affect the display functions of the shared mode and the privacy mode.

[0060] In other embodiments, the reset control signals provided by a greater number of first reset control lines 31a and a greater number of second reset control lines 31b may have the same waveform. For example, the reset control signals provided by every four adjacent reset control lines 31 in the first direction y may have the same waveform. For instance, the reset control signals provided by the first reset control lines 31a in the first row, the second reset control lines 31b in the second row, the first reset control lines 31a in the third row, and the second reset control lines 31b in the fourth row may have the same waveform.

[0061] In the display panel, the driving circuit can illuminate sub-pixels 21 row by row according to a timing sequence to display the image. Figure 2 is a schematic block diagram of a driving circuit provided in an embodiment of this disclosure. Figure 2 can illustrate the driving relationship between the driving circuit and the first sub-pixel group 20a in Figure 1. As shown in Figure 2, the driving circuit may include multiple first driving modules 50, multiple second driving modules 51, and multiple third driving modules 52. It should be noted that Figure 2 is only a schematic block diagram of the structure of the driving circuit and does not imply a specific limitation on the placement of each driving module or the connection relationship between each driving module and the first sub-pixel group.

[0062] For example, the first driving module 50 is used to generate a scanning signal, the second driving module 51 is used to generate a light emission control signal, and the third driving module 52 is used to generate a reset control signal. Referring to Figures 1 and 2, the first driving module 50 in the first row is used to drive the first type sub-pixel group 201 in the first row, the first driving module 50 in the second row is used to drive the second type sub-pixel group 202 in the second row, the first driving module 50 in the third row is used to drive the first type sub-pixel group 201 in the third row, and the first driving module 50 in the fourth row is used to drive the second type sub-pixel group 202 in the fourth row. The scanning signal generated by the first driving module 50 drives the first sub-pixel group 20a in the same row on both sides. The second driving module 51 in the first row is used to drive the first type sub-pixel group 201 in the first row, the second driving module 51 in the second row is used to drive the second type sub-pixel group 202 in the second row, and the third driving module 52 in the third row is used to drive the first type sub-pixel group 202 in the second row. The second driving module 51 is used to drive the first type sub-pixel group 201 in the third row, and the second driving module 51 in the fourth row is used to drive the second type sub-pixel group 202 in the fourth row. The light emission control signal generated by the second driving module 51 drives the first sub-pixel group 20a in the same row on both sides. The third driving module 52 in the first row drives the first type sub-pixel group 201 in the first row and the second type sub-pixel group 202 in the second row simultaneously. The third driving module 52 in the second row drives the first type sub-pixel group 201 in the third row and the second type sub-pixel group 202 in the fourth row simultaneously. The reset control signal generated by the third driving module 52 drives the first sub-pixel groups 20a in both rows on both sides. Here, "dual-side driving" means that for the first sub-pixel group 20a in the same row, an identical driving circuit is set on each of its left and right sides to drive the pixel circuits of each sub-pixel 21 in that row's first sub-pixel group 20a.

[0063] In one possible implementation, the scan signal includes a first scan signal and a second scan signal, with the first driving module 50 used to generate the second scan signal and the third driving module 52 used to generate the first scan signal.

[0064] Figure 3 is a schematic diagram of a pixel circuit provided in an embodiment of this disclosure. As shown in Figure 3, each sub-pixel includes a light-emitting unit and a pixel circuit, with the light-emitting unit electrically connected to the pixel circuit. The pixel circuit includes a pixel sub-circuit 6, a reset control transistor T0, and a first light-emitting control transistor T6. Part (a) of Figure 3 can represent the pixel circuit of a sub-pixel in a first type of sub-pixel group, and part (b) of Figure 3 can represent the pixel circuit of a sub-pixel in an adjacent second type of sub-pixel group. For example, part (a) of Figure 3 can represent the pixel circuit of a sub-pixel in a first type of sub-pixel group in the first row, and part (b) of Figure 3 can represent the pixel circuit of a sub-pixel in a second type of sub-pixel group in the second row. As shown in Figure 3, the first light-emitting control transistor T6 can be turned on and off by a light-emitting control signal, the reset control transistor T0 can be turned on and off by a reset control signal, and the pixel sub-circuit 6 of the sub-pixel in the first type of sub-pixel group can be driven by a first GOA signal and a second GOA signal.

[0065] For example, in the pixel circuit of the sub-pixel in the first type of sub-pixel group, the light emission control signal is EM1, and in the pixel circuit of the sub-pixel in the second type of sub-pixel group, the light emission control signal is EM2. The waveforms of EM1 and EM2 are different.

[0066] For example, in the pixel circuit of the sub-pixel in the first type of sub-pixel group and the pixel circuit of the sub-pixel in the second type of sub-pixel group, the reset control signal is Reset, and the waveform of the reset control signal is the same.

[0067] For example, the waveforms of the scanning signals in the first GOA signal and the second GOA signal are different; the waveforms of other types of GOA signals may be the same or different.

[0068] Figure 4 is a circuit diagram of a pixel circuit provided in an embodiment of this disclosure. Part (a) of Figure 4 can represent the pixel circuit of a sub-pixel in a first type of sub-pixel group, and part (b) of Figure 4 can represent the pixel circuit of a sub-pixel in an adjacent second type of sub-pixel group. For example, part (a) of Figure 4 can represent the pixel circuit of a sub-pixel in a first type of sub-pixel group in the first row, and part (b) of Figure 4 can represent the pixel circuit of a sub-pixel in a second type of sub-pixel group in the second row. In Figure 4, the pixel circuit of each sub-pixel includes eight transistors T1 to T8 and one storage capacitor Cst, which is an 8T1C (eight transistors and one capacitor) circuit.

[0069] As shown in Figure 4, the pixel circuit for each sub-pixel includes a first reset control transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second reset control transistor T7, a node control transistor T8, and a storage capacitor Cst. Among these, the first reset control transistor T1, driving transistor T3, data writing transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, second reset control transistor T7, and node control transistor T8 are P-type transistors, which are off when high-level and on when low-level; the threshold compensation transistor T2 is an N-type transistor, which is on when high-level and off when low-level.

[0070] As shown in Figure 4, the first terminal of the first reset control transistor T1 is used to input the first initialization voltage Vinit1. The second terminal of the first reset control transistor T1 is electrically connected to the second terminal of the driving transistor T3, the first terminal of the second light-emitting control transistor T6, the first terminal of the threshold compensation transistor T2, and the third node N3. The control terminal of the first reset control transistor T1 is electrically connected to the first reset control signal PRESet.

[0071] The second electrode of the threshold compensation transistor T2 is electrically connected to the first node N1, the first electrode plate of the storage capacitor Cst, and the control electrode of the driving transistor T3. The control electrode of the threshold compensation transistor T2 is electrically connected to the first scan signal NGate.

[0072] The first terminal of the driving transistor T3 is electrically connected to the second node N2, the second terminal of the driving transistor T3 is electrically connected to the third node N3, and the control terminal of the driving transistor T3 is electrically connected to the first node N1.

[0073] The first terminal of the data writing transistor T4 is used to input the data voltage Vdata. The second terminal of the data writing transistor T4 is electrically connected to the first terminal and the second node N2 of the driving transistor T3. The control terminal of the data writing transistor T4 is electrically connected to the second scan signal. Furthermore, the waveforms of the second scan signal differ in the pixel circuits of the sub-pixels in the first pixel and the second pixel. In the pixel circuit of the sub-pixels in the first pixel, the second scan signal is PGate1, and in the pixel circuit of the sub-pixels in the second pixel, the second scan signal is PGate2.

[0074] The first terminal of the first light-emitting control transistor T5 is used to input the power supply voltage VDD. The first terminal of the first light-emitting control transistor T5 is electrically connected to the second node N2. The control terminal of the first light-emitting transistor T5 is electrically connected to the light-emitting control signal. Furthermore, the waveforms of the light-emitting control signal are different in the pixel circuits of the sub-pixels in the first pixel and the sub-pixels in the second pixel. In the pixel circuit of the sub-pixels in the first pixel, the light-emitting control signal is EM1, and in the pixel circuit of the sub-pixels in the second pixel, the light-emitting control signal is EM2.

[0075] The first terminal of the second light-emitting control transistor T6 is electrically connected to the third node N3, and the second terminal of the second light-emitting control transistor T6 is electrically connected to the fourth node N4. The control terminal of the second light-emitting transistor T6 is electrically connected to the light-emitting control signal. Furthermore, the waveforms of the light-emitting control signal are different in the pixel circuits of the sub-pixels in the first pixel and the second pixel. In the pixel circuit of the sub-pixels in the first pixel, the light-emitting control signal is EM1, and in the pixel circuit of the sub-pixels in the second pixel, the light-emitting control signal is EM2.

[0076] The first terminal of the second reset control transistor T7 is used to input the second initialization voltage Vinit2. The second terminal of the second reset control transistor T7 is electrically connected to the fourth node N4. The control terminal of the second reset control transistor T7 is electrically connected to the second reset control signal PResetH.

[0077] The first terminal of the node control transistor T8 is used to input the reset voltage Vref, the second terminal of the node control transistor T8 is electrically connected to the second node N2, and the control terminal of the node control transistor T8 is electrically connected to the second reset control signal PRESetH.

[0078] The first electrode of the light-emitting unit L is electrically connected to the fourth node N4, and the second electrode of the light-emitting unit L is used to input the reference voltage VSS.

[0079] For example, in the pixel circuit of the sub-pixel in the first pixel and the pixel circuit of the sub-pixel in the second pixel, the waveforms of the first reset control signal PRESet, the second reset control signal PRESetH and the first scan signal NGate can be the same.

[0080] Figure 5 is a signal timing diagram of a pixel circuit provided in an embodiment of this disclosure. Figure 5 can simultaneously represent the signal timing of the pixel circuit shown in part (a) of Figure 4 and part (b) of Figure 4. As shown in Figures 4 and 5, in the shared mode, both the first pixel and the second pixel need to be lit.

[0081] During the first reset phase P1, the first reset signal PReset is high, the second reset control signal PResetH is low, the first scan signal NGate is high, the second scan signals PGate1 and PGate2 are high, and the light emission control signals EM1 and EM2 are high. At this time, the threshold compensation transistor T2, the second reset control transistor T7, and the node control transistor T8 are turned on, while the other transistors are turned off. This allows the second initialization voltage Vinit2 to be applied to the fourth node N4 through the second reset control transistor T7, resetting the first electrode of the light emission unit L. The reset voltage Vref is applied to the second node N2 through the node control transistor T8, resetting the first electrode of the driving transistor T3. The voltage at the first node N1 is the sum of the reset voltage Vref and the threshold voltage Vth.

[0082] During the second reset phase P2, the first reset signal PReset is low, the second reset control signal PResetH is high, the first scan signal NGate is high, the second scan signals PGate1 and PGate2 are high, and the light emission control signals EM1 and EM2 are high. At this time, the first reset control transistor T1 and the threshold compensation transistor T2 are turned on, while the other transistors are turned off. This allows the first initialization voltage Vinit1 to be applied to the first node N1 and the first electrode plate of the storage capacitor Cst through the first reset control transistor T1 and the threshold compensation transistor T2, thus charging the storage capacitor Cst. The voltage at the second node N2 is the difference between the first initialization voltage Vinit1 and the threshold voltage Vth.

[0083] During the data writing phase P3, the first reset signal PReset is high, the second reset control signal PResetH is high, the first scan signal NGate is high, the second scan signals PGate1 and PGate2 are sequentially low, and the light emission control signals EM1 and EM2 are high. At this time, the threshold compensation transistor T2, the driving transistor T3, and the data writing transistor T4 are turned on, while the other transistors are turned off. This allows the data voltage Vdata to be applied to the first node N1 through the threshold compensation transistor T2, the driving transistor T3, and the data writing transistor T4, thereby achieving threshold compensation and data writing for the third node N3. The voltage of the first node N1 is the sum of the data voltage Vdata and the threshold voltage Vth, and the voltage of the second node N2 is the data voltage Vdata.

[0084] In the third reset phase P4, the first reset signal PReset is high, the second reset control signal PResetH is low, the first scan signal NGate is low, the second scan signals PGate1 and PGate2 are high, and the light emission control signals EM1 and EM2 are high. At this time, the second reset control transistor T7 and the node control transistor T8 are turned on, and the other transistors are turned off. This allows the second initialization voltage Vinit2 to be applied to the fourth node N4 through the second reset control transistor T7, thereby resetting the first electrode of the light emission unit L. The reset voltage Vref is also applied to the second node N2 through the node control transistor T8, thereby resetting the first electrode of the driving transistor T3. The voltage at the second node N2 is the reset voltage Vref.

[0085] During the light-emitting phase P5, the first reset signal PReset is high, the second reset control signal PResetH is high, the first scan signal NGate is low, the second scan signals PGate1 and PGate2 are high, and the light-emitting control signals EM1 and EM2 are sequentially low. At this time, the driving transistor T3, the first light-emitting control transistor T5, and the second light-emitting control transistor T6 are turned on, while the other transistors are turned off, causing the light-emitting unit L to emit light.

[0086] In privacy mode, only the first pixel needs to be lit, while the second pixel does not. In the pixel circuit of the sub-pixels within the first pixel, each GOA signal can operate according to the timing shown in Figure 5 to control the emission of sub-pixels in the first type of sub-pixel group.

[0087] In the pixel circuit of the sub-pixel in the second pixel, the light emission control signal EM2 and the second scan signal PGate2 can be kept at a high level, and the data writing transistor T4, the first light emission control transistor T5 and the second light emission control transistor T6 can be turned off; or, the light emission control signal EM2 and the second scan signal PGate2 can be stopped to control the sub-pixels in the second type of sub-pixel group to not emit light.

[0088] For example, in privacy mode, in the pixel circuit of the sub-pixel in the second pixel, apart from the light emission control signal EM2 and the second scan signal PGate2, the remaining GOA signals can be shared with the GOA signals in the pixel circuit of the sub-pixel in the first type of sub-pixel group, or the remaining GOA signals can work independently, or the remaining GOA signals can be stopped. For example, the first reset control signal PRESET, the second reset control signal PRESETH, and the first scan signal NGate can work according to the timing shown in Figure 5; or, the first reset control signal PRESET, the second reset control signal PRESETH, and the first scan signal NGate can work at a reduced frequency according to other timing sequences; or, the first reset control signal PRESET, the second reset control signal PRESETH, and the first scan signal NGate can be stopped. Working at a reduced frequency or stopping the GOA signals can reduce power consumption in privacy mode.

[0089] Furthermore, because the GOA signal controls all sub-pixels in the second pixel to not emit light in the privacy mode, the data voltage Vdata in the pixel circuit of the sub-pixels in the second type of sub-pixel group can be the same as the data voltage Vdata in the pixel circuit of the sub-pixels in the adjacent row of the first type of sub-pixel group. For example, the data voltage Vdata is the same in the pixel circuits of the first type of sub-pixel group in the first row and the second type of sub-pixel group in the second row, as are the data voltage Vdata in the pixel circuits of the first type of sub-pixel group in the third row and the second type of sub-pixel group in the fourth row.

[0090] In other embodiments, the pixel circuit may also be other types of circuits, such as 7T1C circuit, 8T2C circuit or 9T1C circuit, etc., and this disclosure does not limit it.

[0091] As shown in Figure 1, the sub-pixels 21 included by the plurality of pixels 2 comprise a plurality of second sub-pixel groups 20b arranged sequentially along the second direction x. Each second sub-pixel group 20b comprises a plurality of sub-pixels 21 arranged sequentially along the first direction y. The second sub-pixel group 20b includes sub-pixels 21 from a plurality of first-type sub-pixel groups 201 and sub-pixels 21 from a plurality of second-type sub-pixel groups 202 arranged alternately along the first direction y. The display panel also includes a plurality of data lines 32 located on the substrate 10, and each data line 32 extends along the first direction y. Each data line 32 is electrically connected to a plurality of sub-pixels 21 in a second sub-pixel group 20b. That is, all sub-pixels 21 in a second sub-pixel group 20b are electrically connected to the same data line 32, and sub-pixels 21 connected to different data lines 32 belong to different second sub-pixel groups 20b. This facilitates the supply of data voltage to sub-pixels 21 in a second sub-pixel group 20b via data line 32 in the first direction y and at different time periods to control the luminous brightness of sub-pixels 21 in the second sub-pixel group 20b.

[0092] As shown in Figure 1, multiple sub-pixels 21 in the second sub-pixel group 20b have the same color. The display panel illuminates the sub-pixels 21 row by row in a time sequence. Each data line 32 provides data voltage to a sub-pixel 21 in the second sub-pixel group 20b at different times in the first direction y to control the brightness of the sub-pixels 21 in the sub-pixel group 20b. In privacy mode, only the sub-pixels 21 in the first pixel 2a need to emit light for privacy display. Since the GOA signal can control the sub-pixels 21 in the second pixel 2b to not emit light, the data voltage provided by the data line 32 to the sub-pixels 21 in the second type sub-pixel group 202 can be the same as the data voltage provided by the data line 32 to the sub-pixels 21 in the adjacent row of the first type sub-pixel group 201. For example, the data voltage provided by the data line 32 to the sub-pixels 21 in the first row can be the same as the data voltage provided by the data line 32 to the sub-pixels 21 in the second row. Furthermore, since different colored sub-pixels 21 require different brightness voltages when emitting light, and multiple sub-pixels 21 in the second sub-pixel group 20b have the same color, the data line 32 electrically connected to multiple sub-pixels 21 in the second sub-pixel group 20b in the privacy mode can provide only the brightness voltage required by a sub-pixel 21 of a certain color. Compared with the second sub-pixel group 20b having two colors of sub-pixels 21 that need to switch between no brightness and privacy brightness, this can effectively reduce the analog power consumption generated by the data line 32 electrically connected to multiple sub-pixels 21 in the second sub-pixel group 20b due to data voltage switching in the privacy mode, thereby further reducing the power consumption of the display panel in the privacy mode.

[0093] Furthermore, in the shared mode, each data line 32 only needs to provide the brightness voltage required by the sub-pixel 21 of one color. Compared with the second sub-pixel group 20b, where there are two colors of sub-pixels 21 that need to be lit, the analog power consumption of the data line 32 that is electrically connected to multiple sub-pixels 21 in the second sub-pixel group 20b due to data voltage jumps can be reduced in the shared mode, thereby reducing the power consumption of the display panel in the shared mode.

[0094] Optionally, multiple first pixels 2a and multiple second pixels 2b are alternately arranged in the third direction n and the fourth direction m, where the third direction n and the fourth direction m intersect, and the third direction n intersects both the first direction y and the second direction x, while the fourth direction m intersects both the first direction y and the second direction x. This makes the distribution of the first pixels 2a and the second pixels 2b on the substrate 10 more uniform, thereby improving the display effect of the display panel in privacy mode and sharing mode.

[0095] As shown in Figure 1, in each first pixel 2a and each second pixel 2b, the number of sub-pixels 21 of each color is equal. This reduces the difference in display effect between the privacy mode and the sharing mode, ensuring better uniformity of the display effect between the privacy mode and the sharing mode.

[0096] As shown in Figure 1, each pixel 2 contains a sub-pixel 21, which includes one first-color sub-pixel 21a, two second-color sub-pixels 21b, and one third-color sub-pixel 21c. Furthermore, in each pixel 2, the first-color sub-pixel 21a, the two second-color sub-pixels 21b, and the third-color sub-pixel 21c are arranged sequentially along the second direction x. This ensures a better display effect on the display panel.

[0097] For example, the first color sub-pixel 21a is a red (R) sub-pixel, the second color sub-pixel 21b is a green (G) sub-pixel, and the third color sub-pixel 21c is a blue (B) sub-pixel.

[0098] In other embodiments, the first color sub-pixel 21a can be a blue sub-pixel, the second color sub-pixel 21b can be a green sub-pixel, and the third color sub-pixel 21c can be a red sub-pixel; this disclosure does not limit this.

[0099] In Figure 1, in each first pixel 2a, the third color sub-pixel 21c, the second color sub-pixel 21b, the second color sub-pixel 21b, and the first color sub-pixel 21a are arranged sequentially along the second direction x in a rectangular arrangement. In each second pixel 2b, the second color sub-pixel 21b, the first color sub-pixel 21a, the third color sub-pixel 21c, and the second color sub-pixel 21b are arranged sequentially along the second direction x in a rectangular arrangement. Furthermore, multiple sub-pixels 21 in the same second sub-pixel group 20b have the same color. In Figure 1, in each row of sub-pixels 21, the sub-pixels 21 from left to right repeat and are arranged sequentially in the order of third color sub-pixel 21c, second color sub-pixel 21b, second color sub-pixel 21b, and first color sub-pixel 21a.

[0100] Figure 6 is a schematic diagram of another display panel structure provided in an embodiment of this disclosure. As shown in Figure 6, in each first pixel 2a, the first color sub-pixel 21a, the second color sub-pixel 21b, the second color sub-pixel 21b, and the third color sub-pixel 21c are arranged sequentially along the second direction x in a rectangular arrangement. In each second pixel 2b, the second color sub-pixel 21b, the third color sub-pixel 21c, the first color sub-pixel 21a, and the second color sub-pixel 21b are arranged sequentially along the second direction x in a rectangular arrangement. Furthermore, the colors of multiple sub-pixels 21 in the same second sub-pixel group 20b are the same. In Figure 6, the sub-pixels 21 in each row of sub-pixels 21, from left to right, repeat and are arranged sequentially in the order of first color sub-pixel 21a, second color sub-pixel 21b, second color sub-pixel 21b, and third color sub-pixel 21c.

[0101] Figure 7 is a schematic diagram of another display panel provided in an embodiment of this disclosure. As shown in Figure 7, in each first pixel 2a, the first color sub-pixel 21a, the second color sub-pixel 21b, the third color sub-pixel 21c, and the second color sub-pixel 21b are arranged sequentially along the second direction x in a rectangular arrangement. In each second pixel 2b, the third color sub-pixel 21c, the second color sub-pixel 21b, the first color sub-pixel 21a, and the second color sub-pixel 21b are arranged sequentially along the second direction x in a rectangular arrangement. Furthermore, the colors of multiple sub-pixels 21 in the same second sub-pixel group 20b are the same. In Figure 7, the sub-pixels 21 in each row of sub-pixels 21, from left to right, repeat and are arranged sequentially in the order of first color sub-pixel 21a, second color sub-pixel 21b, third color sub-pixel 21c, and second color sub-pixel 21b.

[0102] Figure 8 is a schematic diagram of another display panel provided in an embodiment of this disclosure. As shown in Figure 8, in each first pixel 2a, the third color sub-pixel 21c, the second color sub-pixel 21b, the first color sub-pixel 21a, and the second color sub-pixel 21b are arranged sequentially along the second direction x in a rectangular arrangement. In each second pixel 2b, the first color sub-pixel 21a, the second color sub-pixel 21b, the third color sub-pixel 21c, and the second color sub-pixel 21b are arranged sequentially along the second direction x in a rectangular arrangement. Furthermore, the colors of multiple sub-pixels 21 in the same second sub-pixel group 20b are the same. In Figure 8, the sub-pixels 21 in each row of sub-pixels 21, from left to right, repeat and are arranged sequentially in the order of third color sub-pixel 21c, second color sub-pixel 21b, first color sub-pixel 21a, and second color sub-pixel 21b.

[0103] Figure 9 is a schematic diagram of another display panel provided in an embodiment of this disclosure. As shown in Figure 9, in each first pixel 2a, the first color sub-pixel 21a, the third color sub-pixel 21c, the second color sub-pixel 21b, and the second color sub-pixel 21b are arranged sequentially along the second direction x in a rectangular arrangement. In each second pixel 2b, the second color sub-pixel 21b, the first color sub-pixel 21a, and the third color sub-pixel 21c are arranged sequentially along the second direction x in a rectangular arrangement. Furthermore, the colors of multiple sub-pixels 21 in the same second sub-pixel group 20b are the same. In Figure 9, the sub-pixels 21 in each row of sub-pixels 21, from left to right, repeat and are arranged sequentially in the order of first color sub-pixel 21a, third color sub-pixel 21c, second color sub-pixel 21b, and second color sub-pixel 21b.

[0104] Figure 10 is a schematic diagram of another display panel provided in an embodiment of this disclosure. As shown in Figure 10, in each first pixel 2a, the third color sub-pixel 21c, the first color sub-pixel 21a, the second color sub-pixel 21b, and the second color sub-pixel 21b are arranged sequentially along the second direction x in a rectangular arrangement. In each second pixel 2b, the second color sub-pixel 21b, the third color sub-pixel 21c, and the first color sub-pixel 21a are arranged sequentially along the second direction x in a rectangular arrangement. Furthermore, the colors of multiple sub-pixels 21 in the same second sub-pixel group 20b are the same. In Figure 10, the sub-pixels 21 in each row of sub-pixels 21, from left to right, repeat and are arranged sequentially in the order of third color sub-pixel 21c, first color sub-pixel 21a, second color sub-pixel 21b, and second color sub-pixel 21b.

[0105] Figure 11 is a schematic diagram of another display panel provided in an embodiment of this disclosure. As shown in Figure 11, in each first pixel 2a, the second color sub-pixel 21b, the third color sub-pixel 21c, and the first color sub-pixel 21a are arranged sequentially along the second direction x in a rectangular arrangement. In each second pixel 2b, the third color sub-pixel 21c, the first color sub-pixel 21a, the second color sub-pixel 21b, and the second color sub-pixel 21b are arranged sequentially along the second direction x in a rectangular arrangement. Furthermore, the colors of multiple sub-pixels 21 in the same second sub-pixel group 20b are the same. In Figure 11, the sub-pixels 21 in each row of sub-pixels 21, from left to right, repeat and are arranged sequentially in the order of second color sub-pixel 21b, second color sub-pixel 21c, and first color sub-pixel 21a.

[0106] Figure 12 is a schematic diagram of another display panel provided in an embodiment of this disclosure. As shown in Figure 12, in each first pixel 2a, the second color sub-pixel 21b, the first color sub-pixel 21a, and the third color sub-pixel 21c are arranged sequentially along the second direction x in a rectangular arrangement. In each second pixel 2b, the first color sub-pixel 21a, the third color sub-pixel 21c, the second color sub-pixel 21b, and the second color sub-pixel 21b are arranged sequentially along the second direction x in a rectangular arrangement. Furthermore, the colors of multiple sub-pixels 21 in the same second sub-pixel group 20b are the same. In Figure 12, the sub-pixels 21 in each row of sub-pixels 21, from left to right, repeat and are arranged sequentially in the order of second color sub-pixel 21b, second color sub-pixel 21b, first color sub-pixel 21a, and third color sub-pixel 21c.

[0107] It should be noted that the display panel shown in Figures 6 to 12 differs from the display panel shown in Figure 1 in that the arrangement order of the sub-pixels 21 of different colors in each first pixel 2a and each second pixel 2b is different.

[0108] In one possible implementation, the light-emitting unit of the sub-pixel 21 can be electrically connected to the pixel circuit through a via connection point, and the center of the orthographic projection of the via connection point of the light-emitting unit of the sub-pixel 21 on the substrate 10 and the center of the orthographic projection of the sub-pixel 21 on the substrate 10 are located at different positions.

[0109] Figure 13 is a schematic diagram of the arrangement of light-emitting units in a display panel according to an embodiment of the present disclosure. As shown in Figure 13, each sub-pixel 21 includes a light-emitting unit 22. Each sub-pixel 21 in each pixel 2 includes a first color sub-pixel 21a, two second color sub-pixels 21b, and a third color sub-pixel 21c. In each pixel 2, the line connecting the center of the orthographic projection of the light-emitting unit 22 of the first color sub-pixel 21a on the substrate 10 and the center of the orthographic projection of the light-emitting unit 22 of the third color sub-pixel 21c on the substrate 10 intersects with the line connecting the center of the orthographic projection of the light-emitting units 22 of the two second color sub-pixels 21b on the substrate 10.

[0110] Optionally, in each pixel 2, the line connecting the center of the orthographic projection of the light-emitting unit 22 of the first color sub-pixel 21a onto the substrate 10 and the center of the orthographic projection of the light-emitting unit 22 of the third color sub-pixel 21c onto the substrate 10 extends in one of the first direction y and the second direction x, and the line connecting the center of the orthographic projection of the light-emitting units 22 of the two second color sub-pixels 21b onto the substrate 10 extends in the other of the first direction y and the second direction x. This allows for a more uniform distribution of the first pixel 2a and the second pixel 2b, thereby improving the display effect in both the privacy mode and the sharing mode.

[0111] As shown in Figure 13, in each pixel 2, the extension direction of the line connecting the center of the orthographic projection of the light-emitting unit 22 of the first color sub-pixel 21a on the substrate 10 and the center of the orthographic projection of the light-emitting unit 22 of the third color sub-pixel 21c on the substrate 10 is the first direction y, and the extension direction of the line connecting the center of the orthographic projection of the light-emitting units 22 of the two second color sub-pixels 21b on the substrate 10 is the second direction x. Figure 1 can illustrate the connection relationship between the light-emitting unit 22 of the sub-pixel 21 and the pixel circuit in the display panel shown in Figure 13, and the connection relationship between the pixel circuit and the first gate driving line 30, the reset control line 31, and the data line 32.

[0112] As shown in Figure 13, in each pixel 2, the line connecting the center of the orthographic projection of the light-emitting unit 22 of the first color sub-pixel 21a onto the substrate 10 and the center of the orthographic projection of the light-emitting unit 22 of the third color sub-pixel 21c onto the substrate 10 passes through the midpoint of the line connecting the centers of the orthographic projections of the light-emitting units 22 of the two second color sub-pixels 21b onto the substrate 10. The first color sub-pixels 21a and the third color sub-pixels 21c are arranged from bottom to top, and the two second color sub-pixels 21b are arranged from left to right. In each pixel 2, one first color sub-pixel 21a, two second color sub-pixels 21b, and one third color sub-pixel 21c are arranged in a similar diamond shape.

[0113] Figure 14 is a schematic diagram of another display panel provided in an embodiment of this disclosure. As shown in Figure 14, the plurality of second sub-pixel groups 20b include a plurality of third type sub-pixel groups 203 and a plurality of fourth type sub-pixel groups 204 arranged alternately along the second direction x. Each third type sub-pixel group 203 includes a plurality of first color sub-pixels 21a and a plurality of third color sub-pixels 21c arranged alternately along the first direction y. Each fourth type sub-pixel group 204 includes a plurality of second color sub-pixels 21b arranged sequentially along the first direction y. In privacy mode, since the GOA signal can control the sub-pixels in the odd-numbered rows of the first type sub-pixel groups 201 to be lit, the sub-pixels 21 in the even-numbered rows of the second type sub-pixel groups 202 will not be lit. This allows only one color sub-pixel 21 in each third type sub-pixel group 203 to be lit in privacy mode. As shown in Figure 14, in privacy mode, in the odd-numbered third-type sub-pixel groups 203 from left to right, the sub-pixels 21 in the odd-numbered rows are all first-color sub-pixels 21a. Therefore, the corresponding data line 32 only needs to provide the luminance voltage required by the first-color sub-pixel 21a. In the even-numbered third-type sub-pixel groups 203, the sub-pixels 21 in the odd-numbered rows are all third-color sub-pixels 21c. Therefore, the corresponding connected data line only needs to provide the luminance voltage required by the third-color sub-pixel 21c. In Figure 14, the third-type sub-pixel group 203 in the first column is the first third-type sub-pixel group 203, the third-type sub-pixel group 203 in the third column is the second third-type sub-pixel group 203, the third-type sub-pixel group 203 in the fifth column is the third third-type sub-pixel group 203, and the third-type sub-pixel group 203 in the seventh column is the fourth third-type sub-pixel group 203. Compared to the second sub-pixel group 20b, where sub-pixels 21 of two colors need to switch between no brightness and privacy brightness, this method can reduce the analog power consumption of the data lines 32 that are electrically connected to multiple sub-pixels 21 in the second sub-pixel group 20b due to data voltage switching in privacy mode. This can also reduce the power consumption of the display panel in privacy mode.

[0114] As shown in Figure 14, in each pixel 2, the first color sub-pixel 21a, the second color sub-pixel 21b, the third color sub-pixel 21c, and the second color sub-pixel 21b are arranged sequentially along the second direction x in a rectangular arrangement. In Figure 14, in the odd-numbered rows of sub-pixels 21, the sub-pixels 21 from left to right repeat and are arranged sequentially in the order of the first color sub-pixel 21a, the second color sub-pixel 21b, the third color sub-pixel 21c, and the second color sub-pixel 21b. In the even-numbered rows of sub-pixels 21, the sub-pixels 21 from left to right repeat and are arranged sequentially in the order of the third color sub-pixel 21c, the second color sub-pixel 21b, the first color sub-pixel 21a, and the second color sub-pixel 21b.

[0115] In other embodiments, the sub-pixels 21 of different colors may also adopt other arrangements, which are not limited in this disclosure.

[0116] Since the light emission efficiency of sub-pixel 21 in the first pixel 2a is different from that of sub-pixel 21 in the second pixel 2b, different gamma voltages can be provided for sub-pixels 21 of the same color in the first pixel 2a and the second pixel 2b in the sharing mode, so that the display brightness of sub-pixels 21 of the same color in the sharing mode is the same, and the white balance of the sharing mode is guaranteed.

[0117] As shown in Figures 1 and 6 to 14, in the sharing mode, a first gamma voltage can be provided to the first color sub-pixel 21a located in odd-numbered rows, and a second gamma voltage can be provided to the first color sub-pixel 21a located in even-numbered rows; a first gamma voltage can be provided to the second color sub-pixel 21b located in odd-numbered rows, and a second gamma voltage can be provided to the second color sub-pixel 21b located in even-numbered rows; a first gamma voltage can be provided to the third color sub-pixel 21c located in odd-numbered rows, and a second gamma voltage can be provided to the third color sub-pixel 21c located in even-numbered rows. Here, the first gamma voltage and the second gamma voltage are respectively the gamma voltages of sub-pixels 21 of the same color in the first pixel 2a and the second pixel 2b in the sharing mode, and the voltage values ​​of the first gamma voltage and the second gamma voltage are different. Furthermore, for sub-pixels 21 of different colors, the voltage values ​​of the first gamma voltage and the second gamma voltage are different.

[0118] In shared mode, both sub-pixels 21 in the first pixel 2a and the second pixel 2b emit light, while in privacy mode, only sub-pixels 21 in the first pixel 2a emit light. The arrangement of the emitted sub-pixels 21 differs between shared mode and privacy mode. Therefore, different gamma voltages can be provided for sub-pixels 21 of the same color in the first pixel 2a in shared mode and privacy mode to ensure white balance in both modes.

[0119] For example, in privacy mode, a third gamma voltage can be provided to sub-pixels 21 in the second pixel 2a. This third gamma voltage is different from the first gamma voltage. Here, the first gamma voltage and the third gamma voltage are respectively the gamma voltages of sub-pixels 21 of the same color in the first pixel 2a in shared mode and privacy mode, and the voltage values ​​of the first gamma voltage and the third gamma voltage are different. Furthermore, for sub-pixels 21 of different colors, the voltage values ​​of the first gamma voltage and the third gamma voltage are also different.

[0120] As shown in Figures 1, 6 to 14, the substrate 10 has a plurality of pixel regions arranged in an array. The plurality of pixel regions include a plurality of first pixel regions 10a and a plurality of second pixel regions 10b. Each first pixel 2a is located in a first pixel region 10a and each second pixel 2b is located in a second pixel region 10b.

[0121] Figure 15 is a partial structural schematic diagram of a display panel in the first pixel region according to an embodiment of the present disclosure. As shown in Figure 15, each sub-pixel 21 includes a light-emitting unit 22 and a color resist block 23 sequentially stacked along a direction away from the substrate 10. The display panel also includes a plurality of dimming structures 40, each dimming structure 40 being located in a first pixel region and between the light-emitting unit 22 and the color resist block 23. The side of the dimming structure 40 away from the substrate 10 has a plurality of first openings 401. A portion of each color resist block 23 in the first pixel region is located in one of the first openings 401, and the refractive index of the dimming structure 40 is less than the refractive index of the color resist block 23.

[0122] The arrows in Figure 15 indicate the propagation path of the light emitted by the light-emitting unit 22 at the edge of the first opening 401, as shown in Figure 15. In the first pixel area, when the light emitted by the light-emitting unit 22 is directed from the color resist block 23 to the dimming structure 40 at the edge of the first opening 401, since the refractive index of the dimming structure 40 is less than that of the color resist block 23, total internal reflection is easily generated when the light enters the film layer with a lower refractive index from the film layer with a higher refractive index. Therefore, total internal reflection is easily generated at the interface between the color resist block 23 and the dimming structure 40, thereby causing this part of the light to converge towards the center of the first opening 401 through the dimming structure 40, and exiting with a smaller viewing angle range, achieving the purpose of privacy display and improving the light emission efficiency of the sub-pixel 21 in the first pixel.

[0123] For example, the dimming structure 40 is made of an organic insulating material or an inorganic insulating material. For example, the dimming structure 40 can be made of polyimide (PI) or silicon dioxide, etc.

[0124] In other embodiments, the display panel can also change the viewing angle range of light emission through other structures as needed. For example, a black matrix or the like can be set as a light-shielding structure, and the area and thickness of the orthogonal projection of the light-shielding structure on the substrate 10 can be set to absorb light with a large viewing angle range to achieve privacy display. This disclosure does not limit this.

[0125] In this embodiment of the present disclosure, the depth of the first opening 401 in a direction perpendicular to the surface of the substrate 10 is equal to the thickness of the dimming structure 40. In other embodiments, the depth of the first opening 401 may be less than the thickness of the dimming structure 40, and this disclosure does not impose any limitations on this.

[0126] Optionally, the outer contour of the orthographic projection of the first opening 401 onto the substrate 10 is a rounded rectangle, a rectangle, or a circle.

[0127] Optionally, the orthographic projection of the end of the first opening 401 closest to the substrate 10 onto the substrate 10 is located inside the orthographic projection of the end of the first opening 401 furthest from the substrate 10 onto the substrate 10. Thus, the shape of the first opening 401 in a cross-section perpendicular to the surface of the substrate 10 can be trapezoidal. When the light emitted by the light-emitting unit 22 is directed by the color resist block 23 towards the sidewall of the first opening 401, the light is more likely to converge towards the center of the first opening 401, thereby effectively reducing the viewing angle range of the emitted light and improving the light emission efficiency of the sub-pixel 21 in the first pixel.

[0128] For example, the outer contour of the orthographic projection of the first opening 401 onto the substrate 10 is a rounded rectangle.

[0129] For example, the display panel also includes a pixel definition layer 41, which has a plurality of pixel openings 411, and a light-emitting unit 22 is disposed in each pixel opening 411.

[0130] Figure 16 is a partial structural diagram of a display panel in the second pixel region according to an embodiment of the present disclosure. Referring to Figures 13, 15 and 16, the plurality of pixel openings 411 include a plurality of second openings 411a and a plurality of third openings 411b, the second openings 411a being located in the first pixel region 10a and the third openings 411b being located in the second pixel region 10b.

[0131] Optionally, in the pixel opening 411 where the light-emitting unit 22 of the sub-pixel 21 of the same color is located, the opening area of ​​the second opening 411a is greater than or less than the opening area of ​​the third opening 411b. Here, the opening area can refer to the area of ​​the orthographic projection of the end of the pixel opening 411 closest to the substrate 10 onto the substrate 10.

[0132] The lifespan of the light-emitting unit 22 is related to its usage time and current density during use. The longer the usage time, the shorter the lifespan. Similarly, the higher the current density during use, the shorter the lifespan. The current density is directly proportional to the current and inversely proportional to the opening area. The color resist block 23 of the sub-pixel 21 in the first pixel area 10a is equipped with a dimming structure 40. The light-emitting efficiency of the sub-pixel 21 in the first pixel area 10a is relatively high. In order to ensure that the display brightness of the sub-pixels 21 of the same color in the first pixel area 10a and the sub-pixels 21 of the same color in the second pixel area 10b is the same in the sharing mode, the current of the light-emitting unit 22 of the sub-pixel 21 in the first pixel area 10a is relatively small, and the current density is relatively small. Simultaneously, in privacy mode, the light-emitting unit 22 in the first pixel area 10a emits light, while the light-emitting unit 22 in the second pixel area 10b does not emit light. In sharing mode, both the light-emitting units 22 in the first pixel area 10a and the second pixel area 10b emit light. Therefore, the areas of the second opening 411a and the third opening 411b can be adjusted to adjust the current density of the light-emitting units in different pixel areas. Combined with their respective usage times, the lifespan of the light-emitting units 22 in the first pixel area 10a and the second pixel area 10b can be better matched, thereby improving the reliability of the display panel. In part (a) of Figure 13, in the pixel opening 411 where the light-emitting units 22 of the same color sub-pixel 21 are located, the opening area of ​​the second opening 411a is larger than the opening area of ​​the third opening 411b. In part (b) of Figure 13, in the pixel opening 411 where the light-emitting units 22 of the same color sub-pixel 21 are located, the opening area of ​​the second opening 411a is smaller than the opening area of ​​the third opening 411b.

[0133] For example, the opening areas of the pixel openings 411 where the light-emitting units 22 of the sub-pixels 21 of different colors are located are different.

[0134] For example, in the same sub-pixel 21, the orthogonal projection of the light-emitting unit 22 on the substrate 10 is located inside the orthogonal projection of the color resist block 23 on the substrate 10.

[0135] As shown in Figures 15 and 16, the display panel further includes an encapsulation layer 42, a touch metal layer 43, a black matrix 44, and a cover layer 45. The encapsulation layer 42 is located between the plurality of light-emitting units 22 and the plurality of color resist blocks 23. The touch metal layer 43 is located between the encapsulation layer 42 and the plurality of color resist blocks 23, and in the first pixel area, the dimming structure 40 covers the surface of the touch metal layer 43 away from the substrate 10 and the sidewalls of the touch metal layer 43. The black matrix 44 is located on the surface of the plurality of color resist blocks 23 away from the substrate 10, and the orthographic projection of the touch metal layer 43 on the substrate 10 is located inside the orthographic projection of the black matrix 44 on the substrate 10. In the first pixel area, the orthographic projection of the black matrix 44 on the substrate 10 is located inside the orthographic projection of the dimming structure 40 on the substrate 10. The cover layer 45 is located on the surface of the black matrix 44 and the plurality of color resist blocks 23 away from the substrate 10.

[0136] The encapsulation layer 42 protects multiple light-emitting units 22, blocking external water and oxygen and improving the reliability of the display panel. Touch functionality is achieved through the touch metal layer 43, and the dimming structure 40 protects the touch metal layer 43 within the first pixel area. The black matrix 44 increases color contrast and prevents light leakage. The orthographic projection of the black matrix 44 onto the substrate 10 is located inside the orthographic projection of the dimming structure 40 onto the substrate 10, reducing the absorption of light reflected by the dimming structure 40 by the black matrix 44, thereby improving the display brightness in privacy mode and sharing mode. The cover layer 45 protects the black matrix 44 and multiple color resist blocks 23.

[0137] Optionally, the display panel further includes a touch protection layer 46, which is located in the second pixel area and covers the surface of the touch metal layer 43 away from the substrate 10 and the sidewalls of the touch metal layer 43. A plurality of color resist blocks 23 in the second pixel area are located on the surface of the touch protection layer 46 away from the substrate 10. In this way, the touch protection layer 46 can protect the touch metal layer 43 in the second pixel area and facilitates planarization between the plurality of color resist blocks 23 and the touch metal layer 43 in the second pixel area.

[0138] For example, the surface of the touch protection layer 46 away from the substrate 10 is planar.

[0139] Optionally, the dimming structure 40 and the touch protection layer 46 are in the same layer. Here, "in the same layer" means formed by the same patterning process, or in contact with the same surface of the same film layer. This simplifies the process flow for fabricating the dimming structure 40.

[0140] Figure 17 is a partial structural diagram of the second pixel area of ​​another display panel provided in an embodiment of this disclosure. As shown in Figure 17, a touch protection layer may not be provided in the second pixel area of ​​the display panel.

[0141] Alternatively, the display panel may be an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, a micro light-emitting diode (Micro LED) display panel, or a liquid crystal (LC) display panel, etc.

[0142] The following explanation uses an OLED display panel as an example.

[0143] Optionally, the substrate 10 can be a drive backplane.

[0144] Optionally, the drive backplane can be a low-temperature polycrystalline oxide (LTPO) backplane or a low-temperature polycrystalline silicon (LTPS) backplane.

[0145] For example, the substrate 10 includes a substrate driving circuit layer that is stacked sequentially along the direction close to the plurality of light-emitting units 22.

[0146] Optionally, the driving circuit layer includes multiple thin-film transistors (TFTs).

[0147] Taking LTPO backplane as an example, multiple TFTs include low-temperature polycrystalline silicon TFTs and metal oxide TFTs.

[0148] Optionally, the driving circuit layer further includes a bottom light-shielding layer, a buffer layer, a first active layer, a first gate insulating layer, a first gate layer, a first insulating layer, a second gate layer, a second gate insulating layer, a second active layer, a third gate insulating layer, a third gate layer, an interlayer dielectric layer, a first source-drain layer, a passivation layer, a first planarization layer, a second source-drain layer, and a second planarization layer, stacked sequentially along the direction close to the plurality of light-emitting units 22.

[0149] For example, the data line is on the same layer as at least one of the first source-drain layer and the second source-drain layer.

[0150] As shown in Figures 15 to 17, the light-emitting unit 22 includes an anode 221, a light-emitting layer 222 and a cathode 223 stacked sequentially in a direction away from the substrate 10. A portion of the light-emitting layer 222 of the light-emitting unit 22 is located in the corresponding pixel opening 411, and the cathodes 223 of multiple light-emitting units 22 are connected.

[0151] For example, the light-emitting layer 222 may include an electron injection layer (EIL), an electron transport layer (ETL), a hole block layer (HBL), a light-emitting material layer, a hole transport layer (HTL), a hole injection layer (HIL), and an electron blocking layer (EBL) stacked sequentially in a direction away from the anode 221.

[0152] It should be noted that the film layer structure of the above-described display panel is only an example. In other embodiments, the display panel may include more or fewer film layer structures, which can be adjusted according to actual needs. This disclosure does not limit this.

[0153] Figure 18 is a flowchart of a control method for a display panel according to an embodiment of this disclosure. This control method can be used to control any of the aforementioned display panels. As shown in Figure 18, the control method includes:

[0154] In step S701, when the display panel is in the shared mode, the first gate driving line controls the light emission of sub-pixels in the first type of sub-pixel group and the second type of sub-pixel group, so as to control the light emission of sub-pixels in the first pixel and the second pixel.

[0155] In step S702, when the display panel is in privacy mode, the light emission of sub-pixels in the first type of sub-pixel group is controlled by the first gate driving line to control the light emission of sub-pixels in the first pixel.

[0156] It should be noted that the steps S701 to S702 above are not in any particular order.

[0157] The beneficial effects of the embodiments disclosed herein are shown in Figures 1 to 18, and will not be repeated here.

[0158] Optionally, if the light emission efficiency of the sub-pixel in the first pixel is greater than that of the sub-pixel in the second pixel, the above step S701 may include: when the display panel is in a shared mode, controlling the light-emitting unit of the target color in the first pixel to emit light at a first brightness, and controlling the light-emitting unit of the target color in the second pixel to emit light at a second brightness, wherein the second brightness is greater than the first brightness.

[0159] For example, the light-emitting unit of the target color can be one of the light-emitting units of the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel.

[0160] Since the light-emitting efficiency of the sub-pixels in the first pixel is greater than that in the second pixel, the light-emitting unit of the sub-pixels in the first pixel can achieve a higher display brightness with a lower light-emitting brightness. The second brightness is greater than the first brightness, which is beneficial to ensure that the display brightness of each sub-pixel of the same color is the same in the shared mode, thereby improving the display effect of the shared mode.

[0161] Optionally, step S702 may include: when the display panel is in privacy mode, controlling the light-emitting unit of the target color in the first pixel to emit light at a third brightness, the third brightness being different from the first brightness.

[0162] Since the light-emitting units of the sub-pixels in the first pixel emit light in both the privacy mode and the sharing mode, the first brightness and the third brightness are different, which helps to ensure the white balance of the privacy mode and thus improves the display effect of the privacy mode.

[0163] Figure 19 is a structural block diagram of a control device for a display panel according to an embodiment of this disclosure. This control device can be used to control any of the aforementioned display panels. As shown in Figure 19, the control device 1000 includes a first control module 1001 and a second control module 1002. The first control module 1001 is used to control the light emission of sub-pixels in a first type of sub-pixel group and a second type of sub-pixel group via a first gate driving line when the display panel is in a shared mode, thereby controlling the light emission of sub-pixels in the first pixel and the second pixel. The second control module 1002 is used to control the light emission of sub-pixels in the first type of sub-pixel group via a first gate driving line when the display panel is in a privacy mode, thereby controlling the light emission of sub-pixels in the first pixel.

[0164] It should be noted that the control device for the display panel provided in the above embodiments is only illustrated by the division of the above functional modules and units when controlling the display panel. In practical applications, the above functions can be assigned to different functional modules and units as needed, that is, the internal structure of the device can be divided into different functional modules and units to complete all or part of the functions described above. In addition, the control device for the display panel provided in the above embodiments and the control method embodiments for the display panel belong to the same concept, and the specific implementation process can be found in the method embodiments, which will not be repeated here.

[0165] This disclosure also provides a display device, which includes any of the aforementioned display panels and a power supply, wherein the display panel is electrically connected to the power supply.

[0166] Optionally, the display device can be any product or component with display function, such as a laptop, mobile phone, tablet, television, monitor, wearable device, or navigator.

[0167] The above description is not intended to limit this disclosure in any way. Although this disclosure has been disclosed above through embodiments, it is not intended to limit this disclosure. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this disclosure. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this disclosure without departing from the content of the technical solution of this disclosure shall still fall within the scope of the technical solution of this disclosure.

Claims

1. A display panel, characterized by, Includes a substrate, multiple pixels, and multiple first gate driving lines. The plurality of pixel arrays are arranged on the substrate. Each pixel includes a plurality of sub-pixels. The plurality of pixels includes a plurality of first pixels and a plurality of second pixels. The maximum light emission angle of the sub-pixels in the first pixels is smaller than the maximum light emission angle of the sub-pixels in the second pixels. The sub-pixels included in the plurality of pixels include a plurality of first sub-pixel groups arranged sequentially along a first direction. Each first sub-pixel group includes a plurality of sub-pixels arranged sequentially along a second direction. The first direction and the second direction intersect. The plurality of first sub-pixel groups include a plurality of first-type sub-pixel groups and a plurality of second-type sub-pixel groups arranged alternately along the first direction. The plurality of sub-pixels in the first-type sub-pixel groups are all sub-pixels in the first pixels. The plurality of sub-pixels in the second-type sub-pixel groups are all sub-pixels in the second pixels. The plurality of first gate driving lines are located on the substrate, and each first gate driving line extends along the second direction, and each first gate driving line is electrically connected to a plurality of sub-pixels in a first sub-pixel group.

2. The display panel of claim 1, wherein, The first gate driving line includes at least one of a light emission control line and a scan line.

3. The display panel of claim 2, wherein, The display panel also includes multiple reset control lines, which are located on the substrate and each of the reset control lines extends along the second direction. The multiple reset control lines include multiple first reset control lines and multiple second reset control lines. Each first reset control line is electrically connected to multiple sub-pixels in a first type sub-pixel group, and each second reset control line is electrically connected to multiple sub-pixels in a second type sub-pixel group. The waveforms of the reset control signals provided by at least one first reset control line and at least one second reset control line are the same.

4. The display panel of claim 3, wherein, The waveforms of the reset control signals provided by each of the first reset control lines and the adjacent second reset control lines are the same.

5. The display panel of any one of claims 1 to 4, wherein, The sub-pixels included in the plurality of pixels include a plurality of second sub-pixel groups arranged sequentially along the second direction, each second sub-pixel group includes a plurality of sub-pixels arranged sequentially along the first direction, and the second sub-pixel group includes sub-pixels in a plurality of first-type sub-pixel groups and a plurality of second-type sub-pixel groups arranged alternately along the first direction. The display panel also includes multiple data lines located on the substrate, each data line extending along the first direction and electrically connected to multiple sub-pixels in a second sub-pixel group.

6. The display panel of claim 5, wherein, The multiple sub-pixels in the second sub-pixel group have the same color.

7. The display panel of claim 5, wherein, The plurality of second sub-pixel groups include a plurality of third type sub-pixel groups and a plurality of fourth type sub-pixel groups arranged alternately along the second direction. Each third type sub-pixel group includes a plurality of first color sub-pixels and a plurality of third color sub-pixels arranged alternately along the first direction. Each fourth type sub-pixel group includes a plurality of second color sub-pixels arranged sequentially along the first direction.

8. The display panel according to any one of claims 1 to 4 and claims 6 to 7, characterized in that, The plurality of first pixels and the plurality of second pixels are arranged alternately in a third direction and a fourth direction. The third direction and the fourth direction intersect each other, and the third direction intersects both the first direction and the second direction. The fourth direction intersects both the first direction and the second direction.

9. The display panel of claim 8, wherein, Each sub-pixel in the pixel includes a first color sub-pixel, two second color sub-pixels and a third color sub-pixel, and in each pixel, the first color sub-pixel, the two second color sub-pixels and the third color sub-pixel are arranged sequentially along the second direction.

10. The display panel of claim 8, wherein, Each sub-pixel includes a light-emitting unit. Each sub-pixel in each pixel includes a first color sub-pixel, two second color sub-pixels, and a third color sub-pixel. In each pixel, the line connecting the center of the orthographic projection of the light-emitting unit of the first color sub-pixel on the substrate and the center of the orthographic projection of the light-emitting unit of the third color sub-pixel on the substrate intersects the line connecting the center of the orthographic projection of the light-emitting units of the two second color sub-pixels on the substrate. The extension direction of the line connecting the center of the orthographic projection of the light-emitting unit of the first color sub-pixel on the substrate and the center of the orthographic projection of the light-emitting unit of the third color sub-pixel on the substrate is one of the first direction and the second direction. The extension direction of the line connecting the center of the orthographic projection of the light-emitting units of the two second color sub-pixels on the substrate is the other of the first direction and the second direction.

11. The display panel of any of claims 1-4, 6-7, and 9-10, wherein, The substrate has a plurality of pixel regions arranged in an array, the plurality of pixel regions including a plurality of first pixel regions and a plurality of second pixel regions, each first pixel being located in a first pixel region and each second pixel being located in a second pixel region; Each of the sub-pixels includes light-emitting units and color resist blocks stacked sequentially in a direction away from the substrate; The display panel further includes a plurality of dimming structures, each of the dimming structures being located in a first pixel area and between the light-emitting unit and the color resist block, and the side of the dimming structure away from the substrate having a plurality of first openings; A portion of each of the color resist blocks in the first pixel region is located in one of the first openings, and the refractive index of the dimming structure is less than the refractive index of the color resist block.

12. A control method of a display panel, characterized by, The control method for controlling the display panel according to any one of claims 1 to 11, the control method comprising: When the display panel is in shared mode, the first gate driving line controls the light emission of sub-pixels in the first type of sub-pixel group and the second type of sub-pixel group, so as to control the light emission of sub-pixels in the first pixel and the second pixel; When the display panel is in privacy mode, the first gate driving line controls the light emission of sub-pixels in the first type of sub-pixel group to control the light emission of sub-pixels in the first pixel.

13. The control method according to claim 12, characterized by, The light extraction efficiency of the sub-pixels in the first pixel is greater than that of the sub-pixels in the second pixel; When the display panel is in shared mode, controlling the emission of sub-pixels in the first type of sub-pixel group and the second type of sub-pixel group through the first gate driving line includes: When the display panel is in the shared mode, the light-emitting unit of the target color in the first pixel is controlled to emit light at a first brightness, and the light-emitting unit of the target color in the second pixel is controlled to emit light at a second brightness, wherein the second brightness is greater than the first brightness.

14. The control method according to claim 13, characterized by, When the display panel is in privacy mode, controlling the light emission of sub-pixels in the first type of sub-pixel group via the first gate driving line includes: When the display panel is in the privacy mode, the light-emitting unit of the target color in the first pixel is controlled to emit light at a third brightness, which is different from the first brightness.

15. A display device comprising: It includes a display panel and a power supply as described in any one of claims 1 to 11, wherein the display panel is electrically connected to the power supply.

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