Roughness optimization method and apparatus
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- SHANGHAI CHUANXIN SEMICON CO LTD
- Filing Date
- 2025-04-02
- Publication Date
- 2026-07-02
AI Technical Summary
Existing technologies are unable to effectively reduce the edge roughness of the mask's light-shielding layer, leading to a decrease in wafer imaging accuracy and affecting device performance.
By depositing and etching light-shielding materials on the sidewalls of the mask light-shielding layer, the conformal growth characteristics of atomic layer deposition and etching are utilized to gradually fill pits and remove protrusions, thereby reducing the roughness of the sidewalls of the light-shielding layer.
It effectively reduces the roughness of the sidewalls of the mask's light-shielding layer, improves wafer imaging accuracy, and meets the requirements of high-precision chip manufacturing.
Smart Images

Figure CN2025086757_02072026_PF_FP_ABST