Superjunction semiconductor device

WO2026138048A1PCT designated stage Publication Date: 2026-07-02SEMICON MFG ELECTRONICS (SHAOXING) CORP

Patent Information

Authority / Receiving Office: WO · WO
Patent Type: Applications
Current Assignee / Owner: SEMICON MFG ELECTRONICS (SHAOXING) CORP
Filing Date: 2025-09-28
Publication Date: 2026-07-02

AI Technical Summary

Technical Problem

During switching, the gate-drain capacitance of superjunction MOSFET devices drops sharply due to the depletion of the P-type and N-type pillars, causing voltage oscillations, affecting system stability and electromagnetic interference characteristics, and limiting their wide application.

Method used

Introducing a second type of well region into a superjunction semiconductor device, by covering and isolating it from the gate, forms a floating state, avoids the influence of the voltage of the first type of well region, and only causes unidirectional depletion in the first type of well region, prolonging the depletion time and slowing down the Cgd decline trend.

Benefits of technology

It effectively suppresses voltage oscillations, increases Cgd, reduces electromagnetic interference, and improves device stability and performance.

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Figure CN2025124934_02072026_PF_FP_ABST

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Abstract

The embodiments of the present application provide a superjunction semiconductor device, comprising: a semiconductor material layer, comprising an upper surface and a lower surface opposite one another; a superjunction structure, located in the semiconductor material layer and comprising a plurality of pillars of a first conductivity type and a plurality of pillars of a second conductivity type that are arranged in an alternating manner; a well region of the first conductivity type, located in the semiconductor material layer and at a top end of each pillar of the first conductivity type, the well region of the first conductivity type comprising a well region of a first type and a well region of a second type; a gate, located on the upper surface; a first conductive plug, which passes through the gate and is conductively connected to the well region of the first type; a second conductive plug, which is located on the gate and is conductively connected thereto; the well region of the second type is covered by the gate, and the well region of the second type is insulated and isolated from both the first conductive plug and the second conductive plug; the well region of the second type extends from a core region to a terminal region, and the well region of the second type is disposed separately from the well region of the first type in both the core region and the terminal region.

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