Back-polished heterojunction solar cell and manufacturing method therefor

Abstract

The present invention provides a back-polished heterojunction solar cell and a manufacturing method therefor. The method comprises the following steps: successively depositing an intrinsic passivation layer, a first doped layer and a silicon nitride layer on the front surface of a double-sided textured silicon substrate, so as to obtain a first intermediate; performing annealing treatment on the first intermediate to obtain a second intermediate; performing back polishing and cleaning treatment and acid pickling treatment on the second intermediate to obtain a third intermediate; successively depositing an intrinsic passivation layer and a second doped layer on the back surface of the third intermediate to obtain a fourth intermediate; and respectively depositing transparent conductive films on surfaces of two sides of the fourth intermediate to prepare electrodes, so as to obtain the back-polished heterojunction solar cell. The method provided by the present invention has the technical effects of low production cost and significantly improving the electrical properties of solar cells.

Description

Back-projected heterojunction solar cells and their fabrication methods

[0001] Cross-reference of related applications

[0002] This application claims priority to Chinese patent application No. CN202411954796.4, filed on December 27, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to the field of photovoltaic technology, and in particular to a back-projected heterojunction solar cell and its preparation method. Background Technology

[0004] With increasing global energy demand and growing environmental problems, solar energy, as a clean and renewable energy source, has received widespread attention. Heterojunction (HJT) solar cells, due to their high efficiency and excellent electrical performance, have become a hot research topic in the photovoltaic industry. Back polishing technology is a crucial step in the production of HJT solar cells, significantly impacting the reflectivity and passivation effect of the cell's back surface.

[0005] In the production process of heterojunction solar cells, back polishing technology is generally used to increase the reflectivity of the back side of the cell, improve the absorption of long-wavelength light inside the cell, and simultaneously improve the passivation and grid contact effect on the back side. This is because a polished surface has a smaller specific surface area and fewer surface dangling bonds compared to a pyramidal surface, making it easier to passivate. When the grid silver paste contacts the back side of the cell, if a textured surface exists, the dangling effect of the pyramidal surface will result in a smaller contact area and increased contact resistance; however, with a polished surface, the paste can make full contact with the back side of the cell, thereby reducing contact resistance.

[0006] Current back polishing technologies typically employ processes such as double-sided texturing, double-sided thermal oxidation, chain-type single-sided pickling, alkaline polishing, and double-sided deposition. Among these, the double-sided thermal oxidation and chain-type single-sided pickling processes require specialized equipment and have higher production costs. Summary of the Invention

[0007] This invention provides a method for preparing a back-projected heterojunction solar cell, which achieves the technical effect of reducing production costs.

[0008] The present invention also provides a solar cell that achieves the technical effect of improving electrical performance.

[0009] This invention provides a method for fabricating a back-sponge heterojunction solar cell, comprising the following steps:

[0010] An intrinsic passivation layer, a first doped layer, and a silicon nitride layer are sequentially deposited on the front side of a double-textured silicon substrate to obtain a first intermediate.

[0011] The first intermediate is annealed, wherein the silicon nitride layer is adapted to release hydrogen and passivate the dangling bonds on the front side of the silicon substrate to obtain the second intermediate.

[0012] The second intermediate was subjected to back polishing and acid washing to obtain the third intermediate.

[0013] An intrinsic passivation layer and a second doped layer are sequentially deposited on the back side of the third intermediate to obtain a fourth intermediate.

[0014] Electrodes are fabricated by depositing transparent conductive films on both sides of the fourth intermediate to obtain the back-polished heterojunction solar cell.

[0015] The first doped layer is selected from either a p-type doped layer or an n-type doped layer, and the second doped layer is selected from either a p-type doped layer or an n-type doped layer.

[0016] Optionally, the annealing treatment is performed at a temperature of 100–200°C for 5–30 minutes.

[0017] Optionally, the refractive index of the silicon nitride layer is 1.5 to 2.0, and the thickness is 20 to 500 nm.

[0018] Optionally, the silicon nitride layer is deposited by PECVD at a temperature less than or equal to 210°C.

[0019] Optionally, the back polishing cleaning process includes a pre-cleaning process, a polishing process, and an RCA cleaning process performed sequentially;

[0020] The pre-cleaning process uses a cleaning solution that includes an alkaline substance and hydrogen peroxide.

[0021] The polishing process uses a cleaning solution that includes alkaline substances and back polishing additives.

[0022] The alkaline substance is selected from at least one of potassium hydroxide, sodium hydroxide, and tetramethylammonium hydroxide.

[0023] Optionally, the mass fraction of alkaline substances in the cleaning solution used in the pre-cleaning treatment is 0.1-10%, and the mass fraction of hydrogen peroxide is 0.1-10%.

[0024] Optionally, the pre-cleaning treatment is carried out at a temperature of 60–80°C for 2–4 minutes.

[0025] Optionally, the mass fraction of alkaline substances in the cleaning solution used for polishing is 0.1-10%, and the mass fraction of back polishing additive is 0.1-10%.

[0026] Optionally, the polishing process is carried out at a temperature of 50–85°C for 2–4 minutes.

[0027] Optionally, the pickling process includes using hydrofluoric acid with a mass fraction of 0.5-10% to remove the silicon nitride layer on the front side of the back-polishing product.

[0028] Optionally, the pickling treatment is carried out at a temperature of 20–35°C for a time of 0.5–6 min.

[0029] The present invention also provides a back-sprayed heterojunction solar cell, which is prepared using the above-described method for preparing a back-sprayed heterojunction solar cell. The back-sprayed heterojunction solar cell includes a silicon substrate, wherein the back side of the silicon substrate is smooth and the front side is textured.

[0030] An intrinsic passivation layer and a first doped layer are sequentially stacked on the front side of the silicon substrate in a direction away from the silicon substrate; an intrinsic passivation layer and a second doped layer are sequentially stacked on the back side of the silicon substrate in a direction away from the silicon substrate.

[0031] The first doped layer and the second doped layer are respectively provided with a transparent conductive film and an electrode on the side away from the silicon substrate.

[0032] This invention proposes an improved back-polishing process. After preparing an intrinsic passivation layer and a first doped layer on the front side of a silicon substrate, a silicon nitride layer is used as a protective layer for back-polishing to complete the single-sided back-polishing cleaning process, ultimately producing a solar cell. This method can be completed without the need for special equipment, offering advantages such as lower production costs and suitability for large-scale production. Furthermore, during the annealing process, the hydrogen released from the silicon nitride layer effectively passivates dangling bonds on the front side of the silicon substrate, thereby reducing the surface state density of the silicon substrate and improving the open-circuit voltage and overall performance of the cell. Additionally, the acid washing process to remove silicon nitride can reduce the thickness of the n-type doped layer to some extent, reducing light absorption and increasing the current density of the solar cell. Therefore, the process provided by this invention can also significantly improve the electrical performance of solar cells. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced one by one below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 is a flowchart of the method for preparing a back-sprayed heterojunction solar cell provided by the present invention;

[0035] Figure 2 is a structural diagram of the first intermediate in an embodiment of the present invention;

[0036] Figure 3 is a structural diagram of the product obtained after back-polishing cleaning of the second intermediate in an embodiment of the present invention.

[0037] Figure 4 is a structural diagram of the third intermediate in an embodiment of the present invention;

[0038] Figure 5 is a structural diagram of the fourth intermediate in an embodiment of the present invention;

[0039] Figure 6 is a structural diagram of a back-projected heterojunction solar cell provided in an embodiment of the present invention.

[0040] Explanation of reference numerals in the attached figures: 10 - Silicon substrate; 20 - Intrinsic passivation layer; 30 - n-type doped layer; 40 - p-type doped layer; 50 - Silicon nitride layer; 60 - Transparent conductive film; 70 - Electrode; 80 - Oxide layer. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in the embodiments of this invention will be clearly and completely described below in conjunction with the embodiments of this invention. Obviously, the described embodiments are only some embodiments of this invention, not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0042] The first aspect of this invention provides a method for fabricating a back-sponge heterojunction solar cell. Referring to Figure 1, the method includes the following steps:

[0043] S10: An intrinsic passivation layer, a first doped layer, and a silicon nitride layer are sequentially deposited on the front side of a double-textured silicon substrate to obtain a first intermediate.

[0044] S20: Anneal the first intermediate, wherein the silicon nitride layer is suitable for releasing hydrogen to passivate the dangling bonds on the front side of the silicon substrate, to obtain the second intermediate;

[0045] S30: The second intermediate is subjected to back polishing and acid washing to obtain the third intermediate;

[0046] S40: An intrinsic passivation layer and a second doped layer are sequentially deposited on the back side of the third intermediate to obtain the fourth intermediate;

[0047] S50: Electrodes are prepared by depositing transparent conductive films on both sides of the fourth intermediate to obtain a back-polished heterojunction solar cell.

[0048] The first doped layer is selected from either a p-type doped layer or an n-type doped layer, and the second doped layer is selected from either a p-type doped layer or an n-type doped layer. For example, when the first doped layer is an n-type doped layer, the second doped layer is a p-type doped layer. The following explanation assumes that the first doped layer is an n-type doped layer and the second doped layer is a p-type doped layer.

[0049] The above-mentioned method for preparing solar cells will be described in detail below with reference to Figures 2 to 6.

[0050] Referring to Figure 2, the fabrication method of the back-polished heterojunction solar cell provided by this invention begins with a double-textured silicon substrate 10. The texturing process forms a micro-textured structure on the silicon substrate 10 to reduce surface reflection and enhance light absorption efficiency. The double-textured silicon substrate 10 used in this invention can be fabricated using conventional methods, for example, by forming a pyramid structure on the surface of the silicon substrate 10 using an alkaline solution (such as potassium hydroxide or sodium hydroxide). By controlling the temperature and time, a surface roughness suitable for subsequent processes can be obtained. Based on this, an intrinsic passivation layer 20 and an n-type doped layer 30 (the first doped layer) are sequentially deposited on the front side of the silicon substrate 10. The intrinsic passivation layer 20 is typically made of undoped amorphous silicon (a-Si) and deposited using plasma-enhanced chemical vapor deposition (PECVD), which effectively reduces surface carrier recombination and improves the lifetime of photogenerated carriers. The n-type doped layer 30 is composed of a phosphorus-doped silicon layer and is mainly used to improve electronic conductivity, contributing to more efficient carrier collection.

[0051] It is worth noting that, since the double-textured silicon substrate 10 has two surfaces, for ease of distinction, in the above steps, the surface on which the intrinsic passivation layer 20, the n-type doped layer 30, and the silicon nitride layer 50 are deposited is called the front side, and the other surface is called the back side. The front and back sides determined in the above steps are applicable and unchanged in the remaining steps.

[0052] To further enhance the passivation effect, the method for fabricating a back-polished heterojunction solar cell provided by this invention deposits a silicon nitride (SiNx) layer as a protective layer using plasma-enhanced chemical vapor deposition (PECVD) on the n-type doped layer 30. The silicon nitride layer 50 not only contributes to passivation but also serves as a protective layer on the front side during subsequent back-polishing and annealing processes, preventing the introduction of impurities. After the silicon nitride layer 50 is deposited, a first intermediate is obtained. This first intermediate includes a silicon substrate 10 that has undergone double-sided texturing. An intrinsic passivation layer 20, an n-type doped layer 30, and a silicon nitride layer 50 are sequentially deposited on the front side of the silicon substrate 10. Subsequently, the first intermediate undergoes an annealing process.

[0053] Annealing refers to heating the first intermediate at a specific temperature for a specific time. This invention does not limit the specific processing conditions of annealing and can use common processing conditions in the field. The second intermediate is obtained after the annealing process is completed.

[0054] Referring to Figures 3 and 4, after annealing, the second intermediate is subjected to back-polishing and acid pickling processes sequentially. Back-polishing removes the pyramidal morphology on the back side of the second intermediate and forms an oxide layer 80, resulting in the structure shown in Figure 3. Acid pickling removes the silicon nitride layer 50 on the front side and the oxide layer 80 on the back side of the second intermediate, resulting in the third intermediate shown in Figure 4. Compared to the first intermediate, the pyramidal structure on the back side of the silicon substrate 10 in the third intermediate is etched away, resulting in a smooth morphology; furthermore, the silicon nitride layer 50 included in the first intermediate is also removed.

[0055] This invention does not limit the specific processing method of back-polishing cleaning. Common processing methods in the art can be used. For example, an aqueous solution containing an alkaline substance (e.g., at least one of potassium hydroxide, sodium hydroxide, and tetramethylammonium hydroxide) can be used to contact the second intermediate to meet the requirement of removing the pyramidal morphology. This invention also does not limit the specific processing method of acid washing. An aqueous solution containing an acidic substance (e.g., hydrogen fluoride) can be used to contact the second intermediate to remove the silicon nitride layer 50 on the front side of the second intermediate, thus completing the back-polishing cleaning process.

[0056] Referring to Figure 5, after back-polishing and acid washing, an intrinsic passivation layer 20 and a p-type doped layer 40 are sequentially deposited on the back side of the third intermediate to form a heterojunction structure on the back side, resulting in the fourth intermediate as shown in Figure 5. Compared to the third intermediate, the fourth intermediate has an intrinsic passivation layer 20 and a p-type doped layer 40 sequentially deposited on the back side of the silicon substrate 10. The p-type doped layer 40 is typically achieved through a boron-doped silicon layer, which, together with the n-type doped layer 30 on the front side of the silicon substrate 10, forms a pn junction.

[0057] Referring to Figure 6, a transparent conductive thin film 60 (such as indium tin oxide (ITO) or zinc aluminum oxide (AZO) is deposited on both the front and back sides of the fourth intermediate to ensure good light transmittance and conductivity of the cell. The front and back electrodes 70 are then fabricated using screen printing or electroplating techniques, ultimately resulting in a back-polished heterojunction solar cell.

[0058] The inventors discovered that the solar cells fabricated using the above method exhibit superior electrical performance. This is because, firstly, since the silicon nitride layer 50 is rich in hydrogen, during the annealing process, hydrogen atoms in the silicon nitride layer 50 diffuse through the n-type doped layer 30 and the intrinsic passivation layer 20 to the interface between the intrinsic passivation layer 20 and silicon, effectively passivating the dangling bonds located there, thereby significantly reducing the surface state density and improving the passivation effect at the interface. Secondly, while the n-type doped layer 30 plays a passivation role, it also absorbs light, affecting the current of the solar cell. The solar cell fabrication method provided by this invention, during the process of removing silicon nitride using an etching method, has a slight etching effect on the n-type doped layer 30, reducing the light absorption of the n-type doped layer 30 and thus increasing the current of the solar cell. In the above process, since the enhanced passivation effect of hydrogen implantation into silicon nitride far outweighs the passivation effect lost by the etching of the n-type doped layer 30, the solar cells fabricated using the above method generally exhibit superior electrical performance.

[0059] Furthermore, after fabricating an intrinsic passivation layer 20 and an n-type doped layer 30 on the front side of the silicon substrate 10, the above process utilizes a silicon nitride layer 50 as a protective layer for back-polishing to complete the single-sided back-polishing cleaning process, ultimately producing a solar cell. This method can be completed without the need for special equipment, offering advantages such as lower production costs and suitability for large-scale production.

[0060] To improve the electrical performance of the fabricated solar cell, in one embodiment, the annealing temperature is controlled to be 100–200°C, and the processing time is controlled to be 5–30 min. Under these temperature and time conditions, hydrogen atoms in the silicon nitride layer 50 gain sufficient diffusion capacity due to thermal energy and gradually migrate to the interface between the n-type doped layer 30 and the silicon substrate 10. Hydrogen atoms can passivate dangling bonds on the silicon surface, reducing interface states and lowering the recombination probability of charge carriers, thereby improving the passivation effect and resulting in a solar cell with better performance. Simultaneously, controlling the temperature below 200°C avoids the formation of lattice defects or surface oxidation caused by excessively high temperatures, thus maintaining the structural and performance stability of the cell. Furthermore, controlling the temperature within the range of 100–200°C avoids surface structural changes or contamination of the silicon substrate 10 caused by high temperatures, thereby maintaining the stability and cleanliness of the device surface. This temperature range facilitates the effective diffusion of hydrogen atoms without introducing new defects or damage.

[0061] In one embodiment, the refractive index of the silicon nitride layer 50 can be controlled to be 1.5–2.0, and its thickness to be 20–500 nm. The refractive index of silicon nitride increases with its silicon content. When the refractive index of silicon nitride is 1.5–2.0, the silicon nitride has a low silicon content, which gives it excellent alkali resistance, preventing corrosion by alkaline substances during subsequent back-polishing and cleaning processes, thus protecting the structure covered by the silicon nitride layer 50. Furthermore, the 20–500 nm thickness of the silicon nitride layer 50 provides sufficient structural integrity and chemical stability for subsequent processes, effectively passivating the surface and preventing direct erosion of the silicon substrate 10 by alkaline and acid washing processes, resulting in high reliability of the battery in subsequent processing and use.

[0062] In one embodiment, a silicon nitride layer 50 can be conveniently and quickly deposited using the PECVD method. To further improve the electrical performance of the solar cell, the deposition temperature of the silicon nitride layer 50 can be controlled to be less than or equal to 210°C. Depositing the silicon nitride layer 50 at a temperature below 210°C allows the hydrogen in the silicon nitride layer 50 to be retained more stably, reducing the escape of hydrogen atoms during the deposition process and providing a sufficient hydrogen source for subsequent annealing. Sufficient hydrogen atoms can diffuse into the silicon substrate 10 and passivate dangling bonds during the subsequent annealing process, further improving the passivation effect.

[0063] In one embodiment, the back polishing cleaning process includes a pre-cleaning process, a polishing process, and an RCA cleaning process performed sequentially.

[0064] The pre-cleaning process uses a cleaning solution that includes alkaline substances and hydrogen peroxide.

[0065] Polishing uses a cleaning solution that includes alkaline substances and back polishing additives;

[0066] The alkaline substance is selected from at least one of potassium hydroxide, sodium hydroxide, and tetramethylammonium hydroxide.

[0067] The purpose of pre-cleaning is to remove organic contaminants and oxide layers from the back of the silicon substrate 10, forming a clean surface. This step is accomplished using a cleaning solution containing an alkaline substance and hydrogen peroxide. Commonly used alkaline substances include at least one of potassium hydroxide (KOH), sodium hydroxide (NaOH), and tetramethylammonium hydroxide (TMAH). By controlling the concentration and temperature of the cleaning solution, effective removal of surface impurities can be achieved, thus laying the foundation for subsequent polishing. In practice, the ratio of alkaline substance to hydrogen peroxide in the cleaning solution can be adjusted according to actual needs to ensure optimal cleaning results.

[0068] The purpose of polishing is to further improve the flatness and reflectivity of the back side of the silicon substrate 10, thereby optimizing its optical properties. This step uses a cleaning solution containing an alkaline substance and a back-polishing additive to make the silicon surface smoother, thus reducing light scattering and loss. The choice of alkaline substance is consistent with the pre-cleaning process, and at least one of potassium hydroxide, sodium hydroxide, and tetramethylammonium hydroxide can be used, while the type and concentration of the back-polishing additive can be adjusted according to the actual process conditions. By controlling the combination of alkaline substances and additives, the polishing process achieves a good flatness on the back side, reduces surface roughness, and thus improves photoelectric conversion efficiency.

[0069] This invention does not limit the specific components of the back-polishing additive; commonly used back-polishing additives in the art can be used. In one embodiment, the back-polishing additive includes sodium benzoate and a surfactant.

[0070] Residual carbon dioxide (RCA) cleaning is a crucial step in removing residual metal ions and microparticles from the back side of the silicon substrate 10 to further purify the back surface. RCA cleaning typically involves two steps: RCA1 and RCA2, which treat the back side using alkaline and acidic solutions, respectively, to remove residual organic matter and metallic impurities. In the RCA1 step, the cleaning solution consists of ammonia or an alkali (e.g., at least one of potassium hydroxide, sodium hydroxide, and tetramethylammonium hydroxide) and hydrogen peroxide to remove organic matter and particles. In the RCA2 step, a mixture of hydrochloric acid and hydrogen peroxide is used to remove metallic impurities. RCA cleaning conditions (such as solution concentration, temperature, and time) can be optimized as needed to ensure the purity of the silicon substrate 10 surface, providing an ideal interface for subsequent deposition processes.

[0071] Through the aforementioned back-polishing cleaning process, the back side of the silicon substrate 10 achieves a high level of cleanliness and smoothness, laying a solid foundation for subsequent production. This treatment method not only ensures high reflectivity and low surface recombination rate on the back side of the battery, but also effectively improves the battery's photoelectric conversion efficiency and long-term stability.

[0072] In one specific embodiment, the back polishing cleaning process includes the following steps: First, pre-cleaning is performed in a mixed solution of 0.1-10% alkaline substance and 0.1-10% hydrogen peroxide, wherein the alkaline substance is preferably at least one of potassium hydroxide, sodium hydroxide, and tetramethylammonium hydroxide, at a temperature of 60-80°C, for a cleaning time of 2-4 minutes; then, back-side polishing is performed in a mixed solution of 0.01-10% alkaline substance and 0.01-10% back polishing additive, wherein the alkaline substance is preferably at least one of potassium hydroxide, sodium hydroxide, and tetramethylammonium hydroxide, at a temperature of 50-85°C, for a reaction time of 2-4 minutes. Finally, RCA cleaning, including RCA1 and RCA2, is performed. First, RCA1 is cleaned using a mixed solution of 0.1-10% alkaline substance and 0.1-10% hydrogen peroxide. The alkaline substance is preferably at least one of potassium hydroxide, sodium hydroxide, and tetramethylammonium hydroxide. The temperature is 60-80℃ and the cleaning time is 2-4 minutes. Then, RCA2 is cleaned using a mixed solution of 0.1-10% hydrochloric acid and 0.1-10% hydrogen peroxide. The temperature is 60-80℃ and the cleaning time is 2-4 minutes.

[0073] To achieve better results in the pre-cleaning treatment, in one embodiment, the mass fraction of the alkaline substance and the hydrogen peroxide in the cleaning solution used for the pre-cleaning treatment are 0.1-10% by mass. Alkaline substances (such as potassium hydroxide, sodium hydroxide, or tetramethylammonium hydroxide) have good dissolving and removal effects on organic contaminants within a concentration range of 0.1-10%, and can slightly etch the oxide layer 80, thereby cleaning the surface. However, due to the moderate concentration, the alkaline substances will not cause excessive corrosion to the silicon substrate 10, effectively controlling the surface roughness and integrity of the silicon substrate 10. Hydrogen peroxide mainly acts as an oxidant in the cleaning solution, achieving a cleaning effect by oxidizing and decomposing surface contaminants. Appropriate use can promote the decomposition of organic matter, but controlling the concentration range of 0.1-10% avoids excessive oxidation of the silicon substrate 10 by hydrogen peroxide, making the surface cleaning gentler.

[0074] Furthermore, the pre-cleaning treatment temperature can be controlled at 60–80℃, and the treatment time at 2–4 minutes. Appropriate treatment temperature and time can achieve efficient cleaning and protection of the substrate surface. Within this temperature range, the reaction rate between the alkaline cleaning solution and hydrogen peroxide is moderate, accelerating the decomposition and removal of organic matter and the oxide layer 80, significantly improving cleaning efficiency. Thorough cleaning can be achieved in a short time, avoiding substrate surface damage caused by prolonged treatment. Simultaneously, this temperature control effectively reduces the depth of etching on the silicon substrate 10, maintaining its surface structural integrity, reducing surface recombination rate, and ensuring that the cleaned silicon substrate 10 is smooth and pure, providing a high-quality interface for subsequent polishing and passivation processes. The balance between temperature and time not only improves the cleaning effect but also provides a good foundation for the photoelectric performance of the battery.

[0075] To achieve better polishing results, in one embodiment, the mass fraction of alkaline substances and the mass fraction of back-polishing additives in the cleaning solution used for polishing can be controlled to be 0.1%–10%. Appropriate cleaning solution concentrations can achieve good surface smoothness and optimized light reflection performance. Within this concentration range, alkaline substances (such as potassium hydroxide, sodium hydroxide, or tetramethylammonium hydroxide) can moderately etch the back side of the silicon substrate 10, removing minor surface defects and impurities without causing over-etching, thereby improving the surface smoothness of the silicon substrate 10 in a shorter time. Adding a back-polishing additive with a mass fraction of 0.1%–10% can further control the etching rate, making the polishing process more uniform, ensuring a smoother substrate surface after treatment, helping to reduce surface light scattering, and improving the back-side reflection effect.

[0076] In the above process, alkaline substances provide the chemical driving force for etching, while back-polishing additives (such as isopropanol and EDTA) can change the viscosity of the solution or adjust the uniformity of etching, enabling the silicon substrate 10 surface to achieve uniform polishing through mild etching. The combined effect of alkaline substances and back-polishing additives within this concentration range helps to effectively control surface roughness, providing a high-reflectivity and low-recombination-rate interface for the back of the battery, thereby improving the photoelectric conversion efficiency and overall performance of the battery.

[0077] In one embodiment, the polishing temperature can be controlled to be 50–85°C, and the processing time to be 2–4 minutes. Suitable processing conditions can achieve efficient and smooth polishing and surface protection of the silicon substrate 10. Within this temperature range, the chemical reaction rate between the alkaline substances in the cleaning solution and the back-polishing additives is moderate, effectively removing minute defects and irregular structures on the surface of the silicon substrate 10, resulting in a smoother surface and reduced light scattering. A higher temperature (close to 85°C) helps to increase the etching rate, thereby completing polishing in a short time, while ensuring a gentle effect of the solution on the surface of the silicon substrate 10, avoiding excessive corrosion that could damage the surface structure.

[0078] Under these temperature and time conditions, the polishing process efficiently removes particles, lightly etches the oxide layer 80, and other impurities from the silicon surface, resulting in a smooth surface. This temperature control range ensures the activity of the cleaning solution without significantly damaging the silicon substrate 10, maintaining the integrity and uniformity of the surface structure. Furthermore, the shorter processing time (2–4 min) avoids excessive etching caused by prolonged processing, ensuring that the polishing process is limited to surface fine-tuning and providing a high-quality, smooth interface for subsequent passivation processes. This optimized polishing effect ultimately improves the reflectivity and photoelectric conversion efficiency of the solar cell, contributing to improved overall performance.

[0079] The acid pickling process involves using 0.5–10% hydrofluoric acid to remove the silicon nitride layer 50 on the front side and the oxide layer 80 on the back side of the product obtained from the back polishing process, facilitating the remaining steps. The oxide layer 80 is formed during the RCA2 cleaning process; specifically, hydrogen peroxide used in the RCA2 cleaning process contacts the silicon substrate 10 to form the oxide layer 80. In one embodiment, the acid pickling temperature can be controlled at 20–35°C, and the processing time at 0.5–6 minutes. These processing conditions allow the acid pickling process to remove the silicon nitride layer 50 and the oxide layer 80 without damaging the silicon substrate 10 or other deposited layers, thereby resulting in a solar cell with better electrical performance.

[0080] In one embodiment, electrode 70 is a metal electrode.

[0081] A second aspect of the present invention provides a solar cell fabricated using any of the solar cell fabrication methods provided in the first aspect of the present invention. The back-polished heterojunction solar cell includes a silicon substrate 10, the back side of which is smooth and the front side is textured.

[0082] An intrinsic passivation layer 20 and a first doped layer are stacked sequentially on the front side of the silicon substrate 10 along the direction away from the silicon substrate 10; an intrinsic passivation layer 20 and a second doped layer are stacked sequentially on the back side of the silicon substrate 10 along the direction away from the silicon substrate 10.

[0083] The first doped layer and the second doped layer are respectively provided with a transparent conductive film 60 and an electrode 70 on the side opposite to the silicon substrate 10.

[0084] In one embodiment, electrode 70 is a metal electrode.

[0085] The solar cell provided by this invention has excellent electrical performance. Specifically, the solar cell provided by this invention has high Jsc (short-circuit current density), Uoc (open-circuit voltage), FF (fill factor), and Eta (photovoltaic conversion efficiency).

[0086] The following detailed description of the method for preparing solar cells provided by the present invention is provided through specific embodiments.

[0087] Example 1

[0088] This embodiment uses the following method to prepare a back-balled heterojunction solar cell:

[0089] 1) An intrinsic passivation layer 20, an n-type doped layer 30, and a silicon nitride layer 50 are sequentially deposited on the front side of a double-textured silicon substrate 10 to obtain a first intermediate.

[0090] The intrinsic passivation layer 20 has a thickness of 6 nm; the n-type doped layer 30 has a thickness of 18 nm; the silicon nitride layer 50 has a refractive index of 1.7 and a thickness of 150 nm; the silicon nitride layer 50 is deposited by PECVD at a deposition temperature of 200 °C.

[0091] 2) Anneal the first intermediate to obtain the second intermediate;

[0092] The annealing process takes 20 minutes and is carried out at a temperature of 150°C.

[0093] 3) The second intermediate is subjected to back polishing and acid washing to obtain the third intermediate;

[0094] The back polishing cleaning process includes pre-cleaning, polishing, and RCA cleaning in sequence.

[0095] The cleaning solution used in the pre-cleaning treatment contains 5% potassium hydroxide and 5% hydrogen peroxide by mass; the pre-cleaning treatment temperature is 70℃ and the treatment time is 3 minutes.

[0096] The cleaning solution used for polishing contains potassium hydroxide at a mass fraction of 5%, and the main components of the back polishing additive are polyvinylpyrrolidone, citric acid, sodium acetate, and polyvinyl alcohol at a mass fraction of 3%. The polishing temperature is 70℃ and the treatment time is 2 minutes.

[0097] The RCA cleaning process includes sequential RCA1 and RCA2 cleaning. RCA1 cleaning is performed using a cleaning solution containing 5% alkaline substance and 5% hydrogen peroxide. The alkaline substance is potassium hydroxide, the temperature is 65°C, and the cleaning time is 4 minutes. RCA2 cleaning is then performed using a mixed solution of 5% hydrochloric acid and 5% hydrogen peroxide at 65°C for 4 minutes.

[0098] The pickling process involves using 5% hydrofluoric acid to remove the silicon nitride layer 50 on the front side and the oxide layer 80 on the back side. The pickling temperature is 25°C and the processing time is 2 minutes.

[0099] 4) An intrinsic passivation layer 20 and a p-type doped layer 40 are sequentially deposited on the back side of the third intermediate to obtain the fourth intermediate;

[0100] The intrinsic passivation layer 20 has a thickness of 6 nm; the p-type doped layer 40 has a thickness of 20 nm.

[0101] 5) After depositing transparent conductive films 60 on both sides of the fourth intermediate, metal electrodes 70 are prepared to obtain a back-sprayed heterojunction solar cell A.

[0102] Comparative Example 1

[0103] 1) A silicon substrate 10 with a dense oxide layer 80 on both the front and back sides is obtained by double-sided oxidation in a diffusion furnace after texturing the silicon substrate 10 on both sides.

[0104] 2) Remove the oxide layer 80 on one side using a chain pickling machine with 5% HF acid to obtain the first intermediate;

[0105] 3) The first intermediate is subjected to back polishing and acid washing to obtain the second intermediate;

[0106] The back polishing cleaning process includes pre-cleaning, polishing, and RCA cleaning in sequence.

[0107] The cleaning solution used in the pre-cleaning treatment contains 5% potassium hydroxide and 5% hydrogen peroxide by mass; the pre-cleaning treatment temperature is 70℃ and the treatment time is 3 minutes.

[0108] The cleaning solution used for polishing contains potassium hydroxide at a mass fraction of 5%, and the main components of the back polishing additive are polyvinylpyrrolidone, citric acid, sodium acetate, and polyvinyl alcohol at a mass fraction of 3%. The polishing temperature is 70℃ and the treatment time is 2 minutes.

[0109] The RCA cleaning process includes sequential RCA1 and RCA2 cleaning. RCA1 cleaning is performed using a cleaning solution containing 5% alkaline substance and 5% hydrogen peroxide. The alkaline substance is potassium hydroxide, the temperature is 65°C, and the cleaning time is 4 minutes. RCA2 cleaning is then performed using a mixed solution of 5% hydrochloric acid and 5% hydrogen peroxide at 65°C for 4 minutes. Finally, 5% hydrofluoric acid is used to remove the oxide layer 80 on both sides. The acid pickling treatment is performed at 25°C for 2 minutes.

[0110] 4) An intrinsic passivation layer 20 is deposited on the front and back sides of the second intermediate, and then an n-type doped layer 30 is deposited on the front side and a p-type doped layer 40 is deposited on the back side to obtain the third intermediate.

[0111] The intrinsic passivation layer 20 has a thickness of 6 nm; the n-type doped layer 30 has a thickness of 18 nm; and the p-type doped layer 40 has a thickness of 20 nm.

[0112] 5) After depositing transparent conductive films 60 on both sides of the fourth intermediate, metal electrodes 70 are prepared to obtain a back-sprayed heterojunction solar cell B.

[0113] Test case

[0114] The electrical performance of back-projected heterojunction solar cells A and B was tested using a Halm IV tester, and the results are shown in Table 1.

[0115] Table 1 Electrical performance test data

[0116] As shown in Table 1, compared to battery B, the short-circuit current density of battery A increased by 0.086 mA / cm². 2 The open-circuit voltage increased by 0.0017V, the fill factor increased by 0.27%, and the photoelectric conversion efficiency increased by 0.19%. This indicates that the preparation method provided by this invention can effectively improve the short-circuit current density, open-circuit voltage, fill factor, and photoelectric conversion efficiency of back-sprayed heterojunction solar cells.

[0117] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for fabricating a back-polished heterojunction solar cell, characterized in that, Includes the following steps: An intrinsic passivation layer, a first doped layer, and a silicon nitride layer are sequentially deposited on the front side of a double-textured silicon substrate to obtain a first intermediate. The first intermediate is annealed, wherein the silicon nitride layer is adapted to release hydrogen and passivate the dangling bonds on the front side of the silicon substrate to obtain the second intermediate. The second intermediate was subjected to back polishing and acid washing to obtain the third intermediate. An intrinsic passivation layer and a second doped layer are sequentially deposited on the back side of the third intermediate to obtain a fourth intermediate. Electrodes are fabricated by depositing transparent conductive films on both sides of the fourth intermediate to obtain the back-polished heterojunction solar cell. The first doped layer is selected from either a p-type doped layer or an n-type doped layer, and the second doped layer is selected from either a p-type doped layer or an n-type doped layer.

2. The preparation method according to claim 1, characterized in that, The annealing process is carried out at a temperature of 100–200°C for 5–30 minutes.

3. The preparation method according to claim 1 or 2, characterized in that, The silicon nitride layer has a refractive index of 1.5 to 2.0 and a thickness of 20 to 500 nm.

4. The preparation method according to any one of claims 1 to 3, characterized in that, The silicon nitride layer is deposited by PECVD at a temperature less than or equal to 210°C.

5. The preparation method according to any one of claims 1 to 4, characterized in that, The back-polishing cleaning process includes a pre-cleaning process, a polishing process, and an RCA cleaning process performed sequentially. The pre-cleaning process uses a cleaning solution that includes an alkaline substance and hydrogen peroxide. The polishing process uses a cleaning solution that includes alkaline substances and back polishing additives. The alkaline substance is selected from at least one of potassium hydroxide, sodium hydroxide, and tetramethylammonium hydroxide.

6. The preparation method according to claim 5, characterized in that, The pre-cleaning treatment uses a cleaning solution with an alkaline substance mass fraction of 0.1-10% and a hydrogen peroxide mass fraction of 0.1-10%; and / or, The pre-cleaning process is carried out at a temperature of 60–80°C for 2–4 minutes.

7. The preparation method according to claim 5 or 6, characterized in that, The cleaning solution used in the polishing process contains 0.1-10% alkaline substances by mass and 0.1-10% back polishing additives by mass; and / or, The polishing process is carried out at a temperature of 50–85°C for 2–4 minutes.

8. The preparation method according to any one of claims 1 to 7, characterized in that, The pickling process includes using hydrofluoric acid with a mass fraction of 0.5-10% to remove the silicon nitride layer on the front side of the back-polishing product.

9. The preparation method according to any one of claims 1 to 8, characterized in that, The pickling process is carried out at a temperature of 20–35°C for a duration of 0.5–6 min.

10. A back-projected heterojunction solar cell, characterized in that, The back-polished heterojunction solar cell, prepared using the method of any one of claims 1 to 9, comprises a silicon substrate, wherein the back side of the silicon substrate is smooth and the front side is textured. An intrinsic passivation layer and a first doped layer are sequentially stacked on the front side of the silicon substrate in a direction away from the silicon substrate; an intrinsic passivation layer and a second doped layer are sequentially stacked on the back side of the silicon substrate in a direction away from the silicon substrate. The first doped layer and the second doped layer are respectively provided with a transparent conductive film and an electrode on the side away from the silicon substrate.

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