Pixel circuit, display panel and electronic device

Abstract

The present application provides a pixel circuit, a display panel and an electronic device. The pixel circuit comprises: an analog drive module, a digital PWM module and a drive current output module, wherein the digital PWM module can generate, on the basis of bit-by-bit comparison between a data signal and a cyclic counting signal, a single-pulse light-emission signal used for indicating a target duration, so as to control a target duration of a driving current, thereby reducing the complexity of the digital PWM module adjusting the target duration of the drive current, and further reducing the overall circuit complexity and calculation complexity of the PWM module, a pixel circuit where the PWM module is located, and a display panel.

Description

Pixel circuits, display panels and electronic devices

[0001] This application claims priority to Chinese patent application filed on December 27, 2024, with application number 202411956809.1 and entitled "Pixel Circuit, Display Panel and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, and more particularly to a pixel circuit, display panel, and electronic device. Background Technology

[0003] In some electronic device display panels, light-emitting devices such as Micro-LEDs are arranged in rows and columns to form a basic display structure, with each light-emitting device connected to a corresponding pixel circuit. The pixel circuit can generate driving current and send it to the corresponding light-emitting device to make it emit light.

[0004] In existing technologies, pixel circuits can adjust the current value and duration of the driving current they send to the light-emitting device. When the current value and duration of the driving current received by the light-emitting device are different, the brightness of the light emitted by the light-emitting device will also be different. However, the method of adjusting the duration of the driving current in existing technologies is relatively complex, resulting in high circuit complexity and computational complexity of the pixel circuit and the display panel in which it is located. Summary of the Invention

[0005] This application provides a pixel circuit, a display panel, and an electronic device to reduce the complexity of adjusting the duration of the drive current in the pixel circuit, thereby reducing the overall circuit complexity and computational complexity of the pixel circuit.

[0006] A first aspect of this application provides a pixel circuit, comprising: an analog driving module for generating a driving current; a digital PWM module for generating a single-pulse light-emitting signal of a one-bit structure for indicating a target duration by comparing a multi-bit data signal with a cyclic counting signal bit by bit, and storing the single-pulse light-emitting signal to ensure driving control of the single-pulse light-emitting signal within the target duration; and a driving current output module for providing the driving current to at least one light-emitting device within the target duration according to the single-pulse light-emitting signal.

[0007] A second aspect of this application provides a display panel, including at least one pixel circuit as provided in the first aspect of this application; and a control circuit for sending at least one of a data signal, a scan signal, a count signal, an indication signal, a first flip indication signal, or a second flip indication signal to the digital PWM module to control the digital PWM module to generate a single-pulse light emission signal indicating the target duration.

[0008] A third aspect of this application provides an electronic device, including the display panel provided in the second aspect of this application.

[0009] The pixel circuit, display panel, and electronic device provided in this application integrate analog driving processing and digital modulation processing. That is, the pixel circuit can adjust the current value of the driving current through analog adjustment and adjust the duration of the driving current through digital adjustment. This achieves more flexible adjustment of the driving current and reduces the number of analog components required when the pixel circuit adjusts the driving current through pure analog means, thereby reducing the physical space occupied by the pixel circuit. At the same time, the digital PWM module can generate a single-pulse light emission signal to indicate the continuous emission of the target by comparing the data signal with the cyclic counting signal bit by bit, thereby controlling the target duration of the driving current. Therefore, the complexity of the digital PWM module of the pixel circuit adjusting the target duration of the driving current is reduced, thereby reducing the circuit complexity and computational complexity of the PWM module, the pixel circuit, and the display panel as a whole. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 is a structural schematic diagram of an embodiment of the display panel provided in this application;

[0012] Figure 2 is a structural schematic diagram of an embodiment of the display panel provided in this application;

[0013] Figure 3 is a structural schematic diagram of an embodiment of the digital PWM module provided in this application;

[0014] Figure 4 is a schematic diagram of the circuit structure of an embodiment of the digital PWM module provided in this application;

[0015] Figure 5 is a signal timing diagram of the digital PWM module provided in this application;

[0016] Figure 6 is another signal timing diagram of the digital PWM module provided in this application;

[0017] Figure 7 is a schematic diagram of the circuit structure of another embodiment of the digital PWM module provided in this application;

[0018] Figure 8 is a schematic diagram of the circuit structure of an embodiment of the storage structure provided in this application;

[0019] Figure 9 is a schematic diagram of the circuit structure of an embodiment of the signal storage unit provided in this application;

[0020] Figure 10 is a schematic diagram of the circuit structure of an embodiment of the comparison result output device provided in this application;

[0021] Figure 11 is a schematic diagram of the circuit structure of another embodiment of the comparison result output device provided in this application;

[0022] Figure 12 is a schematic diagram of the circuit structure of another embodiment of the comparison result output device provided in this application;

[0023] Figure 13 is a schematic diagram of the storage structure provided in this application for storing data according to a one-bit scan signal;

[0024] Figure 14 is a schematic diagram of the storage structure provided in this application receiving a one-bit scan signal;

[0025] Figure 15 is a timing diagram of the storage structure provided in this application for storing data according to a one-bit scan signal;

[0026] Figure 16 is a schematic diagram of the storage structure provided in this application receiving multi-bit scan signals;

[0027] Figure 17 is a schematic diagram of the storage structure provided in this application for storing data according to a multi-bit scan signal;

[0028] Figure 18 is a structural schematic diagram of another embodiment of the display panel provided in this application;

[0029] Figure 19 is a control timing diagram of a display panel provided in this application;

[0030] Figure 20 is another control timing diagram of the display panel provided in this application;

[0031] Figure 21 is a schematic diagram of the first type of row control timing of the display panel provided in this application;

[0032] Figure 22 is a schematic diagram of the second type of row control timing of the display panel provided in this application;

[0033] Figure 23 is a schematic diagram of the third type of row control timing for the display panel provided in this application. Detailed Implementation

[0034] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0035] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0036] Figure 1 is a schematic diagram of an embodiment of the display panel provided in this application. As shown in Figure 1, the display panel can be applied to electronic devices with relevant display requirements, such as mobile phones, tablets, desktop computers, or televisions. The display panel may include multiple light-emitting devices 11 arranged in rows and columns, and multiple pixel circuits 12 also arranged in rows and columns. The pixel circuits 12 may also be referred to as driving circuits. The pixel circuits 12 can be used to provide driving current to at least one light-emitting device 11 connected to them, causing the light-emitting device 11 to emit light according to the received driving current.

[0037] In the example of Figure 1, taking a display panel comprising nine light-emitting devices 11 arranged in 3 rows and 3 columns as an example, these three rows and three columns of light-emitting devices can be a subset of the light-emitting devices in the display panel. It is understood that the other light-emitting devices in the display panel adopt the same arrangement. Simultaneously, the display panel is provided with nine pixel circuits 12, also arranged in 3 rows and 3 columns. Each pixel circuit 12 is used to provide driving current to one light-emitting device 11 connected to it. Furthermore, in other possible embodiments, the display panel may also have only three pixel circuits 12 arranged in 3 rows, each pixel circuit 12 providing driving current to one column of three light-emitting devices 11 connected to it simultaneously; or, the display panel may also have only three pixel circuits 12 arranged in 3 columns, each pixel circuit 12 providing driving current to one row of three light-emitting devices 11 connected to it simultaneously; or, the display panel may also have only one pixel circuit 12, which can be used to simultaneously provide driving current to the nine light-emitting devices 11 in the three rows and three columns connected to it. The matrix arrangement shown in Figure 1 helps to precisely control each light-emitting device, thereby enabling the display panel to display high-resolution images.

[0038] In one embodiment, the display panel can display images through pixels, and each pixel can include at least one light-emitting device 11 to achieve different color display effects. The light-emitting device 11 can be a light-emitting diode (LED), a micro light-emitting diode (Micro LED), an organic light-emitting diode (OLED), etc. Taking the pixel display color based on the Red-Green-Blue (RGB) color model as an example, each pixel includes three light-emitting devices 11 for red, blue, and green, and the arrangement of the three light-emitting devices 11 in the pixel can be arranged in a preset order. In this arrangement, by adjusting the brightness of each light-emitting device 11, each pixel can display the corresponding color. For example, when the red and green sub-pixels are lit at the same brightness, the human eye sees yellow. This arrangement is widely used in common display technologies such as liquid crystal displays (LCDs) and organic light-emitting diode displays (OLEDs). In addition, the colors displayed by pixels can also be based on other color models, such as the Red-Green-Blue-White (RGBW) color model. In this case, the arrangement of subpixels in the pixel is the same as that of the color model.

[0039] More specifically, the display panel also includes a control circuit, which can be used to control at least one pixel circuit 12 in the display panel so that at least one pixel circuit 12 can provide driving current to its respective connected light-emitting device 11.

[0040] Referring to the display panel shown in Figure 1, when the display panel displays one frame of image, the control circuit sends a scan signal WL_1 to the pixel circuit 12 of the first row, and sequentially sends data signals BL_1<0:Q-1>, BL_2<0:Q-1>, and BL_3<0:Q-1> to the three pixel circuits 12 of the first row. The scan signal WL_1 enables the pixel circuits 12 of the first row, ensuring that each pixel circuit receives the data signal BL at an appropriate time, thus avoiding interference and confusion between the data signals BL. Subsequently, the control circuit also sends a scan signal WL_2 to the pixel circuit 12 of the second row, and sends data signals BL_1<0:Q-1>, BL_2<0:Q-1> and BL_3<0:Q-1> to the three pixel circuits 12 of the second row in sequence, and sends a scan signal WL_3 to the pixel circuit 12 of the third row, and sends data signals BL_1<0:Q-1>, BL_2<0:Q-1> and BL_3<0:Q-1> to the three pixel circuits 12 of the third row in sequence.

[0041] Specifically, the data signal BL can be used to characterize the brightness information of the light-emitting device 11 driven by the pixel circuit 12. The data signal can include multiple bits. For example, when the number of bits of the data signal BL is 8, its form can be represented as 0000 0001, 1000 1001, etc. Then each pixel circuit 12 can generate a corresponding driving current according to the received data signal and send it to the light-emitting device 11 connected to it, thereby driving the light-emitting device 11 to emit light according to the received driving current.

[0042] Based on the above display panel, when the required luminous brightness of the light-emitting device 11 is different, the control circuit can control the pixel circuit 12 to adjust the current value and duration of the driving current provided to the light-emitting device 11, so that the light-emitting device 11 presents different luminous brightness according to different driving currents. For example, FIG2 is a schematic diagram of the structure of an embodiment of the display panel provided in this application. The display panel shown in FIG2 can be applied to the scenario shown in FIG1. ​​The display panel shown in FIG2 specifically includes: a control circuit 10, at least one pixel circuit 12, and multiple light-emitting devices 11.

[0043] Multiple light-emitting devices 11 can be arranged in rows and columns as shown in Figure 1. In a specific implementation, the light-emitting device provided in this application embodiment can be a micro LED.

[0044] At least one pixel circuit 12 can be arranged in rows and columns as shown in FIG1, and each pixel circuit 12 can be used to provide a driving current I to at least one light-emitting device 11, thereby driving at least one light-emitting device 11 to emit light according to the received driving current I.

[0045] The control circuit 10 can be used to control at least one pixel circuit 12. Specifically, the control circuit 10 controls the current value of the driving current I provided by each pixel circuit 12 to at least one light-emitting device 11 connected to it, as well as the duration of providing the driving current I, thereby adjusting the light emission brightness of the at least one light-emitting device 11 connected to the pixel circuit 12 by adjusting the current value and duration of the driving current I.

[0046] Therefore, in the display panel provided in this embodiment, the control circuit 10 can not only control the current value of the driving current I provided by the pixel circuit 12 to at least one light-emitting device 11, but also control the duration of the driving current I provided by the pixel circuit 12 to at least one light-emitting device 11. This allows the light-emitting device 11 to exhibit different brightness levels not only based on the different current values ​​of the received driving current I, but also based on the different durations of the received driving current I. For the control circuit 10, the control of the pixel circuit 12 can be achieved by combining the parameters of the current value and duration of the driving current I. This allows the pixel circuit 12 to provide at least one light-emitting device 11 with more driving currents I of different current values ​​and durations, thereby enriching the different brightness levels that the light-emitting device 11 can exhibit, improving the accuracy of adjusting the brightness of the light-emitting device 11, and enabling each light-emitting device of the display panel to achieve more brightness variations. Consequently, the display panel provided in this embodiment can be applied to scenarios with high brightness requirements, which is beneficial to the use and promotion of the display panel and the electronic device in which it is located.

[0047] Specifically, the pixel circuit 12 shown in Figure 2 includes: an analog driving module 121, a digital PWM (Pulse Width Modulation) module 122, and a driving current output module 123.

[0048] The analog drive module 121 is connected to the drive current output module 123 and the control circuit 10. The control circuit 10 can be used to send data signals to the analog drive module 121, so that the analog drive module 121 generates drive current I according to the data signals and sends it to the drive current output module 123.

[0049] The digital PWM module 122 is connected to the drive current output module 123 and the control circuit 10. The control circuit 10 can send data signals and counting signals to the digital PWM module 122, so that the digital PWM module 122 generates a single-pulse light-emitting signal EM with a one-bit structure to indicate the target duration based on the data signals and calculation signals, and sends it to the drive current output module 123. In this embodiment, the digital PWM module 122 specifically generates the single-pulse light-emitting signal EM with a one-bit structure to indicate the target duration by comparing the received multi-bit data signal with the cyclic counting signal bit by bit.

[0050] The drive current output module 123 is connected to at least one light-emitting device 11 and is used to receive the drive current I sent by the analog drive module 121 and the single-pulse light-emitting signal EM of a one-bit structure sent by the digital PWM module 122, and to provide the drive current I to at least one light-emitting device 11 within the target duration of the single-pulse light-emitting signal EM according to the single-pulse light-emitting signal EM.

[0051] In one embodiment, as shown in FIG2, the drive current output module 123 is a switching transistor. The first end of the switching transistor is connected to the analog drive module 121, the second end is connected to at least one light-emitting device 11, and the control end is connected to the digital PWM module 122. The switching transistor is turned on during the target duration of the single-pulse light-emitting signal EM received by the control end, so that the drive current I provided by the analog drive module 121 is sent to at least one light-emitting device 11 through the drive current output module 123.

[0052] As shown in Figure 2, the pixel circuit 12 integrates analog driving processing and digital modulation processing. That is, the pixel circuit 12 can adjust the current value of the driving current I through analog adjustment and adjust the duration of the driving current I through digital adjustment. This achieves more flexible adjustment of the driving current I and reduces the number of analog devices required when the pixel circuit 12 adjusts the driving current I through pure analog means, thereby reducing the physical space occupied by the pixel circuit 12.

[0053] Furthermore, addressing the issue of the complex adjustment method for the duration of the drive current by the digital PWM module 122 of the pixel circuit 12 in the prior art, the digital PWM module 122 provided in this application can generate a single-pulse light emission signal with a one-bit structure to indicate the duration of the target through a relatively simple comparison logic between a multi-bit data signal and a cyclic counting signal, thereby controlling the target duration of the drive current I. This significantly reduces the complexity of the digital PWM module 122 of the pixel circuit 12 in adjusting the target duration of the drive current I, thereby reducing the circuit complexity and computational complexity of the PWM module 122, its pixel circuit 12, and the overall display panel. Especially when the display panel is equipped with micro-LED light-emitting devices, and the space reserved for the pixel circuit 12 of each light-emitting device is small, the PWM module 122 and pixel circuit 12 provided in this application can be set up and accommodated, thereby realizing the adjustment of the drive current I. This further enriches the application scenarios of the pixel circuit 12, display panel, and electronic device provided in this application, and is more conducive to the use and promotion of the embodiments of this application.

[0054] More specifically, Figure 3 is a schematic diagram of an embodiment of the digital PWM module provided in this application. As shown in Figure 3, the PWM module 122 can be applied to the pixel circuit 12 shown in Figure 1 or Figure 2. Specifically, the PWM module 122 shown in Figure 3 includes: a data storage unit 1221, a comparison unit 1222, and a light emission signal output unit 1223.

[0055] The data storage unit 1221 is used to receive and store multi-bit data signals, selectively load data signals through scanning signals, and send the stored multi-bit data signals to the comparison unit 1222.

[0056] The comparison unit 1222 is used to receive and store multi-bit data signals sent by the data storage unit 1222, and to receive cyclic counting signals. It compares the data signals with multiple counting signals, generating a comparison result signal by performing a multi-bit successive comparison operation on the data signals and the counting signals in each comparison process, and then sending the comparison result signal to the light-emitting signal output unit 1223. It can be understood that after comparing the data signals with multiple counting signals, the comparison unit 1222 generates multiple comparison result signals, which are then sent to the light-emitting signal output unit 1223 respectively.

[0057] The light emission signal output unit 122 is used to receive the data signal sent by the comparison unit 1222 and the multiple comparison result signals generated by the multiple counting signals in a cycle, and to generate a single pulse light emission signal EM of target duration based on the multiple comparison result signals.

[0058] The working principle of the digital PWM module provided in this application will be described below with reference to the circuit in Figure 4. Figure 4 is a schematic diagram of the circuit structure of an embodiment of the digital PWM module provided in this application. Figure 4 shows a specific circuit implementation of the digital PWM module provided in Figure 3.

[0059] In the example shown in Figure 4, the data storage unit receives the data signal BL. <q-1:0>This is a Q-bit data signal, where Q is a constant greater than or equal to 1. Data storage unit 1222 can be used to receive data signal BL based on scan signal WL. <q-1:0>The pixel circuit 12 provides a storage function to store the received data signal BL. <q-1:0>Each bit in the data, and the data signal BL selectively loaded via the scan signal WL. <q-1:0>.

[0060] In one embodiment, the data storage unit 12210 is provided with Q storage structures, the number of which is related to the data signal BL. <q-1:0>The number of bits is the same, and each storage structure is used to store the data signal BL according to a single scan signal WL.<Q-1:0> The data in the corresponding bit of the signal. More specifically, the Q storage structures in the data storage unit 12210 can receive and store the data in the corresponding bit of the data signal according to at least one scan signal WL.

[0061] Subsequently, the comparison unit 1222 receives the data signal BL sent by the data storage unit 1221.<Q-1:0> It also receives a cyclic counting signal Counter<0:Q-1> sent by the control circuit 10. For example, when the multi-bit data signal BL...<Q-1:0> When the bit length is 8 bits, the bit length of the counting signal Counter<0:Q-1> is also 8 bits, and it is an 8-bit cyclic signal between 0000 0000 and 1111 1111. The cyclic counting signal Counter<0:Q-1> cycles from 0000 0000 to 1111 1111 once, which is recorded as one cycle. The comparison unit 1222 can receive the cyclic counting signal Counter<0:Q-1> within one cycle, and at the end of one cycle, it can receive the cyclic counting signal Counter<0:Q-1> within the next cycle.

[0062] Therefore, the comparison unit 1222 can compare the 8-bit data signal BL sent by the data storage unit 1221.<Q-1:0> Each of the count signals Counter<0:Q-1> received within one cycle is compared, and the data signal BL is specifically compared.<Q-1:0> A comparison result signal Cmp is generated by comparing the counter signal Counter<0:Q-1> with the counter signal Counter<0:Q-1> through a multi-bit successive comparison operation.

[0063] For example, when the data signal is 0000 0100, during one cycle of the cyclic counting signal Counter<0:Q-1> increasing from 0000 0000 to 1111 1111, or decreasing from 1111 1111 to 0000 0000, the comparison unit 1222, when the counting signal Counter<0:Q-1> is 0000 0100, will compare the data signal BL.<Q-1:0> By performing a multi-bit successive comparison operation with the counting signal Counter<0:Q-1>, the counting signal Counter<0:Q-1> and the data signal BL can be obtained.<Q-1:0> The comparison results are identical for each bit in the data signal BL.<Q-1:0> Other comparison results during the loop of the counting signal Counter<0:Q-1> are all between the counting signal Counter<0:Q-1> and the data signal BL.<Q-1:0> The comparison results are not identical for each individual.

[0064] Specifically, the comparison unit 1222 will compare the data signal BL<Q-1:0> It is compared one by one with multiple counting signals Counter<0:Q-1>, and in each multi-bit successive comparison operation, it is based on the data signal BL<Q-1:0> The comparison result is used to determine whether each bit in the counting signal Counter<0:Q-1> is the same, thereby forming a comparison result signal Cmp that is sent to the light emission signal output unit 1223. The comparison result signal Cmp can be used to indicate the data signal BL.<Q-1:0> Check if each bit of the counting signal Counter<0:Q-1> is the same.

[0065] Finally, the light emission signal output unit 1223 receives the comparison result signal Cmp sent by the comparison unit 1222 for each comparison. The light emission signal output unit 1223 also receives the first flip indicator signal Set, the second flip indicator signal Reset, and the indicator signal SYNC_CLOCK corresponding to the bit count signal Counter<0:Q-1>. It then performs a flip processing on the previously generated light emission signal EM to output the current light emission signal. Finally, based on the multiple comparison signal results formed by the multiple comparisons between the data signal and the cyclic count signal, a single pulse light emission signal EM is finally formed.

[0066] In one embodiment, the light emission signal output unit 1223 includes a calculation unit 12231 and a signal storage unit 12232. The calculation unit 12231 receives the previously output light emission signal EM from the light emission signal output unit 1223, and sends a temporary light emission signal Em_tmp to the signal storage unit 12232 based on the previously output light emission signal EM and the comparison result signal Cmp. The signal storage unit 12232 performs a flipping process on the previously generated light emission signal EM based on the temporary light emission signal Em_tmp, a first flipping indicator signal Set, and a second flipping indicator signal Reset, thereby outputting the current light emission signal EM. The current light emission signal EM may be the same as or different from the previous light emission signal EM.

[0067] The following description, with reference to Figures 5 and 6, illustrates the light emission signal EM output by the digital PWM module 122 shown in Figure 4. Figure 5 is a schematic diagram of one signal timing for the digital PWM module provided in this application, and Figure 6 is a schematic diagram of another signal timing for the digital PWM module provided in this application.

[0068] As shown in Figure 5, the multi-bit structure data signal BL<Q-1:0> The corresponding loop counter signals Counter<0:Q-1> are arranged sequentially and incremented, and are numbered 0, 1, 2, ..., 2 in sequence. Q -1. Data signal BL as shown in Figure 6<Q-1:0> The corresponding counting signals Counter<0:Q-1> are arranged sequentially and decremented, and are recorded as 2 in sequence. Q -1, ..., 3, 2, 1, 0. Each counting signal Counter<0:Q-1> contains Gamma information, therefore the length of each counting signal Counter<0:Q-1> is not exactly the same in time.

[0069] The indicator signal SYNC_CLOCK corresponds to the counting signal Counter<0:Q-1>. It is used by the signal storage unit 12232 to store the received temporary light-emitting signal EM_tmp within one cycle of the counting signal Counter<0:Q-1> and toggles the level of the output light-emitting signal EM. In other words, the indicator signal SYNC_CLOCK here acts as a switch signal, allowing the signal storage unit 12232 to toggle the output light-emitting signal EM based on the received temporary light-emitting signal EM_tmp after receiving the indicator signal SYNC_CLOCK.

[0070] The first flip indicator signal Set can be used to indicate that the count value of the counter signal Counter<0:Q-1> cycles from 0 to 2 once in one period. Q During the increment process of -1, the signal storage unit 12232 performs a toggle process on the previously generated light-emitting signal EM according to the first toggle indicator signal Set and the temporary light-emitting signal EM_tmp, specifically, it can toggle from low level to high level. The second toggle indicator signal Reset can be used to increment the count value of the counting signal Counter<0:Q-1> from 2. Q During the decrementing process from -1 to 0, the signal storage unit 12232 performs a toggle process on the previously generated light-emitting signal EM according to the second toggle indication signal and the temporary light-emitting signal EM_tmp. Specifically, this can be a toggle from high level to low level. Alternatively, in other possible implementations, the specific toggle processes of low level to high level and high level to low level can be set according to different circuits in different application scenarios.

[0071] Specifically, referring to Figure 5, after receiving the first flip indicator signal Set at time t1, if the previous light-emitting signal EM was low, the signal storage unit 12232 flips the level of the previous light-emitting signal EM, causing the single-pulse light-emitting signal EM output this time to switch to a high level after time t1. At times t11, t12, and t13, the signal storage unit 12232 outputs the current light-emitting signal EM according to the received indicator signal SYNC_CLOCK and the temporary light-emitting signal Em_tmp, respectively. However, since the initial light-emitting signal Em_tmp is also high at this time, the level of the current output light-emitting signal EM does not flip compared to the level of the previous output light-emitting signal EM. Subsequently, during the incrementing process of the count value of the counting signal Counter<0:Q-1>, the fifth counting signal Counter<0:4> and the data signal BL<Q-1:0> If every bit in the count signal is the same, then the temporary light-emitting signal Em_tmp sent by the calculation unit 12231 to the signal storage unit 12232 changes at time T4 corresponding to the counting signal Counter<0:4>. Therefore, at times t2 and t21 after time T4, when the signal storage unit 12232 outputs the current light-emitting signal EM according to the received indication signal SYNC_CLOCK, since the temporary light-emitting signal Em_tmp is low at this time, the level of the light-emitting signal EM output at time t2 flips to a low level and remains low. Finally, the duration of the single-pulse light-emitting signal EM output by the signal storage unit 12232 is time t1 - time t2.

[0072] Referring to Figure 6, in the counting signal Counter<Q-1:0> During the decrementing process of the count value, the fifth-to-last cyclic count signal Counter<4:0> and the data signal BL<Q-1:0> If each bit is identical, the temporary light-emitting signal Em_tmp sent by the calculation unit 12231 to the signal storage unit 12232 changes at time T4, corresponding to the counting signal looping to Counter<4:0>. Therefore, at times t3, t31, and t32 after time T4, the signal storage unit 12232, based on the received indication signal SYNC_CLOCK, flips the level of the light-emitting signal EM to a high level and maintains it at a high level. Subsequently, after receiving the second flip indication signal Reset at time t4, the signal storage unit 12232 flips the level of the light-emitting signal EM, causing the output light-emitting signal to switch to a low level after time t1. Finally, the duration of the single-pulse light-emitting signal EM output by the signal storage unit 12232 is from time t3 to time t4.

[0073] As can be seen from the above embodiments, in order to control the pixel circuit 12 to output a single-pulse light emission signal EM, the control circuit 10 sends a data signal BL to the digital PWM module 122 in the pixel circuit 12.<Q-1:0> The counting signal Counter<0:Q-1>, the first flip indicator signal Set, and the second flip indicator signal Reset cause the digital PWM module 122 to flip the previously generated light-emitting signal EM according to these signals, thereby outputting a single-pulse light-emitting signal EM with a target duration of one bit structure.

[0074] In one embodiment, the control circuit 10 includes a Q-bit counting module. The control circuit 10 can input a clock signal, Emission Clock, into the counting module and receive counting signals Counter<0:Q-1> output by the counting module. The counting module can add corresponding Gamma information to each counting signal Counter<0:Q-1>.

[0075] In one embodiment, the counting module can be located inside the pixel circuit 12 or outside the pixel circuit 12. When the resources inside the pixel circuit 12 are limited by pixel pitch requirements, the counting module is located outside the pixel circuit 12 to meet the requirements. However, when high pixel array capability and high trace width requirements are needed, the counting module can be located inside the pixel circuit 12 to alleviate trace pressure.

[0076] Figure 7 is a circuit structure diagram of another embodiment of the digital PWM module provided in this application. As shown in Figure 7, another specific circuit implementation is provided based on the digital PWM module provided in Figure 4.

[0077] The comparison unit 1222 shown in Figure 7 includes multiple comparators and a comparison result output device 12222. The number of comparators depends on the data signal BL.<Q-1:0> In the example shown in Figure 7, Q comparators are used to compare the data signal BL.<Q-1:0> Each bit in the comparison signal is compared with the corresponding bit in a counting signal Counter<0:Q-1>. Each comparator sends the bit comparison result E to the comparison result output device 12222. <0> E <1> ... E <q-1>Subsequently, the comparison result output device 12222 outputs a total of Q bit comparison results E provided by the Q comparators. <0> E <1> ... E <q-1>The comparison result signal Cmp is generated and output to the light emission signal output unit 1223.

[0078] Figure 8 is a schematic diagram of the circuit structure of an embodiment of the storage structure provided in this application. Figure 8 shows a possible circuit structure of the storage structure 12210 of the data storage unit 122 in the digital PWM module 122 shown in Figure 4 or Figure 7.

[0079] The storage structure 12210 provided in this application includes a first memory and a first write switch. The first memory is used to receive and store data signal BL.<Q-1:0> The data corresponding to the bit in the middle, the first write switch is used to receive the scan signal WL, and according to the scan signal WL, the received data signal BL is...<Q-1:0> The corresponding bit data is written into the first memory. Clearly, the multi-bit data signal BL...<Q-1:0> If there are Q bits, then the storage structure 12210 in the data storage unit 122 has Q elements, that is, the number of storage structures is related to the number of data signals BL.<Q-1:0> The number of digits corresponds to the number of digits.

[0080] Specifically, as shown in Figure 8, the first write switch in the storage structure 12210 includes a first switch transistor K1 and a second switch transistor K2, and the first memory includes a first inverter R1 and a second inverter R2. The first terminal of the first switch transistor K1 is used to receive the multi-bit data signal BL.<Q-1:0> Inverted signal BLB<Q-1:0> The second terminal of the first switch K1 is connected to the positive terminal of the first inverter R1 and the negative terminal of the second inverter R2. The first terminal of the second switch K2 is used to receive the multi-bit data signal BL.<Q-1:0> Correspondingly, the second terminal of the second switch K2 is connected to the negative terminal of the first inverter R1 and the positive terminal of the second inverter R2. The control terminals of the first switch K1 and the second switch K2 are used to receive the scan signal WL, and the second terminal of the second switch K2 is also used to output the data signal BL stored in the first memory.<Q-1:0> One of them.

[0081] When the storage structure 12210 shown in Figure 8 receives the scan signal WL, the first switch K1 and the second switch K2 are turned on, and the data signal BL is activated.<Q-1:0> The corresponding bit, through the second switch K2, causes the voltage level of point Q at the negative terminal of the first inverter R1 and the positive terminal of the second inverter R2 to be related to the data signal BL.<Q-1:0> The corresponding bit level values ​​are the same, and at the same time, the data signal BL<Q-1:0> Inverted signal BLB<Q-1:0> The corresponding bit, through the first switch K1, causes the voltage level at point Q_b, located at the positive terminal of the first inverter R1 and the negative terminal of the second inverter R2, to be synchronized with the inverted signal BLB.<Q-1:0> When the corresponding bit level values ​​are the same, the first memory can store the data and output the data signal BL through point Q.<Q-1:0> The corresponding bit level value enables control of the data signal BL.<Q-1:0> The corresponding bit of data is stored.

[0082] Figure 9 is a schematic diagram of the circuit structure of an embodiment of the signal storage unit provided in this application. Figure 9 shows a possible circuit structure of the signal storage structure 12232 of the signal storage unit shown in Figure 4 or Figure 7.

[0083] The signal storage structure 12232 provided in this application includes a second memory, a second write switch, a first toggle switch, and a second toggle switch. The second memory is used to receive and store a temporary light-emitting signal Em_tmp. The second write switch is used to receive an indication signal SYNC_CLOCK and write the temporary light-emitting signal Em_tmp into the second memory according to the indication signal SYNC_CLOCK. The first toggle switch is used to receive a first toggle indication signal Set and write the first toggle indication signal Set into the second memory. The second toggle switch is used to receive a second toggle indication signal Reset and write the second toggle indication signal Reset into the second memory.

[0084] Specifically, the second write switch in the signal storage structure 12232 shown in Figure 9 includes a third switch K3 and a fourth switch K4, the first toggle switch includes a fifth switch K5 and an eighth switch K8, the second toggle switch includes a sixth switch K6 and a seventh switch K7, and the second memory includes a third inverter R3 and a fourth inverter R4. Specifically, the first terminal of the third switch K3 is used to receive the temporary light emission signal Em_tmp. The second terminal of the third switch K3 is connected to the first terminal of the fifth switch K5, the first terminal of the seventh switch K7, the negative terminal of the third inverter R3, and the positive terminal of the fourth inverter R4. The first terminal of the fourth switch K4 is used to receive the inverted signal Em_tmp_b of the temporary light emission signal Em_tmp. The second terminal of the fourth switch K4 is connected to the first terminal of the sixth switch K6, the first terminal of the eighth switch K8, the positive terminal of the third inverter R3, and the negative terminal of the fourth inverter R4. The control terminals of the third switch K3 and the fourth switch K4 are used to receive the indication signal SYNC_CLOCK. The control terminal of the fifth switch K5 is used to receive the first toggle indication signal Set. The control terminal of the seventh switch K7 is used to receive the second toggle indication signal Reset. The control terminal of the sixth switch K6 is used to receive the inverted signal Reset_b of the second toggle indication signal Reset. The control terminal of the eighth switch K8 is used to receive the inverted signal Set_b of the first toggle indication signal Set. The second terminal of the sixth switch K6 is connected to the power supply, the second terminal of the fifth switch K5 is connected to the power supply, the second terminal of the eighth switch K8 is grounded, and the second terminal of the seventh switch K7 is grounded.

[0085] When the signal storage structure 12232 shown in Figure 9 receives the indication signal SYNC_CLOCK, the third switch K3 and the fourth switch K4 are turned on. The temporary light-emitting signal Em_tmp passes through the third switch K3, making the level value of point EM at the negative terminal of the third inverter R3 and the positive terminal of the fourth inverter R4 the same as the level value of the temporary light-emitting signal Em_tmp. At the same time, the inverted signal Em_tmp_b of the temporary light-emitting signal Em_tmp passes through the fourth switch K4, making the level value of point EM_b at the positive terminal of the third inverter R3 and the negative terminal of the fourth inverter R4 the same as the level value of the inverted signal Em_tmp_b. At this time, the second memory can save and output the level value of the temporary light-emitting signal Em_tmp through point Q, thereby realizing the storage of the temporary light-emitting signal Em_tmp.

[0086] When the signal storage structure 12232 shown in Figure 9 receives the first flip indicator signal Set, the fifth switch K5 and the eighth switch K8 are turned on. The first flip indicator signal Set passes through the fifth switch K5, making the voltage level of point EM the same as the power supply voltage level. The inverted signal Set_b of the first flip indicator signal Set passes through the eighth switch K8, making point EM_b grounded.

[0087] When the signal storage structure 12232 shown in Figure 9 receives the second toggle indicator signal Reset, the sixth switch K6 and the seventh switch K7 are turned on. The second toggle indicator signal Reset is grounded through the seventh switch K7. The inverted signal Reset_b of the second toggle indicator signal Reset is made to make the voltage level of the EM_b point the same as the voltage level of the power supply through the sixth switch K6.

[0088] This application also provides several possible implementations of the comparison result output device 12222 shown in Figure 7. Specifically, the comparison result output device 12222 performs logical operations on multiple bit comparison results and / or the feedback results of multiple bit comparison results, and then forms a comparison result signal based on the logical operation results.

[0089] In the first embodiment, the comparison result output device 12222 includes a multi-input AND gate. The multiple input terminals of the multi-input AND gate are respectively used to receive the bit comparison results sent by multiple comparators. When all the multiple bit comparison results are 1, the gate outputs a comparison result signal Cmp=1 corresponding to the same bit comparison result. When at least one of the multiple bit comparison results is not 1, that is, at least one of the multiple bit comparison results is 0, the gate outputs a comparison result signal Cmp=0 corresponding to the different bit comparison results.

[0090] In the second embodiment, Figure 10 is a circuit structure diagram of an embodiment of the comparison result output device provided in this application. The comparison result output device 12222 includes multiple positive switches K1-0, K1-1…K1-Q-1, and multiple reverse switches K2-0…K2-Q-2, K2-Q-1. The control terminals of the multiple positive switches are respectively used to receive the comparison results sent by the multiple comparators. Simultaneously, the control terminals of the multiple reverse switches are also respectively used to receive the comparison results sent by the multiple comparators. The multiple reverse switches are connected in series and then cascaded with the multiple positive switches. The cascade point is used to output the comparison result signal. When multiple bit comparison results are all 1, the output comparison result signal Cmp = 1; when at least one of the multiple bit comparison results is not 1, the output comparison result signal Cmp = 0.

[0091] In a third embodiment, Figure 11 is a circuit diagram of another embodiment of the comparison result output device provided in this application. The comparison result output device 12222 includes multiple positive switches K1-0, K1-1…K1-Q-1, and a first inverting switch K2-01. The control terminals of the multiple positive switches are respectively used to receive the bit comparison results sent by the multiple comparators. The control terminal of the first inverting switch K2-01 is used to receive a first reset signal Precharge1. The first inverting switch K2-01 is cascaded with the multiple positive switches, and the cascade point is used to output the comparison result signal Cmp. The control circuit can be used to send the first reset signal Precharge1 to the comparison result output device 12222 to set the output comparison result signal Cmp to a low level. When all multiple bit comparison results are 1, the output comparison result signal Cmp = 1; otherwise, when not all multiple bit comparison results are 1, the output comparison result signal Cmp = 0. Thus, the first reset signal Precharge1 reduces the computational load required to obtain the comparison result signal Cmp from the bit comparison results, improving the computational efficiency of the comparison output device 12222.

[0092] In the fourth embodiment, Figure 12 is a circuit structure diagram of another embodiment of the comparison result output device provided in this application. The comparison result output device 12222 includes multiple inverting switches K2-0...K2-Q-2, K2-Q-1, and a first positive switch K1-01. The control terminals of the multiple inverting switches are respectively used to receive the bit comparison results sent by the multiple comparators. The control terminal of the first positive switch K1-01 is used to receive the second reset signal Precharge2. The multiple inverting switches are connected in series and cascaded with the first positive switch K1-01. The cascade point is used to output the comparison result signal Cmp. The control circuit can be used to send a second reset signal Precharge2 to the comparison result output unit 12222 to set the output comparison result signal Cmp to a high level. When multiple bit comparison results are all 1, the output comparison result signal Cmp = 1; otherwise, when multiple bit comparison results are not all 1, the output comparison result signal Cmp = 0. Thus, the second reset signal Precharge2 reduces the amount of calculation required to obtain the comparison result signal Cmp from the bit comparison results, thereby improving the calculation efficiency of the comparison output unit 12222.

[0093] Figure 13 is a schematic diagram of the storage structure provided in this application storing data according to a one-bit scan signal. As shown in Figure 13, the control circuit sends a data signal BL to the data storage unit 1221 at time T0.<Q-1:0> Denoteed as Data0, for each storage structure in data storage unit 1221, at time T0' when the scan signal WL is received, one bit of the data signal Data0 is received and stored. The data signals stored by multiple storage structures are denoted as DATA_M.<Q-1:0> .

[0094] Figure 14 is a schematic diagram of the storage structure provided in this application receiving a one-bit scan signal. As shown in Figure 14, each storage structure in the data storage unit 1221 receives the data signal BL according to the received scan signal WL.<Q-1:0> One of them is stored.

[0095] Figure 15 is a timing diagram of the storage structure provided in this application storing data according to a one-bit scan signal. As shown in Figure 15, each storage structure receives the corresponding data signal BL at the moment the scan signal WL is received.<Q-1:0> And store it.

[0096] Figure 16 is a schematic diagram of the storage structure provided in this application receiving multi-bit scan signals. As shown in Figure 16, the storage structure in the data storage unit 1221 can receive different scan signals WL.<Q-1:0> And according to the corresponding scan signal WL<Q-1:0> Receive data signal BL<Q-1:0> One of them is stored.

[0097] Figure 17 is a schematic diagram of the storage structure provided in this application for storing data based on a multi-bit scan signal. As shown in Figure 17, a 2-bit scan signal WL is used. <0> and WL <1> For example, at time T0, the scanning signal WL <0> and WL <1> Simultaneously given, the data signal BL<Q-1:0> Each bit in WL is written and stored. At time T1-1, WL <1> The signal is given, thereby controlling BL<Q-1:0> Data is written and stored in bits 1 to Q-1 of the BL.<Q-1:0> The 0th bit in WL is not written or stored. At time T1-2, WL <0> The signal is given, thereby controlling the data signal BL.<Q-1:0> The 0th bit in the array is used for writing and storing data.

[0098] Figure 18 is a schematic diagram of another embodiment of the display panel provided in this application. Figure 18 shows the specific implementation of the control circuit 10 when the display panel shown in Figure 1 is controlled. As shown in Figure 18, the timing controller (TCON) 101 in the control circuit 10 controls the row scan driver 102 to send the scan signal WL and the control signal ROW_CTRO_SIGNAL to the pixel circuit 12 of each row. The TCON 101 controls the data column buffer driver 104 to send the data signal BL to the pixel circuit 12 of each column.<Q-1:0> .

[0099] In one embodiment, after the control circuit 10 sends a scan signal WL to the digital PWM module 122 of the pixel circuit 12, it sends a corresponding data signal BL to the digital PWM module 122.<Q-1:0> This enables the digital PWM module 122 to receive the data signal BL according to the scan signal WL.<Q-1:0> The specific implementation method can be seen in the examples shown in Figures 13-17.

[0100] For example, Figure 19 is a control timing diagram of a display panel provided in this application. Figure 19 shows the scan signal WL and data signal BL sent by the control circuit 10 to the digital PWM modules corresponding to different pixel circuits 12 in the display panel as shown in Figure 18.<Q-1:0> The timing diagram shows that the control circuit 10 sends data signals BL_1<0:Q-1>, BL_2<0:q->.......BL_N<0:q-1> to the first row pixel circuit 12, and sends a scan signal WL_0 to the first row pixel circuit 12. Subsequently, it sends data signals BL_1<0:Q-1>, BL_2<0:Q-1>.......BL_N<0:q-1> to the second row pixel circuit 12, and sends a scan signal WL_1 to the second row pixel circuit 12, and so on. Finally, it sends Q-bit data signals BL_1<0:Q-1>, BL_2<0:Q-1>......BL_N<0:Q-1> to the Mth row pixel circuit 12, and sends a scan signal WL_M to the Mth row pixel circuit 12, thus completing the control of one frame of image and realizing the writing of the data signal of one frame of image into the corresponding pixel circuit 12.

[0101] As shown in Figure 16, for the Z-th frame image, the control circuit 10 sends a scan signal WL and a data signal BL<0:Q-1> to all pixel circuits 12 in the display panel, writing the data signal of one frame image into the corresponding pixel circuit 12. Subsequently, for each frame image, the control circuit 10 can send signals in the manner shown in Figure 16, writing the data signal of one frame image into the corresponding pixel circuit 12.

[0102] Alternatively, in another embodiment, since the digital PWM module 122 in the pixel circuit 12 provided in this application embodiment includes a data storage unit 1221, which can be used to store the data signal BL<0:Q-1>, when the data signal <0:Q-1> of the current frame image is the same as the data signal BL<0:Q-1> of the previous frame image, the control circuit 10 may not repeatedly send the same data signal BL<0:Q-1> to all pixel circuits 12. When the data signal <0:Q-1> of the current frame image is different from the data signal <0:Q-1> of the previous frame image, the control circuit 10 may send the same data signal BL<0:Q-1> to one of them again. Some pixel circuits 12 send data signals BL<0:Q-1> and corresponding scan signals WL to update the data signals BL<0:Q-1>. When the data signal <0:Q-1> of the current frame image is the same as the data signal <0:Q-1> of the previous frame image, the control circuit 10 does not need to send the same data signal BL<0:Q-1> and corresponding scan signals WL to these pixel circuits 12 again. Therefore, these pixel circuits 12 do not need to update the data signal BL<0:Q-1>, thereby reducing the signal interaction between the control circuit 10 and the pixel circuits 12 and improving control efficiency.

[0103] For example, Figure 20 is another control timing diagram of the display panel provided in this application. As shown in Figure 20, in the display panel shown in Figure 18, the control circuit 10 sends the scan signal WL and the multi-bit data signal BL to the digital PWM modules corresponding to different pixel circuits 12 in the display panel.

[0104] In this case, compared to the previous frame Z, the data signals BL<0:Q-1> in the pixel circuits 12 of the first, second, fourth, and fifth rows change in the current (Z+1)th frame. Therefore, the control circuit 10 sends scan signals WL to the pixel circuits 12 of the first, second, fourth, and fifth rows at different times. The column data signals BL_1<0:Q-1>, BL_2<0:Q-1>...BL_N<0:Q-1> are then written and stored accordingly when the corresponding row scan signal is given. For pixel circuits 12 in other rows, the control circuit 10 does not send scan signals WL, and the column data signals BL_1<0:Q-1>, BL_2<0:Q-1>...BL_N<0:Q-1> in the corresponding rows are not written and stored, thus controlling the data signal writing for pixel circuits 12 in different rows.

[0105] In the example shown in Figure 20, the control circuit 10 sends the scan signal WL and the data signal BL<0:Q-1> to the pixel circuits 12 of the second row, the first row, the fourth row, and the fifth row in sequence as an example. The control circuit 10 can also control the pixel circuits 12 of different rows to write the data signal BL<0:Q-1> according to different sequences, thereby realizing a more flexible setting and adjustment of the writing order.

[0106] Based on the method shown in Figure 19 or Figure 20, the control circuit 10 in the display panel writes the data signal of a frame of image into the corresponding pixel circuit 12 by sending a scan signal WL and a data signal BL<0:Q-1> to the pixel circuit 12. Subsequently, the control circuit 10 can send control signals to the pixel circuit 12, causing each pixel circuit 12 to drive its connected light-emitting device to emit light, thereby enabling the display panel to display a frame of image.

[0107] Specifically, the control circuit can control all the light-emitting devices driven by the pixel circuits 12 in the display panel to light up simultaneously, or control all the light-emitting devices driven by the pixel circuits 12 to light up sequentially, or control some of the light-emitting devices driven by the pixel circuits 12 to light up while others do not light up.

[0108] Figure 21 is a schematic diagram of the first type of row control timing of the display panel provided in this application. As shown in Figure 21, the control circuit 10 can simultaneously send control signals to the pixel circuits 12 of each row on the display panel at the same specified time, so that the pixel circuits 12 of each row can drive all light-emitting devices to light up simultaneously based on the same specified time. For example, the control circuit 10 sends control signals ROW_CTRO_SIGNAL, counting signals Counter<0:Q-1>, and first flip indicator signals Set to the pixel circuits 12 of the first row, so that the pixel circuits of the first row generate a single-pulse light-emitting signal EM starting at time t0. Similarly, the control circuit 10 sends control signals ROW_CTRO_SIGNAL, counting signals Counter<0:Q-1>, and first flip indicator signals Set to the pixel circuits 12 of all rows at the same specified time, so that the starting time of the single-pulse light-emitting signal EM generated by the pixel circuits 12 of each row is the specified time t0, thereby realizing the joint control of the entire display panel.

[0109] Figure 22 is a schematic diagram of the second type of row control timing for the display panel provided in this application. As shown in Figure 22, the control circuit 10 can send control signals to different pixel circuits 12 at different specified times, so that the start time of the single-pulse light emission signal generated by each pixel circuit 12 is the specified time corresponding to each pixel circuit, thereby realizing the control of the light emission start time of different light-emitting devices on the display panel, making the control of the display panel more flexible and controllable. For example, at time t0, the control circuit 12 simultaneously sends the control signal ROW_CTRO_SIGNAL, the counting signal Counter<0:Q-1>, the first flip indicator signal Set, etc. to the pixel circuit 12 of the first row ROW_0 on the display panel; at time t1, it simultaneously sends the control signal ROW_CTRO_SIGNAL, the bit indication signal Counter<0:Q-1>, the first flip indicator signal Set, etc. to the pixel circuit 12 of the second row ROW_1 on the display panel, and so on. At this time, the starting time of the single-pulse light emission signal EM generated by the pixel circuit 12 in the first row is t0, the starting time of the single-pulse light emission signal EM generated by the pixel circuit 12 in the second row is t1, and so on, with the starting time of the single-pulse light emission signal EM generated by the pixel circuit 12 in the Mth row being t2. This causes the pixel circuit 12 in the first row to drive the corresponding light-emitting device to light up based on the specified time t1, the pixel circuit 12 in the second row to drive the corresponding light-emitting device to light up based on the specified time t2, and so on.

[0110] Figure 23 is a schematic diagram of the third type of row control timing for the display panel provided in this application. As shown in Figure 23, the control circuit 10 can send control signals to a portion of the pixel circuits 12 while not sending control signals to another portion of the pixel circuits. This causes a portion of the pixel circuits to drive the light-emitting devices to emit light, while the other portion of the pixel circuits 12 does not drive the light-emitting devices to emit light, thereby achieving control over the light-emitting devices at different positions on the display panel. At time t0, the control circuit 10 simultaneously sends the control signal ROW_CTRO_SIGNAL, the counting signal Counter<0:Q-1>, and the first flip indicator signal Set to the pixel circuit 12 of the first row ROW_0 on the display panel, and does not send control signals to the pixel circuits 12 of other rows. This causes the light-emitting devices corresponding to the pixel circuits 12 of the first row of the display panel to emit light, while the light-emitting devices corresponding to the pixel circuits 12 of other rows do not emit light.

[0111] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0112] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A pixel circuit, characterized in that, include: The analog drive module is used to generate drive current; The digital PWM module is used to generate a single-pulse light-emitting signal with a one-bit structure for indicating the target duration by comparing the multi-bit structured data signal with the cyclic counting signal bit by bit, and to store the single-pulse light-emitting signal to ensure the drive control of the single-pulse light-emitting signal within the target duration. A drive current output module is used to provide the drive current to at least one light-emitting device during the target duration according to the single-pulse light emission signal.

2. The pixel circuit according to claim 1, characterized in that, The digital PWM module includes: A data storage unit is used to receive and store the data signal of the multi-bit structure, and to selectively load the data signal through a scanning signal; The comparison unit is used to generate a comparison result signal through multi-bit successive comparison operations; The light emission signal output unit is used to generate the single-pulse light emission signal of the target duration based on multiple comparison result signals generated by the data signal and the counting signal of the cycle, respectively.

3. The pixel circuit according to claim 2, characterized in that, In the multi-bit successive comparison operation of the comparison unit, the comparison result signal is generated based on whether each bit of the data signal and the counting signal is the same.

4. The pixel circuit according to claim 3, characterized in that, The comparison unit includes, Multiple comparators are provided, which are used to generate a bit comparison result based on whether a bit of the data signal is the same as a bit of the corresponding bit of the counting signal, and send the bit comparison result to a comparison result output device. A comparison result outputter is used to form the comparison result signal based on the bit comparison results sent by the plurality of comparators respectively.

5. The pixel circuit according to claim 4, characterized in that, The comparison result output device is specifically used for: The multiple bit comparison results and / or the inverse results of the multiple bit comparison results are combined to perform logical operations to form the comparison result signal.

6. The pixel circuit according to claim 5, characterized in that, The comparison result output device specifically includes: A multi-input AND gate, with its input terminals used to receive the bit comparison results sent by the multiple comparators respectively, and its output terminal used to output the logic operation result to form the comparison result signal; Alternatively, multiple positive switches and multiple negative switches are used, wherein the control terminals of the multiple positive switches are respectively used to receive the bit comparison results sent by the multiple comparators, and the control terminals of the multiple negative switches are respectively used to receive the bit comparison results sent by the multiple comparators. The multiple negative switches are connected in series and then cascaded with the multiple positive switches. The cascade point is used to output the logic operation result to form the comparison result signal. Alternatively, multiple forward switches and a first reverse switch are used, wherein the control terminals of the multiple forward switches are respectively used to receive the bit comparison results sent by the multiple comparators, the control terminal of the first reverse switch is used to receive a first reset signal, the first reverse switch is cascaded with the multiple forward switches, and the cascade point is used to output the logic operation result to form the comparison result signal; Alternatively, multiple reverse switches and a first forward switch are used, wherein the control terminals of the multiple reverse switches are respectively used to receive the bit comparison results sent by the multiple comparators, and the control terminal of the first forward switch is used to receive a second reset signal. The multiple reverse switches are connected in series and then cascaded with the first forward switch. The cascade point is used to output the logic operation result to form the comparison result signal.

7. The pixel circuit according to any one of claims 2-6, characterized in that, The light emission signal output unit includes: The calculation unit is used to receive the previous light emission signal output by the light emission signal output unit, and send a temporary light emission signal to the signal storage unit according to the previous light emission signal and the comparison result signal; The signal storage unit is used to receive the first flip indicator signal and the second flip indicator signal of the counting signal, and to perform flip processing on the previously generated light-emitting signal based on the first flip indicator signal, the second flip indicator signal and the temporary light-emitting signal.

8. The pixel circuit according to claim 7, characterized in that, The signal storage unit is specifically used for: When the count value of the counting signal increases in a cycle, the previously generated light-emitting signal is flipped according to the first flip indication signal and the temporary light-emitting signal. When the count value of the counting signal decreases in a cycle, the previously generated light-emitting signal is flipped according to the second flip indication signal and the temporary light-emitting signal.

9. The pixel circuit according to claim 8, characterized in that, The signal storage unit includes: A second memory is used to receive and store the temporary light emission signal; The second write switch is used to receive an indication signal and write the temporary light-emitting signal into the second memory according to the indication signal; A first flip switch is configured to receive the first flip indication signal and write the first flip indication signal into the second memory; The second flip switch is used to receive the second flip indication signal and write the second flip indication signal into the second memory.

10. The pixel circuit according to claim 9, characterized in that, The second write switch includes a third switch and a fourth switch, the first toggle switch includes a fifth switch and an eighth switch, the second toggle switch includes a sixth switch and a seventh switch, and the second memory includes a third inverter and a fourth inverter. Wherein, the first terminal of the third switch is used to receive the temporary light emission signal; the second terminal of the third switch is connected to the first terminal of the fifth switch, the first terminal of the seventh switch, the negative terminal of the third inverter, and the positive terminal of the fourth inverter; the first terminal of the fourth switch is used to receive the inverted signal of the temporary light emission signal; the second terminal of the fourth switch is connected to the first terminal of the sixth switch, the first terminal of the eighth switch, the positive terminal of the third inverter, and the negative terminal of the fourth inverter; the control terminals of the third and fourth switches are used to receive the indication signal; the control terminal of the fifth switch is used to receive the first flip indication signal; the control terminal of the seventh switch is used to receive the second flip indication signal; the control terminal of the sixth switch is used to receive the inverted signal of the second flip indication signal; and the control terminal of the eighth switch is used to receive the inverted signal of the first flip indication signal.

11. The pixel circuit according to any one of claims 2-10, characterized in that, The data storage unit includes: Multiple storage structures are provided, wherein the multiple storage structures are used to store data of corresponding bits in the data signal according to a scan signal, or the multiple storage structures are used to receive multiple scan signals, and each storage structure is used to receive a corresponding scan signal among the multiple scan signals and store data of corresponding bits in the data signal according to the corresponding scan signal.

12. The pixel circuit according to claim 11, characterized in that, The storage structure includes: A first memory is used to receive and store data corresponding to the bits in the data signal; A first write switch is used to receive the scan signal and write the data of the corresponding bit in the data signal into the first memory according to the scan signal.

13. The pixel circuit according to claim 12, characterized in that, The storage structure specifically includes: The first write switch includes a first switching transistor and a second switching transistor, and the first memory includes a first inverter and a second inverter; Wherein, the first terminal of the first switch is used to receive the inverted signal of the scan signal, the second terminal of the first switch is connected to the positive terminal of the first inverter and the negative terminal of the second inverter, the first terminal of the second switch is used to receive one bit of the data signal, the second terminal of the second switch is connected to the negative terminal of the first inverter and the positive terminal of the second inverter, the control terminals of the first switch and the second switch are used to receive the scan signal, and the second terminal of the second switch is also used to output one bit of the data signal.

14. A display panel, characterized in that, include: At least one pixel circuit as described in any one of claims 1-13; A control circuit is configured to send at least one of a data signal, a scan signal, a count signal, an indicator signal, a first flip indicator signal, or a second flip indicator signal to the digital PWM module to control the digital PWM module to generate a single-pulse light-emitting signal with a one-bit structure indicating the target duration.

15. The display panel according to claim 14, characterized in that, The control circuit is used for: A clock signal is input to the counting module, and the counting signal output by the counting module is received. Each bit of the counting signal includes the Gamma information corresponding to that bit.

16. The display panel according to claim 14 or 15, characterized in that, When the display panel displays a frame of image, the control circuit is used to: Data signals and scan signals are sequentially sent to the digital PWM module of the at least one pixel circuit, respectively; Alternatively, data signals and scan signals may be sent to the digital PWM module of a portion of the pixel circuits in the at least one pixel circuit, wherein the portion of the pixel circuits is a pixel circuit whose data signals for the current frame image displayed on the display panel are different from those for the previous frame image.

17. The display panel according to any one of claims 14-16, characterized in that, The control circuit is also used for: The light-emitting devices driven by the at least one pixel circuit are controlled to light up simultaneously, or the light-emitting devices driven by the at least one pixel circuit are controlled to light up sequentially, or some of the light-emitting devices driven by the at least one pixel circuit are controlled to light up.

18. The display panel according to claim 17, characterized in that, The control circuit is used for: At a specified time, the counting signal, the first flip indicator signal, and the second flip indicator signal are sent to the digital PWM module of the pixel circuit, respectively, so that the start time of the single pulse light emission signal generated by the pixel circuit is the specified time, and the light emission device is driven to light up at the specified time.

19. An electronic device, characterized in that, Includes the display panel as described in any one of claims 14-18.

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