Display device

Abstract

Provided is a display device having high display quality and a narrow bezel. The display device includes a circuit unit and a display unit. The circuit unit has a region overlapping the display unit. The circuit unit includes a first transistor, a second transistor, a first insulating layer, and a second insulating layer. The display unit includes a third transistor. The first transistor includes a first semiconductor layer. The second transistor includes a second semiconductor layer. The third transistor includes a third semiconductor layer. The first insulating layer is located on the first semiconductor layer. The second semiconductor layer is located on the first insulating layer. The second insulating layer is located on the second semiconductor layer. The third semiconductor layer is located on the second insulating layer. The first semiconductor layer includes polycrystalline silicon. Each of the second semiconductor layer and the third semiconductor layer includes indium oxide.

Description

display device

[0001] One aspect of the present invention relates to a display device and a method for manufacturing the same. Another aspect of the present invention relates to a transistor and a method for manufacturing the same. Another aspect of the present invention relates to a display device having a transistor.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), methods for driving them, or methods for manufacturing them.

[0003] In this specification, a semiconductor device refers to a device that utilizes semiconductor properties, including circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.), devices having such circuits, etc. It also refers to any device that can function by utilizing semiconductor properties. For example, integrated circuits, chips equipped with integrated circuits, and electronic components with chips housed in packages are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices, and may each have a semiconductor device.

[0004] In recent years, there has been a growing demand for high-definition display devices. Devices requiring high-definition display capabilities include those for virtual reality (VR), augmented reality (AR), substitute reality (SR), and mixed reality (MR), all of which are being actively developed.

[0005] Examples of display devices include display devices having liquid crystal elements and display devices having light-emitting elements (also called light-emitting devices). Examples of light-emitting elements include organic EL (Electroluminescence) elements and light-emitting diodes (LEDs). Patent document 1 discloses a high-definition display device using organic EL elements.

[0006] Technology related to transistors using semiconductor thin films is attracting attention. These transistors are widely applied in electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors are also attracting attention as other materials.

[0007] Examples of oxide semiconductors applicable to transistors include indium oxide and indium gallium zinc oxide. Non-patent documents 1 and 2 disclose thin-film transistors using indium oxide.

[0008] International Publication No. 2016 / 038508

[0009] Dhananjay and C. W. Chu, Realization of In▲2▼O▲3▼ thin film transistors through reactive evaporation process. Appl. Phys. Lett. 91, 132111 (2007). Y. Magari et al. Takashi Koida, “High-mobility hydrogenerated polycrystalline In2O3 (In2O3:H) thin-film transistors”, Nature Communications, 13, 1078 (2022) Takashi Koida, “High-mobility transparent conductive film”, National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Presentation Meeting 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0010] One aspect of the present invention aims to provide a semiconductor device or display device having a transistor with high field-effect mobility. Alternatively, it aims to provide a semiconductor device or display device having a transistor with high on-current. Alternatively, it aims to provide a semiconductor device or display device having a transistor of a very small size. Alternatively, it aims to provide a semiconductor device or display device having a transistor with a short channel length. Alternatively, it aims to provide a semiconductor device or display device having a transistor with good electrical characteristics. Alternatively, it aims to provide a semiconductor device or display device that operates at high speed. Alternatively, it aims to provide a semiconductor device with a small footprint. Alternatively, it aims to provide a semiconductor device or display device with low wiring resistance. Alternatively, it aims to provide a semiconductor device or display device with low power consumption. Alternatively, it aims to provide a highly reliable transistor, semiconductor device, or display device. Alternatively, it aims to provide a narrow-bezel display device. Alternatively, it aims to provide a display device with high display quality. Alternatively, it aims to provide a high-definition display device. Alternatively, it aims to provide a method for manufacturing the aforementioned transistor, semiconductor device, or display device. Alternatively, one of the objectives is to provide a highly productive method for manufacturing transistors, semiconductor devices, or display devices. Alternatively, one of the objectives is to provide novel transistors, semiconductor devices, display devices, or methods for manufacturing the same.

[0011] Furthermore, the description of these problems does not preclude the existence of other problems. One aspect of the present invention does not necessarily have to solve all of these problems. It is possible to extract other problems from the description in the specification, drawings, and claims.

[0012] One aspect of the present invention is a display device having a circuit section and a display section. The circuit section has a region that overlaps with the display section. The circuit section has a first transistor, a second transistor, a first insulating layer, and a second insulating layer. The display section has a third transistor. The first transistor has a first semiconductor layer. The second transistor has a second semiconductor layer. The third transistor has a third semiconductor layer. The first insulating layer is located on the first semiconductor layer. The second semiconductor layer is located on the first insulating layer. The second insulating layer is located on the second semiconductor layer. The third semiconductor layer is located on the second insulating layer. The first semiconductor layer has polycrystalline silicon. The second semiconductor layer and the third semiconductor layer each have indium oxide.

[0013] In the aforementioned display device, it is preferable that the second semiconductor layer and the third semiconductor layer each have crystal grains. The particle size of the crystal grains is preferably 0.3 μm or larger.

[0014] In the aforementioned display device, it is preferable that the second semiconductor layer and the third semiconductor layer each include a first metal oxide layer, a second metal oxide layer on the first metal oxide layer, and a third metal oxide layer on the second metal oxide layer. It is preferable that the second metal oxide layer has a region with a higher hydrogen concentration than the first metal oxide layer and the third metal oxide layer, respectively.

[0015] In the aforementioned display device, the second metal oxide layer has a hydrogen concentration of 5 × 10 ２０ atoms / cm ３ The above 5 x 10 ２１ atoms / cm ３ Preferably, the following regions are present: The first metal oxide layer and the third metal oxide layer each preferably have a region in which the hydrogen concentration is 1 / 100 or more and 1 / 8 or less of the hydrogen concentration in the second metal oxide layer.

[0016] In the aforementioned display device, it is preferable that the second metal oxide layer has a region with a lower film density than the first metal oxide layer and the third metal oxide layer, respectively.

[0017] In the aforementioned display device, it is preferable that the thickness of the second metal oxide layer is greater than the thickness of the first metal oxide layer and the thickness of the third metal oxide layer.

[0018] In the aforementioned display device, the thickness of the second metal oxide layer is preferably 1 nm or more and 30 nm or less. The thicknesses of the first metal oxide layer and the third metal oxide layer are preferably 0.5 nm or more and 10 nm or less, respectively.

[0019] In the aforementioned display device, it is preferable that one or both of the first semiconductor layer and the second semiconductor layer have a region that overlaps with the third semiconductor layer.

[0020] In the aforementioned display device, the first insulating layer is preferably an organic insulating layer. The second insulating layer is also preferably an organic insulating layer.

[0021] In the aforementioned display device, the first insulating layer is preferably an inorganic insulating layer. The second insulating layer is preferably an organic insulating layer.

[0022] In the aforementioned display device, it is preferable to have a substrate. The circuit section is preferably located between the substrate and the display section. The substrate is preferably translucent.

[0023] In the aforementioned display device, the substrate is preferably a glass substrate.

[0024] In the aforementioned display device, it is preferable to have a substrate. The circuit section is preferably located between the substrate and the display section. The substrate is preferably flexible.

[0025] One aspect of the present invention can provide a semiconductor device or display device having a transistor with high field-effect mobility. Alternatively, it can provide a semiconductor device or display device having a transistor with high on-current. Alternatively, it can provide a semiconductor device or display device having a transistor of a very small size. Alternatively, it can provide a semiconductor device or display device having a transistor with a short channel length. Alternatively, it can provide a semiconductor device or display device having a transistor with good electrical characteristics. Alternatively, it can provide a semiconductor device or display device that operates at high speed. Alternatively, it can provide a semiconductor device with a small footprint. Alternatively, it can provide a semiconductor device or display device with low wiring resistance. Alternatively, it can provide a semiconductor device or display device with low power consumption. Alternatively, it can provide a highly reliable transistor, semiconductor device, or display device. Alternatively, it can provide a narrow-bezel display device. Alternatively, it can provide a display device with high display quality. Alternatively, it can provide a high-definition display device. Alternatively, it can provide a method for manufacturing the aforementioned transistor, semiconductor device, or display device. Alternatively, it can provide a highly productive method for manufacturing a transistor, semiconductor device, or display device. Alternatively, it can provide a novel transistor, semiconductor device, display device, or method for manufacturing them.

[0026] Furthermore, the description of these effects does not preclude the existence of other effects. One aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description, drawings, and claims.

[0027] Figure 1A is a perspective view showing an example of a display device. Figures 1B and 1C are cross-sectional views showing an example of a display device. Figure 2A is a perspective view showing an example of a display device. Figures 2B and 2C are cross-sectional views showing an example of a display device. Figures 3A and 3B are cross-sectional views showing an example of a semiconductor device. Figures 4A, 4B, and 4C are top views showing an example of a semiconductor device. Figures 5A, 5B, 5C, and 5D are cross-sectional views showing an example of a semiconductor device. Figure 6 is a cross-sectional view showing an example of a semiconductor device. Figures 7A and 7B are cross-sectional views showing an example of a semiconductor device. Figures 8A and 8B are top views showing an example of a semiconductor device. Figure 9 is a cross-sectional view showing an example of a semiconductor device. Figures 10A and 10B are cross-sectional views showing an example of a semiconductor device. Figure 11 is a cross-sectional view showing an example of a semiconductor device. Figure 12 is a cross-sectional view showing an example of a semiconductor device. Figures 13A and 13B are cross-sectional views showing an example of a semiconductor device. Figures 14A and 14B are top views showing an example of a semiconductor device. Figures 15A and 15B are cross-sectional views showing an example of a display device. Figures 16A and 16B are cross-sectional views showing an example of a display device. Figure 17 is an example of a block diagram of the display device circuit. Figure 18 is an example of a block diagram of the display device circuit. Figure 19 is an example of a block diagram of the display device circuit. Figure 20 is an example of a block diagram of the display device circuit. Figures 21A and 21B are examples of circuit diagrams of a display device. Figures 22A, 22B, 22C, 22D, 22E, and 22F are circuit diagrams of pixel circuits. Figures 23A, 23B, 23C, and 23D are circuit diagrams of pixel circuits. Figures 24A and 24B are circuit diagrams of pixel circuits. Figures 25A and 25B are circuit diagrams of pixel circuits. Figure 26 is a circuit diagram of a pixel circuit. Figures 27A and 27B illustrate the carrier concentration dependence of hole mobility. Figure 27C is a cross-sectional view illustrating an indium oxide film. Figures 28A, 28B, 28C, and 28D show examples of electronic devices. Figures 29A, 29B, 29C, 29D, 29E, and 29F show examples of electronic devices. Figures 30A, 30B, 30C, 30D, 30E, 30F, and 30G show examples of electronic devices.Figures 31A and 31B show an example of a vehicle.

[0028] Embodiments will be described in detail with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the present invention. Accordingly, the present invention shall not be construed as being limited to the descriptions of the embodiments shown below.

[0029] In the configuration of the invention described below, the same reference numerals are used in common across different drawings for parts that are identical or have similar functions, and repeated explanations are omitted. In addition, when referring to similar functions, the hatching patterns are the same, and reference numerals may not be assigned.

[0030] The position, size, and scope of each component shown in the drawings may not represent the actual position, size, and scope for the sake of ease of understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, and scope disclosed in the drawings.

[0031] In this specification, ordinal numbers such as "first," "second," etc., are used to avoid confusion of components and do not limit the number of components or the order of components (e.g., process order or stacking order). Furthermore, even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion of components. Even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Even if a term has an ordinal number in this specification, an ordinal number may be omitted in the claims.

[0032] In this specification and drawings, when the same reference numeral is used for multiple elements, and especially when it is necessary to distinguish them, the reference numeral may be accompanied by an identifying numeral such as "_1", "[n]", or "[m,n]". Furthermore, when describing a common matter for multiple elements with identifying numerals, or when it is not necessary to distinguish them, the identifying numeral may be omitted.

[0033] The words "film" and "layer" can be interchanged depending on the context or situation. For example, the term "conductive layer" can be changed to "conductive film." Or, for example, the term "insulating film" can be changed to "insulating layer."

[0034] A transistor is a type of semiconductor device that can perform functions such as amplifying current or voltage, and switching operations that control conduction or non-conductivity. Transistors as used herein include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0035] The functions of "source" and "drain" may be reversed when transistors with different polarities are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably. Furthermore, the names of the source and drain of a transistor can be appropriately rephrased as source terminal and drain terminal, or source electrode and drain electrode, depending on the situation.

[0036] The terms "gate" and "back gate" are interchangeable. Therefore, in this specification, the terms "gate" and "back gate" may be used interchangeably. Furthermore, the names of the gate and back gate of a transistor can be appropriately rephrased as gate electrode and back gate electrode, etc., depending on the context.

[0037] In this specification, "connection" includes, for example, "electrical connection." The term "electrical connection" is sometimes used to define the connection relationship of circuit elements as a physical object. Furthermore, "electrical connection" includes both "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the use of circuit elements (e.g., transistors, switches, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected through one or more circuit elements. A and B refer to objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0038] For example, assuming a circuit including A and B is in operation, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected" as physical objects. Furthermore, even if there is a timing during the circuit's operation when no electrical signals are exchanged or potential interactions occur between A and B, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected."

[0039] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where "A and B are not indirectly connected" is when an insulator is interposed in the path from A to B. Specifically, this includes cases where a capacitive element is connected between A and B, or where a transistor gate insulating film is interposed between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of a transistor are indirectly connected."

[0040] Another example of a situation where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via source and drain in the path from A to B, and a constant potential V is supplied to the nodes between the transistors from a power supply, GND, etc.

[0041] In this specification, unless otherwise specified, on-current refers to the drain current (also called the conduction state) when the transistor is in the on state. Unless otherwise specified, the on state refers to the state in an n-channel transistor where the voltage between the gate and source (gate voltage, also called Vg or Vgs) is equal to or greater than the threshold voltage (also called Vth), and in a p-channel transistor where it is less than or equal to the threshold voltage.

[0042] In this specification, unless otherwise specified, off-current refers to the source-drain leakage current when the transistor is in the off state (also called the non-conductive state or cutoff state). Unless otherwise specified, the off state refers to the state in an n-channel transistor where the voltage between the gate and source is lower than the threshold voltage, and in a p-channel transistor where it is higher than the threshold voltage.

[0043] In this specification, "parallel" means a state in which two lines are positioned at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Furthermore, "approximately parallel" means a state in which two lines are positioned at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" means a state in which two lines are positioned at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Furthermore, "approximately perpendicular" means a state in which two lines are positioned at an angle of 60 degrees or more and 120 degrees or less.

[0044] In this specification, the top surface shape of a component refers to the contour shape of the component when viewed from above (also called a plan view). Furthermore, a top view refers to viewing from the direction normal to the surface on which the component is formed, or to the surface of the support (e.g., substrate) on which the component is formed.

[0045] In this specification, "matching or roughly matching top shapes" means that at least a portion of the contours overlap between stacked layers. For example, this includes cases where the upper and lower layers are processed with the same mask pattern, or partially with the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer; in this case, it may also be said that the "matching or roughly matching top shapes" apply. Furthermore, when the top shapes match or roughly match, it can also be said that the "edges match or roughly match," or "the edges are aligned or roughly aligned."

[0046] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. The angle formed between the inclined side surface and the substrate surface or the surface to be formed is sometimes referred to as the taper angle.

[0047] In this specification, "step breakage" refers to the phenomenon in which a layer, film, or electrode is divided due to the shape of the surface on which it is formed (e.g., a step).

[0048] In this specification, "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated. For example, an island-like metal oxide layer refers to a state in which the metal oxide layer and adjacent metal oxide layers are physically separated.

[0049] In this specification, devices fabricated using a metal mask or FMM (Fine Metal Mask, a high-resolution metal mask) may be referred to as MM (Metal Mask) structured devices. Furthermore, in this specification, devices fabricated without using a metal mask or FMM may be referred to as MML (Metal Maskless) structured devices.

[0050] In this specification, a structure in which different light-emitting layers are created using light-emitting devices with different emission wavelengths is sometimes referred to as an SBS (Side By Side) structure.

[0051] In this specification, holes or electrons may be referred to as "carriers." For example, in a light-emitting element, a hole injection layer or electron injection layer may be called a "carrier injection layer," a hole transport layer or electron transport layer may be called a "carrier transport layer," and a hole blocking layer or electron blocking layer may be called a "carrier blocking layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier blocking layer may not always be clearly distinguishable. Furthermore, a single layer may combine the functions of two or three of the carrier injection layer, carrier transport layer, and carrier blocking layer.

[0052] In this specification, a light-emitting element has an EL layer between a pair of electrodes (a first electrode and a second electrode). The light-emitting element includes a first electrode, an EL layer on the first electrode, and a second electrode on the EL layer. The EL layer has at least a light-emitting layer. Here, examples of layers (also called functional layers) that the EL layer has include a light-emitting layer, a carrier injection layer (hole injection layer and electron injection layer), a carrier transport layer (hole transport layer and electron transport layer), and a carrier block layer (hole block layer and electron block layer). In this specification, a photodetector (also called a photodetector device) has at least an active layer that functions as a photoelectric conversion layer between a pair of electrodes. In this specification, one of the first electrode and the second electrode may be referred to as a pixel electrode, and the other as a common electrode.

[0053] In this specification, flexibility refers to the property of an object being flexible and able to bend. It is the property of an object being able to deform in response to an external force applied to it, regardless of whether it is elastic or able to return to its original shape.

[0054] For example, flexible electronic devices, flexible display devices (also called flexible displays, etc.), flexible batteries (also called flexible batteries, etc.), and flexible substrates (also called flexible substrates, etc.) can each be deformed in response to external forces. Flexible electronic devices, flexible display devices, flexible batteries, and flexible substrates can each be used fixed in a deformed state, used after repeated deformation, or used in an undeformed state. The phrase "deforms in response to external forces" above means that it can be deformed by the average adult's hand without requiring excessive force. Flexibleness can be evaluated using testing machines capable of stress-strain measurement (tensile testing machines, compression testing machines, etc.). In stress-strain measurement, the flexibility of an object can be quantified by applying an external force to the object and measuring the strain of the object caused by the resulting stress.

[0055] In this specification, when an object is described as having flexibility, it means that at least a part of the object is flexible. In other words, a flexible object may also have parts that are not flexible (which can be called rigid parts).

[0056] In this specification, when two objects are deformed by the same external force, the object that deforms more is said to be the object with higher flexibility. Also, when a first part and a second part of an object are deformed by the same external force, the part that deforms more is said to be the part with higher flexibility.

[0057] (Embodiment 1) In this embodiment, a display device and a semiconductor device according to one aspect of the present invention will be described with reference to Figures 1A to 14B. The semiconductor device according to one aspect of the present invention can be suitably used, for example, in one or both of the pixel circuit and the drive circuit of a display device.

[0058] <Example of Display Device Configuration 1> Figure 1A shows a perspective view of a display device 70, which is one embodiment of the present invention. The display device 70 has a display unit 62 and a circuit unit 64. The circuit unit 64 is provided in an area that overlaps with the display unit 62. The circuit unit 64 is provided on the opposite side of the display surface of the display unit 62. Note that the circuit unit 64 is omitted in Figure 1A. By providing the circuit unit 64 in an area that overlaps with the display unit 62, a narrow-bezel display device can be made.

[0059] The display device 70 has a configuration in which a substrate 51 and a substrate 52 are bonded together. In Figure 1A, the substrate 52 is shown by a dashed line. The display device 70 has a display unit 62 and a circuit unit 64 between the substrate 51 and the substrate 52.

[0060] The display unit 62 is an area for displaying an image and has a plurality of pixels 19 arranged periodically. Figure 1A shows a magnified view of one pixel 19. The pixel 19 shown in Figure 1A has pixels 17R, 17G, and 17B that function as sub-pixels. For example, pixel 17R emits red light, pixel 17G emits green light, and pixel 17B emits blue light. By combining multiple sub-pixels that emit different colors into a single pixel, full-color display can be achieved. The number of sub-pixels that a single pixel has and the combination of sub-pixel colors are not particularly limited.

[0061] Each pixel 17R, pixel 17G, and pixel 17B includes a display element and a pixel circuit that controls the driving of the display element.

[0062] There are no particular limitations on the pixel arrangement in the display device of this embodiment, and various methods can be applied. Examples of pixel arrangements include stripe arrangements, S-stripe arrangements, matrix arrangements, delta arrangements, Bayer arrangements, and pentile arrangements.

[0063] The circuit unit 64 has the function of controlling the pixel circuit. The circuit unit 64 includes, for example, a scan line drive circuit (also called a gate driver). It is preferable that the circuit unit 64 includes both a scan line drive circuit and a signal line drive circuit (also called a source driver). By having the signal line drive circuit in the circuit unit 64, there is no need to provide an external signal line drive circuit. Therefore, the manufacturing cost of the display device can be reduced.

[0064] The circuit section 64 can utilize various circuits, including shift register circuits, level shifter circuits, inverter circuits, latch circuits, analog switch circuits, demultiplexer circuits, and logic circuits. Transistors and capacitive elements can also be used in the circuit section 64.

[0065] A display device according to one aspect of the present invention can be used in a display module. Examples of display modules include a display module to which a connector such as a flexible printed circuit board (FPC) or TCP (Tape Carrier Package) is attached, and a display module on which an integrated circuit (IC) is mounted using the COG (Chip On Glass) method or COF (Chip On Film) method.

[0066] The display device 70 includes a display unit 62 and a circuit unit 64, as well as a connection unit 40 and a conductive layer 65. Figure 1A also shows an example in which an FPC 72 is mounted on the display device 70. Therefore, the configuration shown in Figure 1A can also be described as a display module having a display device 70 and an FPC 72.

[0067] The connection portion 40 is provided on the outside of the display unit 62. The connection portion 40 can be provided along one or more sides of the display unit 62. There can be one or more connection portions 40. Figure 1A shows an example in which the connection portion 40 is provided so as to surround all four sides of the display unit 62. The connection portion 40 connects the common electrode of the display element to the conductive layer, and can supply potential to the common electrode.

[0068] The conductive layer 65 has the function of supplying signals and power to the display unit 62 and the circuit unit 64. These signals and power are input to the conductive layer 65 from the outside via the FPC 72.

[0069] Figure 1B shows a cross-sectional view illustrating the configuration of the display unit 62 and the circuit unit 64. Figure 1B shows the pixels 17 that can be applied to the sub-pixels (for example, pixels 17R, 17G, and 17B) of the display unit 62.

[0070] Each pixel 17 includes a display element 13 and a pixel circuit 15. The pixel circuit 15 includes a transistor 30A. The transistor 30A is connected to the display element 13. The number of transistors included in the pixel circuit 15 is not particularly limited. The pixel circuit 15 can be configured to have multiple transistors 30A.

[0071] The circuit section 64 is provided in an area that overlaps with the pixel circuit 15. The circuit section 64 includes a transistor 10A and a transistor 20A. Preferably, the transistor 10A has an area that overlaps with the transistor 20A. This reduces the area occupied by the circuit section 64. It is even more preferable that one or both of the transistors 10A and 20A have areas that overlap with the transistor 30A. This further reduces the area occupied by the circuit section 64. The number of transistors included in the circuit section 64 is not particularly limited. The circuit section 64 can be configured to have multiple transistors 10A and multiple transistors 20A. Also, the connection relationships between the transistors included in the pixel circuit 15 and the circuit section 64 are not particularly limited.

[0072] Transistors 10A, 20A, and 30A can each be formed by different processes. Figure 1B shows a layer 11 containing transistor 10A, a layer 21 containing transistor 20A, and a layer 31 containing transistor 30A. Layer 11 containing transistor 10A is provided on the substrate 51, layer 21 containing transistor 20A is provided on layer 11, layer 31 containing transistor 30A is provided on layer 21, and a display element 13 is provided on layer 31. Note that layers 11 and 21 may not be clearly distinguishable. Similarly, layers 21 and 31 may not be clearly distinguishable. Furthermore, a configuration in which a part of the transistors in one layer is included in the other layer is possible. For example, a configuration in which a part of transistor 10A is included in layer 21 is possible. Transistor 20A can be formed after forming transistor 10A or a part of transistor 10A. A part of transistor 10A and a part of transistor 20A can be formed in a common process. Similarly, transistor 30A can be formed after forming transistor 20A or a part of transistor 20A. Part of transistor 20A and part of transistor 30A can be formed in a common process.

[0073] By placing the transistors of the circuit section 64 in layers 11 and 21, the area occupied by the circuit section 64 can be reduced. This makes it possible to create a display device with a narrow bezel.

[0074] The structures of the transistors provided in layer 11 (here, transistor 10A), layer 21 (here, transistor 20A), and layer 31 (here, transistor 30A) are not particularly limited. Furthermore, transistors with the same structure can be applied to the transistors provided in layer 11, layer 21, and layer 31. Alternatively, transistors with different structures can be applied to some or all of the transistors provided in layer 11, layer 21, and layer 31.

[0075] The semiconductor layer of transistor 10A (hereinafter also referred to as the first semiconductor layer), the semiconductor layer of transistor 20A (hereinafter also referred to as the second semiconductor layer), and the semiconductor layer of transistor 30A (hereinafter also referred to as the third semiconductor layer) can be formed by different processes. Therefore, different materials can be used for some or all of the first, second, and third semiconductor layers, thereby broadening the range of materials that can be used for these semiconductor layers.

[0076] In this specification, "different materials" means materials in which some or all of the constituent elements are different, or materials in which the constituent elements are the same but the composition is different.

[0077] The electrical characteristics and reliability of a transistor differ depending on the material used in the semiconductor layer. It is preferable to use different materials for some or all of the first, second, and third semiconductor layers, depending on the required electrical characteristics and reliability for transistors 10A, 20A, and 30A. This makes it possible to create a display device that achieves both high display quality and high reliability.

[0078] Alternatively, the same material can be used for the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer. This allows the equipment used to form the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer to be common, thereby reducing the manufacturing cost of the display device.

[0079] The semiconductor materials used in the first, second, and third semiconductor layers are not particularly limited. For example, semiconductors made of elemental materials or compound semiconductors can be used. Examples of semiconductors made of elemental materials include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors (OS). These semiconductor materials may contain impurities as dopants.

[0080] The crystallinity of the semiconductor material is not particularly limited; amorphous semiconductors, single-crystal semiconductors, or semiconductors with crystalline properties other than single crystals (microcrystalline semiconductors, polycrystalline semiconductors, or semiconductors with crystalline regions in part) can all be used. Using a single-crystal semiconductor or a semiconductor with crystalline properties is preferable because it can suppress the degradation of transistor characteristics.

[0081] For example, silicon can be used for one or more of the first, second, and third semiconductor layers. Examples of silicon include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low-temperature polysilicon (LTPS). Transistors using amorphous silicon for the channel formation region can be fabricated at low cost on large glass substrates. Transistors using polycrystalline silicon for the channel formation region have high field-effect mobility and can operate at high speeds. Transistors using microcrystalline silicon for the channel formation region have higher field-effect mobility and can operate at high speeds than transistors using amorphous silicon. Note that transistors using silicon for the channel formation region are sometimes referred to as Si transistors, and transistors using LTPS for the channel formation region are sometimes referred to as LTPS transistors.

[0082] It is preferable to use a metal oxide (also called an oxide semiconductor) exhibiting semiconductor properties in one or more of the first, second, and third semiconductor layers. The band gap of the metal oxide in the semiconductor layer is preferably 2.0 eV or more, and more preferably 2.5 eV or more. Transistors using oxide semiconductors (hereinafter also referred to as OS transistors) have extremely high field-effect mobility compared to transistors using amorphous silicon. Furthermore, OS transistors have a remarkably low off-current and can retain the charge stored in a capacitor connected in series with the transistor for a long period of time. In addition, by applying OS transistors, the power consumption of the display device can be reduced. When a metal oxide is used in the semiconductor layer, the semiconductor layer can be called a metal oxide layer or a metal oxide film.

[0083] It is preferable to use metal oxides for the first, second, and third semiconductor layers, respectively. In other words, it is preferable to apply OS transistors to both the display unit 62 and the circuit unit 64. Furthermore, all transistors in the display device can be OS transistors. This makes it possible to create a display device with low power consumption. It also makes it possible to keep manufacturing costs low.

[0084] Alternatively, it is preferable to use a metal oxide in one or more of the first, second, and third semiconductor layers, and LTPS in the other semiconductor layers. This makes it possible to have an OS transistor that achieves both low off-current and high field-effect mobility, and an LTPS transistor with high field-effect mobility, resulting in a display device that achieves both high display quality and low power consumption. For example, LTPS can be suitably used in the first semiconductor layer, and metal oxides can be suitably used in the second and third semiconductor layers, respectively. Furthermore, by making transistor 10A a p-channel type LTPS transistor and transistor 20A an n-channel type OS transistor, a CMOS (Complementary Metal Oxide Semiconductor) circuit can be realized. By making the circuit section 64 having a CMOS circuit, the degree of design freedom of the circuit section 64 is increased, and the occupied area can be reduced. The connection relationship between transistor 10A and transistor 20A is not particularly limited.

[0085] In the following explanation, we may use a configuration in which silicon (e.g., LTPS) is used for the first semiconductor layer, and metal oxides are used for the second and third semiconductor layers, respectively, as an example.

[0086] Examples of metal oxides include indium oxide, gallium oxide, and zinc oxide. It is preferable to use an oxide containing indium as the metal oxide. It is even more preferable that the metal oxide has a high indium content. By using a metal oxide with a high indium content in the semiconductor layer of a transistor, a transistor with a large on-current can be made, and thus a transistor that can operate at high speed can be made. For example, it is preferable to apply a transistor using a metal oxide with a high indium content to a signal line drive circuit (source driver) so that it can operate at high speed. This makes it possible to make a display device with high display quality. In addition, transistors using a metal oxide with a high indium content in the semiconductor layer have high field-effect mobility and can obtain a large on-current even with a small channel width, so the area occupied by the transistor can be reduced. By applying a transistor using a metal oxide with a high indium content in the semiconductor layer to the pixel circuit 15, the area occupied by the pixel circuit 15 can be reduced, making it possible to make a high-definition display device. By applying a transistor using a metal oxide with a high indium content in the semiconductor layer to the circuit section 64, the area occupied by the circuit section 64 can be reduced, making it possible to make a display device with a narrow bezel. Indium oxide can be suitably used as the metal oxide.

[0087] The metal oxide preferably contains at least indium. Alternatively, the metal oxide preferably contains either or both indium and zinc. Alternatively, the metal oxide preferably has one or more elements selected from indium, element M, and zinc. Element M is a metallic or metalloid element with a high bond energy to oxygen, for example, a metallic or metalloid element with a higher bond energy to oxygen than indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M present in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from gallium, aluminum, tin, and yttrium, and even more preferably one or more of gallium, aluminum, and tin. These elements are more preferred because they have high bonding energy with oxygen and their ionic radii are similar to those of indium or zinc. Furthermore, tin is more preferred because its tetravalent state can increase carrier mobility. In this specification, metallic elements and metalloid elements are sometimes collectively referred to as "metallic elements," and the "metallic elements" described in this specification may include metalloid elements.

[0088] In this specification, the ratio of the number of indium atoms to the sum of the total number of atoms of all contained metal elements may be referred to as the indium content. The same applies to other metal elements. If element M contains multiple elements, the sum of the ratios of the number of atoms of element M to the sum of the total number of atoms of all contained metal elements may be referred to as the element M content.

[0089] Examples of metal oxides include indium zinc oxide (In-Zn oxide, also known as IZO®), indium tin oxide (In-Sn oxide, also known as ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium tungsten oxide (In-W oxide, also known as IWO), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also known as IGTO), gallium zinc oxide (Ga-Zn oxide, also known as GZO), and aluminum zinc oxide (Al-Zn oxide). Other suitable materials include indium aluminum zinc oxide (also written as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also written as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also written as ITZO®), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as IGAZO, IGZAO, or IAGZO), etc. Alternatively, silicon-containing indium tin oxide (also written as ITSO), gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc.

[0090] Furthermore, the metal oxide can be composed of one or more metal elements with high periodic numbers in the periodic table, either in place of indium or in addition to indium. The greater the overlap of the metal element orbitals, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including metal elements with high periodic numbers, the field-effect mobility of the transistor can be increased. Examples of metal elements with high periodic numbers include those belonging to the 5th period and those belonging to the 6th period. Specifically, these metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0091] Metal oxides may contain one or more nonmetallic elements. The presence of nonmetallic elements in metal oxides can increase carrier concentration or reduce the band gap, potentially improving the field-effect mobility of transistors. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0092] By increasing the zinc content in a metal oxide, a highly crystalline metal oxide is obtained, which suppresses the diffusion of impurities within the metal oxide. Therefore, fluctuations in the electrical characteristics of the transistor are suppressed, and its reliability can be improved.

[0093] By increasing the content of element M in the metal oxide, a metal oxide with a large band gap can be produced. This allows for the formation of oxygen vacancies (V) in the metal oxide. Ｏ The formation of oxygen deficiency (V) is suppressed. ＯCarrier generation caused by ) is suppressed. Therefore, the shift in the transistor's threshold voltage is suppressed, allowing it to be a normally-off transistor, and the drain current (hereinafter also referred to as cutoff current) that flows when the gate voltage (Vg) is 0V can be reduced. In addition, it is possible to create a transistor with a small off-current. Furthermore, fluctuations in the transistor's electrical characteristics are suppressed, and reliability can be improved.

[0094] By using a metal oxide with a large band gap in the semiconductor layer, oxygen vacancies (V) can be created in the semiconductor layer by light. Ｏ The formation of ) is suppressed, and the negative shift of the transistor's threshold voltage can be suppressed. Therefore, a transistor with high reliability against light can be made. A metal oxide having element M can be suitably used in the semiconductor layer of a transistor provided in a region where light can be incident (for example, a display unit).

[0095] When a metal oxide is used in a semiconductor layer, it is preferable that the semiconductor layer is crystalline. Examples of crystalline metal oxide structures include single crystals, polycrystalline structures, CAAC (c-axis aligned crystal) structures, microcrystalline structures, and nanocrystalline (nc: nano-crystal) structures. By using a crystalline metal oxide, the defect level density in the semiconductor layer can be reduced, enabling the realization of a highly reliable semiconductor device.

[0096] When a metal oxide is used for the semiconductor layer, the crystallinity of the semiconductor layer is preferably high, and it is preferable that it be polycrystalline or single-crystal. A polycrystalline indium oxide film is preferably used as the semiconductor layer, and a single-crystal indium oxide film is more preferable.

[0097] The crystallinity of a semiconductor layer can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these methods can be used for analysis.

[0098] Single-crystal films are particularly preferred because they do not have grain boundaries, thus suppressing carrier scattering at grain boundaries and enabling transistors with high field-effect mobility. Compared to microcrystalline and amorphous films, polycrystalline films can reduce carrier scattering and enable transistors with high field-effect mobility. When using a polycrystalline film as the semiconductor layer, it is preferable that the grain size of the crystals contained in the semiconductor layer is large. By using a polycrystalline film with large grain size, the number of crystal grain boundaries located in the channel formation region can be reduced, and the length of the crystal grain boundaries located in the channel formation region can be shortened, thus enabling transistors with high field-effect mobility. Furthermore, it is preferable to have a small number of crystal grain boundaries that intersect with the direction of drain current flow (also known as the channel length direction) in the channel formation region. Note that even with a polycrystalline film, if there are no crystal grain boundaries located in the channel formation region, the same effects as a single-crystal film can be achieved.

[0099] When a polycrystalline indium oxide film is used as the semiconductor layer, the grain size of the crystal grains contained in the semiconductor layer is preferably 0.1 μm or larger, more preferably 0.2 μm or larger, more preferably 0.3 μm or larger, more preferably 0.4 μm or larger, more preferably 0.5 μm or larger, more preferably 0.6 μm or larger, and more preferably 0.7 μm or larger. Since a larger grain size is preferable, there is no particular upper limit on the grain size. Note that the grain size of the crystal grains is not limited to the above range.

[0100] The grain size of crystal grains contained in a semiconductor layer can be analyzed, for example, by transmission electron microscopy (TEM), scanning transmission electron microscopy (STEM), or electron backscatter diffraction (EBSD or EBSP). Alternatively, a combination of these methods can be used for analysis. For example, the average grain size of multiple crystal grains can be used as the grain size. Furthermore, the grain size of a crystal grain can be defined as, for example, the diameter of a circle with the same area as the crystal grain. This diameter is sometimes called the equivalent diameter of a circle.

[0101] In this specification, a grain boundary refers to, for example, the boundary between adjacent grains with different crystal orientations. Therefore, in this specification, boundaries between adjacent grains with the same crystal orientation are not included in grain boundaries. For example, even if a boundary is observed between two grains in a TEM image, if the crystal orientations of those two grains are the same or approximately the same, the boundary may not be called a grain boundary. Also, in EBSD, if the difference in crystal orientation between adjacent measurement points is small (for example, if the difference in crystal orientation is less than 5 degrees), these measurement points can be considered to belong to the same grain.

[0102] In this specification, space groups are denoted using the international notation (or Hermann-Mauguin notation) Short notation. In addition, space group numbers from the International Tables for Crystallography Volume A (hereinafter also referred to as ITA) may be included. Furthermore, Miller indices are used to indicate crystal planes and crystal directions. In crystallography, space groups, crystal planes, and crystal directions are indicated by a bar above the number, but in this specification, due to formatting constraints, a minus sign (-) may be placed before the number instead of a bar above it. In addition, individual orientations indicating directions within a crystal are indicated by [ ], collective orientations indicating all equivalent directions are indicated by < >, individual planes indicating crystal planes are indicated by ( ), and collective planes with equivalent symmetry are indicated by {}. Note that even with the same space group number, the notation for the space group may differ depending on how the crystal axis is defined.

[0103] The cubic crystal structure of indium oxide, for example, belongs to space group Ia-3 (space group number 206).

[0104] The grain size of the crystal grains can also be confirmed, for example, using an optical microscope or a scanning electron microscope (SEM). Furthermore, by creating irregularities on the surface of the semiconductor layer using etchants with different etching rates depending on the crystal plane or crystallinity, the crystal grains can be more easily observed with an optical microscope or scanning electron microscope (SEM). When using an indium oxide film as the semiconductor layer, using an etchant containing an acid can make it easier to observe the indium oxide crystal grains. For example, one or more of phosphoric acid, oxalic acid, nitric acid, and hydrochloric acid can be used as the acid. However, if the etching rate is too fast, a portion of the semiconductor layer may disappear, making it difficult to observe the crystal grains. Therefore, it is preferable to adjust the etching rate by controlling the concentration, temperature, and processing time of the etchant so that the semiconductor layer does not disappear but its thickness is reduced (also called half-etching). Half-etching allows for easy observation of the crystal grains.

[0105] Note that when the thickness of the semiconductor layer is thin, it may be impossible to evaluate the crystallinity and the grain size of the crystal grains.

[0106] The concentration of impurities in the channel formation region is preferably low. The channel formation region is preferably of high purity. In the channel formation region, impurities can become carrierscattering sources and thus can be a factor in reducing the field-effect mobility. Also, impurities can be a factor in inhibiting crystal growth.

[0107] For the analysis of the impurity concentration in the semiconductor layer, for example, secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry) or X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectrometry, or ESCA: Electron Spectrometry for Chemical Analysis) can be used. When using XPS analysis, by combining ion sputtering from the front or back surface side of the sample and XPS analysis, the concentration distribution in the depth direction can be known. Note that in regions where the concentration is low, quantification may be difficult or may be below the detection limit.

[0108] Examples of impurities in the indium oxide film include gallium, zinc, boron, aluminum, and silicon. In the channel formation region, the concentration of each of these impurities is preferably 1 atomic% or less, more preferably 0.1 atomic% or less, and even more preferably 0.01 atomic% (100 ppm) or less. Note that elements that can be contained in the indium oxide film include, for example, carbon and hydrogen. Carbon and hydrogen are elements that can be contained in the film-forming gas (e.g., precursor) of the indium oxide film and may be present in the indium oxide film in a greater amount than the aforementioned impurities. Note that ppm is an abbreviation for "parts per million", and 1 ppm is 1×10 −６ as follows. <{

[0109] The concentrations of gallium, zinc, boron, aluminum, and silicon in the channel formation region of the indium oxide film are each 1×10 ２０ atoms / cm３ The following is preferable, and moreover, 5 × 10 １９ atoms / cm ３ The following is preferable, and moreover, 3 × 10 １９ atoms / cm ３ The following are preferable, and moreover, 1 × 10 １９ atoms / cm ３ The following is preferable, and moreover, 3 × 10 １８ atoms / cm ３ The following are preferable, and moreover, 1 × 10 １８ atoms / cm ３ The following are preferable.

[0110] By using an indium oxide film with large grain size and low impurity concentration in the transistor, the field-effect mobility of the transistor can be increased to 50 cm⁻¹. ２ / (V・s) or more, and even 100 cm ２ / (V・s) or more, and even 150cm ２ / (V・s) or more, and even 200 cm ２ / (V・s) or more, and even 250 cm ２ It can be set to (V・s) or more.

[0111] Figures 1C to 2C show examples of configurations different from the one shown in Figure 1B.

[0112] The configuration shown in Figure 1C differs from the configuration shown in Figure 1B mainly in that the circuit section 64 has transistors 10B, 20B, and 30B. The pixel circuit 15 has transistor 30A. The circuit section 64 has transistors 10A, 20A, 10B, 20B, and 30B.

[0113] Layer 11 includes transistor 10A and transistor 10B. Transistor 10B can be configured in the same way as transistor 10A and can be formed using the same materials and in the same process as transistor 10A. Similarly, layer 21 includes transistor 20A and transistor 20B. Transistor 20B can be configured in the same way as transistor 20A and can be formed using the same materials and in the same process as transistor 20A. Layer 31 includes transistor 30A and transistor 30B. Transistor 30B can be configured in the same way as transistor 30A and can be formed using the same materials and in the same process as transistor 30A. In other words, some of the transistors in the circuit section 64 can be formed using the same process as the transistors in the pixel circuit 15. Also, transistors 10B, 20B, and 30B can be provided in regions that do not overlap with the pixel circuit 15. In other words, the circuit section 64 has regions that overlap with the pixel circuit 15 and regions that do not overlap with the pixel circuit 15. Figure 2A shows a perspective view of a display device 70 to which the configuration shown in Figure 1C is applied. In Figure 2A, the region of the circuit section 64 that does not overlap with the pixel circuit 15 is clearly indicated.

[0114] By arranging the transistors of the circuit section 64 in layers 11, 21, and 31, the area occupied by the circuit section 64 can be reduced compared to the case where the same number of transistors are not provided in layer 11 but are provided in layers 21 and 31. This makes it possible to create a display device with a narrow bezel.

[0115] The configuration shown in Figure 2B differs from the configuration shown in Figure 1C mainly in that the pixel circuit 15 has a transistor 20A. The pixel circuit 15 has transistor 20A and transistor 30A. The circuit section 64 has transistor 10A, transistor 10B, transistor 20B and transistor 30B. By providing the transistors of the pixel circuit 15 in layers 11 and 21, the occupied area of ​​the pixel circuit 15 can be reduced. This makes it possible to create a high-definition display device.

[0116] The configuration shown in Figure 2C differs from the configuration shown in Figure 1C mainly in that the pixel circuit 15 has transistors 10A and 20A. The pixel circuit 15 has transistors 10A, 20A and 30A. The circuit section 64 has transistors 10B, 20B and 30B. By providing the transistors of the pixel circuit 15 in layers 11, 21 and 31, the area occupied by the pixel circuit 15 can be reduced. This makes it possible to create a high-definition display device.

[0117] Although Figures 2B and 2C show a configuration in which the display element 13 is connected to the transistor 30A, the present invention is not limited to this configuration. The display element 13 can also be connected to the transistor 10A or the transistor 20A.

[0118] [Semiconductor Layer] The metal oxides that can be used in the semiconductor layer will be described in detail. As mentioned above, it is preferable that the metal oxide contains at least indium.

[0119] When the metal oxide is an In-M-Zn oxide, it is preferable that the atomic ratio of In in the In-M-Zn oxide is equal to or greater than the atomic ratio of element M. Examples of such atomic ratios of metal elements in an In-M-Zn oxide include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:1, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, and In:M Compositions such as Zn=5:1:9, In:M:Zn=6:1:6, In:M:Zn=10:1:1, In:M:Zn=10:1:3, In:M:Zn=10:1:4, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=5:2:5, In:M:Zn=10:1:10, In:M:Zn=20:1:10, In:M:Zn=40:1:10, and compositions near these. In this specification, "nearby composition" includes a range of ±30% of the desired atomic ratio. Increasing the atomic ratio of indium in the metal oxide can increase the on-current or field-effect mobility of the transistor.

[0120] The atomic ratio of In in an In-M-Zn oxide can be less than the atomic ratio of element M. Examples of such atomic ratios of metal elements in an In-M-Zn oxide include In:M:Zn = 1:3:2, In:M:Zn = 1:3:3, In:M:Zn = 1:3:4, In:M:Zn = 1:3:6, and compositions close to these. By increasing the proportion of M atoms in the metal oxide, oxygen deficiency (V) can be reduced. Ｏ This can suppress the generation of ()

[0121] Furthermore, if element M comprises multiple elements, the sum of their atomic ratios can be used as the atomic ratio of element M.

[0122] By using a material with a high indium content in the semiconductor layer, the on-current or field-effect mobility of the transistor can be increased. Furthermore, the presence of element M allows for oxygen deficiency (V ＯThe generation of ) can be suppressed. The content of element M is preferably 0.1% to 25%, more preferably 0.1% to 20%, more preferably 0.1% to 10%, more preferably 0.1% to 8%, more preferably 0.1% to 6%, and more preferably 0.1% to 4%. This makes it possible to make a transistor with good electrical characteristics. For example, it is preferable to use a metal oxide in which In:M:Zn = 40:1:10 or a similar ratio. Element M is preferably one or more of the above elements, and more preferably one or more selected from aluminum, gallium, tin, and yttrium. Specifically, a metal oxide in which In:Sn:Zn = 40:1:10 or a similar ratio can be suitably used. Alternatively, a metal oxide in which In:Al:Zn = 40:1:10 or a similar ratio can be suitably used.

[0123] A metal oxide that does not contain element M can be applied to the semiconductor layer. When the metal oxide is an In-Zn oxide, examples of atomic ratios of the metal elements include In:Zn=1:1, In:Zn=2:1, In:Zn=1:2, In:Zn=3:1, In:Zn=3:2, In:Zn=2:3, In:Zn=4:1, In:Zn=4:3, In:Zn=5:1, In:Zn=5:2, In:Zn=5:3, In:Zn=5:4, In:Zn=5:6, In:Zn=5:7, In:Zn=5:8, In:Zn=5:9, In:Zn=7:1, In:Zn=10:1, In:Zn=10:3, In:Zn=10:7, and compositions near these. Furthermore, it is more preferable that the atomic ratio of In is greater than or equal to the atomic ratio of Zn. By increasing the atomic ratio of indium in a metal oxide, the on-current or field-effect mobility of a transistor can be increased.

[0124] For analyzing the composition of semiconductor layers, for example, energy-dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS or ESCA), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled high-frequency plasma atomic emission spectroscopy (ICP-AES) can be used. Alternatively, a combination of these methods can be used for analysis. It is preferable to separate the peaks of the spectrum obtained from the analysis and then identify and quantify the elements. Note that for elements with low content, the actual content may differ from the content obtained from the analysis due to the effect of analytical accuracy. For example, if the content of element M is low, the content of element M obtained by analysis may be lower than the actual content, it may be difficult to quantify the content of element M, or element M may be below the detection limit.

[0125] Furthermore, when depositing metal oxide films by sputtering, the composition of the deposited metal oxide film may differ from the composition of the sputtering target. In particular, the zinc content in the deposited metal oxide film may decrease to about 50% of the content in the sputtering target.

[0126] Here, in metal oxides, oxygen deficiency (V Ｏ A defect in which hydrogen has entered (hereinafter referred to as V Ｏ The H (denoted as H) functions as a donor, and electrons, which are carriers, may be generated. When a metal oxide is used in the semiconductor layer, the V of the channel formation region Ｏ It is preferable to reduce H as much as possible and make it high-purity intrinsic or substantially high-purity intrinsic. In this way, V Ｏ To obtain a metal oxide with sufficiently reduced H content, impurities such as water and hydrogen must be removed from the metal oxide (sometimes referred to as dehydration and dehydrogenation treatment), and oxygen must be supplied to the metal oxide to eliminate oxygen deficiency (V). Ｏ It is important to repair ). ＯBy using a metal oxide with sufficiently reduced impurities such as H in the channel formation region, a transistor with stable electrical characteristics can be made. Furthermore, by supplying oxygen to the metal oxide, oxygen deficiencies (V) can be reduced. Ｏ The process of repairing this is sometimes referred to as oxygenation treatment.

[0127] OS transistors exhibit minimal fluctuations in electrical properties due to radiation exposure, meaning they have high resistance to radiation, making them suitable for use in environments where radiation may be incident. OS transistors can also be said to have high reliability against radiation. For example, OS transistors can be suitably used in the pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton beams, and neutron beams).

[0128] The semiconductor layer may have a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystalline structure. Such layered materials have high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0129] Examples of the above-mentioned layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogens (elements belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specifically, a transition metal chalcogenide applicable as a channel formation region in transistors is molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum tellurium (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) are some examples.

[0130] <Example of Semiconductor Device Configuration 1> A semiconductor device according to one aspect of the present invention will be described. This semiconductor device according to one aspect of the present invention can be suitably used, for example, in the pixel circuit 15 and circuit section 64 of a display device.

[0131] [Example of Semiconductor Device Configuration 1-1] Figures 3A and 3B show cross-sectional views of a semiconductor device 80, which is one embodiment of the present invention. The semiconductor device 80 includes a transistor 100, a transistor 200, and a transistor 300. The semiconductor device 80 is provided on an insulating surface. Figures 3A and 3B show a configuration in which the semiconductor device 80 is provided on a substrate 102 having an insulating surface. Alternatively, an insulating film can be provided on the substrate 102, and the semiconductor device 80 can be provided on the insulating film.

[0132] Figure 4A shows a top view of the semiconductor device 80. To avoid making the diagram too complex, Figure 4A shows an excerpt of the top view of transistor 300. Figure 4B shows a top view of transistor 200, and Figure 4C shows a top view of transistor 100. Figure 3A is a cross-sectional view of the section along the dashed line A1-A2 shown in Figures 4A to 4C, and Figure 3B is a cross-sectional view of the section along the dashed line B1-B2. Note that in Figures 4A to 4C, some components of the semiconductor device 80 (such as the gate insulating layer) are omitted. In subsequent drawings, as in Figures 4A to 4C, some components of the top view of the semiconductor device will also be omitted.

[0133] An insulating layer 191 is provided on transistor 100, an insulating layer 231 is provided on insulating layer 191, and an insulating layer 167 is provided on insulating layer 231. A transistor 200 is provided on insulating layer 167, an insulating layer 193 is provided on transistor 200, an insulating layer 233 is provided on insulating layer 193, and an insulating layer 169 is provided on insulating layer 233. A transistor 300 is provided on insulating layer 169, and an insulating layer 195 is provided on transistor 300.

[0134] Transistor 100 can be used for transistors 10A and 10B, transistor 200 can be used for transistors 20A and 20B, and transistor 300 can be used for transistors 30A and 30B. Although Figure 3A and other figures show a configuration in which transistors 100, 200, and 300 are all the same size, the size of each transistor is not particularly limited. At least one of transistors 100, 200, and 300 may be a different size from the others.

[0135] The transistor 100 has a conductive layer 103 on a substrate 102, an insulating layer 105 on the conductive layer 103, a semiconductor layer 108 on the insulating layer 105, an insulating layer 106 on the semiconductor layer 108, and a conductive layer 104 on the insulating layer 106.

[0136] The conductive layer 104 has a region that overlaps with the semiconductor layer 108 via the insulating layer 106. In the transistor 100, the conductive layer 104 functions as a first gate electrode, and the insulating layer 106 functions as a first gate insulating layer. The conductive layer 103 has a region that overlaps with the conductive layer 104 via the insulating layer 105, the semiconductor layer 108, and the insulating layer 106. In the transistor 100, the conductive layer 103 functions as a second gate electrode, and the insulating layer 105 functions as a second gate insulating layer. It is preferable that the conductive layer 103 has a region that protrudes from the edge of the conductive layer 104. This enhances the effect (also called the electric field shielding effect) of the conductive layer 103 shielding from electric fields generated outside the transistor, making it difficult for the externally generated electric field to act on the channel formation region.

[0137] The semiconductor layer 108 has regions 108P and 108Q that do not overlap with the conductive layer 104. In the transistor 100, region 108P functions as one of the source region and drain region, and region 108Q functions as the other of the source region and drain region. In the semiconductor layer 108, the region located between the source region and drain region and overlapping with the conductive layer 104 via the insulating layer 106 functions as the channel formation region of the transistor 100.

[0138] Furthermore, in the semiconductor layer 108, the region overlapping with at least one of the conductive layer 104 and the conductive layer 103 functions as a channel-forming region. For the sake of simplicity, the region of the semiconductor layer 108 that overlaps with the conductive layer 104 is sometimes referred to as the channel-forming region, but a region that does not overlap with the conductive layer 104 but overlaps with the conductive layer 103 can also function as a channel-forming region.

[0139] Transistor 100 has gate electrodes (a first gate electrode and a second gate electrode) on both sides of the channel formation region, and can be described as a dual-gate type transistor. Note that one of the first and second gate electrodes may be referred to as the front gate electrode (or simply as the gate electrode), and the other as the back gate electrode.

[0140] By providing a back gate electrode, the potential on the back gate electrode side (also called the back channel side) of the semiconductor layer 108 is fixed, thereby increasing the saturation in the Id-Vd characteristics. Furthermore, by fixing the potential on the back channel side of the semiconductor layer 108, the threshold voltage shift can be suppressed. Therefore, a transistor with a small cutoff current can be made, resulting in a semiconductor device with low power consumption. Here, transistors 100, 200, and 300 are shown having back gates, but the present invention is not limited to this. Transistors without back gates can be used in semiconductor devices.

[0141] In this specification, the term "high saturation" may be used to describe a transistor where the change in current in the saturation region of the Id-Vd characteristic is small.

[0142] In the following, matters common to both the first gate insulating layer and the second gate insulating layer may be referred to simply as the gate insulating layer. Similarly, matters common to both the first gate electrode and the second gate electrode may be referred to simply as the gate electrode.

[0143] An insulating layer 191 is provided on the conductive layer 104 and the insulating layer 106. The insulating layer 191 and the insulating layer 106 have an opening 147a reaching region 108P and an opening 147b reaching region 108Q. A conductive layer 112a is provided so as to cover the opening 147a, and a conductive layer 112b is provided so as to cover the opening 147b. The conductive layer 112a is in contact with region 108P at the opening 147a and is connected to region 108P. The conductive layer 112b is in contact with region 108Q at the opening 147b and is connected to region 108Q. In the transistor 100, the conductive layer 112a functions as one of the source electrode and drain electrode, and the conductive layer 112b functions as the other of the source electrode and drain electrode.

[0144] An insulating layer 231 is provided on the conductive layer 112a, the conductive layer 112b, and the insulating layer 191, and an insulating layer 167 is provided on the insulating layer 231.

[0145] The insulating layer 231 preferably functions as a planarizing layer, and an organic insulating layer is preferred. By providing a planarizing layer on the transistor 100, irregularities caused by the transistor 100 can be reduced. This makes the surface on which the layer is formed on the insulating layer 231 flatter, and prevents defects such as step breaks or porosity from occurring in the layer. Examples of materials that can be used for the organic insulating layer include acrylic resins, polyimide resins, epoxy resins, polyamide resins, polyimidoamide resins, siloxane resins, benzocyclobutene resins, phenolic resins, and precursors of these resins.

[0146] The insulating layer 167 preferably functions as an etching protection layer, and an inorganic insulating layer is preferred. By providing the insulating layer 167, it is possible to suppress the formation of recesses in the insulating layer 231 when the transistor 200 is formed. This makes the surface of the layer formed on the insulating layer 231 flatter, and it is possible to suppress the occurrence of defects such as step breaks or porosity in the layer. Examples of materials that can be used for the inorganic insulating layer include oxides, nitrides, oxidized nitrides, and nitride oxides. Examples of oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, zinc gallium oxide, and hafnium aluminate. Examples of nitrides include silicon nitride and aluminum nitride. Examples of oxidized nitrides include silicon oxidized nitride, aluminum oxidized nitride, gallium oxidized nitride, yttrium oxidized nitride, and hafnium oxidized nitride. Examples of nitride oxides include silicon nitride and aluminum nitride.

[0147] In this specification, the term "oxidogenic nitride" refers to a material whose composition contains more oxygen than nitrogen. The term "nitride oxide" refers to a material whose composition contains more nitrogen than oxygen.

[0148] The insulating layer 167 preferably functions as a barrier film. By providing a barrier film between the planarization layer and the transistor 200, it is possible to suppress the diffusion of impurities contained in the layer below the insulating layer 167 (for example, the insulating layer 231) into the transistor 200.

[0149] In this specification, the term "barrier film" refers to a film that possesses barrier properties. Barrier properties refer to one or both of the following functions: a function that makes it difficult for the target substance to diffuse, thereby suppressing the permeation of the substance through the film (also known as low permeability); and a function that captures or fixes the substance (also known as gettering).

[0150] The barrier film can be made from, for example, one or more oxides having aluminum and / or hafnium, an oxide having magnesium, an oxide having gallium, a nitride having silicon, an oxidized nitride having silicon, and an oxide nitride having silicon. Typically, the barrier film can be made from one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, zinc gallium oxide, silicon nitride, silicon oxidized nitride, and silicon nitride oxide.

[0151] The transistor 200 includes a conductive layer 203 on an insulating layer 167, an insulating layer 205 on the conductive layer 203, a semiconductor layer 208 on the insulating layer 205, an insulating layer 206 on the semiconductor layer 208, and a conductive layer 204 on the insulating layer 206. The conductive layer 204 has a region that overlaps with the semiconductor layer 208 via the insulating layer 206. In the transistor 200, the conductive layer 204 functions as a first gate electrode, and the insulating layer 206 functions as a first gate insulating layer. The conductive layer 203 has a region that overlaps with the conductive layer 204 via the insulating layer 205, the semiconductor layer 208, and the insulating layer 206. In the transistor 200, the conductive layer 203 functions as a second gate electrode, and the insulating layer 205 functions as a second gate insulating layer.

[0152] The semiconductor layer 208 has regions 208P and 208Q that do not overlap with the conductive layer 204. In the transistor 200, region 208P functions as one of the source region and drain region, and region 208Q functions as the other of the source region and drain region. In the semiconductor layer 208, the region located between the source region and drain region and overlapping with the conductive layer 204 via the insulating layer 206 functions as the channel formation region of the transistor 200.

[0153] An insulating layer 193 is provided on the conductive layer 204 and the insulating layer 206. The insulating layer 193 and the insulating layer 206 have an opening 247a that reaches region 208P and an opening 247b that reaches region 208Q. A conductive layer 212a is provided so as to cover the opening 247a, and a conductive layer 212b is provided so as to cover the opening 247b. The conductive layer 212a is in contact with region 208P at the opening 247a and is connected to region 208P. The conductive layer 212b is in contact with region 208Q at the opening 247b and is connected to region 208Q. In the transistor 200, the conductive layer 212a functions as one of the source electrode and drain electrode, and the conductive layer 212b functions as the other of the source electrode and drain electrode.

[0154] An insulating layer 233 is provided on the conductive layer 212a, the conductive layer 212b, and the insulating layer 193, and an insulating layer 169 is provided on the insulating layer 233. For details on the insulating layer 233 and the insulating layer 169, refer to the description relating to the insulating layer 231 and the insulating layer 167.

[0155] The transistor 300 includes a conductive layer 303 on an insulating layer 169, an insulating layer 305 on the conductive layer 303, a semiconductor layer 208 on the insulating layer 305, an insulating layer 306 on the semiconductor layer 308, and a conductive layer 304 on the insulating layer 306. The conductive layer 304 has a region that overlaps with the semiconductor layer 308 via the insulating layer 306. In the transistor 300, the conductive layer 304 functions as a first gate electrode, and the insulating layer 306 functions as a first gate insulating layer. The conductive layer 303 has a region that overlaps with the conductive layer 304 via the insulating layer 305, the semiconductor layer 308, and the insulating layer 306. In the transistor 300, the conductive layer 303 functions as a second gate electrode, and the insulating layer 305 functions as a second gate insulating layer.

[0156] The semiconductor layer 308 has regions 308P and 308Q that do not overlap with the conductive layer 304. In the transistor 300, region 308P functions as one of the source region and drain region, and region 308Q functions as the other of the source region and drain region. In the semiconductor layer 308, the region located between the source region and drain region and overlapping with the conductive layer 304 via the insulating layer 306 functions as the channel formation region of the transistor 300.

[0157] An insulating layer 195 is provided on the conductive layer 304 and the insulating layer 306. The insulating layer 195 and the insulating layer 306 have an opening 347a that reaches region 308P and an opening 347b that reaches region 308Q. A conductive layer 312a is provided so as to cover the opening 347a, and a conductive layer 312b is provided so as to cover the opening 347b. The conductive layer 312a is in contact with region 308P at the opening 347a and is connected to region 308P. The conductive layer 312b is in contact with region 308Q at the opening 347b and is connected to region 308Q. In the transistor 200, the conductive layer 312a functions as one of the source electrode and drain electrode, and the conductive layer 312b functions as the other of the source electrode and drain electrode.

[0158] Transistors 100, 200, and 300 are planar transistors, each with semiconductor layers arranged in a planar configuration. They are also so-called top-gate transistors, having a gate electrode above the semiconductor layer. Furthermore, by supplying impurities to the semiconductor layer 108 using the conductive layer 104, which functions as the gate electrode, as a mask, regions 108P and 108Q, which function as the source and drain regions, can be formed in a self-aligned manner. Similarly, regions 208P and 208Q can be formed in a self-aligned manner using the conductive layer 204 as a mask. Regions 308P and 308Q can be formed in a self-aligned manner using the conductive layer 304 as a mask. Transistors 100, 200, and 300 can each be described as TGSA (Top Gate Self-Aligned) type transistors.

[0159] TGSA-type transistors allow for a larger physical distance between the source and drain electrodes and the gate electrode, thereby reducing parasitic capacitance between them.

[0160] For semiconductor layers 108, 208, and 308, refer to the descriptions of the first, second, and third semiconductor layers mentioned above. For example, silicon can be used for semiconductor layer 108, and metal oxides can be used for semiconductor layers 208 and 308, respectively. It is preferable that the indium content of the metal oxide is high, and indium oxide can be suitably used for semiconductor layers 208 and 308. In the following, a configuration in which silicon (e.g., LTPS) is used for semiconductor layer 108 and metal oxides are used for semiconductor layers 208 and 308, respectively, may be used as an example in the explanation.

[0161] The semiconductor layers 108, 208, and 308 can each be a single layer or a multilayer structure of two or more layers. When a metal oxide is used for the semiconductor layer, it is preferable that the semiconductor layer has a multilayer structure. Figure 5A shows a configuration in which semiconductor layer 208 has a multilayer structure, and Figure 5B shows a configuration in which semiconductor layer 308 has a multilayer structure. Figure 5A shows a configuration in which semiconductor layer 208 has a three-layer structure consisting of semiconductor layer 208a, semiconductor layer 208b on semiconductor layer 208a, and semiconductor layer 208c on semiconductor layer 208b. Figure 5B shows a configuration in which semiconductor layer 308 has a three-layer structure consisting of semiconductor layer 308a, semiconductor layer 308b on semiconductor layer 308a, and semiconductor layer 308c on semiconductor layer 308b. Furthermore, an enlarged view of semiconductor layer 208 and its vicinity is shown in Figure 5C, and an enlarged view of semiconductor layer 308 and its vicinity is shown in Figure 5D.

[0162] The band gaps of the metal oxides in semiconductor layers 208a, 208b, 208c, 308a, 308b, and 308c are preferably 2.0 eV or greater, and more preferably 2.5 eV or greater.

[0163] The semiconductor layers 208a, 208b, and 208c can use the same material for all of them. This allows for the use of common equipment for depositing the semiconductor layers 208a, 208b, and 208c, thereby reducing the manufacturing cost of semiconductor devices. Alternatively, different materials can be used for at least one of the semiconductor layers 208a, 208b, and 208c. This broadens the range of materials that can be used for the semiconductor layers 208a, 208b, and 208c.

[0164] In this specification, "different materials" means materials in which some or all of the constituent elements are different, or materials in which the constituent elements are the same but the composition is different.

[0165] In some cases, the boundaries between semiconductor layer 208a and semiconductor layer 208b, and between semiconductor layer 208b and semiconductor layer 208c, cannot be clearly identified. Therefore, in Figure 5A and other figures, these boundaries are shown with dashed lines.

[0166] Preferably, the conductivity of semiconductor layer 208b is higher than that of either semiconductor layer 208a or semiconductor layer 208c. This ensures that the main current path in transistor 200 is semiconductor layer 208b. On the other hand, in semiconductor layer 208, it is preferable that semiconductor layer 208a, which is provided in contact with the second gate insulating layer, and semiconductor layer 208c, which is provided in contact with the first gate insulating layer, are denser and have fewer defects than semiconductor layer 208b.

[0167] Trap levels caused by impurities or defects may form at the interface between the insulating layer 206, which functions as the first gate insulating layer, and the semiconductor layer 208, and at the interface between the insulating layer 205, which functions as the second gate insulating layer, and the semiconductor layer 208, and at the interface at the interface at the interface at the interface. Furthermore, when the insulating layer 206 is deposited, damage may be inflicted on the interface between the insulating layer 206 and the semiconductor layer 208, causing trap levels to form at the interface between the insulating layer 206 and the semiconductor layer 208, and at the interface at the interface at the interface. By sandwiching the semiconductor layer 208b, which is the main current path, between semiconductor layers 208a and 208c, the semiconductor layer 208b can be moved away from the interface between the semiconductor layer 208 and the insulating layer, thereby reducing the trap levels at and near the interface of the semiconductor layer 208b. This makes it possible to create a transistor with high field-effect mobility.

[0168] Here, when a high potential is applied to the conductive layer 204, which functions as the first gate electrode, trap levels may be formed at and near the interface between the insulating layer 206 and the semiconductor layer 208. Similarly, when a high potential is applied to the conductive layer 203, which functions as the second gate electrode, trap levels may be formed at and near the interface between the insulating layer 205 and the semiconductor layer 208. If electrons are trapped in these trap levels, the threshold voltage of the transistor may shift to the positive side, potentially reducing reliability. By providing a semiconductor layer 208c with few defects in contact with the insulating layer 206, the formation of trap levels at and near the interface between the insulating layer 206 and the semiconductor layer 208 can be suppressed. Similarly, by providing a semiconductor layer 208a with few defects in contact with the insulating layer 205, the formation of trap levels at and near the interface between the insulating layer 205 and the semiconductor layer 208 can be suppressed. This makes it possible to create a highly reliable transistor.

[0169] In this way, by sandwiching the highly conductive semiconductor layer 208b between the less defective semiconductor layers 208a and 208c, a transistor can be made that achieves both high field-effect mobility and high reliability. Therefore, a semiconductor device can be made that achieves both high-speed operation and high reliability.

[0170] In the channel formation region, it is preferable that the carrier mobility of semiconductor layer 208b is higher than that of semiconductor layers 208a and 208c. Here, when a non-single-crystal (e.g., polycrystalline) metal oxide is used for the semiconductor layer, the carrier mobility can be increased by increasing the carrier concentration. It is preferable that the carrier concentration of semiconductor layer 208b is higher than that of semiconductor layers 208a and 208c. As a result, the conductivity of semiconductor layer 208b, which is the main current path, is increased, and a transistor with high field-effect mobility can be made.

[0171] It is preferable that semiconductor layers 208a, 208b, and 208c each contain an element that increases the carrier concentration (hereinafter also referred to as the first element). When metal oxides are used for semiconductor layers 208a, 208b, and 208c, for example, one or more of hydrogen, carbon, and nitrogen can be used as the first element. Hydrogen can be suitably used as the first element. Hydrogen reacts with oxygen bonded to the metal atoms of the metal oxide to form water, thereby creating oxygen vacancies (V) in the metal oxide. Ｏ ) is formed. Furthermore, oxygen deficiency (V Ｏ A defect (V) into which hydrogen has entered Ｏ H) functions as a donor, generating electrons, which are carriers, thereby increasing the carrier concentration in the metal oxide. Note that in the following explanation, hydrogen may be used as the first element.

[0172] In the channel formation region, it is preferable that semiconductor layer 208b has a region with a higher concentration of the first element compared to semiconductor layer 208a and semiconductor layer 208c. Typically, it is preferable that semiconductor layer 208b has a region with a higher hydrogen concentration compared to semiconductor layer 208a and semiconductor layer 208c. In the channel formation region, semiconductor layer 208b has a concentration of the first element (for example, hydrogen) of 1 × 10⁻¹⁶. １９ atoms / cm ３ The above 1 x 10 ２２ atoms / cm ３ Preferably, it has the following region, and more preferably 1 × 10 ２０ atoms / cm ３The above 1 x 10 ２２ atoms / cm ３ Preferably, it has the following region, and more preferably 5 × 10 ２０ atoms / cm ３ The above 1 x 10 ２２ atoms / cm ３ Preferably, it has the following region, and more preferably 5 × 10 ２０ atoms / cm ３ The above 5 x 10 ２１ atoms / cm ３ It is preferable to have the following regions. If the concentration of the first element in the semiconductor layer 208b is too low, the carrier concentration will be low, and there is a risk that the carrier mobility will be low. On the other hand, if the concentration of the first element in the semiconductor layer 208b is too high, the V of the channel formation region will be low. Ｏ An increase in the amount of H may cause a shift in the threshold voltage and a larger cutoff current. By setting the concentration of the first element in the semiconductor layer 208b within the aforementioned range, a transistor can be made that achieves both high field-effect mobility and a small cutoff current. Note that the concentration of the first element in the semiconductor layer 208 may have a gradient in the thickness direction of the semiconductor layer 208. It is preferable that the maximum value of the concentration of the first element in the semiconductor layer 208b is within the aforementioned range. Note that the concentration of the first element in the semiconductor layer 208b is not limited to the aforementioned range.

[0173] In the channel formation region, it is preferable that semiconductor layer 208a and semiconductor layer 208c each have regions where the concentration of the first element is lower than that of semiconductor layer 208b. In the channel formation region, it is preferable that semiconductor layer 208a and semiconductor layer 208c each have regions where the concentration of the first element (e.g., hydrogen) is 1 / 100 to 1 / 2 of the concentration of the first element in semiconductor layer 208b, more preferably 1 / 100 to 1 / 4, more preferably 1 / 100 to 1 / 6, more preferably 1 / 100 to 1 / 8, and more preferably 1 / 100 to 1 / 10. If the concentration of the first element in semiconductor layer 208a and semiconductor layer 208c is too high, the film density will be low, and there is a risk of many defects. On the other hand, if the concentration of the first element in semiconductor layer 208a and semiconductor layer 208c is too low, the carrier concentration will be low, resulting in low carrier mobility, which may lead to low field-effect mobility. By setting the concentration of the first element in semiconductor layer 208a and semiconductor layer 208c within the aforementioned range, a transistor can be made that achieves both high field-effect mobility and high reliability. As mentioned above, the concentration of the first element in semiconductor layer 208 may have a gradient in the thickness direction of semiconductor layer 208. It is preferable that the minimum value of the concentration of the first element in semiconductor layer 208a and the minimum value of the concentration of the first element in semiconductor layer 208c are within the aforementioned range. However, the concentration of the first element in semiconductor layer 208a and semiconductor layer 208c is not limited to the aforementioned range.

[0174] For analyzing the concentration of the first element in the semiconductor layer 208, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS or ESCA) can be used. For example, SIMS can be suitably used for analyzing the hydrogen concentration. However, the reliability of the measured values ​​may be low at the interface between the semiconductor layer 208 and the layer in contact with the semiconductor layer 208, and in its vicinity, due to the matrix effect. For example, when measuring in the direction from the insulating layer 206 towards the semiconductor layer 208, the reliability of the measured values ​​may be low at the interface between the insulating layer 206 and the semiconductor layer 208, and in its vicinity. Measured values ​​in unreliable regions should not be treated as the concentration of the first element in the semiconductor layer 208. Furthermore, the accuracy of the analysis of the concentration of the first element in the semiconductor layer 208 can sometimes be improved by combining measurements in the direction from the insulating layer 206 towards the semiconductor layer 208 with measurements in the direction from the insulating layer 205 towards the semiconductor layer 208.

[0175] In concentration analysis, the intensity of the constituent elements of the metal oxide can sometimes be used to estimate the location of the interface between the insulating layer 206 and the semiconductor layer 208, and the location of the interface between the insulating layer 205 and the semiconductor layer 208. For example, the semiconductor layer 208 can be defined as the range where the intensity of the constituent elements of the metal oxide present in the semiconductor layer 208 is 1 / 2 or more of its maximum value. When indium oxide is used for the semiconductor layer 208 and SIMS is used for the concentration analysis of the first element, the semiconductor layer 208 can be defined as the range where the secondary ion intensity of indium is 1 / 2 or more of its maximum value, and the layers other than the semiconductor layer 208 (e.g., insulating layer 205 and insulating layer 206) can be defined as the range where the secondary ion intensity of an indium-containing cluster (e.g., an indium-oxygen cluster) is 1 / 2 or more of its maximum value, and the layers other than the semiconductor layer 208 (e.g., insulating layer 205 and insulating layer 206) can be defined as the range where the secondary ion intensity of an indium-containing cluster (e.g., an indium-oxygen cluster) is 1 / 2 or more of its maximum value.

[0176] Preferably, the film density of semiconductor layer 208a and semiconductor layer 208c is higher than that of semiconductor layer 208b. This reduces defects in semiconductor layer 208a and semiconductor layer 208c. Furthermore, by providing a semiconductor layer 208c with a high film density on semiconductor layer 208b, damage to semiconductor layer 208b during the deposition of the insulating layer 206 can be suppressed. Film density can be evaluated using, for example, Rutherford backscattering spectrum (RBS) or X-ray reflectivity (XRR).

[0177] Differences in film density can sometimes be evaluated using a cross-sectional transmission electron microscope (TEM) image. In TEM observation, a high film density results in a darker (more intense) transmission electron (TE) image, while a low film density results in a lighter (brighter) transmission electron (TE) image. Therefore, even when the same material, such as indium oxide, is used for semiconductor layers 208a, 208b, and 208c, differences in film density among these layers can sometimes be observed as differences in contrast in cross-sectional TEM observations. Specifically, in the TE image, semiconductor layers 208a and 208c may have darker (more intense) regions compared to semiconductor layer 208b. Also, semiconductor layer 208b may have lighter (brighter) regions compared to semiconductor layers 208a and 208c.

[0178] Furthermore, the film densities of semiconductor layer 208a and semiconductor layer 208c can be configured to be the same as, or lower than, the film densities of semiconductor layer 208b.

[0179] Even when using the same material, the etching rate may be slower if the film is denser and has a higher film density. It is preferable that the etching rate in one etchant of semiconductor layer 208a and semiconductor layer 208c is slower than the etching rate of semiconductor layer 208b. It is also preferable to provide a semiconductor layer 208c with a slow etching rate on top of semiconductor layer 208b. This makes it possible to suppress the disappearance of semiconductor layer 208c in the etching process after the formation of semiconductor layer 208, and to suppress the thinning of the thickness of semiconductor layer 208.

[0180] In Figure 5C, the thicknesses T208a of semiconductor layer 208a, T208b of semiconductor layer 208b, and T208c of semiconductor layer 208c are indicated by arrows. Thicknesses T208a, T208b, and T208c are the thicknesses of each layer in the region of semiconductor layer 208 that overlaps with the conductive layer 204 in a cross-sectional view. Note that thicknesses T208a, T208b, and T208c can be controlled by the processing time (also referred to as deposition time) during the deposition of semiconductor layers 208a, 208b, and 208c, respectively.

[0181] The thickness T208b is preferably thicker than the thickness T208a, and preferably thicker than the thickness T208c. By increasing the thickness T208b of the semiconductor layer 208b, which is the main current path, a transistor with a large on-current can be made. However, if the thickness T208b is too thick, oxygen vacancies and V in the semiconductor layer 208b may occur. Ｏ An increase in the amount of H can cause a shift in the transistor's threshold voltage, potentially leading to a larger cutoff current. The thickness T208b is preferably 1 nm to 30 nm, more preferably 2 nm to 30 nm, more preferably 2 nm to 20 nm, more preferably 4 nm to 20 nm, and more preferably 4 nm to 10 nm. By setting the thickness T208b within the above range, a transistor with a large on-current can be made. Furthermore, by suppressing the shift in the threshold voltage, the cutoff current can be reduced, resulting in a normally-off transistor. Note that the thickness T208b is not limited to the above range.

[0182] It is preferable that thicknesses T208a and T208c are each thinner than thickness T208b. Furthermore, thicknesses T208a and T208c are preferably 0.5 nm to 10 nm, more preferably 0.5 nm to 6 nm, more preferably 0.5 nm to 4 nm, more preferably 0.5 nm to 3 nm, and more preferably 1 nm to 3 nm. If thickness T208c is too thick, the physical distance between the conductive layer 204, which functions as the first gate electrode, and the semiconductor layer 208b becomes longer, which may result in a decrease in field-effect mobility. On the other hand, if thickness T208c is too thin, the physical distance between the trap levels at the interface and near the interface of the insulating layer 206 and the semiconductor layer 208, and the semiconductor layer 208b, which is the main current path, becomes shorter, which may result in a decrease in field-effect mobility. In addition, reliability may decrease. The same applies to thickness T208a. By setting the thicknesses T208a and T208c within the aforementioned ranges, a transistor with high field-effect mobility and high reliability can be obtained. Note that the thicknesses T208a and T208c are not limited to the aforementioned ranges.

[0183] The thickness T208a and the thickness T208c can be the same or different. When the film quality and thickness T208a of semiconductor layer 208a are the same as those of semiconductor layer 208c, that is, when the first deposition conditions and deposition time are the same as those of the third deposition conditions and deposition time, the processing program (also called a recipe) used for deposition of semiconductor layer 208a and the recipe used for deposition of semiconductor layer 208c can be made common. This reduces the number of recipes to be managed in the manufacturing of semiconductor devices, thereby increasing productivity. Alternatively, the thickness T208c can be made thicker than the thickness T208a. When the insulating layer 206 is deposited, damage may occur at the interface between the insulating layer 206 and the semiconductor layer 208 and its vicinity. By increasing the thickness T208c, damage to the semiconductor layer 208b when the insulating layer 206 is deposited can be effectively suppressed. Furthermore, the relative sizes of thickness T208a and thickness T208c are not particularly limited; for example, thickness T208a can be greater than thickness T208c.

[0184] Furthermore, it may be difficult to clearly identify the boundary between semiconductor layer 208a and semiconductor layer 208b, and the boundary between semiconductor layer 208b and semiconductor layer 208c, making it difficult to measure the thicknesses T208a, T208b, and T208c.

[0185] In Figure 5D, the thicknesses T308a of semiconductor layer 308a, T308b of semiconductor layer 308b, and T308c of semiconductor layer 308c are indicated by arrows. Thicknesses T308a, T308b, and T308c are the thicknesses of each layer in the region of semiconductor layer 308 that overlaps with the conductive layer 204 in a cross-sectional view. For details on thicknesses T308a, T308b, and T308c, please refer to the description related to thicknesses T208a, T208b, and T208c.

[0186] The semiconductor layer 208 can be formed by depositing a metal oxide film and processing the metal oxide film into island shapes. It is preferable to perform a heat treatment to crystallize the metal oxide film after depositing it or after processing the metal oxide film into island shapes. By performing the heat treatment, the particle size of the crystal grains contained in the semiconductor layer 208 can be increased and the crystallinity of the semiconductor layer 208 can be improved. In addition, the heat treatment can reduce defects in the semiconductor layer 208. Furthermore, the heat treatment can remove impurities contained in the semiconductor layer 208 or adsorbed on its surface.

[0187] When the semiconductor layer 208 has a three-layer structure consisting of semiconductor layer 208a, semiconductor layer 208b, and semiconductor layer 208c, the metal oxide films are formed in the following order: a first metal oxide film to become semiconductor layer 208a, a second metal oxide film to become semiconductor layer 208b, and a third metal oxide film to become semiconductor layer 208c.

[0188] The first, second, and third metal oxide films are preferably deposited by sputtering using a metal target or a metal oxide target. Alternatively, the first, second, and third metal oxide films are preferably deposited by atomic layer deposition (ALD). The ALD method allows for easy control of the deposition rate, enabling the deposition of thin films with good yield. Therefore, the ALD method is particularly suitable when the metal oxide film is thin. Alternatively, chemical vapor deposition (CVD) can also be used.

[0189] Examples of power supplies used in sputtering apparatuses include DC (Direct Current) power supplies, RF (Radio Frequency) power supplies, and AC (Alternating Current) power supplies. A pulsed DC power supply that applies a pulsed voltage to the target can also be used. Furthermore, the magnetron sputtering method, which utilizes the magnetic field of a magnet, offers a high deposition rate, thus increasing productivity. The deposition of the first, second, and third metal oxide films can be suitably performed using sputtering methods, particularly magnetron sputtering. In the following, the magnetron sputtering method may be used as an example to describe the deposition methods for the first, second, and third metal oxide films.

[0190] When forming the first metal oxide film, the second metal oxide film, and the third metal oxide film, an inert gas (for example, helium gas, argon gas, xenon gas, etc.) can be used.

[0191] It is preferable to deposit a second metal oxide film in a vacuum after depositing a first metal oxide film, without exposing the surface of the first metal oxide film to the atmosphere. Similarly, it is preferable to deposit a third metal oxide film in a vacuum after depositing a second metal oxide film, without exposing the surface of the second metal oxide film to the atmosphere. By depositing the first, second, and third metal oxide films in succession, it is possible to suppress the adhesion of airborne impurities to the surfaces of the first and second metal oxide films. Examples of such impurities include water and organic matter.

[0192] When using the same material for two or more of the first, second, and third metal oxide films, the films can be deposited in the same processing chamber using the same sputtering target.

[0193] It is particularly preferable that semiconductor layers 208a, 208b, and 208c use the same material. The first metal oxide film, the second metal oxide film, and the third metal oxide film can be deposited continuously in the same processing chamber using the same sputtering target. This increases the productivity of semiconductor devices and reduces manufacturing costs. Furthermore, it is possible to suppress the adhesion of airborne impurities to the surfaces of the first metal oxide film and the second metal oxide film.

[0194] When using one or more different materials for semiconductor layer 208a, semiconductor layer 208b, and semiconductor layer 208c, that is, when using two or more sputtering targets, it is preferable to continuously deposit the metal oxide film in a vacuum within the same apparatus without exposing the surface of the metal oxide film to the atmosphere. For example, it is preferable to continuously deposit each metal oxide film in different processing chambers within the same apparatus in a vacuum.

[0195] As mentioned above, there are cases where the boundary between semiconductor layer 208a and semiconductor layer 208b, and the boundary between semiconductor layer 208b and semiconductor layer 208c, cannot be clearly identified. In particular, in configurations where the same material is used for semiconductor layer 208a, semiconductor layer 208b, and semiconductor layer 208c, these boundaries may not be clearly identified. Furthermore, by continuously depositing the first metal oxide film, the second metal oxide film, and the third metal oxide film in a vacuum, no interface may be formed between each metal oxide film, and these boundaries may not be identified. In such cases, semiconductor layer 208a, semiconductor layer 208b, and semiconductor layer 208c can be read as the first region, the second region, and the third region. Semiconductor layer 208 has a first region (corresponding to semiconductor layer 208a) on the insulating layer 205 side, a third region (corresponding to semiconductor layer 208c) on the insulating layer 206 side, and a second region (corresponding to semiconductor layer 208b) between the first region and the third region.

[0196] Preferably, the concentration of the first element in the second region is higher than the concentration of the first element in the first region and higher than the concentration of the first element in the third region. The concentration of the first element in the second region can be referenced from the description relating to the concentration of the first element in semiconductor layer 208b described above. The concentrations of the first element in the first region and the third region can be referenced from the descriptions relating to the concentrations of the first element in semiconductor layer 208a and semiconductor layer 208c described above, respectively. Note that the concentrations of the first element in the first region, the second region and the third region are not limited to the ranges described above.

[0197] Preferably, the film density of the first region and the third region is higher than the film density of the second region. When observing the cross-section of the semiconductor layer 208 using TEM, the first region and the third region may have denser (darker) areas in the TE image compared to the second region. Also, the second region may have thinner (brighter) areas compared to the first and third regions.

[0198] Here, by varying the deposition conditions for the metal oxide film, the film quality of the metal oxide film (later the semiconductor layer) can be varied. Examples of film quality include conductivity, band gap, defect amount, impurity concentration, and crystallinity. Examples of deposition conditions include power density, pressure, gas type, gas flow rate, substrate temperature, and the distance between the sputtering target and the substrate (also called T-S distance or TS distance). When varying the deposition conditions, one or more of the power density, pressure, gas type, gas flow rate, substrate temperature, and T-S distance can be varied. Note that changing the substrate temperature and T-S distance may take time. Therefore, when depositing two or more metal oxide films in the same processing chamber, it is preferable to keep the substrate temperature and T-S distance the same. Note that even when using the same material, the band gap may differ by varying the deposition conditions.

[0199] It is preferable that the deposition conditions for the first metal oxide film are different from those for the second metal oxide film. It is also preferable that the deposition conditions for the third metal oxide film are different from those for the second metal oxide film. For example, it is preferable that one or both of the power density and pressure in the deposition of the first metal oxide film are different from those in the deposition of the second metal oxide film. Similarly, it is preferable that one or both of the power density and pressure in the deposition of the second metal oxide film are different from those in the deposition of the second metal oxide film. It is particularly preferable that the power density and pressure in the deposition of the first metal oxide film are different from those in the deposition of the second metal oxide film, and that the power density and pressure in the deposition of the third metal oxide film are different from those in the deposition of the second metal oxide film.

[0200] Preferably, the power density during the deposition of the first and third metal oxide films is higher than the power density during the deposition of the second metal oxide film. By increasing the power density, dense and defect-free semiconductor layers 208a and 208c can be obtained. The power density during the deposition of the first and third metal oxide films is 0.3 W / cm². ２ More than 2W / cm ２ The following is preferable, and more preferably 0.4 W / cm². ２ More than 2W / cm ２ The following is preferable, and more preferably 0.5 W / cm². ２ More than 2W / cm ２ The following is preferable, and more preferably 0.6 W / cm². ２ More than 2W / cm ２ The following is preferable, and more preferably 0.6 W / cm². ２ 1W / cm or more ２The following is preferable. If the power density is too low, there is a risk of an increase in defects in the semiconductor layer 208a and semiconductor layer 208c, while if the power density is too high, there is a risk of an increased load on the device. By setting the power density during the deposition of the first metal oxide film and the third metal oxide film within the aforementioned range, it is possible to obtain dense semiconductor layers 208a and 208c with few defects, and to reduce the load on the device. Note that the power density during the deposition of the first metal oxide film and the third metal oxide film is not limited to the aforementioned range.

[0201] Power density is calculated by dividing the power applied to the substrate by the magnet area. The magnet area is the area of ​​the surface of the magnet that overlaps with the sputtering target.

[0202] The power density during the deposition of the second metal oxide film was 0.1 W / cm². ２ 1W / cm or more ２ The following is preferable, and more preferably 0.2 W / cm². ２ 1W / cm or more ２ The following is preferable, and more preferably 0.2 W / cm². ２ 0.8W / cm or more ２ The following is preferable, and more preferably 0.2 W / cm². ２ 0.6W / cm or more ２ The following is preferable, and more preferably 0.3 W / cm². ２ 0.6W / cm or more ２ The following is preferable. Furthermore, it is preferable that the power density during the deposition of the second metal oxide film is lower than the power density during the deposition of the first and third metal oxide films. If the power density is too high, the conductivity of the semiconductor layer 208b may decrease, while if the power density is too low, the deposition rate will be slow, which may reduce productivity. Also, if the power density is too low, the discharge may become unstable. By setting the power density during the deposition of the second metal oxide film within the above range, it is possible to obtain a semiconductor layer 208b with high conductivity and to increase productivity. Note that the power density during the deposition of the second metal oxide film is not limited to the above range.

[0203] The pressure used in the deposition of the first and third metal oxide films is preferably lower than the pressure used in the deposition of the second metal oxide film. Lowering the pressure allows for the formation of dense semiconductor layers 208a and 208c with fewer defects. The pressure used in the deposition of the first and third metal oxide films is preferably 0.1 Pa or more and 0.8 Pa or less, more preferably 0.1 Pa or more and 0.6 Pa or less, more preferably 0.1 Pa or more and 0.4 Pa or less, and more preferably 0.1 Pa or more and 0.3 Pa or less. If the pressure is too high, there is a risk of an increase in defects in semiconductor layers 208a and 208c, while if the pressure is too low, it may take a long time to adjust the pressure in the processing chamber, potentially reducing productivity. Furthermore, if the pressure is too low, arcing may occur, making it difficult to discharge normally. By setting the pressure during the deposition of the first and third metal oxide films within the aforementioned ranges, it is possible to obtain dense semiconductor layers 208a and 208c with few defects, and to increase productivity. However, the pressure during the deposition of the first and third metal oxide films is not limited to the aforementioned ranges.

[0204] The pressure used in the deposition of the second metal oxide film is preferably 0.2 Pa or more and 1 Pa or less, more preferably 0.3 Pa or more and 1 Pa or less, more preferably 0.4 Pa or more and 1 Pa or less, and more preferably 0.4 Pa or more and 0.8 Pa or less. Furthermore, the pressure used in the deposition of the second metal oxide film is preferably higher than the pressure used in the deposition of the first and third metal oxide films. If the pressure is too low, the conductivity of the semiconductor layer 208b may be low. On the other hand, if the pressure is too high, the deposition rate will be slow, which may reduce productivity. Also, if the pressure is too high, discharge may become difficult. By setting the pressure used in the deposition of the second metal oxide film within the above range, it is possible to obtain a semiconductor layer 208b with high conductivity and increase productivity. Note that the pressure used in the deposition of the second metal oxide film is not limited to the above range.

[0205] For semiconductor layers 308a, 308b, and 308c, refer to the descriptions relating to semiconductor layers 208a, 208b, and 208c.

[0206] Regions 108P, 108Q, 208P, 208Q, 308P, and 308Q each contain impurities. By supplying impurities to semiconductor layers 108, 208, and 308, the electrical resistance of regions 108P, 108Q, 208P, 208Q, 308P, and 308Q can be lowered. The impurity concentrations in regions 108P and 108Q are higher than the impurity concentrations in the channel-forming regions of semiconductor layer 108. The same applies to semiconductor layer 208, regions 208P, and 208Q, as well as semiconductor layer 308, regions 308P, and 308Q.

[0207] When silicon is used as the semiconductor layer and an n-channel type transistor is constructed, one or more elements of phosphorus and arsenic can be used as the impurity element (hereinafter also referred to as the second element). When silicon is used as the semiconductor layer and a p-channel type transistor is constructed, one or more elements of boron, aluminum, and gallium can be used as the second element.

[0208] When a metal oxide is used in the semiconductor layer, one or more of the following can be used as the second element: hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, and noble gases. Representative examples of noble gases include helium, neon, argon, krypton, and xenon. It is particularly preferable to use one or more of the following as the second element: hydrogen, boron, phosphorus, aluminum, magnesium, and silicon.

[0209] When a metal oxide is used in the semiconductor layer 208 and an element that readily bonds with oxygen is used as the second element, the second element removes oxygen from the semiconductor layer 208 and exists in a state bonded with oxygen. In addition, oxygen vacancies (V) exist in the semiconductor layer 208. Ｏ). When an element that becomes stable by binding to oxygen is used as the second element, the second element in the semiconductor layer 208 exists stably in an oxidized state. Therefore, it is difficult to desorb due to heat applied during the manufacturing process of the semiconductor device, and the electrical resistance of the regions 208P and 208Q supplied with the second element can be kept low. From this, it is preferable to use, as the second element, an element whose oxide can exist as a solid at least at the temperature during the manufacturing process. As the second element, one or both of boron and phosphorus can be preferably used.

[0210] When boron is used as the second element, the boron contained in the regions 208P and 208Q can exist in a state of being combined with oxygen. This can be confirmed by observing a spectral peak caused by the B ２ O ３ bond in XPS analysis. Also, in XPS analysis, a spectral peak caused by the state in which boron element exists alone may not be observed, or the spectral peak intensity may be extremely small to the extent of the background.

[0211] Hydrogen causes oxygen vacancies (V Ｏ ) to occur upon its supply, and V Ｏ H occurs by entering the oxygen vacancy (V Ｏ ). Therefore, the electrical resistance of the regions 208P and 208Q can be efficiently lowered. Thus, hydrogen can be preferably used as the second element.

[0212] In the supply of impurities, it is preferable to adjust the supply conditions so that the concentration of impurities is highest on the surface of the semiconductor layer 208 or in a region close to the surface.

[0213] Here, a configuration using a metal oxide for the semiconductor layer 208 has been described as an example, but the same applies when a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 308. [[ID=​For the supply of impurities, the ion implantation method can be preferably used. The ion implantation method can control the concentration profile in the depth direction with high precision according to the acceleration energy and dose amount of ions. Also, by using an ion implantation method in which a source gas is ionized and the ions are mass-separated and supplied, ions of a specific mass can be supplied, and the purity of the supplied impurities can be increased. Alternatively, by using an ion implantation method in which ions are supplied without mass separation, productivity can be increased. In this specification and the like, unless otherwise specified, the presence or absence of mass separation is not limited. Note that, in some cases, the method of mass-separating and supplying ions is called the ion implantation method, and the method of supplying ions without mass separation is called the ion doping method.

[0215] As the raw material used for the supply of impurities, for example, a gas containing a second element can be used. When supplying boron, typically, B ２ H ６ gas, or one or more of BF ３ gases can be used. Also, when supplying phosphorus, typically, PH ３ gas can be used. Further, a gas obtained by diluting these raw material gases with a noble gas can also be used.

[0216] As the raw material used for the supply of impurities, for example, CH ４ 、N ２ 、NH ３ 、AlH ３ 、AlCl ３ 、SiH ４ 、Si ２ H ６ 、F ２ 、HF、H ２ 、(C ５ H ５ ) ２ Mg, and noble gases can be used. Note that the raw material is not limited to a gas, and a solid or a liquid can also be heated and vaporized for use.

[0217] The supply of impurities can be controlled by setting conditions such as acceleration voltage and dose amount, taking into consideration the composition, density, and thickness of the insulating layer 106 and the semiconductor layer 108. When supplying impurities to the semiconductor layer 108 (regions 108P and 108Q) via the insulating layer 106 using the conductive layer 104 as a mask, impurities may be supplied to regions of the insulating layer 106 that do not overlap with the conductive layer 104, resulting in those regions containing impurities. Similarly, impurities may be supplied to regions of the insulating layer 105 that do not overlap with the conductive layer 104, resulting in those regions containing impurities.

[0218] The method of supplying impurities is not limited to this; for example, plasma treatment or treatment utilizing thermal diffusion by heating can also be used. In the case of plasma treatment, impurities can be supplied by generating plasma in a gas atmosphere containing the impurities to be supplied and performing plasma treatment. As the apparatus for generating the plasma, dry etching apparatus, ashing apparatus, plasma CVD apparatus, high-density plasma CVD apparatus, etc., can be used.

[0219] Detailed explanations of regions 208P and 208Q, and regions 308P and 308Q are omitted as they can be described in relation to regions 108P and 108Q. The second element in regions 108P and 108Q, the second element in regions 208P and 208Q, and the second element in regions 308P and 308Q can have the same configuration. This allows for the common use of equipment for supplying the second element, thereby reducing the manufacturing cost of semiconductor devices. Alternatively, some or all of the second elements in regions 108P and 108Q, the second element in regions 208P and 208Q, and the second element in regions 308P and 308Q can have different configurations. The appropriate second element can be selected depending on the materials used for semiconductor layer 108, semiconductor layer 208, and semiconductor layer 308. This expands the range of choices for the second element supplied to semiconductor layer 108, the second element supplied to semiconductor layer 208, and the second element supplied to semiconductor layer 308.

[0220] Here, a configuration is shown in which transistors 100, 200, and 300 are each TGSA transistors, but the present invention is not limited to this. The structure of the transistors in the semiconductor device is not particularly limited.

[0221] The materials that can be used for each component will be explained.

[0222] [Conductive layer 104, conductive layer 204, conductive layer 304, conductive layer 103, conductive layer 203, conductive layer 303, conductive layer 112a, conductive layer 112b, conductive layer 212a, conductive layer 212b, conductive layer 312a, conductive layer 312b] Conductive layer 104, conductive layer 204, conductive layer 304, conductive layer 103, conductive layer 203, conductive layer 303, conductive layer 112a, conductive layer 112b, conductive layer 212a, conductive layer 212b, conductive layer 312a and conductive layer 312b can each be a single layer or a laminated structure of two or more layers. Materials that can be used for these conductive layers include, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, as well as alloys composed of one or more of the aforementioned metals. These conductive layers can preferably be made of conductive materials with low electrical resistivity, each containing one or more of copper, silver, gold, and aluminum. Copper or aluminum are particularly preferred due to their excellent mass productivity.

[0223] Conductive layers 104, 204, 304, 103, 203, 303, 112a, 112b, 212a, 212b, 312a, and 312b can each be made of a conductive metal oxide (also called an oxide conductor (OC)). Examples of oxide conductors include indium oxide, zinc oxide, ITO, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, ITSO, zinc oxide with added gallium, and In-Ga-Zn oxide. Oxide conductors containing indium are particularly preferred due to their high conductivity.

[0224] When oxygen vacancies are formed in a metal oxide with semiconductor properties, and hydrogen is added to these vacancies, donor levels are formed near the conduction band. As a result, the metal oxide becomes highly conductive and turns into a conductor. A metal oxide that has become conductive can be called an oxide conductor.

[0225] Conductive layers 104, 204, 304, 103, 203, 303, 112a, 112b, 212a, 212b, 312a, and 312b can each be a laminated structure of a conductive film containing the aforementioned oxide conductor (a conductive metal oxide) and a conductive film containing a metal or alloy. By using a conductive film containing a metal or alloy, the wiring resistance can be reduced.

[0226] Conductive layers 104, 204, 304, 103, 203, 303, 112a, 112b, 212a, 212b, 312a, and 312b can each be made of nitride conductors. Examples of nitride conductors include tantalum nitride and titanium nitride.

[0227] Conductive layers 104, 204, 304, 103, 203, 303, 112a, 112b, 212a, 212b, 312a, and 312b can each be fitted with a Cu-X alloy film (where X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti). By using a Cu-X alloy film, processing can be done by wet etching, thus reducing manufacturing costs.

[0228] Note that conductive layers 104, 204, 304, 103, 203, 303, 112a, 112b, 212a, 212b, 312a, and 312b may be made of the same material. Alternatively, at least one of them may be made of a different material.

[0229] [Insulating layer 106, insulating layer 206, insulating layer 306, insulating layer 105, insulating layer 205, insulating layer 305] Insulating layer 106, insulating layer 206, insulating layer 306, insulating layer 105, insulating layer 205, and insulating layer 305 can each be a single layer or a laminated structure of two or more layers. It is preferable that insulating layer 106, insulating layer 206, insulating layer 306, insulating layer 105, insulating layer 205, and insulating layer 305 each have one or more inorganic insulating layers. For materials that can be used for the inorganic insulating layer, refer to the above description.

[0230] The insulating layers 106, 206, 306, 105, 205, and 305, which function as gate insulating layers, each have a region in contact with the semiconductor layer. When silicon or a metal oxide is used for the semiconductor layer, it is preferable that at least a portion of the region of the gate insulating layer in contact with the semiconductor layer contains oxygen in order to improve the interfacial characteristics between the semiconductor layer and the gate insulating layer. Specifically, it is preferable that the region of the gate insulating layer in contact with the channel-forming region contains oxygen. One or more oxides and oxiditrides can be suitably used in the region of the gate insulating layer in contact with the channel-forming region. For example, it is preferable that each gate insulating layer contains silicon and oxygen. It is preferable that each gate insulating layer contains silicon oxide or silicon oxiditride.

[0231] In the case of miniature transistors, if the thickness of the gate insulating layer is reduced, the leakage current may increase. By using a material with a high dielectric constant (also called a high-k material) for the gate insulating layer, it is possible to reduce the voltage during transistor operation while maintaining the physical film thickness. Examples of high-k materials that can be used for the gate insulating layer include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxides containing aluminum and hafnium, oxides containing silicon and hafnium, oxides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0232] Although the gate insulating layer is shown as a single-layer structure in Figure 3A, etc., one aspect of the present invention is not limited thereto. The gate insulating layer can be a laminated structure of two or more layers. When the gate insulating layer is a laminated structure, it is preferable that the insulating layer on the semiconductor layer side has an oxide or oxidizride. The insulating layer on the semiconductor layer side can preferably be one or more of silicon oxide, silicon oxidizride, or aluminum oxide.

[0233] It is preferable to provide a barrier film on one or more of the layers constituting the gate insulating layer. By providing a barrier film, the diffusion of metal components contained in the gate electrode into the semiconductor layer via the gate insulating layer can be suppressed. Furthermore, when a metal oxide is used in the semiconductor layer, the diffusion of oxygen contained in the semiconductor layer to the gate electrode side via the gate insulating layer can be suppressed. This prevents oxygen vacancies (V) in the semiconductor layer. Ｏ This suppresses the formation of (a specific type of ion). Furthermore, it suppresses oxidation of the gate electrode by oxygen in the semiconductor layer, which increases the electrical resistance of the gate electrode. As a result, a transistor with good electrical characteristics and high reliability can be achieved.

[0234] The first gate insulating layer can be, for example, a laminated structure of a silicon oxide nitride film and a silicon nitride film on the silicon oxide nitride film. Alternatively, the first gate insulating layer can be a laminated structure of a silicon oxide nitride film and an aluminum oxide film on the silicon oxide nitride film. Alternatively, the first gate insulating layer can be a laminated structure of an aluminum oxide film and a silicon oxide nitride film on the aluminum oxide film. Alternatively, the first gate insulating layer can be a laminated structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film.

[0235] The second gate insulating layer can be, for example, a laminated structure of a silicon nitride film and a silicon oxynitride film on the silicon nitride film. Alternatively, the second gate insulating layer can be a laminated structure of an aluminum oxide film and a silicon oxynitride film on the aluminum oxide film. Alternatively, the second gate insulating layer can be a laminated structure of a silicon oxynitride film and an aluminum oxide film on the silicon oxynitride film. Alternatively, the second gate insulating layer can be a laminated structure of a silicon nitride film and an aluminum oxide film on the silicon nitride film.

[0236] Here, an example is shown in which the gate insulating layer has a two-layer laminated structure, but the present invention is not limited to this. The gate insulating layer can also have a three-layer or more laminated structure.

[0237] [Insulating layer 191, insulating layer 193, insulating layer 195] Insulating layer 191, insulating layer 193, and insulating layer 195 can each be a single layer or a laminated structure of two or more layers. Insulating layer 191, insulating layer 193, and insulating layer 195 can each be an inorganic insulating layer, an organic insulating layer, or both. For materials that can be used for the inorganic insulating layer and the organic insulating layer, please refer to the above description. It is preferable that insulating layer 191, insulating layer 193, and insulating layer 195 each have one or more inorganic insulating layers.

[0238] A barrier film can also be used on one or more of the insulating layers 191, 193, and 195. By providing a barrier film, the diffusion of impurities (e.g., water and hydrogen) into the transistor from the outside can be effectively suppressed, thereby improving the reliability of the semiconductor device. For details on the barrier film, please refer to the above description. For the insulating layer 195, one or more of silicon nitride, silicon oxide nitride, and silicon oxynitride can be suitably used.

[0239] When silicon is used for the semiconductor layer 108, it is preferable that the insulating layer 191 has a layer that releases hydrogen when heat is applied. The insulating layer 191 can preferably be, for example, silicon oxide nitride containing hydrogen, silicon nitride oxide containing hydrogen, or silicon nitride containing hydrogen. Furthermore, it is preferable that the insulating layer 191 contains a high amount of hydrogen. It is even more preferable to perform a heat treatment in a hydrogen-containing atmosphere after forming the insulating layer 191. This supplies hydrogen from the insulating layer 191 to the semiconductor layer 108, and the dangling bonds in the semiconductor layer 108 are terminated by hydrogen (hereinafter also referred to as hydrogenation or hydrogen termination). Therefore, the amount of dangling bonds in the semiconductor layer 108 can be reduced.

[0240] Furthermore, if a high temperature is applied after hydrogen termination, hydrogen in the semiconductor layer 108 may be desorbed, potentially increasing the number of dangling bonds in the semiconductor layer 108. However, compared to Si transistors, OS transistors can be manufactured at lower process temperatures (typically below 350°C). Therefore, if transistor 100 is a Si transistor, by making transistors 200 and 300, which are formed after transistor 100, OS transistors, the temperature applied to the semiconductor layer 108 during the manufacturing process of transistors 200 and 300 can be reduced, thereby suppressing the increase of dangling bonds in the semiconductor layer 108.

[0241] When an organic insulating layer is used as the insulating layer 231, it is preferable that the process temperature after forming the insulating layer 231 is lower than the heat resistance temperature of the organic insulating layer. Therefore, OS transistors with a low process temperature can be suitably used for transistors 200 and 300.

[0242] Here, if a hydrogen-releasing material is used for the insulating layer 191, and the amount of hydrogen released from the insulating layer 191 is too large, the amount of hydrogen diffusing into the channel-forming regions of the semiconductor layer 208 and semiconductor layer 308 may increase. When metal oxides are used for the semiconductor layer 208 and semiconductor layer 308, oxygen vacancies (V) in the semiconductor layer 208 and semiconductor layer 308 may occur. Ｏ ) and V ＯThere is a risk that the amount of H will increase. Therefore, when silicon is used for semiconductor layer 108 and metal oxides are used for semiconductor layers 208 and 308, it is preferable to provide a barrier layer on the insulating layer 191. For example, it is preferable to provide an insulating layer 167 that functions as a barrier layer on the insulating layer 191. By providing an insulating layer 167 on the insulating layer 191, it is possible to suppress the diffusion of hydrogen contained in the insulating layer 191 into the channel formation regions of semiconductor layers 208 and 308 via the insulating layer 231 and insulating layer 167. This makes it possible to obtain transistors 100, 200 and 300 with good electrical characteristics. Furthermore, by providing a barrier layer on the insulating layer 205, it is possible to suppress the diffusion of hydrogen into the channel formation regions of semiconductor layers 208 and 308.

[0243] [Substrate 102] There are no major restrictions on the material of the substrate 102, but it must have at least enough heat resistance to withstand subsequent heat treatment. For example, single-crystal semiconductor substrates made of silicon or silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates, glass substrates, quartz substrates, sapphire substrates, ceramic substrates, or resin substrates can be used as the substrate 102. In addition, a substrate on which a semiconductor element is provided can be used as the substrate 102. A substrate with an insulating film formed on its surface can be used as the substrate 102. The shape of the substrate 102 is not particularly limited and can be circular or rectangular, for example.

[0244] It is preferable to use a material for the substrate 102 that has high transmittance to visible light (also described as having light-transmitting properties). By using a material with high light-transmitting properties as the substrate 102, the efficiency of light extraction can be increased. It is preferable that the substrate 102 has a transmittance of 70% or more for visible light (wavelength 400 nm to 750 nm), more preferably 80% or more, and more preferably 85% or more. For example, a glass substrate can be suitably used as the substrate 102.

[0245] A flexible substrate can be used as the substrate 102, and transistors 100, etc., can be formed directly on the flexible substrate. Alternatively, a release layer can be provided between the substrate 102 and the transistors 100, etc. By providing a release layer, after partially or completely completing the semiconductor device on it, it can be separated from the substrate 102 and transferred to another substrate. In this case, the transistors 100, etc., can also be transferred to a substrate with low heat resistance or a flexible substrate.

[0246] The following describes a configuration example of a semiconductor device that differs in some aspects from the aforementioned configuration example 1-1. Note that in the following, explanations of parts that overlap with configuration example 1-1 may be omitted. Furthermore, in the drawings shown below, parts having the same function as those in configuration example 1-1 may use the same hatching pattern and may not be labeled with reference numerals.

[0247] [Semiconductor Device Configuration Example 1-2] Figures 6 to 7B show cross-sectional views of a semiconductor device 80A, which is one embodiment of the present invention. The semiconductor device 80A includes a transistor 100, a transistor 200, and a transistor 300.

[0248] Figure 8A shows a top view of semiconductor device 80A. To avoid making the diagram too complex, Figure 8A shows only an excerpt of the top view of transistor 300. Figures 8B show top views of transistors 100 and 200. Figure 6 is a cross-sectional view of the section along the dashed-dotted line A1-A2 shown in Figures 8A and 8B, Figure 7A is a cross-sectional view of the section along the dashed-dotted line B1-B2, and Figure 7B is a cross-sectional view of the section along the dashed-dotted lines B3-B4 and B5-B6.

[0249] The semiconductor device 80A differs from the semiconductor device 80 shown in Figure 3A, etc., in that the conductive layer 203 has a region in contact with the insulating layer 106, and that it does not have insulating layers 191, 231, and 167.

[0250] A conductive layer 103 is provided on the substrate 102, an insulating layer 105 is provided on the conductive layer 103, a semiconductor layer 108 is provided on the insulating layer 105, an insulating layer 106 is provided on the semiconductor layer 108, and a conductive layer 104 and a conductive layer 203 are provided on the insulating layer 106.

[0251] The conductive layer 104 and the conductive layer 203 each have a region that contacts the upper surface of the insulating layer 106. The conductive layer 104 and the conductive layer 203 can be formed using the same material and the same process. This simplifies the process and keeps manufacturing costs low. Alternatively, the conductive layer 104 and the conductive layer 203 can be formed using different processes. This allows for the use of different materials for the conductive layer 104 and the conductive layer 203, broadening the range of materials that can be used for the conductive layer 104 and the conductive layer 203.

[0252] An insulating layer 205 is provided on the insulating layer 106, conductive layer 104, and conductive layer 203, a semiconductor layer 208 is provided on the insulating layer 205, an insulating layer 206 is provided on the semiconductor layer 208, and a conductive layer 204 is provided on the insulating layer 206. An insulating layer 193 is provided on the insulating layer 206 and conductive layer 204.

[0253] Insulating layer 193, insulating layer 206, insulating layer 205, and insulating layer 106 have an opening 147a reaching region 108P and an opening 147b reaching region 108Q. A conductive layer 112a is provided to cover the opening 147a, and a conductive layer 112b is provided to cover the opening 147b. Insulating layer 193 and insulating layer 206 have an opening 247a reaching region 208P and an opening 247b reaching region 208Q. A conductive layer 212a is provided to cover the opening 247a, and a conductive layer 212b is provided to cover the opening 247b.

[0254] Conductive layers 112a, 112b, 212a, and 212b can be formed using the same material and the same process. This simplifies the process and keeps manufacturing costs low. However, some parts of conductive layers 112a, 112b, 212a, and 212b can be formed using different processes. This allows for the use of different materials for these conductive layers, broadening the range of material choices.

[0255] Transistor 100 and transistor 200 can be formed by sharing some manufacturing processes. This increases the productivity of semiconductor devices and lowers manufacturing costs.

[0256] An insulating layer 233 is provided on conductive layers 112a, 112b, 212a, 212b, and insulating layer 193, an insulating layer 169 is provided on insulating layer 233, and a transistor 300 is provided on insulating layer 169. Refer to the above description for details on insulating layer 233, insulating layer 169, and transistor 300.

[0257] Figure 9 shows a configuration in which the insulating layer 205 has a laminated structure. Figure 9 shows a configuration in which the insulating layer 205 has a three-layer structure consisting of insulating layer 205a, insulating layer 205b on insulating layer 205a, and insulating layer 205c on insulating layer 205b.

[0258] When silicon is used for the semiconductor layer 108, it is preferable that the insulating layer 205a provided on the transistor 100 side releases hydrogen when heat is applied. The insulating layer 205a can preferably be, for example, silicon oxynitride containing hydrogen, silicon nitride oxide containing hydrogen, or silicon nitride containing hydrogen. For details regarding the insulating layer 205a, please refer to the description relating to the insulating layer 191.

[0259] When a hydrogen-releasing material is used for the insulating layer 205a and metal oxides are used for the semiconductor layer 208 and semiconductor layer 308, it is preferable that the insulating layer 205b provided on the insulating layer 205a functions as a barrier layer. For example, silicon nitride can be suitably used for the insulating layer 205b. For details regarding the insulating layer 205b, refer to the description relating to the insulating layer 167. For the insulating layer 205c having a region in contact with the semiconductor layer 208, one or more oxides and oxiditrides can be suitably used. For example, silicon oxide or silicon oxiditride can be suitably used for the insulating layer 205c.

[0260] Here, a configuration in which the insulating layer 205 has a three-layer structure is shown, but the present invention is not limited to this. The insulating layer 205 can also have a two-layer or four-layer or more laminated structure.

[0261] [Semiconductor Device Configuration Example 1-3] Figure 10A shows a cross-sectional view of a semiconductor device 80B, which is one embodiment of the present invention. The semiconductor device 80B includes transistor 100A, transistor 200A, and transistor 300A. Top views of transistors 100A, 200A, and 300A can be found in Figures 8A and 8B. Figure 10A is a cross-sectional view of the section along the dashed line A1-A2 shown in Figures 8A and 8B.

[0262] Transistor 100A differs from transistor 100 shown in Figure 6, etc., in that the edge of the insulating layer 106 coincides with or approximately coincides with the edge of the conductive layer 104. Transistor 200A differs from transistor 200 in that the edge of the insulating layer 206 coincides with or approximately coincides with the edge of the conductive layer 204. Transistor 300A differs from transistor 300 in that the edge of the insulating layer 306 coincides with or approximately coincides with the edge of the conductive layer 304.

[0263] The edges of the insulating layer 106 are in contact with the upper surface of the semiconductor layer 108. The edges of the insulating layer 106 overlap with the semiconductor layer 108, or are located on the semiconductor layer 108. Furthermore, the insulating layer 106 does not overlap with either region 108P or region 108Q. The upper surface shape of the insulating layer 106 is said to be consistent with, or roughly consistent with, the conductive layer 104. The insulating layer 106 can be formed, for example, by processing using a resist mask for processing the conductive layer 104. For details regarding the insulating layers 206 and 306, please refer to the description relating to the insulating layer 106.

[0264] The insulating layer 205 has regions that are in contact with the upper and side surfaces of the semiconductor layer 108, the side surfaces of the insulating layer 106, the upper and side surfaces of the conductive layer 104, and the upper surface of the insulating layer 105. The insulating layer 205 has regions that are in contact with region 108P and region 108Q.

[0265] The insulating layer 193 has regions that are in contact with the upper and side surfaces of the semiconductor layer 208, the side surfaces of the insulating layer 206, the upper and side surfaces of the conductive layer 204, and the upper surface of the insulating layer 205. The insulating layer 193 also has regions that are in contact with region 208P and region 208Q.

[0266] The insulating layer 195 has regions that are in contact with the upper and side surfaces of the semiconductor layer 308, the side surfaces of the insulating layer 306, the upper and side surfaces of the conductive layer 304, and the upper surface of the insulating layer 305. The insulating layer 195 also has regions that are in contact with region 308P and region 308Q.

[0267] For the supply of impurities to regions 108P, 108Q, 208P, 208Q, 308P, and 308Q, please refer to the above description. For example, after forming the conductive layer 204, plasma processing can be performed using a plasma CVD apparatus in an atmosphere containing a gas containing a second element (e.g., hydrogen) to supply the second element as an impurity to regions of the semiconductor layer 208 that do not overlap with the conductive layer 204, thereby forming regions 208P and 208Q. Furthermore, by using a plasma CVD apparatus for supplying impurities and forming the insulating layer 193, the supply of impurities and the formation of the insulating layer 193 can be performed continuously within the plasma CVD apparatus, thereby increasing productivity.

[0268] [Semiconductor Device Configuration Example 1-4] Figure 10B shows a cross-sectional view of a semiconductor device 80C, which is one embodiment of the present invention. The semiconductor device 80C includes transistor 100B, transistor 200B, and transistor 300B. Top views of transistors 100B, 200B, and 300B can be found in Figures 8A and 8B. Figure 10B is a cross-sectional view of the section along the dashed line A1-A2 shown in Figures 8A and 8B.

[0269] Transistor 100B differs from transistor 100A shown in Figure 10A mainly in that the insulating layer 106 has a region that protrudes from the edge of the conductive layer 104. Transistor 200B differs from transistor 200A mainly in that the insulating layer 206 has a region that protrudes from the edge of the conductive layer 204. Transistor 300B differs from transistor 300A mainly in that the insulating layer 306 has a region that protrudes from the edge of the conductive layer 304.

[0270] The edges of the insulating layer 106 are located on the semiconductor layer 108, and the edges of the conductive layer 104 are located on the insulating layer 106. It can also be said that the edges of the insulating layer 106 are located outside the edges of the conductive layer 104. The insulating layer 106 has a region that overlaps with the conductive layer 104 and a region that does not overlap with the conductive layer 104 on the semiconductor layer 108.

[0271] The semiconductor layer 108 has a channel formation region, regions 108R and 108S that sandwich the channel formation region, and regions 108P and 108Q located outside of them. Regions 108R and 108S are regions of the semiconductor layer 108 that overlap with the insulating layer 106 and do not overlap with the conductive layer 104. Region 108R is located between the channel formation region and region 108P, and region 108S is located between the channel formation region and region 108Q.

[0272] Regions 108R and 108S function as buffer regions to mitigate the drain electric field. Since regions 108R and 108S do not overlap with the conductive layer 104, channels are hardly formed in these regions even when a gate voltage is applied to the conductive layer 104. It is preferable that the carrier concentration in regions 108R and 108S is higher than that in the channel formation region. This allows regions 108R and 108S to function as LDD (Lightly Doped Drain) regions.

[0273] Regions 108R and 108S can also be described as regions with similar or lower electrical resistance, similar or higher carrier concentration, similar or higher oxygen defect density, and similar or higher impurity concentration compared to the channel-forming region.

[0274] Regions 108R and 108S can also be described as regions with similar or higher electrical resistance, similar or lower carrier concentration, similar or lower oxygen defect density, and similar or lower impurity concentration, compared to regions 108P and 108Q.

[0275] By providing region 108R between the channel formation region and region 108P, the physical distance between the channel formation region and region 108P can be increased. Similarly, by providing region 108S, the physical distance between the channel formation region and region 108Q can be increased. This suppresses the diffusion of impurities contained in regions 108P and 108Q into the channel formation region. Therefore, it is possible to suppress the deterioration of the transistor's electrical characteristics and reliability.

[0276] For regions 208R and 208S, and regions 308R and 308S, refer to the descriptions relating to regions 108R and 108S.

[0277] The semiconductor device can be used in combination with multiple types of transistors 100 to 100B, 200 to 200B, and 300 to 300B as described above.

[0278] The semiconductor device 80D shown in Figure 11 includes transistors 100, 200, and 300A. Ion implantation is suitably used for supplying impurities to semiconductor layer 108 and semiconductor layer 208, respectively. This allows for the use of common equipment for supplying impurities to semiconductor layer 108 and semiconductor layer 208, thereby reducing the manufacturing cost of the semiconductor device. Furthermore, after forming the conductive layer 304, impurities can be supplied to semiconductor layer 308 using a plasma CVD apparatus, and then the insulating layer 195 can be continuously deposited within the plasma CVD apparatus. This increases the productivity of the semiconductor device.

[0279] <Example of semiconductor device configuration 2> Figures 12 to 13B show cross-sectional views of a semiconductor device 90, which is one aspect of the present invention. The semiconductor device 90 includes a transistor 100, a transistor 220, a transistor 320, an insulating layer 210, and an insulating layer 310.

[0280] Figure 14A shows a top view of the semiconductor device 90. To avoid making the diagram too complex, Figure 14A shows only an excerpt of the top view of transistor 320. Figures 14B show top views of transistors 100 and 220. Figure 12 is a cross-sectional view of the section along the dashed-dotted line A1-A2 shown in Figures 14A and 14B, Figure 13A is a cross-sectional view of the section along the dashed-dotted line B1-B2, and Figure 13B is a cross-sectional view of the section along the dashed-dotted lines B3-B4 and B5-B6.

[0281] An insulating layer 191 is provided on transistor 100, and transistor 220 is provided on insulating layer 191. An insulating layer 198 is provided on transistor 220, an insulating layer 233 is provided on insulating layer 198, and an insulating layer 169 is provided on insulating layer 233. Transistor 320 is provided on insulating layer 169. For details on transistor 100, please refer to the above description.

[0282] The transistor 220 has a conductive layer 224, an insulating layer 226, a semiconductor layer 228, a conductive layer 222a, and a conductive layer 222b. In the transistor 220, the conductive layer 224 functions as a gate electrode, and the insulating layer 226 functions as a gate insulating layer. The conductive layer 222a functions as one of the source electrode and the drain electrode, and the conductive layer 222b functions as the other. Of the semiconductor layer 228, the region between the source electrode and the drain electrode that overlaps with the gate electrode via the gate insulating layer functions as a channel-forming region. Also, of the semiconductor layer 228, the region in contact with the source electrode functions as a source region, and the region in contact with the drain electrode functions as a drain region. In the semiconductor layer 228, the channel-forming region is located between the source region and the drain region.

[0283] A conductive layer 222a is provided on an insulating layer 191, an insulating layer 210 is provided on the conductive layer 222a, and a conductive layer 222b is provided on the insulating layer 210. The insulating layer 210 has a region that is in contact with and sandwiched between the conductive layers 222a and 222b. The conductive layer 222a has a region that overlaps with the conductive layer 222b via the insulating layer 210. The conductive layer 222b and the insulating layer 210 have an opening 241 that reaches the conductive layer 222a. It can also be said that the conductive layer 222a is exposed at the opening 241. The opening 241 includes an opening in the insulating layer 210 and an opening in the conductive layer 222b. The opening in the insulating layer 210 is provided at a position that overlaps with the opening in the conductive layer 222b.

[0284] The semiconductor layer 228 is provided so as to cover the opening 241. The semiconductor layer 228 has a region in contact with the upper surface of the conductive layer 222a, the side surface of the insulating layer 210, and the side surface of the conductive layer 222b at the opening 241. Furthermore, it is preferable that the semiconductor layer 228 has a region in contact with the upper surface of the conductive layer 222b. The semiconductor layer 228 has a shape that conforms to the upper and side surfaces of the conductive layer 222b, the side surface of the insulating layer 210, and the upper surface of the conductive layer 222a.

[0285] The insulating layer 226 is provided so as to cover the opening 241. The insulating layer 226 is provided on the semiconductor layer 228, the conductive layer 222b, and the insulating layer 210. The insulating layer 226 has regions that are in contact with the upper and side surfaces of the semiconductor layer 228, the upper and side surfaces of the conductive layer 222b, and the upper surface of the insulating layer 210. The insulating layer 226 has a shape that follows the upper and side surfaces of the semiconductor layer 228.

[0286] The conductive layer 224 is provided on the insulating layer 226 and has a region in contact with the upper surface of the insulating layer 226. The conductive layer 224 has a region at the opening 241 that faces the semiconductor layer 228 through the insulating layer 226. The conductive layer 224 has a shape that conforms to the upper and side surfaces of the insulating layer 226.

[0287] The transistor 320 has a conductive layer 324, an insulating layer 326, a semiconductor layer 328, a conductive layer 322a, and a conductive layer 322b. In the transistor 320, the conductive layer 324 functions as a gate electrode, and the insulating layer 326 functions as a gate insulating layer. The conductive layer 322a functions as one of the source electrode and the drain electrode, and the conductive layer 322b functions as the other. Of the semiconductor layer 328, the region between the source electrode and the drain electrode that overlaps with the gate electrode via the gate insulating layer functions as a channel formation region. Also, of the semiconductor layer 328, the region in contact with the source electrode functions as a source region, and the region in contact with the drain electrode functions as a drain region. In the semiconductor layer 328, the channel formation region is located between the source region and the drain region.

[0288] A conductive layer 322a is provided on an insulating layer 169, an insulating layer 310 is provided on the conductive layer 322a, and a conductive layer 322b is provided on the insulating layer 310. The insulating layer 310 has a region that is in contact with and sandwiched between the conductive layers 322a and 322b. The conductive layer 322a has a region that overlaps with the conductive layer 322b via the insulating layer 310. The conductive layer 322b and the insulating layer 310 have an opening 341 that reaches the conductive layer 322a. It can also be said that the conductive layer 322a is exposed at the opening 341. The opening 341 includes an opening in the insulating layer 310 and an opening in the conductive layer 322b. The opening in the insulating layer 310 is provided at a position that overlaps with the opening in the conductive layer 322b.

[0289] The semiconductor layer 328 is provided so as to cover the opening 341. The semiconductor layer 328 has a region in contact with the upper surface of the conductive layer 322a, the side surface of the insulating layer 310, and the side surface of the conductive layer 322b at the opening 341. Furthermore, it is preferable that the semiconductor layer 328 has a region in contact with the upper surface of the conductive layer 322b. The semiconductor layer 328 has a shape that conforms to the shape of the upper and side surfaces of the conductive layer 322b, the side surface of the insulating layer 310, and the upper surface of the conductive layer 322a.

[0290] The insulating layer 326 is provided so as to cover the opening 341. The insulating layer 326 is provided on the semiconductor layer 328, the conductive layer 322b, and the insulating layer 310. The insulating layer 326 has regions that are in contact with the upper and side surfaces of the semiconductor layer 328, the upper and side surfaces of the conductive layer 322b, and the upper surface of the insulating layer 310. The insulating layer 326 has a shape that conforms to the upper and side surfaces of the semiconductor layer 328.

[0291] The conductive layer 324 is provided on the insulating layer 326 and has a region that is in contact with the upper surface of the insulating layer 326. The conductive layer 324 has a region that faces the semiconductor layer 328 through the insulating layer 326 at the opening 341. The conductive layer 324 has a shape that conforms to the shape of the upper and side surfaces of the insulating layer 326.

[0292] The transistor 320 and the insulating layer 310 have the same configuration as the transistor 220 and the insulating layer 210. Therefore, for the transistor 320 and the insulating layer 310, refer to the description relating to the transistor 220 and the insulating layer 210. For the semiconductor layer 328, the insulating layer 326, the conductive layer 324, the conductive layer 322a, and the conductive layer 322b, refer to the description relating to the semiconductor layer 228, the insulating layer 226, the conductive layer 224, the conductive layer 222a, and the conductive layer 222b, respectively. In the following, the transistor 220 and the insulating layer 210 may be used as examples in the explanation.

[0293] In transistor 220, the source electrode and drain electrode are located at different heights relative to the surface being formed (here, the surface of the insulating layer 191), and the drain current flows perpendicular to the surface being formed, or approximately perpendicular. In transistor 220, it can also be said that the drain current flows in the vertical direction. Similarly, in transistor 320, the drain current flows perpendicular to the surface being formed (here, the surface of the insulating layer 169), or approximately perpendicular. Therefore, transistors 220 and 320 can also be called VFETs (Vertical Field Effect Transistors), vertical transistors, vertical channel transistors, or vertical channel type transistors, respectively. Furthermore, the conductive layer 222a can be called the lower electrode of transistor 220, and the conductive layer 222b can be called the upper electrode. The conductive layer 322a can be called the lower electrode of transistor 320, and the conductive layer 322b can be called the upper electrode. Because VFETs allow the source electrode, semiconductor layer, and drain electrode to be stacked, they can significantly reduce the occupied area compared to so-called planar transistors, which have semiconductor layers arranged in a planar configuration.

[0294] The channel length of transistor 220 can be controlled by the thickness of the insulating layer 210 provided between conductive layer 222a and conductive layer 222b. Similarly, the channel length of transistor 320 can be controlled by the thickness of the insulating layer 310 provided between conductive layer 322a and conductive layer 322b. Therefore, transistors with channel lengths shorter than the minimum exposure dimension of the exposure apparatus used to manufacture the transistors can be manufactured with high precision. Furthermore, variations in characteristics between multiple transistors are reduced. As a result, the operation of the semiconductor device 90 becomes more stable and its reliability is improved. In addition, when variations in transistor characteristics are reduced, the degree of freedom in circuit design increases, and the operating voltage of the semiconductor device can be lowered. As a result, the power consumption of the semiconductor device can be reduced.

[0295] Although Figure 12 and other figures show an example in which the semiconductor layer 228, insulating layer 226, and conductive layer 224 cover the opening 241, the present invention is not limited to this. A step can be formed by the insulating layer 210 and conductive layer 222b and the conductive layer 222a, and the semiconductor layer 228, insulating layer 226, and conductive layer 224 can be provided along this step.

[0296] The insulating layer 210 has a region that is in contact with the semiconductor layer 208. To improve the interfacial properties between the semiconductor layer 208 and the insulating layer 210, it is preferable that at least a portion of the region of the insulating layer 210 that is in contact with the semiconductor layer 208 contains oxygen. Specifically, it is preferable that the region of the insulating layer 210 that is in contact with the channel-forming region of the semiconductor layer 208 contains oxygen. One or more oxides and oxiditrides can be suitably used in the region of the insulating layer 210 that is in contact with the channel-forming region of the semiconductor layer 208. The insulating layer 210 can be made from the materials listed for insulating layer 106.

[0297] When a metal oxide is used for the semiconductor layer 208, it is preferable that at least a portion of the region of the insulating layer 210 that is in contact with the semiconductor layer 208 releases oxygen when heat is applied. This supplies oxygen from the insulating layer 210 to the semiconductor layer 208, reducing oxygen deficiencies (V) in the semiconductor layer 208. Ｏ ) and V Ｏ H can be reduced.

[0298] It is preferable that the insulating layer 210 and the insulating layer 310 each have a laminated structure. Figure 12 and the like show an example in which the insulating layer 210 has an insulating layer 210a, an insulating layer 210b on the insulating layer 210a, and an insulating layer 210c on the insulating layer 210b, and the insulating layer 310 has an insulating layer 310a, an insulating layer 310b on the insulating layer 310a, and an insulating layer 310c on the insulating layer 310b. The insulating layers 210a, 210b, 210c, 310a, 310b, and 310c can each be made from the materials listed for insulating layer 106.

[0299] The region of the semiconductor layer 208 that is in contact with the insulating layer 210b functions as a channel-forming region. The insulating layer 210b preferably contains oxygen, and it is preferable to use one or more of the aforementioned oxides and oxiditrides. Specifically, silicon oxide and silicon oxiditride, or both, can be suitably used for the insulating layer 210b.

[0300] It is more preferable to use a material that releases oxygen when heat is applied for the insulating layer 210b. The heat applied during the manufacturing process of the semiconductor device 90 causes the insulating layer 210b to release oxygen, thereby supplying oxygen to the semiconductor layer 208. By supplying oxygen from the insulating layer 210b to the semiconductor layer 208, particularly to the channel formation region, oxygen deficiencies (V) can be reduced. Ｏ ) is repaired, and oxygen deficiency (V Ｏ This can reduce the V in the channel formation region. Ｏ H can be reduced. Therefore, a transistor with good electrical characteristics and high reliability can be obtained.

[0301] For example, oxygen can be supplied to the insulating layer 210b by heat treatment in an oxygen-containing atmosphere or by plasma treatment in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied to the upper surface of the insulating layer 210b by forming a film in an oxygen-containing atmosphere using a sputtering method. The film can then be removed.

[0302] The insulating layer 210b is preferably deposited using sputtering or plasma CVD. In particular, by depositing the film using a method that does not use gases containing hydrogen (e.g., hydrogen gas and ammonia gas) as the deposition gas, a film with an extremely low hydrogen content can be obtained. The sputtering method is particularly suitable for depositing the insulating layer 210b. This suppresses the supply of hydrogen to the channel formation region, thereby stabilizing the electrical characteristics of the transistor 220.

[0303] The insulating layer 210a is provided between the insulating layer 210b and the conductive layer 222a. The insulating layer 210c is provided between the insulating layer 210b and the conductive layer 222b. It is preferable that the insulating layer 210a and the insulating layer 210c each release small amounts of impurities (e.g., water and hydrogen). Furthermore, it is preferable that the insulating layer 210a and the insulating layer 210c each function as barrier films. This suppresses the diffusion of oxygen contained in the insulating layer 210b to the conductive layer 222a side via the insulating layer 210a. Similarly, it suppresses the diffusion of oxygen contained in the insulating layer 210b to the conductive layer 222b side via the insulating layer 210c. This increases the amount of oxygen supplied from the insulating layer 210b to the channel formation region of the semiconductor layer 208, resulting in oxygen deficiencies (V) in the channel formation region. Ｏ ) and V Ｏ H can be reduced. Therefore, a transistor with good electrical characteristics and high reliability can be made. In addition, oxidation of the conductive layer 222a by oxygen contained in the insulating layer 210b and an increase in the electrical resistance of the conductive layer 222a can be suppressed. Similarly, oxidation of the conductive layer 222b by oxygen contained in the insulating layer 210b and an increase in the electrical resistance of the conductive layer 222b can be suppressed. Therefore, a transistor with a large on-current can be made.

[0304] For insulating layer 210a and insulating layer 210c, one or more of the following can be suitably used, for example: aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, zinc gallium oxide, silicon nitride, and silicon nitride oxide. The insulating layer 210a and insulating layer 210c can be made of the same material, or they can be made of different materials.

[0305] By using an oxide or oxiditride for the insulating layer 210c, oxygen can be supplied to the insulating layer 210b (or the insulating film that becomes the insulating layer 210b) when the insulating layer 210c (or the insulating film that becomes the insulating layer 210c) is formed.

[0306] For insulating layers 310a, 310b, and 310c, refer to the descriptions relating to insulating layers 210a, 210b, and 210c, respectively.

[0307] The top surface shape of openings 241 and 341 is not limited and can be, for example, a circle, an ellipse, a triangle, a quadrilateral (including rectangles, rhombuses, and squares), a pentagon, or a polygon with rounded corners. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles of 180 degrees or less). As shown in Figures 14A and 14B, the top surface shapes of openings 241 and 341 are preferably circular. By making the top surface shape of the openings circular, the processing accuracy when forming the openings can be improved, and openings of a fine size can be formed. In this specification, "circular" is not limited to a perfect circle. Furthermore, the top surface shapes of opening 241 and opening 341 can be different.

[0308] In this specification, the upper surface shape of the opening 241 refers to the shape of the upper edge of the insulating layer 210 on the opening 241 side. Similarly, the upper surface shape of the opening 341 refers to the shape of the upper edge of the insulating layer 310 on the opening 341 side.

[0309] I will now explain a specific example of the display device configuration.

[0310] The display device of this embodiment can be a high-resolution display device or a large-screen display device. Therefore, the display device of this embodiment can be used, for example, in television equipment, desktop or notebook computers, computer monitors, large game machines such as pachinko machines, and electronic devices with relatively large screens such as digital signage. It can also be used, for example, in the display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal information terminals, and audio playback devices.

[0311] The display device of this embodiment can be a high-definition display device. Therefore, the display device of this embodiment can be used, for example, as a display unit for information terminals (wearable devices) such as wristwatches and bracelets, as well as as a display unit for wearable devices that can be worn on the head, such as VR devices such as head-mounted displays (HMDs) and AR devices such as glasses.

[0312] The display device of this embodiment may also function as a touch panel. For example, the display device can be fitted with various detection elements (also called sensor elements) that can detect the proximity or contact of an object to be detected, such as a finger.

[0313] Examples of sensor types include capacitive, resistive, surface acoustic wave, infrared, optical, and pressure-sensitive sensors.

[0314] Examples of capacitance methods include surface capacitance and projected capacitance. Furthermore, projected capacitance methods include self-capacitance and mutual capacitance. Mutual capacitance is preferable because it enables simultaneous multi-point detection.

[0315] Examples of touch panels include out-cell, on-cell, and in-cell types. An in-cell touch panel refers to a configuration in which electrodes constituting the sensing element are provided on one or both of the substrate supporting the display element and the opposing substrate.

[0316] Various elements can be used as display elements, such as liquid crystal elements and light-emitting elements. In addition, display elements using shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems), microcapsule-type, electrophoretic-type, electrowetting-type, or electronic powder fluid (registered trademark)-type methods can also be used. Furthermore, QLEDs (Quantum-dot LEDs) using a light source and color conversion technology using quantum dot materials can be used.

[0317] Examples of display devices using liquid crystal elements include transmissive liquid crystal display devices, reflective liquid crystal display devices, and semi-transmissive liquid crystal display devices.

[0318] Modes that can be used in display devices using liquid crystal elements include, for example, Vertical Alignment (VA) mode, FFS (Fringe Field Switching) mode, IPS (In-Plane-Switching) mode, TN (Twisted Nematic) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, and ECB (Electrically Examples of VA modes include Controlled Birefringence mode and Guest Host mode. Examples of VA modes include MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, and ASV (Advanced Super View) mode.

[0319] Examples of liquid crystal materials that can be used in liquid crystal elements include thermotropic liquid crystals, low molecular weight liquid crystals, polymer liquid crystals, polymer dispersed liquid crystals (PDLC), polymer network liquid crystals (PNLC), ferroelectric liquid crystals, and antiferroelectric liquid crystals. Depending on the conditions, these liquid crystal materials exhibit cholesteric phases, smectic phases, cubic phases, chiral nematic phases, isotropic phases, blue phases, etc. Furthermore, either positive-type or negative-type liquid crystals can be used as the liquid crystal material, and can be selected according to the applied mode or design.

[0320] Examples of light-emitting elements include self-emissive light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), and semiconductor lasers. For example, mini-LEDs and micro-LEDs can be used as LEDs.

[0321] The light-emitting element can emit light in the following colors: infrared, red, green, blue, cyan, magenta, yellow, or white. Furthermore, the color purity can be improved by adding a micro-cavity structure to the light-emitting element.

[0322] Of the pair of electrodes in a light-emitting element, one electrode functions as the anode and the other electrode functions as the cathode.

[0323] Furthermore, a display device according to one aspect of the present invention can be a top-emission type that emits light in the direction opposite to the substrate on which the light-emitting element is formed, a bottom-emission type that emits light toward the substrate on which the light-emitting element is formed, or a dual-emission type that emits light on both sides.

[0324] The aforementioned semiconductor device can be suitably used in a display device according to one aspect of the present invention. The semiconductor device according to one aspect of the present invention can be suitably used in either or both of the display unit 62 and the circuit unit 64. Furthermore, the semiconductor device according to one aspect of the present invention can be used in both the display unit 62 and the circuit unit 64, that is, all of the transistors in the display device can be OS transistors. By making all of the transistors in the display device OS transistors in this way, the manufacturing cost can be kept low.

[0325] By using a semiconductor device according to one aspect of the present invention in the display unit 62, the pixel size can be reduced, resulting in a high-resolution display device. Furthermore, by using a semiconductor device according to one aspect of the present invention in the circuit unit 64, the occupied area of ​​the circuit unit 64 can be reduced, resulting in a narrow-bezel display device.

[0326] <Example of Display Device Configuration 2> Figure 15A shows an example of a cross-section when a portion of the display device 50A, including the FPC 72, a portion of the circuit section 64, a portion of the display section 62, a portion of the connection section 40, and a portion of the end section are cut.

[0327] The display device 50A shown in Figure 15A has transistors 207D, 209D, 205R, 205G, 205B, light-emitting elements 130R, 130G, and 130B between substrates 51 and 52. Light-emitting element 130R is a display element of a pixel 17R that emits red light, light-emitting element 130G is a display element of a pixel 17G that emits green light, and light-emitting element 130B is a display element of a pixel 17B that emits blue light.

[0328] The display device 50A employs a structure (also known as the SBS (Side By Side) structure) that creates separate light-emitting layers using light-emitting elements (light-emitting devices) with different emission wavelengths. The SBS structure allows for optimization of materials and configurations for each light-emitting element, thus increasing the freedom of material and configuration selection and making it easier to improve brightness and reliability.

[0329] The display device 50A is a top-emission type. In the top-emission type, transistors and the like can be placed overlapping with the light-emitting region of the light-emitting element, which allows for a higher aperture ratio of pixels compared to the bottom-emission type.

[0330] Figure 15A shows an example configuration in which the pixel circuit and circuit section 64 of the display unit 62 are fitted with the semiconductor device 80A shown in Figure 6. For transistor 207D, refer to the description for transistor 100. For transistor 209D, refer to the description for transistor 200. For transistors 205R, 205G, and 205B, refer to the descriptions for transistor 300, respectively.

[0331] An insulating layer 218 is provided on transistors 205R, 205G, and 205B, and an insulating layer 235 is provided on the insulating layer 218. The insulating layer 218 can be made from the materials listed for insulating layer 106. The insulating layer 235 can be made from the materials listed for insulating layer 231.

[0332] A light-emitting element 130R, a light-emitting element 130G, and a light-emitting element 130B are provided on the insulating layer 235.

[0333] The light-emitting element 130R has a pixel electrode 111R on an insulating layer 235, an EL layer 113R on the pixel electrode 111R, and a common electrode 115 on the EL layer 113R. The light-emitting element 130R shown in Figure 15A emits red light (R). The EL layer 113R has a light-emitting layer that emits red light.

[0334] The light-emitting element 130G has a pixel electrode 111G on an insulating layer 235, an EL layer 113G on the pixel electrode 111G, and a common electrode 115 on the EL layer 113G. The light-emitting element 130G shown in Figure 15A emits green light (G). The EL layer 113G has a light-emitting layer that emits green light.

[0335] The light-emitting element 130B has a pixel electrode 111B on an insulating layer 235, an EL layer 113B on the pixel electrode 111B, and a common electrode 115 on the EL layer 113B. The light-emitting element 130B shown in Figure 15A emits blue light (B). The EL layer 113B has a light-emitting layer that emits blue light.

[0336] In Figure 15A, EL layers 113R, 113G, and 113B are all shown to be the same thickness, but this is not limited to this. The thicknesses of EL layers 113R, 113G, and 113B may be different. For example, it is preferable to set the thickness of EL layers 113R, 113G, and 113B so that the optical path length is such that the light emitted by each is intensified. This makes it possible to realize a microcavity structure and improve the color purity of the light emitted from each light-emitting element.

[0337] The pixel electrode 111R is connected to the conductive layer 312b of the transistor 205R at openings provided in the insulating layer 306, insulating layer 218, and insulating layer 235. Similarly, the pixel electrode 111G is connected to the conductive layer 312b of the transistor 205G, and the pixel electrode 111B is connected to the conductive layer 312b of the transistor 205B.

[0338] The ends of each of the pixel electrodes 111R, 111G, and 111B are covered by an insulating layer 237. The insulating layer 237 functions as a partition. The insulating layer 237 can be provided in a single-layer or multi-layer structure using one or both of an inorganic insulating material and an organic insulating material. For example, the insulating layer 237 can be made of materials that can be used for the insulating layer 218 and materials that can be used for the insulating layer 235. The insulating layer 237 provides electrical insulation between the pixel electrodes and the common electrode. In addition, the insulating layer 237 provides electrical insulation between adjacent light-emitting elements.

[0339] The insulating layer 237 is provided at least on the display unit 62. The insulating layer 237 may be provided not only on the display unit 62, but also on the connection unit 40 and the circuit unit 64. Furthermore, the insulating layer 237 may extend to the end of the display device 50A.

[0340] The common electrode 115 is a continuous film provided in common to the light-emitting elements 130R, 130G, and 130B. The common electrode 115, which is shared by multiple light-emitting elements, is connected to a conductive layer 123 provided at the connection portion 40. It is preferable to use a conductive layer for the conductive layer 123 that is made of the same material and formed using the same process as the pixel electrodes 111R, 111G, and 111B.

[0341] In a display device according to one aspect of the present invention, among the pixel electrodes and common electrodes, the electrode that extracts light is preferably made of a conductive film that transmits visible light. Furthermore, it is preferable that the electrode that does not extract light is made of a conductive film that reflects visible light.

[0342] A conductive film that transmits visible light may also be used on the electrode that does not extract light. In this case, it is preferable to place the electrode between the reflective layer and the EL layer. In other words, the light emitted from the EL layer may be reflected by the reflective layer and extracted from the display device.

[0343] As the material for forming the pair of electrodes of the light-emitting element, metals, alloys, electrically conductive compounds, and mixtures thereof can be used as appropriate. Specifically, such materials include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, and alloys containing these in appropriate combinations. Other materials include ITO, ITSO, In-Zn oxide, and In-W-Zn oxide. Furthermore, such materials include aluminum-containing alloys (aluminum alloys) such as aluminum, nickel, and lanthanum alloys (Al-Ni-La), as well as silver-magnesium alloys and silver-containing alloys such as silver-palladium-copper alloys (Ag-Pd-Cu, also written as APC). Other materials include elements belonging to Group 1 or Group 2 of the periodic table not exemplified above (e.g., lithium, cesium, calcium, strontium), rare earth metals such as europium and ytterbium, alloys containing these in appropriate combinations, graphene, and the like.

[0344] It is preferable that the light-emitting element has a microcavity structure. Therefore, it is preferable that one of the pair of electrodes in the light-emitting element is an electrode that transmits and reflects visible light (a semi-transmitting / semi-reflective electrode), and the other is an electrode that reflects visible light (a reflective electrode). By having a microcavity structure in the light-emitting element, the light emitted from the light-emitting layer can be resonated between the two electrodes, thereby strengthening the light emitted from the light-emitting element.

[0345] The light transmittance of the transparent electrode shall be 40% or more. For example, it is preferable to use an electrode with a transmittance of 40% or more for visible light (light with a wavelength of 400 nm or more and less than 750 nm) for the transparent electrode of the light-emitting element. The visible light reflectance of the semi-transparent and semi-reflective electrodes shall be 10% or more and 95% or less, preferably 30% or more and 80% or less. The visible light reflectance of the reflective electrode shall be 40% or more and 100% or less, preferably 70% or more and 100% or less. Furthermore, the electrical resistivity of these electrodes shall be 1 × 10⁻⁶ −２ A value of Ωcm or less is preferable.

[0346] The EL layers 113R, 113G, and 113B are each provided in an island-like manner. In Figure 15A, the edges of adjacent EL layers 113R and 113G overlap, the edges of adjacent EL layers 113G and 113B overlap, and the edges of adjacent EL layers 113R and 113B overlap. When forming island-like EL layers using a fine metal mask, the edges of adjacent EL layers may overlap as shown in Figure 15A, but this is not the only case. In other words, adjacent EL layers may not overlap and may be separated from each other. Furthermore, in a display device, there may be both areas where adjacent EL layers overlap and areas where adjacent EL layers do not overlap and are separated.

[0347] Each of the EL layers 113R, 113G, and 113B has at least one light-emitting layer. The light-emitting layer has one or more types of light-emitting materials. As the light-emitting material, a material that exhibits a light-emitting color such as blue, purple, blue-violet, green, yellow-green, yellow, orange, or red can be used as appropriate. In addition, a material that emits near-infrared light can also be used as the light-emitting material.

[0348] Examples of luminescent materials include fluorescent materials, phosphorescent materials, thermally activated delayed fluorescence (TADF) materials, and inorganic compounds (such as quantum dot materials).

[0349] In Figure 15A, when a tandem light-emitting element is used, it is preferable that the EL layer 113R has a structure having multiple light-emitting units that emit red light, the EL layer 113G has a structure having multiple light-emitting units that emit green light, and the EL layer 113B has a structure having multiple light-emitting units that emit blue light.

[0350] A protective layer 131 is provided on the light-emitting elements 130R, 130G, and 130B. The protective layer 131 and the substrate 52 are bonded via an adhesive layer 142. A light-shielding layer 117 is provided on the substrate 52. For sealing the light-emitting elements, for example, a solid sealing structure or a hollow sealing structure can be applied. In Figure 15A, the space between the substrate 52 and the substrate 51 is filled with the adhesive layer 142, and a solid sealing structure is applied. Alternatively, the space may be filled with an inert gas (such as nitrogen or argon), and a hollow sealing structure may be applied. In this case, the adhesive layer 142 may be provided in a frame shape so as not to overlap with the light-emitting elements. Furthermore, the space may be filled with a resin different from the adhesive layer 142 provided in a frame shape.

[0351] A connection portion 197 is provided in the region of substrate 51 where substrate 52 does not overlap. At the connection portion 197, the conductive layer 65 is connected to the FPC 72 via conductive layer 234, conductive layer 166, and connection layer 242. Figure 15A shows an example where conductive layer 65 is a conductive layer obtained by processing the same conductive film as conductive layer 112b. It also shows an example where conductive layer 234 is a conductive layer obtained by processing the same conductive film as conductive layer 303. It also shows an example where conductive layer 166 is a conductive layer obtained by processing the same conductive film as pixel electrode 111R, pixel electrode 111G, and pixel electrode 111B. Figure 15A shows an example configuration in which an opening is provided in the upper layer of conductive layer 65, conductive layer 234 is provided so as to cover the opening, and conductive layer 65 and conductive layer 234 are in contact at the opening, thus connecting these conductive layers. Similarly, an example configuration is shown in which an opening is provided in the upper layer of the conductive layer 234, a conductive layer 166 is provided so as to cover the opening, and the conductive layer 166 and the conductive layer 234 are in contact at the opening, thereby connecting these conductive layers. The conductive layer 166 is exposed on the upper surface of the connection portion 197. This allows the connection portion 197 and the FPC 72 to be connected via the connection layer 242.

[0352] <Example of Display Device Configuration 3> Figure 15B shows an example of a cross-section of the display unit 62 of the display device 50B. The display device 50B differs from the display device 50A in that each sub-pixel of each color uses a light-emitting element having a common EL layer 113 and a coloring layer (such as a color filter). The configuration shown in Figure 15B can be combined with the configuration of the region including the FPC 72, the circuit unit 64, the laminated structure from the substrate 51 to the insulating layer 235 of the display unit 62, the connection unit 40, and the end portion shown in Figure 15A. Note that in the following description of the display device, parts that are the same as those described earlier may be omitted.

[0353] The display device 50B shown in Figure 15B includes light-emitting elements 130R, 130G, 130B, a colored layer 132R that transmits red light, a colored layer 132G that transmits green light, and a colored layer 132B that transmits blue light, etc.

[0354] The light-emitting element 130R includes a pixel electrode 111R, an EL layer 113 on the pixel electrode 111R, and a common electrode 115 on the EL layer 113. The light emitted from the light-emitting element 130R is extracted as red light to the outside of the display device 50B via the colored layer 132R.

[0355] The light-emitting element 130G includes a pixel electrode 111G, an EL layer 113 on the pixel electrode 111G, and a common electrode 115 on the EL layer 113. The light emitted from the light-emitting element 130G is extracted as green light to the outside of the display device 50B via the colored layer 132G.

[0356] The light-emitting element 130B includes a pixel electrode 111B, an EL layer 113 on the pixel electrode 111B, and a common electrode 115 on the EL layer 113. The light emitted from the light-emitting element 130B is extracted as blue light to the outside of the display device 50B via the colored layer 132B.

[0357] The light-emitting elements 130R, 130G, and 130B each share an EL layer 113 and a common electrode 115. Providing a common EL layer 113 for each sub-pixel of each color reduces the number of manufacturing steps compared to providing a different EL layer for each sub-pixel of each color.

[0358] For example, the light-emitting elements 130R, 130G, and 130B shown in Figure 15B emit white light. The white light emitted by the light-emitting elements 130R, 130G, and 130B passes through the colored layers 132R, 132G, and 132B, thereby obtaining light of a desired color.

[0359] A light-emitting element that emits white light preferably includes two or more light-emitting layers. When obtaining white light emission using two light-emitting layers, the light-emitting layers can be selected such that their emission colors are complementary. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary, a configuration can be obtained in which the entire light-emitting element emits white light. Furthermore, when obtaining white light emission using three or more light-emitting layers, the emission colors of the three or more light-emitting layers combine to create a configuration in which the entire light-emitting element emits white light.

[0360] The EL layer 113 preferably has, for example, a light-emitting layer containing a light-emitting substance that emits blue light and a light-emitting layer containing a light-emitting substance that emits visible light with a wavelength longer than blue. The EL layer 113 preferably has, for example, a light-emitting layer that emits yellow light and a light-emitting layer that emits blue light. Alternatively, the EL layer 113 preferably has, for example, a light-emitting layer that emits red light, a light-emitting layer that emits green light, and a light-emitting layer that emits blue light.

[0361] It is preferable to use a tandem structure for the light-emitting element that emits white light. Specifically, a two-stage tandem structure having a light-emitting unit that emits yellow light and a light-emitting unit that emits blue light, a two-stage tandem structure having a light-emitting unit that emits red and green light and a light-emitting unit that emits blue light, a three-stage tandem structure having a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light, and a light-emitting unit that emits blue light in this order, or a three-stage tandem structure having a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light and red light, and a light-emitting unit that emits blue light in this order can be applied. For example, as the number of stacked layers of the light-emitting unit and the order of colors, from the anode side, a two-stage structure of B, Y, a two-stage structure of B and the light-emitting unit X, a three-stage structure of B, Y, B, and a three-stage structure of B, X, B can be mentioned. As the number of stacked layers of the light-emitting layer in the light-emitting unit X and the order of colors, from the anode side, a two-layer structure of R, Y, a two-layer structure of R, G, a two-layer structure of G, R, a three-layer structure of G, R, G, or a three-layer structure of R, G, R can be used. Also, another layer may be provided between the two light-emitting layers.

[0362] Note that by applying a microcavity structure, a light-emitting element configured to emit white light may emit light with a specific wavelength such as red, green, or blue being enhanced.

[0363] Alternatively, for example, the light-emitting elements 130R, 130G, and 130B shown in Figure 15B emit blue light. In this case, the EL layer 113 has one or more light-emitting layers that emit blue light. In the pixel 17B that emits blue light, the blue light emitted by the light-emitting element 130B can be extracted. In addition, in the pixel 17R that emits red light and the pixel 17G that emits green light, by providing a color conversion layer between the light-emitting element 130R or light-emitting element 130G and the substrate 52, the blue light emitted by the light-emitting element 130R or light-emitting element 130G can be converted into longer wavelength light, and red or green light can be extracted. The color conversion layer can be described in the above description. Specifically, the various quantum dot materials described above can be used for the color conversion layer. Furthermore, it is preferable to provide a coloring layer 132R between the color conversion layer and the substrate 52 on the light-emitting element 130R, and a coloring layer 132G between the color conversion layer and the substrate 52 on the light-emitting element 130G. Some of the light emitted by a light-emitting element may pass through without being converted by the color conversion layer. By extracting the light that has passed through the color conversion layer via a colored layer, the color of light other than the desired color can be absorbed by the colored layer, thereby increasing the color purity of the light exhibited by the subpixel.

[0364] <Example of Display Device Configuration 4> The display device 50C shown in Figure 16A is an example of a display device to which an MML (metal maskless) structure is applied. In other words, the display device 50C has a light-emitting element that is manufactured without using a fine metal mask.

[0365] In a display device using an MML structure, the island-shaped light-emitting layers in the light-emitting elements are formed by depositing a light-emitting layer onto one surface and then processing it using lithography. Therefore, it is possible to realize high-definition display devices or display devices with high aperture ratios, which have been difficult to achieve until now. Furthermore, since the light-emitting layers can be made separately for each color, it is possible to realize a display device that is extremely vivid, has high contrast, and displays high quality. For example, if the display device is composed of three types of light-emitting elements, such as a blue light-emitting element, a green light-emitting element, and a red light-emitting element, three types of island-shaped light-emitting layers can be formed by repeating the deposition of the light-emitting layer and processing by lithography three times.

[0366] Since a device with an MML structure can be manufactured without using a metal mask, it can exceed the upper limit of fineness caused by the alignment accuracy of the metal mask. Also, when manufacturing a device without using a metal mask, the equipment related to the manufacture of the metal mask and the cleaning process of the metal mask can be made unnecessary. Further, for lithographic processing, since a device common or similar to the one used when manufacturing transistors can be used, there is no need to introduce a special device for manufacturing a device with an MML structure. Thus, since the MML structure can keep the manufacturing cost low, it is suitable for mass production of devices.

[0367] In a display device to which an MML structure is applied, for example, since there is no need to apply a special pixel arrangement such as a pentile arrangement to pseudo-increase the fineness, a so-called stripe arrangement in which the sub-pixels of R, G, and B are arranged in one direction, and a high-definition (for example, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, or 5000 ppi or more) display device can be realized.

[0368] By providing a sacrificial layer on the light-emitting layer, the damage that the light-emitting layer receives during the manufacturing process of the display device can be reduced, and the reliability of the light-emitting element can be enhanced.

[0369] By adopting a film-forming process using an area mask and a processing process using a resist mask, a light-emitting element can be manufactured with a relatively simple process.

[0370] Note that since the laminated structure from the substrate 51 to the insulating layer 235 and the laminated structure from the protective layer 131 to the substrate 52 are the same as those of the display device 50A, the description thereof is omitted.

[0371] In FIG. 16A, light-emitting elements 130R, 130G, and 130B are provided on the insulating layer 235. Regarding the laminated structure from the substrate 51 (not shown in FIG. 16A) to the insulating layer 235, reference can be made to the description according to FIG. 15A.

[0372] The light-emitting element 130R includes a conductive layer 124R on an insulating layer 235, a conductive layer 126R on the conductive layer 124R, a layer 133R on the conductive layer 126R, a common layer 114 on the layer 133R, and a common electrode 115 on the common layer 114. The light-emitting element 130R shown in Figure 16A emits red light (R). Layer 133R has a light-emitting layer that emits red light. In the light-emitting element 130R, layer 133R and the common layer 114 can be collectively called the EL layer. In addition, one or both of the conductive layer 124R and the conductive layer 126R can be called the pixel electrode.

[0373] The light-emitting element 130G includes a conductive layer 124G on an insulating layer 235, a conductive layer 126G on the conductive layer 124G, a layer 133G on the conductive layer 126G, a common layer 114 on the layer 133G, and a common electrode 115 on the common layer 114. The light-emitting element 130G shown in Figure 16A emits green light (G). Layer 133G has a light-emitting layer that emits green light. In the light-emitting element 130G, layer 133G and the common layer 114 can be collectively called the EL layer. In addition, one or both of the conductive layer 124G and the conductive layer 126G can be called the pixel electrode.

[0374] The light-emitting element 130B includes a conductive layer 124B on an insulating layer 235, a conductive layer 126B on the conductive layer 124B, a layer 133B on the conductive layer 126B, a common layer 114 on the layer 133B, and a common electrode 115 on the common layer 114. The light-emitting element 130B shown in Figure 16A emits blue light (B). Layer 133B has a light-emitting layer that emits blue light. In the light-emitting element 130B, layer 133B and the common layer 114 can be collectively called the EL layer. In addition, one or both of the conductive layer 124B and the conductive layer 126B can be called the pixel electrode.

[0375] In this specification, among the EL layers of a light-emitting element, layers provided in an island-like manner for each light-emitting element are referred to as layer 133B, layer 133G, or layer 133R, and a layer shared by multiple light-emitting elements is referred to as the common layer 114. In this specification, the common layer 114 may be omitted, and layers 133R, 133G, and 133B may be referred to as island-like EL layers, island-shaped EL layers, etc. Furthermore, light-emitting elements manufactured without using a metal mask do not need to have a common layer, and all layers constituting the EL layer may be formed in an island-like manner.

[0376] Layers 133R, 133G, and 133B are separated from each other. By providing the EL layer in an island-like configuration for each light-emitting element, leakage current between adjacent light-emitting elements can be suppressed. This prevents unintended light emission caused by crosstalk, enabling the realization of a display device with extremely high contrast.

[0377] Note that in Figure 16A, layers 133R, 133G, and 133B are all shown to be the same thickness, but this is not the only option. The thicknesses of layers 133R, 133G, and 133B may be different.

[0378] The conductive layer 124R is connected to the conductive layer 312b of transistor 205R at openings provided in the insulating layer 106, insulating layer 218, and insulating layer 235. Similarly, the conductive layer 124G is connected to the conductive layer 312b of transistor 205G, and the conductive layer 124B is connected to the conductive layer 312b of transistor 205B.

[0379] The conductive layers 124R, 124G, and 124B are formed to cover the openings provided in the insulating layer 235. Layer 128 is embedded in the recesses of the conductive layers 124R, 124G, and 124B, respectively.

[0380] Layer 128 has the function of flattening the recesses of conductive layers 124R, 124G, and 124B. Conductive layers 126R, 126G, and 126B, which are connected to conductive layers 124R, 124G, and 124B, are provided on conductive layers 124R, 124G, and 124B and on layer 128. Therefore, regions overlapping with the recesses of conductive layers 124R, 124G, and 124B can also be used as light-emitting regions, thereby increasing the aperture ratio of the pixels. It is preferable to use conductive layers that function as reflective electrodes for conductive layers 124R and 126R.

[0381] Layer 128 may be an insulating layer or a conductive layer. Various inorganic insulating materials, organic insulating materials, and conductive materials can be used for layer 128 as appropriate. In particular, it is preferable that layer 128 be formed using an insulating material, and especially preferable that it be formed using an organic insulating material. For example, an organic insulating material that can be used for the insulating layer 237 described above can be applied to layer 128.

[0382] Figure 16A shows an example where the upper surface of layer 128 has a flat portion, but the shape of layer 128 is not particularly limited. The upper surface of layer 128 can have at least one of a convex curved surface, a concave curved surface, and a flat surface.

[0383] The height of the top surface of layer 128 and the height of the top surface of conductive layer 124R may be the same, approximately the same, or different from each other. For example, the height of the top surface of layer 128 may be lower or higher than the height of the top surface of conductive layer 124R.

[0384] The end of the conductive layer 126R may be aligned with the end of the conductive layer 124R, or it may cover the side surface of the end of the conductive layer 124R. Preferably, the ends of the conductive layer 124R and the conductive layer 126R have a tapered shape. Specifically, it is preferable that the ends of the conductive layer 124R and the conductive layer 126R have a tapered shape with a taper angle greater than 0 degrees and less than 90 degrees. When the end of the pixel electrode has a tapered shape, the layer 133R provided along the side surface of the pixel electrode has an inclined portion. By making the side surface of the pixel electrode tapered, the coverage of the EL layer provided along the side surface of the pixel electrode can be improved.

[0385] Since conductive layers 124G, 126G, 124B, and 126B are the same as conductive layers 124R and 126R, a detailed explanation is omitted.

[0386] The top and sides of the conductive layer 126R are covered by layer 133R. Similarly, the top and sides of the conductive layer 126G are covered by layer 133G, and the top and sides of the conductive layer 126B are covered by layer 133B. Therefore, the entire region where conductive layers 126R, 126G, and 126B are provided can be used as the light-emitting region of the light-emitting elements 130R, 130G, and 130B, thereby increasing the aperture ratio of the pixels.

[0387] The upper surfaces and sides of layers 133R, 133G, and 133B are covered by insulating layers 125 and 127. A common layer 114 is provided on layers 133R, 133G, 133B, and insulating layers 125 and 127, and a common electrode 115 is provided on the common layer 114. The common layer 114 and the common electrode 115 are each a continuous film provided in common to multiple light-emitting elements.

[0388] In Figure 16A, the insulating layer 237 shown in Figure 15A, etc., is not provided between the conductive layer 126R and layer 133R. Similarly, the insulating layer 237 is not provided between the conductive layer 126G and layer 133G, and between the conductive layer 126B and layer 133B. In other words, the display device 50C does not have an insulating layer (also called a partition, bank, spacer, etc.) that is in contact with the pixel electrodes and covers the upper edges of the pixel electrodes. Therefore, the spacing between adjacent light-emitting elements can be made extremely narrow. Consequently, a high-definition or high-resolution display device can be made. In addition, a mask for forming the insulating layer is not required, and the manufacturing cost of the display device can be reduced.

[0389] As described above, layers 133R, 133G, and 133B each have an emissive layer. Preferably, layers 133R, 133G, and 133B each have one or both of a carrier transport layer (electron transport layer or hole transport layer) and a carrier block layer (hole block layer or electron block layer) on the emissive layer. Since the surfaces of layers 133R, 133G, and 133B are exposed during the manufacturing process of the display device, providing one or both of the carrier transport layer and the carrier block layer on the emissive layer suppresses exposure of the emissive layer to the outermost surface and reduces damage to the emissive layer. This improves the reliability of the light-emitting element.

[0390] The common layer 114 may have, for example, an electron injection layer or a hole injection layer. Alternatively, the common layer 114 may have an electron transport layer and an electron injection layer stacked together, or a hole transport layer and a hole injection layer stacked together. The common layer 114 is shared by the light-emitting element 130R, the light-emitting element 130G, and the light-emitting element 130B.

[0391] Each side of layer 133R, layer 133G, and layer 133B is covered by the insulating layer 125. The insulating layer 127 covers each side of layer 133R, layer 133G, and layer 133B via the insulating layer 125.

[0392] The sides (and even a portion of the top surface) of layers 133R, 133G, and 133B are covered by at least one of the insulating layers 125 and 127. This prevents the common layer 114 (or common electrode 115) from coming into contact with the pixel electrode and the sides of layers 133R, 133G, and 133B, thereby suppressing short circuits in the light-emitting element. This improves the reliability of the light-emitting element.

[0393] Preferably, the insulating layer 125 has regions that are in contact with the respective sides of layers 133R, 133G, and 133B. By configuring the insulating layer 125 to be in contact with layers 133R, 133G, and 133B, peeling of the layers 133R, 133G, and 133B can be prevented, and the reliability of the light-emitting element can be improved.

[0394] The insulating layer 127 is provided on the insulating layer 125 so as to fill the recess of the insulating layer 125. Preferably, the insulating layer 127 covers at least a part of the side surface of the insulating layer 125.

[0395] By providing the insulating layer 125 and the insulating layer 127, it is possible to fill the space between adjacent island-shaped layers, thereby reducing the large unevenness in the height difference of the surface to be formed of the layer provided on the island-shaped layer (such as the carrier injection layer and the common electrode), and making it flatter. Therefore, the covering property of the carrier injection layer and the common electrode can be enhanced.

[0396] The common layer 114 and the common electrode 115 are provided on the layer 133R, the layer 133G, the layer 133B, the insulating layer 125, and the insulating layer 127. Before providing the insulating layer 125 and the insulating layer 127, a step difference occurs due to the region where the pixel electrode and the island-shaped EL layer are provided and the region where the pixel electrode and the island-shaped EL layer are not provided (the region between the light-emitting elements). The display device according to one aspect of the present invention can flatten the step difference by having the insulating layer 125 and the insulating layer 127, and can improve the covering property of the common layer 114 and the common electrode 115. Therefore, it is possible to suppress connection failure due to step discontinuity. In addition, it is possible to suppress the local thinning of the common electrode 115 due to the step difference and the increase in electrical resistance.

[0397] Preferably, the upper surface of the insulating layer 127 has a highly flat shape. The upper surface of the insulating layer 127 may have at least one of a flat surface, a convex curved surface, and a concave curved surface. For example, the upper surface of the insulating layer 127 preferably has a convex curved surface shape with a large radius of curvature.

[0398] The insulating layer 125 can be a single-layer structure or a laminated structure of two or more layers. Preferably, the insulating layer 125 has one or more inorganic insulating layers. The insulating layer 125 can be made of any material that can be used for the insulating layer 106. In particular, aluminum oxide is preferred because it has a high selectivity ratio with the EL layer during etching and has the function of protecting the EL layer during the formation of the insulating layer 127. In particular, by applying an inorganic insulating layer such as an aluminum oxide film, hafnium oxide film, or silicon oxide film formed by the ALD method to the insulating layer 125, an insulating layer 125 can be formed with fewer pinholes and excellent function in protecting the EL layer. Alternatively, the insulating layer 125 may be a laminated structure of a film formed by the ALD method and a film formed by the sputtering method. For example, the insulating layer 125 may be a laminated structure of an aluminum oxide film formed by the ALD method and a silicon nitride film formed by the sputtering method.

[0399] Preferably, the insulating layer 125 functions as a barrier insulating layer against at least one of water and oxygen. Preferably, the insulating layer 125 has the function of suppressing the diffusion of at least one of water and oxygen. Furthermore, preferably, the insulating layer 125 has the function of capturing or fixing (getting) at least one of water and oxygen.

[0400] The insulating layer 125 functions as a barrier insulating layer, thereby suppressing the intrusion of impurities (typically at least one of water and oxygen) that could diffuse from the outside into each light-emitting element. This configuration makes it possible to provide a highly reliable light-emitting element and, furthermore, a highly reliable display device.

[0401] The insulating layer 127 provided on the insulating layer 125 has the function of flattening the large height differences and irregularities in the insulating layer 125 formed between adjacent light-emitting elements. In other words, the presence of the insulating layer 127 has the effect of improving the flatness of the surface forming the common electrode 115.

[0402] As the insulating layer 127, an insulating layer having an organic material can be suitably used. Preferably, a photosensitive resin is used as the organic material; for example, a photosensitive resin composition containing an acrylic resin is preferred. In this specification, the term "acrylic resin" does not refer only to polymethacrylate esters or methacrylic resins, but may refer to acrylic polymers in a broad sense.

[0403] As the insulating layer 127, acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimidoamide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins may be used. Alternatively, as the insulating layer 127, organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin may be used. Furthermore, a photoresist may be used as the photosensitive resin. Either a positive-type or negative-type material may be used as the photosensitive resin.

[0404] The insulating layer 127 may be made of a material that absorbs visible light. By absorbing the light emitted from the light-emitting element, the insulating layer 127 can suppress light leakage (stray light) from the light-emitting element to adjacent light-emitting elements through the insulating layer 127. This improves the display quality of the display device. Furthermore, since the display quality can be improved without using a polarizing plate in the display device, the display device can be made lighter and thinner.

[0405] Examples of materials that absorb visible light include materials containing pigments such as black, materials containing dyes, light-absorbing resin materials (e.g., polyimide), and resin materials that can be used in color filters (color filter materials). In particular, it is preferable to use a resin material obtained by laminating or mixing two or more color filter materials, as this can enhance the visible light shielding effect. In particular, by mixing three or more color filter materials, it is possible to create a black or near-black resin layer.

[0406] <Example of Display Device Configuration 5> Figure 16B shows an example of a cross-section of the display unit 62 of the display device 50D. The display device 50D differs from the display device 50C mainly in that a coloring layer (such as a color filter) is provided for each sub-pixel of each color. The configuration shown in Figure 16B can be combined with the configuration shown in Figure 16A, which includes the region containing the FPC 72, the circuit unit 64, the laminated structure from the substrate 51 to the insulating layer 235 of the display unit 62, the connection unit 40, and the end.

[0407] The display device 50D shown in Figure 16B includes light-emitting elements 130R, 130G, 130B, a colored layer 132R that transmits red light, a colored layer 132G that transmits green light, and a colored layer 132B that transmits blue light, etc.

[0408] The light emitted from the light-emitting element 130R is extracted as red light to the outside of the display device 50D via the colored layer 132R. Similarly, the light emitted from the light-emitting element 130G is extracted as green light to the outside of the display device 50D via the colored layer 132G. The light emitted from the light-emitting element 130B is extracted as blue light to the outside of the display device 50D via the colored layer 132B.

[0409] Each of the light-emitting elements 130R, 130G, and 130B has a layer 133. These three layers 133 are formed using the same material and the same process. Furthermore, these three layers 133 are spaced apart from each other. By providing the EL layer in an island-like configuration for each light-emitting element, leakage current between adjacent light-emitting elements can be suppressed. This prevents unintended light emission caused by crosstalk, enabling the realization of a display device with extremely high contrast.

[0410] For example, the light-emitting elements 130R, 130G, and 130B shown in Figure 16B emit white light. The white light emitted by the light-emitting elements 130R, 130G, and 130B passes through the colored layers 132R, 132G, and 132B, thereby obtaining light of a desired color.

[0411] Alternatively, for example, the light-emitting elements 130R, 130G, and 130B shown in Figure 16B emit blue light. In this case, layer 133 has one or more light-emitting layers that emit blue light. In the pixel 17B that emits blue light, the blue light emitted by the light-emitting element 130B can be extracted. Furthermore, in the pixel 17R that emits red light and the pixel 17G that emits green light, by providing a color conversion layer between the light-emitting element 130R or light-emitting element 130G and the substrate 52, the blue light emitted by the light-emitting element 130R or light-emitting element 130G can be converted into longer wavelength light, and red or green light can be extracted. Moreover, it is preferable to provide a coloring layer 132R between the color conversion layer and the substrate 52 on the light-emitting element 130R, and a coloring layer 132G between the color conversion layer and the substrate 52 on the light-emitting element 130G. By extracting the light that has passed through the color conversion layer via the colored layer, the colored layer absorbs light of colors other than the desired color, thereby increasing the color purity of the light exhibited by the subpixel.

[0412] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0413] (Embodiment 2) In this embodiment, an example of a display device according to one aspect of the present invention will be described. A configuration applicable to the display unit 62 and circuit unit 64 described above will be explained.

[0414] Figure 17 is an example of a block diagram of the circuit of a display device 70 according to one embodiment of the present invention. The display device 70 has, for example, a display unit 62. Alternatively, the display device 70 has, for example, a circuit 33. Alternatively, the display device 70 has, for example, a circuit 34. Alternatively, the display device 70 has, for example, a circuit 35. Alternatively, the display device 70 has, for example, a circuit 36. However, one embodiment of the present invention is not limited to these. The display device 70 does not have to have at least one of the display unit 62, circuit 33, circuit 34, circuit 35 and circuit 36. Alternatively, the display device 70 may have yet another circuit. Alternatively, the display device 70 may have yet another region including pixels.

[0415] The display unit 62 has, for example, a plurality of pixels. Each of the plurality of pixels has, for example, a display element and a transistor. Alternatively, each of the plurality of pixels has, for example, a sensor element and a transistor. Alternatively, each of the plurality of pixels has, for example, a display element, a sensor element and a transistor. However, one aspect of the present invention is not limited to these. For example, the display unit 62 may have something other than a pixel. Alternatively, for example, the plurality of pixels in the display unit 62 may have a plurality of pixels with different configurations. Alternatively, for example, the display unit 62 may have only one pixel.

[0416] Various elements can be used as display elements. Examples include organic EL elements, liquid crystal elements, light-emitting diodes, and electrophoretic elements.

[0417] Various types of sensor elements can be used. Examples include photodiodes, image sensors, illuminance sensors, ultrasonic detection elements, and touch sensor elements.

[0418] The display unit 62 may have at least one display area and one sensor area. In this case, one pixel may have at least one of a display element, a sensor element, and a transistor. Alternatively, one pixel may have a display element and a transistor, and another pixel may have a sensor element and a transistor. Therefore, pixels having sensor elements and pixels having display elements may be arranged adjacent to each other. For example, in the display unit 62, the display area and the sensor area may be arranged to overlap. However, one aspect of the present invention is not limited to these. In the display unit 62, the display area and the sensor area may be arranged separately. Alternatively, the display unit 62 may have multiple display areas. Alternatively, the display unit 62 may have multiple sensor areas. Alternatively, the display unit 62 may have only display areas and not have sensor areas. Alternatively, the display unit 62 may have display elements and not have sensor elements. Alternatively, the display unit 62 may have only a sensor area and not a display area. Or, the display unit 62 may have a sensor element and not a display element. If the display unit 62 does not have a display area or a display element, but has a sensor area or a sensor element, it may be referred to by a different device name (for example, an imaging device, a sensor device, a reading device, etc.) instead of a display device. Similarly, if it has a sensor element, it may be referred to as an imaging unit, a sensor unit, or a reading unit instead of a display unit.

[0419] Furthermore, as an example, transistors formed in different layers may be used as transistors in a pixel. For example, a pixel may have transistors formed in one layer and transistors formed in another layer. Or, a pixel may have transistors formed in yet another layer. Or, the layer on which the transistors are formed may differ depending on the type of pixel. In this way, by using transistors formed in multiple layers, the layout area of ​​the pixel can be reduced. As a result, the display resolution of the display unit 62 can be improved. However, the embodiments of the present invention are not limited to these. For example, a certain pixel may be composed only of transistors formed in the same layer.

[0420] For example, a pixel may consist only of transistors formed in the same layer, while transistors formed in a different layer may be used in circuits 33, 34, 35, or 36. In this case, the display unit 62 can be arranged in overlapping configuration with circuits 33, 34, 35, or 36. This allows for miniaturization of the display device 70. However, the present invention is not limited to these embodiments. The display unit 62 may be arranged so as not to overlap with circuits 33, 34, 35, or 36.

[0421] Furthermore, the multiple transistors in a pixel may have different performance requirements. For example, some transistors require a low off-current (leakage current), others require a high on-current, some need to be suitable for use as switches, others need to be highly reliable when continuously supplying current, and some need current characteristics such that the drain current does not change significantly even when the drain voltage is increased in the saturation region. Others need to be suitable for use as a current source.

[0422] Therefore, by combining transistors formed in different layers within a pixel, it is possible to construct a pixel with good overall characteristics. For example, as different layers, an LTPS transistor can be formed in the first layer, and an OS transistor can be formed in the second layer. These can be combined to form the pixel configuration. However, the present invention is not limited to this embodiment. The transistors formed in the first layer and the second layer can also be the same. Furthermore, another layer can be included in addition to the first and second layers.

[0423] One example of a transistor formed with different layers is the LTPS transistor. LTPS transistors may have the disadvantage of having a large off-current (leakage current). However, they have advantages, such as a large on-current, or they are easy to use as a switch, or they offer high reliability when continuously supplying current, or the drain current does not change much even when the drain voltage is increased in the saturation region, or they are easy to use as a current source.

[0424] Furthermore, LTPS transistors can be configured as p-channel type transistors. Therefore, for example, by combining them with n-channel type transistors formed in different layers, a CMOS configuration can be achieved.

[0425] Furthermore, in the case of p-channel transistors, there is an advantage that, for example, it is easier to drive organic EL elements in pixels where organic EL elements are used as display elements. In particular, using a p-channel transistor for the transistor that controls the current of the organic EL element (the transistor that operates as a current source) makes control easier. However, the present invention is not limited to these. For example, an n-channel transistor may be used for the transistor that controls the current of the organic EL element (the transistor that operates as a current source).

[0426] Furthermore, LTPS transistors can be configured as n-channel type transistors. In addition, LTPS transistors can be formed as both n-channel and p-channel types. Therefore, when using LTPS transistors, they can be configured as CMOS transistors formed on the same layer.

[0427] Another example of a transistor formed in different layers is the OS transistor. OS transistors have advantages such as, for example, low off-current (leakage current), or relatively large on-current, or are easy to operate as a switch, or are highly reliable when current is continuously flowing, or have a drain current that does not change much even when the drain voltage is increased in the saturation region, or are easy to operate as a current source. However, it can be difficult to construct a p-channel OS transistor. Therefore, when constructing a CMOS configuration, it is combined with an LTPS transistor (in the case of a p-channel type). In other words, a CMOS configuration can be achieved by combining an OS transistor with a p-channel type LTPS transistor.

[0428] However, transistor characteristics may differ depending on the type of oxide semiconductor. For example, when indium and oxygen are present (for instance, when gallium is absent, or when zinc is absent, or when gallium and zinc are absent), the on-current is relatively large, and it may be possible to achieve an on-current similar to that of an LTPS transistor. In that case, by combining an OS transistor with a p-channel type LTPS transistor, a CMOS configuration can be achieved with a more appropriate transistor size. However, when indium and oxygen are present (for example, when gallium is absent, or when zinc is absent, or when gallium and zinc are absent), the threshold voltage may be negative (so-called normally on).

[0429] On the other hand, when the oxide semiconductor contains, for example, indium, gallium, zinc, and oxygen, the on-current may be smaller than that of an LTPS transistor. In that case, when an OS transistor and a p-channel type LTPS transistor are combined, the transistor sizes may become unbalanced (the channel width W of the OS transistor may need to be very large). However, when indium, gallium, zinc, and oxygen are present, the threshold voltage may tend to be positive (so-called normally-off). Furthermore, the off-current (leakage current) may be smaller when indium, gallium, zinc, and oxygen are present than when indium and oxygen are present (for example, when gallium is not present, or when zinc is not present, or when gallium and zinc are not present). Therefore, when the off-current (leakage current) is important, indium, gallium, zinc, and oxygen may be present. However, the present invention is not limited to these embodiments.

[0430] In other words, when forming transistors in different layers and configuring OS transistors with multiple layers, for example, an OS transistor may be configured having indium, gallium, zinc, and oxygen, and an OS transistor may be configured having indium and oxygen (for example, without gallium, without zinc, or without gallium and zinc). However, the embodiments of the present invention are not limited to these. For example, when configuring OS transistors with multiple layers, for example, an OS transistor may be configured using only an OS transistor having indium and oxygen (for example, without gallium, without zinc, or without gallium and zinc). Or, for example, when configuring OS transistors with multiple layers, for example, an OS transistor may be configured using only an OS transistor having indium, gallium, zinc, and oxygen.

[0431] Thus, even when using oxide semiconductors, it is possible to construct better circuits by changing the materials according to various conditions.

[0432] Circuit 33, for example, has the function of a gate driver circuit. Circuit 33 may have the function of driving gate lines arranged in the display unit 62. Alternatively, circuit 33 may have the function of driving wiring connected to pixels.

[0433] Circuit 34, for example, has the function of a gate driver circuit. Circuit 34 may have the function of driving gate lines arranged in the display unit 62. Alternatively, circuit 34 may have the function of driving wiring connected to pixels.

[0434] Furthermore, circuits 33 and 34 may, for example, drive the same gate line from both the left and right sides (so-called dual-insertion). In that case, signals can be supplied from both sides to the same wiring. Therefore, it can be operated at high speed. Alternatively, even if the size of the display unit 62 is large, or if the length of the gate line is long, it can be operated at an appropriate speed.

[0435] Alternatively, circuits 33 and 34 may drive separate gate lines (so-called single-sided input). In this case, the circuits that drive the gate lines can be separated and arranged on the left and right sides, thus reducing the layout area of ​​the circuits.

[0436] Circuit 35 has the function of, for example, a source driver circuit. Circuit 35 has the function of driving source lines arranged in the display unit 62. Alternatively, circuit 35 has the function of driving wiring connected to pixels.

[0437] Furthermore, if circuit 35 has the function of a source driver circuit, it can be configured to handle many or all of its source driver functions. This reduces the number of circuits on the so-called external single-crystal silicon chip. However, one aspect of the present invention is not limited to these. Circuit 35 may handle only some of the functions of a source driver. For example, circuit 35 may only have the function of an output switching circuit (DEMUX). In that case, the other source driver functions may be handled by the circuits on the single-crystal silicon chip.

[0438] Circuit 35, for example, has the function of a reading circuit. Circuit 35 has the function of reading signals from sensor lines arranged in the display unit 62. As a result, the signals read from the sensor elements of the display unit 62 can be extracted to the outside with as little attenuation as possible.

[0439] Alternatively, circuit 35 may have the function of reading current from an output line located on the display unit 62, for example. Or, circuit 35 may have the function of reading signals from wiring connected to a pixel. Current can be supplied from the transistors in the pixels and sent to circuit 35 via the output lines. As a result, for example, variations in the characteristics of the pixel's transistors can be read by circuit 35. This makes it possible to correct for variations in the characteristics of the pixel's transistors.

[0440] Furthermore, if circuit 35 has the function of a read circuit, it can be configured to handle many or all of its functions as a read circuit. This reduces the number of circuits on the so-called external single-crystal silicon chip. However, the present invention is not limited to these. For example, circuit 35 may handle only a part of the functions of the read circuit. For example, circuit 35 may only have the function of a sample-and-hold circuit. In that case, the other functions may be handled by the circuits on the single-crystal silicon chip.

[0441] Circuit 36 ​​has the function of, for example, a source driver circuit. Circuit 36 ​​has the function of driving source lines arranged in the display unit 62. Alternatively, circuit 36 ​​has the function of driving wiring connected to pixels.

[0442] Furthermore, if circuit 36 ​​has the function of a source driver circuit, it can be configured to handle many or all of its source driver functions. This reduces the number of circuits on the so-called external single-crystal silicon chip. However, the present invention is not limited to these. For example, circuit 36 ​​may handle only a part of the functions of a source driver. For example, circuit 36 ​​may only have the function of an output switching circuit (DEMUX). In that case, the other source driver functions may be handled by the circuits on the single-crystal silicon chip.

[0443] Circuit 36, for example, has the function of a reading circuit. Circuit 36 ​​has the function of reading signals from sensor lines arranged in the display unit 62. As a result, the signals read from the sensor elements of the display unit 62 can be extracted to the outside with as little attenuation as possible.

[0444] Alternatively, circuit 36 ​​may have the function of reading current from an output line located on the display unit 62, for example. Alternatively, circuit 36 ​​may have the function of reading signals from wiring connected to a pixel. Current can be supplied from the transistors in the pixels, and the current from the pixels can be supplied to circuit 36 ​​via the output line. As a result, for example, variations in the characteristics of the pixel transistors can be read by circuit 36. This makes it possible to correct variations in the characteristics of the pixel transistors.

[0445] Furthermore, if circuit 36 ​​has the function of a reading circuit, it can be configured to handle many or all of its reading circuit functions. This reduces the number of circuits on the so-called external single-crystal silicon chip. However, the present invention is not limited to these. For example, circuit 36 ​​may handle only a part of the functions of the reading circuit. For example, circuit 36 ​​may only have the function of a sample-and-hold circuit. In that case, the other functions may be handled by the circuits on the single-crystal silicon chip.

[0446] Furthermore, circuits 35 and 36 may, for example, drive the same source line from both the upper and lower sides (so-called dual-insertion). In that case, signals can be supplied from both sides to the same wiring. Therefore, it can be operated at high speed. Alternatively, even if the size of the display unit 62 is large, or if the length of the source line is long, it can be operated at an appropriate speed.

[0447] Alternatively, circuits 35 and 36 may drive separate source lines (so-called single-ended connections). In this case, the circuits that drive the source lines can be separated and arranged on the left and right sides, thus reducing the circuit layout area.

[0448] When circuits 35 and 36 drive different source lines, for example, circuit 35 may drive pixels that display one color and pixels that display another color, while circuit 36 ​​may drive pixels that display the remaining colors. In other words, circuit 35 may drive pixels that display a first color and pixels that display a second color, while circuit 36 ​​may drive pixels that display a third color. By separating the layout of circuits 35 and 36 by color in this way, the layout area of ​​the circuits can be reduced. For example, if the pixel arrangement is a pentile arrangement or a diamond arrangement, the number of pixels will differ depending on the color. In that case, by making the number of pixels of a color driven by circuit 35 different from the number of pixels of a color driven by circuit 36, it is possible to make the layout area of ​​circuits 35 and 36 more uniform.

[0449] Alternatively, circuits 35 and 36 may read signals from, for example, another sensor line. In that case, the circuits that read signals from the sensor line can be arranged separately, one above the other, thus reducing the overall circuit layout area.

[0450] Alternatively, circuits 35 and 36 may read current from, for example, a different output line. In that case, the circuit that reads current from a different output line can be arranged separately above and below, thus reducing the layout area of ​​the circuit.

[0451] When circuits 35 and 36 read current from different output lines, for example, circuit 35 may read current from pixels displaying one color and pixels displaying another color, while circuit 36 ​​may read current from pixels displaying the remaining colors. In other words, circuit 35 may read current from pixels displaying a first color and pixels displaying a second color, while circuit 36 ​​may read current from pixels displaying a third color. By separating the layout of circuits 35 and 36 by color in this way, the layout area of ​​the circuits can be reduced. For example, if the pixel arrangement is a pentile arrangement or a diamond arrangement, the number of pixels differs depending on the color. In that case, by making the number of pixels of each color read by circuit 35 different from the number of pixels of each color read by circuit 36, the layout area of ​​circuits 35 and 36 can be made equal.

[0452] Alternatively, for example, circuit 35 may be connected to the source line and drive the source line, while circuit 36 ​​may be connected to the sensor line and read signals from the sensor line. In this case, circuit 35 will drive all the color pixels.

[0453] Alternatively, for example, circuit 35 may be connected to the source line and drive the source line, and circuit 36 ​​may be connected to the output line and read current from the output line. In this case, circuit 35 will drive all color pixels, and circuit 36 ​​will read current from all color pixels.

[0454] Alternatively, for example, circuit 35 may be connected to the source line and drive the source line, circuit 36 ​​may be connected to the output line and read current from the output line, and circuit 36 ​​may be connected to the sensor line and read a signal from the sensor line. In this case, circuit 35 will drive pixels of all colors, and circuit 36 ​​will read current from pixels of all colors.

[0455] Furthermore, the transistors in circuits 33, 34, 35, or 36 may be transistors formed on different layers. For example, circuits 33, 34, 35, or 36 may have transistors formed on one layer and transistors formed on another layer. Also, for example, circuits 33, 34, 35, or 36 may have transistors formed on yet another layer. Alternatively, the layers on which transistors are formed may differ depending on the type of circuit. In this way, by using transistors formed on multiple layers, the layout area of ​​circuits 33, 34, 35, or 36 can be reduced. As a result, the area around the display unit 62 of the display device 70 (the so-called bezel) can be reduced. However, the embodiments of the present invention are not limited to these. For example, a certain circuit may consist only of transistors formed on the same layer.

[0456] Furthermore, by using transistors formed on different layers, it becomes easier to construct transistors with different polarities. This makes it easier to implement a CMOS configuration. By using a CMOS configuration, compared to the case of using only n-channel or only p-channel types, the number of transistors that make up logic circuits (e.g., inverters, clocked inverters, NAND, NOR, AND, OR, level shifters, analog switches, transfer gates, shift registers, latches, buffers, pulse width control circuits, etc.) and analog circuits (e.g., source followers, amplifier circuits, operational amplifiers, current sources, etc.) can be reduced. Alternatively, by using a CMOS configuration, the circuit configuration can be simplified, for example. Alternatively, by using a CMOS configuration, power consumption can be reduced, for example. Alternatively, by using a CMOS configuration, the operating voltage can be reduced, for example. Alternatively, by using a CMOS configuration, reliability can be improved, for example.

[0457] Furthermore, the transistors in circuits 33, 34, 35, or 36 may have different performance requirements. For example, some transistors may require a small off-current (leakage current), others a large on-current, some transistors may be suitable for use as switches, others have high reliability when continuously supplying current, and some transistors may have current characteristics such that the drain current does not change significantly even when the drain voltage is increased during operation in the saturation region, or others are suitable for use as current sources.

[0458] Therefore, by combining transistors formed on different layers in circuits 33, 34, 35, or 36, a circuit with good overall characteristics can be constructed. Alternatively, a CMOS configuration can be easily implemented. By using a CMOS configuration, for example, the number of transistors that make up logic circuits, analog circuits, etc. can be reduced. Alternatively, by using a CMOS configuration, for example, the circuit configuration can be simplified. Alternatively, by using a CMOS configuration, for example, power consumption can be reduced. Alternatively, by using a CMOS configuration, for example, the operating voltage can be reduced. Alternatively, by using a CMOS configuration, for example, reliability can be improved.

[0459] One example of a transistor formed with different layers is the LTPS transistor. This LTPS transistor may have disadvantages, such as a large off-current (leakage current). However, it has advantages such as a large on-current. Or, for example, it has the advantage of being easy to operate as a switch. Or, for example, it has the advantage of high reliability when current is continuously flowing. Or, for example, it has the advantage that the drain current does not change much even when the drain voltage is increased in operation in the saturation region. Or, for example, it has the advantage of being easy to operate as a current source.

[0460] Furthermore, LTPS transistors can be configured as p-channel type transistors. Therefore, for example, by combining them with n-channel type transistors formed in different layers, a CMOS configuration can be achieved.

[0461] Furthermore, LTPS transistors can be configured as n-channel type transistors. In addition, LTPS transistors can be formed as both n-channel and p-channel types. Therefore, when using LTPS transistors, they can be configured as CMOS transistors formed on the same layer.

[0462] Another example of a transistor formed in different layers is the OS transistor. This OS transistor has the advantage of low off-current (leakage current). Alternatively, it may have the advantage of relatively large on-current. Alternatively, it may be easy to operate as a switch. Alternatively, it may have high reliability when continuously supplying current. Alternatively, it may have the advantage of the drain current not changing much even when the drain voltage is increased during operation in the saturation region. Alternatively, it may be easy to operate as a current source. However, it can be difficult to construct a p-channel type OS transistor. Therefore, when constructing a CMOS configuration, it is combined with an LTPS transistor (in the case of a p-channel type). In other words, a CMOS configuration can be achieved by combining an OS transistor with a p-channel type LTPS transistor.

[0463] However, transistor characteristics may differ depending on the type of oxide semiconductor. For example, when indium and oxygen are present (for instance, when gallium is absent, or when zinc is absent, or when gallium and zinc are absent), the on-current is relatively large, and it may be possible to achieve an on-current similar to that of an LTPS transistor. In that case, by combining an OS transistor with a p-channel type LTPS transistor, a CMOS configuration can be achieved with a more appropriate transistor size. However, when indium and oxygen are present (for example, when gallium is absent, or when zinc is absent, or when gallium and zinc are absent), the threshold voltage may be negative (so-called normally on).

[0464] On the other hand, when the oxide semiconductor contains, for example, indium, gallium, zinc, and oxygen, the on-current may be smaller than that of an LTPS transistor. In that case, when combining an OS transistor with a p-channel type LTPS transistor, the transistor size may become unbalanced (the channel width W of the OS transistor may need to be very large). However, when indium, gallium, zinc, and oxygen are present, the threshold voltage may tend to be positive (so-called normally-off). Furthermore, the off-current (leakage current) may be smaller when indium, gallium, zinc, and oxygen are present than when indium and oxygen are present (for example, when gallium is not present, or when zinc is not present, or when gallium and zinc are not present). Therefore, when the off-current (leakage current) is important, indium, gallium, zinc, and oxygen may be included. However, the present invention is not limited to these embodiments.

[0465] In other words, when forming transistors in different layers and configuring OS transistors with multiple layers, for example, an OS transistor may be configured having indium, gallium, zinc, and oxygen, and an OS transistor may be configured having indium and oxygen (for example, without gallium, without zinc, or without gallium and zinc). However, the embodiments of the present invention are not limited to these. For example, when configuring OS transistors with multiple layers, for example, an OS transistor may be configured using only an OS transistor having indium and oxygen (for example, without gallium, without zinc, or without gallium and zinc). Or, for example, when configuring OS transistors with multiple layers, for example, an OS transistor may be configured using only an OS transistor having indium, gallium, zinc, and oxygen.

[0466] Thus, even when using oxide semiconductors, it is possible to construct better circuits by changing the materials according to various conditions.

[0467] Next, Figure 18 shows an example of a circuit block included in circuit 33, or a circuit block included in circuit 34. Circuit 33 or circuit 34 may, for example, include circuits 43, 44, and 45. However, one aspect of the present invention is not limited to these. Circuit 33 or circuit 34 may not have at least one of circuits 43, 44, and 45. Alternatively, circuit 33 or circuit 34 may have yet another circuit. Alternatively, for example, circuit 33 or circuit 34 may have an output switching circuit (DEMUX). Alternatively, for example, circuit 33 or circuit 34 may have only an output switching circuit (DEMUX).

[0468] In Figure 18, circuits 43, 44, and 45 can be considered, for example, to represent a block of one row of circuitry. Alternatively, since Figure 18 is a block diagram, circuits 43, 44, and 45 can be considered, for example, to represent the entire (all rows of) circuitry of the display device 70.

[0469] Circuit 43, for example, has the function of a shift register circuit. A shift register circuit, for example, has the function of outputting a signal to select one row at a time. This shift register circuit can be constructed, for example, using a p-channel LTPS transistor and an n-channel OS transistor as transistors formed in different layers. In other words, circuit 43 can be constructed as a CMOS circuit, for example. Therefore, for example, the number of transistors that make up the logic circuit can be reduced. Alternatively, by using a CMOS configuration, for example, the circuit configuration can be simplified. Alternatively, by using a CMOS configuration, for example, power consumption can be reduced. Alternatively, by using a CMOS configuration, for example, the operating voltage can be reduced. Alternatively, by using a CMOS configuration, for example, reliability can be improved.

[0470] Furthermore, as the OS transistor in circuit 43, a transistor containing indium and oxygen (for example, one without gallium, or one without zinc, or one without gallium and zinc) may be used. In this case, because the on-current is large, a CMOS configuration can be achieved with a more appropriate transistor size by combining the OS transistor with a p-channel type LTPS transistor.

[0471] Furthermore, when OS transistors are composed of multiple different layers, for example, they may be connected in parallel between different layers. This allows the currents to be added together, thereby increasing the on-current. However, the present invention is not limited to these examples. For example, when OS transistors are composed of multiple different layers, they may be connected in series between different layers. This allows the source-drain voltage of each OS transistor to be reduced. Therefore, the breakdown voltage of the OS transistors can be increased, or the reliability of the OS transistors can be increased, or the off-current of the OS transistors can be reduced.

[0472] Circuit 44 can be driven, for example, using the signal output from circuit 43. Circuit 44 can function, for example, as a level shifter circuit. A level shifter circuit can function, for example, to increase the amplitude of an input signal and output it. This level shifter circuit can be constructed, for example, using a p-channel LTPS transistor and an n-channel OS transistor as transistors formed in different layers. In other words, circuit 44 can be constructed as a CMOS circuit, for example. Therefore, for example, the number of transistors that make up the logic circuit can be reduced. Alternatively, by using a CMOS configuration, for example, the circuit configuration can be simplified. Alternatively, by using a CMOS configuration, for example, power consumption can be reduced. Alternatively, by using a CMOS configuration, for example, the operating voltage can be reduced. Alternatively, by using a CMOS configuration, for example, reliability can be improved.

[0473] Furthermore, as the OS transistor in circuit 44, a transistor containing indium and oxygen (for example, one without gallium, or one without zinc, or one without gallium and zinc) may be used. In this case, because the on-current is large, a CMOS configuration can be achieved with a more appropriate transistor size by combining the OS transistor with a p-channel type LTPS transistor.

[0474] Furthermore, when OS transistors are composed of multiple different layers, for example, they may be connected in parallel between different layers. This allows the currents to be added together, thereby increasing the on-current. However, the present invention is not limited to these examples. For example, when OS transistors are composed of multiple different layers, they may be connected in series between different layers. This allows the source-drain voltage of each OS transistor to be reduced. Therefore, the breakdown voltage of the OS transistors can be increased, or the reliability of the OS transistors can be increased, or the off-current of the OS transistors can be reduced.

[0475] Circuit 45 can be driven, for example, using the signal output from circuit 44. Circuit 45 has the function of a buffer circuit, for example. The buffer circuit has the function of increasing the current of the input signal and outputting it, for example. This buffer circuit can be constructed, for example, using a p-channel LTPS transistor and an n-channel OS transistor as transistors formed in different layers. In other words, circuit 45 can be constructed as a CMOS circuit, for example. Therefore, for example, the number of transistors that make up the logic circuit can be reduced. Alternatively, by using a CMOS configuration, for example, the circuit configuration can be simplified. Alternatively, by using a CMOS configuration, for example, power consumption can be reduced. Alternatively, by using a CMOS configuration, for example, the operating voltage can be reduced. Alternatively, by using a CMOS configuration, for example, reliability can be improved.

[0476] Furthermore, as the OS transistor in circuit 45, a transistor containing indium and oxygen (for example, one without gallium, or one without zinc, or one without gallium and zinc) may be used. In this case, because the on-current is large, a CMOS configuration can be achieved with a more appropriate transistor size by combining the OS transistor with a p-channel type LTPS transistor.

[0477] Furthermore, when OS transistors are composed of multiple different layers, for example, they may be connected in parallel between different layers. This allows the currents to be added together, thereby increasing the on-current. However, the present invention is not limited to these examples. For example, when OS transistors are composed of multiple different layers, they may be connected in series between different layers. This allows the source-drain voltage of each OS transistor to be reduced. Therefore, the breakdown voltage of the OS transistors can be increased, or the reliability of the OS transistors can be increased, or the off-current of the OS transistors can be reduced.

[0478] Next, Figure 19 shows an example of a circuit block included in circuit 35, or a circuit block included in circuit 36. Circuit 35 or circuit 36 ​​includes, for example, circuits 53, 54, and 55. However, one aspect of the present invention is not limited to these. Circuit 35 or circuit 36 ​​does not have to have at least one of circuits 53, 54, and 55. Alternatively, circuit 35 or circuit 36 ​​may have yet another circuit. Alternatively, for example, circuit 35 or circuit 36 ​​may have an output switching circuit (DEMUX). Alternatively, for example, circuit 35 or circuit 36 ​​may have only an output switching circuit (DEMUX).

[0479] In Figure 19, circuits 53, 54, and 55 can be considered, for example, to represent a block of one row of circuits. Alternatively, since Figure 19 is a block diagram, circuits 53, 54, and 55 can be considered, for example, to represent the entire (all rows of) circuit of the display device 70.

[0480] Circuit 53, for example, has the function of a shift register circuit. A shift register circuit, for example, has the function of outputting a signal to select one row at a time. This shift register circuit can be constructed, for example, using a p-channel LTPS transistor and an n-channel OS transistor as transistors formed in different layers. In other words, circuit 53 can be constructed as a CMOS circuit, for example. Therefore, for example, the number of transistors that make up the logic circuit can be reduced. Alternatively, by using a CMOS configuration, for example, the circuit configuration can be simplified. Alternatively, by using a CMOS configuration, for example, power consumption can be reduced. Alternatively, by using a CMOS configuration, for example, the operating voltage can be reduced. Alternatively, by using a CMOS configuration, for example, reliability can be improved.

[0481] Furthermore, as the OS transistor in circuit 53, a transistor containing indium and oxygen (for example, one without gallium, or one without zinc, or one without gallium and zinc) may be used. In this case, because the on-current is large, a CMOS configuration can be achieved with a more appropriate transistor size by combining the OS transistor with a p-channel type LTPS transistor.

[0482] Furthermore, when OS transistors are composed of multiple different layers, for example, they may be connected in parallel between different layers. This allows the currents to be added together, thereby increasing the on-current. However, the present invention is not limited to these examples. For example, when OS transistors are composed of multiple different layers, they may be connected in series between different layers. This allows the source-drain voltage of each OS transistor to be reduced. Therefore, the breakdown voltage of the OS transistors can be increased, or the reliability of the OS transistors can be increased, or the off-current of the OS transistors can be reduced.

[0483] Circuit 54 can be driven, for example, using the signal output from circuit 53. Circuit 54 has the function of a latch circuit, for example. A latch circuit has the function of storing an input signal and then simultaneously outputting the stored signal. This latch circuit can be constructed, for example, using a p-channel LTPS transistor and an n-channel OS transistor as transistors formed in different layers. In other words, circuit 54 can be constructed as a CMOS circuit, for example. Therefore, for example, the number of transistors that make up a logic circuit or analog circuit can be reduced. Alternatively, by using a CMOS configuration, for example, the circuit configuration can be simplified. Alternatively, by using a CMOS configuration, for example, power consumption can be reduced. Alternatively, by using a CMOS configuration, for example, the operating voltage can be reduced. Alternatively, by using a CMOS configuration, for example, reliability can be improved.

[0484] Furthermore, as the OS transistor in circuit 54, a transistor containing indium and oxygen (for example, one without gallium, or one without zinc, or one without gallium and zinc) may be used. In this case, because the on-current is large, a CMOS configuration can be achieved with a more appropriate transistor size by combining the OS transistor with a p-channel type LTPS transistor.

[0485] Furthermore, when OS transistors are composed of multiple different layers, for example, they may be connected in parallel between different layers. This allows the currents to be added together, thereby increasing the on-current. However, the present invention is not limited to these examples. For example, when OS transistors are composed of multiple different layers, they may be connected in series between different layers. This allows the source-drain voltage of each OS transistor to be reduced. Therefore, the breakdown voltage of the OS transistors can be increased, or the reliability of the OS transistors can be increased, or the off-current of the OS transistors can be reduced.

[0486] Circuit 55 can be driven, for example, using the signal output from circuit 44. Circuit 55 has the function of a buffer circuit, for example. The buffer circuit has the function of increasing the current of the input signal and outputting it, for example. This buffer circuit can be constructed, for example, using a p-channel LTPS transistor and an n-channel OS transistor as transistors formed in different layers. In other words, circuit 55 can be constructed as a CMOS circuit, for example. Therefore, for example, the number of transistors that make up the logic circuit can be reduced. Alternatively, by using a CMOS configuration, for example, the circuit configuration can be simplified. Alternatively, by using a CMOS configuration, for example, power consumption can be reduced. Alternatively, by using a CMOS configuration, for example, the operating voltage can be reduced. Alternatively, by using a CMOS configuration, for example, reliability can be improved.

[0487] Furthermore, if the buffer circuit has a source follower circuit, for example, a p-channel LTPS transistor or an n-channel OS transistor may be used as the current source.

[0488] Furthermore, as the OS transistor in circuit 55, a transistor containing indium and oxygen (for example, one without gallium, or one without zinc, or one without gallium and zinc) may be used. In this case, because the on-current is large, a CMOS configuration can be achieved with a more appropriate transistor size by combining the OS transistor with a p-channel type LTPS transistor.

[0489] Furthermore, when OS transistors are composed of multiple different layers, for example, they may be connected in parallel between different layers. This allows the currents to be added together, thereby increasing the on-current. However, the present invention is not limited to these examples. For example, when OS transistors are composed of multiple different layers, they may be connected in series between different layers. This allows the source-drain voltage of each OS transistor to be reduced. Therefore, the breakdown voltage of the OS transistors can be increased, or the reliability of the OS transistors can be increased, or the off-current of the OS transistors can be reduced.

[0490] Next, Figure 20 shows an example of a circuit block included in circuit 35, or a circuit block included in circuit 36. Circuit 35 or circuit 36 ​​may, for example, include circuits 67, 68, and 69. However, one aspect of the present invention is not limited to these. Circuit 35 or circuit 36 ​​may not have at least one of circuits 67, 68, and 69. Alternatively, circuit 35 or circuit 36 ​​may have yet another circuit. Alternatively, for example, circuit 35 or circuit 36 ​​may have an output switching circuit (DEMUX). Alternatively, for example, circuit 35 or circuit 36 ​​may have only an output switching circuit (DEMUX).

[0491] In Figure 20, circuits 67, 68, and 69 can be considered, for example, to represent a block of one row of circuits. Alternatively, since Figure 20 is a block diagram, circuits 67, 68, and 69 can be considered, for example, to represent the entire (all rows of) circuit of the display device 70.

[0492] Circuit 67, for example, has the function of a shift register circuit. A shift register circuit, for example, has the function of outputting a signal to select one row at a time. This shift register circuit can be constructed, for example, using a p-channel LTPS transistor and an n-channel OS transistor as transistors formed in different layers. In other words, circuit 67 can be constructed as a CMOS circuit, for example. Therefore, for example, the number of transistors that make up the logic circuit can be reduced. Alternatively, by using a CMOS configuration, for example, the circuit configuration can be simplified. Alternatively, by using a CMOS configuration, for example, power consumption can be reduced. Alternatively, by using a CMOS configuration, for example, the operating voltage can be reduced. Alternatively, by using a CMOS configuration, for example, reliability can be improved.

[0493] Furthermore, as the OS transistor in circuit 67, a transistor containing indium and oxygen (for example, one without gallium, or one without zinc, or one without gallium and zinc) may be used. In this case, because the on-current is large, a CMOS configuration can be achieved with a more appropriate transistor size by combining the OS transistor with a p-channel type LTPS transistor.

[0494] Furthermore, when OS transistors are composed of multiple different layers, for example, they may be connected in parallel between different layers. This allows the currents to be added together, thereby increasing the on-current. However, the present invention is not limited to these examples. For example, when OS transistors are composed of multiple different layers, they may be connected in series between different layers. This allows the source-drain voltage of each OS transistor to be reduced. Therefore, the breakdown voltage of the OS transistors can be increased, or the reliability of the OS transistors can be increased, or the off-current of the OS transistors can be reduced.

[0495] Circuit 68 can be driven, for example, using the signal output from circuit 67. Circuit 68 also functions as a buffer circuit, for example. A buffer circuit, for example, has the function of increasing the current of an input signal and outputting it. This buffer circuit can be configured, for example, using a p-channel LTPS transistor and an n-channel OS transistor as transistors formed in different layers. In other words, circuit 68 can be configured as a CMOS circuit, for example. Therefore, for example, the number of transistors that make up a logic circuit or an analog circuit can be reduced. Alternatively, by using a CMOS configuration, for example, the circuit configuration can be simplified. Alternatively, by using a CMOS configuration, for example, power consumption can be reduced. Alternatively, by using a CMOS configuration, for example, the operating voltage can be reduced. Alternatively, by using a CMOS configuration, for example, reliability can be improved.

[0496] Furthermore, as the OS transistor in circuit 68, a transistor containing indium and oxygen (for example, one without gallium, or one without zinc, or one without gallium and zinc) may be used. In this case, because the on-current is large, a CMOS configuration can be achieved with a more appropriate transistor size by combining the OS transistor with a p-channel type LTPS transistor.

[0497] Furthermore, when OS transistors are composed of multiple different layers, for example, they may be connected in parallel between different layers. This allows the currents to be added together, thereby increasing the on-current. However, the present invention is not limited to these examples. For example, when OS transistors are composed of multiple different layers, they may be connected in series between different layers. This allows the source-drain voltage of each OS transistor to be reduced. Therefore, the breakdown voltage of the OS transistors can be increased, or the reliability of the OS transistors can be increased, or the off-current of the OS transistors can be reduced.

[0498] Furthermore, if the buffer circuit has a source follower circuit, for example, a p-channel LTPS transistor or an n-channel OS transistor may be used as the current source.

[0499] Circuit 69 can store the signal or current output from the display unit 62. Circuit 55, for example, has the function of a sample-and-hold circuit. A sample-and-hold circuit, for example, has the function of storing an input signal (voltage, current, or charge). This sample-and-hold circuit can be configured, for example, using a p-channel LTPS transistor and an n-channel OS transistor as transistors formed in different layers. In other words, circuit 55 can be configured as a CMOS circuit, for example. Therefore, for example, the number of transistors that make up the circuit can be reduced. Alternatively, by using a CMOS configuration, for example, the circuit configuration can be simplified. Alternatively, by using a CMOS configuration, for example, power consumption can be reduced. Alternatively, by using a CMOS configuration, for example, the operating voltage can be reduced. Alternatively, by using a CMOS configuration, for example, reliability can be improved.

[0500] Furthermore, when OS transistors are composed of multiple different layers, for example, they may be connected in parallel between different layers. This allows the currents to be added together, thereby increasing the on-current. However, the present invention is not limited to these examples. For example, when OS transistors are composed of multiple different layers, they may be connected in series between different layers. This allows the source-drain voltage of each OS transistor to be reduced. Therefore, the breakdown voltage of the OS transistors can be increased, or the reliability of the OS transistors can be increased, or the off-current of the OS transistors can be reduced.

[0501] Furthermore, a transistor containing indium, gallium, zinc, and oxygen may be used as the OS transistor in circuit 69. In this case, since the off-current is small, the charge can be appropriately stored in the capacitive elements of the sample-and-hold circuit.

[0502] When configuring a sample-and-hold circuit, it is sometimes desirable to have a small off-current. In such cases, for example, the circuit may be constructed using only OS transistors. As an example of this, a circuit for one row is shown in Figure 21A. Wiring 91 is connected to the display unit 62, for example. Wiring 92 is connected to circuit 69, for example. A signal is stored in the capacitive element 74 via transistor 81. This signal is supplied to circuit 69 via wiring 92. The charge of the capacitive element 74 is initialized to the potential of wiring 95, for example, using transistor 83. Transistor 81 is controlled by wiring 93. Transistor 83 is controlled by wiring 94. Wirings 93, 94, and 95 are each connected to the sample-and-hold circuit in the adjacent row.

[0503] However, the present invention is not limited to these embodiments. The sample-and-hold circuit may also be configured as a CMOS. As an example of this, a circuit for one row is shown in Figure 21B. A CMOS configuration can be achieved by using p-channel transistors 85 and 87. Wiring 96 is supplied with a signal that is the inverse of that of wiring 93. Wiring 97 is supplied with a signal that is the inverse of that of wiring 94. By using a CMOS configuration, for example, power consumption can be reduced. Alternatively, by using a CMOS configuration, for example, the operating voltage can be reduced. Alternatively, by using a CMOS configuration, for example, reliability can be improved.

[0504] The display device 70 can be mounted on various substrates. For example, the display device 70 can be mounted on a glass substrate. Alternatively, for example, the display device 70 can be mounted on a flexible substrate (e.g., plastic, polyimide, etc.).

[0505] When the display device 70 is mounted on a flexible substrate, its weight can be reduced and it can be made less prone to breakage. For example, the display device 70 can be mounted on portable electronic devices (such as smartphones, smartwatches, and bracelet-type information terminals). Portable devices may require a function to read information (for example, light, finger touch, etc.). In such cases, for example, a sensor element provided on the display device 70 may be used to read some kind of information.

[0506] Furthermore, the display device 70 can be installed not only in portable devices, but also in vehicles, for example. For example, the display device 70 can be installed on the dashboard of a car. In this case, information (for example, light, finger touch, etc.) can be read using the sensor elements provided on the display device 70. For example, by reading the driver's actions, gestures, and state, various actions can be taken. For example, if the driver is in a position where they are likely to fall asleep while driving, the sensor elements provided on the display device 70 can be used to read that information and warn the driver (for example, by displaying a warning on the display device 70). When installing the display device 70 in a vehicle, for example, by installing the display device 70 on a flexible substrate, flexible placement such as conforming to the curved surface of the vehicle becomes possible.

[0507] Furthermore, when a display device 70 is installed on the dashboard of a car, there may be areas where the screen display is refreshed at high speed and areas where the screen display is refreshed at a low speed. For example, the area that is refreshed at high speed may be the part that displays the speedometer. For example, the area that is refreshed at a low speed may be the part that displays the time and the amount of gasoline. In this case, by providing multiple display units 62, circuits 33, 34, 35, 36, etc., the areas that refresh the screen display at high speed and the areas that refresh the screen display at a low speed may be controlled individually.

[0508] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0509] (Embodiment 3) In this embodiment, an example of the configuration of a pixel circuit that can be applied to a display device according to one aspect of the present invention will be described.

[0510] An example of the configuration of pixel 17 is shown in Figure 22A. Pixel 17 has a pixel circuit 15A and a light-emitting element 61.

[0511] The pixel circuit 15A includes transistors 37A and 37B, and a capacitive element 39. The pixel circuit 15A is a 2Tr1C type pixel circuit having two transistors and one capacitive element. The pixel circuit that can be applied to the display device according to one embodiment of the present invention is not particularly limited.

[0512] The anode of the light-emitting element 61 is connected to one of the source and drain of transistor 37B. The other of the source and drain of transistor 37B is connected to one electrode of the capacitive element 39 and to wiring ANO. The gate of transistor 37B is connected to one of the source and drain of transistor 37A and to the other electrode of the capacitive element 39. The region where one of the source and drain of transistor 37A, the gate of transistor 37B, and the other electrode of the capacitive element 39 are connected functions as node FN.

[0513] The source and drain of transistor 37A are connected to wiring SL. The gate of transistor 37A is connected to wiring GL. The cathode of light-emitting element 61 is connected to wiring VCOM.

[0514] Wiring VCOM is a wire that provides a potential for supplying current to the light-emitting element 61. Transistor 37A has the function of controlling the conduction or non-conduction state between wiring SL and the gate of transistor 37B based on the potential of wiring GL. For example, VDD is supplied to wiring ANO and VSS is supplied to wiring VCOM.

[0515] In this specification, the high power supply potential VDD (also simply referred to as "VDD") refers to a power supply potential that is higher than the low power supply potential VSS. The low power supply potential VSS (also simply referred to as "VSS") refers to a power supply potential that is lower than the high power supply potential VDD. Furthermore, the ground potential GND (also simply referred to as "GND") can also be used as VDD or VSS. For example, if VDD is GND, then VSS is at a lower potential than GND, and if VSS is GND, then VDD is at a higher potential than GND.

[0516] Transistor 37A functions as a selection transistor for controlling the selected state of pixel 17. By making transistor 37A conductive, an image signal is supplied from wiring SL to node FN. Subsequently, by making transistor 37A non-conductive, the image signal is held at node FN. To reliably hold the image signal supplied to node FN, it is preferable to use a transistor with a small off-current for transistor 37A. For example, it is preferable to use an OS transistor as transistor 37A.

[0517] Transistor 37B functions as a drive transistor that controls the amount of current flowing to the light-emitting element 61. Capacitive element 39 has the function of maintaining the gate potential of transistor 37B. The intensity of the light emitted by the light-emitting element 61 is controlled according to the image signal supplied to the gate (i.e., node FN) of transistor 37B.

[0518] The pixel circuit 15A shown in Figure 22A has a configuration in which an n-channel transistor is used for transistor 37A and a p-channel transistor is used for transistor 37B. However, the present invention is not limited to this, and an n-channel transistor can be used for transistor 37B, as in the pixel circuit 15A shown in Figure 22B. When an n-channel transistor is used for transistor 37B, one electrode of the capacitive element 39 can be connected to one of the source and drain of transistor 37B.

[0519] The aforementioned semiconductor device can be used in the pixel circuit 15A. This reduces the area occupied by the pixel circuit 15A, enabling a high-resolution display device. It also enables a high-speed display device.

[0520] By using multiple transistors and capacitive elements in a pixel circuit, a high-performance display device can be created. By applying a semiconductor device according to one aspect of the present invention, the occupied area can be reduced even if the number of transistors and capacitive elements increases, resulting in a high-performance and high-resolution display device. For example, a display device with a resolution of 300 ppi or more, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, or 3000 ppi or more can be realized.

[0521] A semiconductor device according to one aspect of the present invention can reduce the occupied area, thereby increasing the aperture ratio of pixels in a display device with a bottom emission structure. For example, a display device with an aperture ratio of 50% or more, 55% or more, or 60% or more can be realized.

[0522] In this specification, the term "aperture ratio" refers to the ratio of the area of ​​the region from which light is emitted to the area of ​​the pixel.

[0523] Figures 22C to 26 show examples of configurations different from those of pixel 17 shown in Figures 22A and 22B.

[0524] The pixel 17 shown in Figures 22C and 22D has a pixel circuit 15B and a light-emitting element 61. The pixel circuit 15B mainly differs from the pixel circuit 15A shown in Figures 22A and 22B in that it has a transistor 37C. The pixel circuit 15B has transistors 37A, 37B, 37C, and a capacitive element 39. The pixel circuit 15B is a 3Tr1C type pixel circuit having three transistors and one capacitive element.

[0525] The pixel circuit 15B shown in Figure 22C has a configuration in which a transistor 37C is added to the pixel circuit 15A shown in Figure 22A. One of the source and drain of transistor 37C is connected to one of the source and drain of transistor 37B. The other of the source and drain of transistor 37C is connected to wiring V0. For example, a reference potential is supplied to wiring V0.

[0526] The gate of transistor 37A is connected to wiring GL1. Wiring GL1 corresponds to wiring GL shown in Figures 22A and 22B. The gate of transistor 37C is connected to wiring GL2. Transistor 37C has the function of controlling the conduction or non-conduction state between the source and drain of transistor 37B and wiring V0 based on the potential of wiring GL2.

[0527] The wiring V0 can be used to obtain current values ​​that can be used to set pixel parameters. Specifically, wiring V0 can function as a monitor line to output the current flowing through transistor 37B or the current flowing through light-emitting element 61 to the outside. The current output to wiring V0 can be converted into a voltage by a source follower circuit and output to the outside. Alternatively, it can be converted into a digital signal by an AD converter and output to the outside.

[0528] As shown in the pixel circuit 15B in Figure 22D, an n-channel transistor can be used for transistor 37B. The pixel circuit 15B shown in Figure 22D has a configuration in which transistor 37C is added to the pixel circuit 15A shown in Figure 22B. When an n-channel transistor is used for transistor 37B, one electrode of the capacitive element 39 can be connected to one of the source and drain of transistor 37B.

[0529] Figures 22C and 22D show an example configuration in which the gates of transistor 37A and transistor 37C are connected to different wirings. This allows the operation of transistor 37A and transistor 37C to be controlled independently. However, the present invention is not limited to this, and as shown in the pixel circuit 15C in Figures 22E and 22F, the gates of transistor 37A and transistor 37C can be connected to the same wiring (here, wiring GL). This reduces the number of wirings and the occupied area of ​​the pixel circuit.

[0530] The pixel 17 shown in Figures 23A and 23B has a pixel circuit 15D and a light-emitting element 61. The pixel circuit 15D mainly differs from the pixel circuit 15B shown in Figures 22C and 22D in that it has a transistor 37D. The pixel circuit 15D has transistors 37A, 37B, 37C, 37D, and a capacitive element 39. The pixel circuit 15D is a 4Tr1C type pixel circuit having four transistors and one capacitive element.

[0531] The pixel circuit 15D shown in Figure 23A has a configuration in which a transistor 37D is added to the pixel circuit 15C shown in Figure 22C. One of the source and drain of transistor 37D is connected to wiring ANO. The other of the source and drain of transistor 37D is connected to one of the source and drain of transistor 37A, the other electrode of the capacitive element 39, and the gate of transistor 37B. The region where the other of the source and drain of transistor 37D, one of the source and drain of transistor 37A, the other electrode of the capacitive element 39, and the gate of transistor 37B are connected functions as node FN.

[0532] The gate of transistor 37A is connected to wiring GL1, the gate of transistor 37C is connected to wiring GL2, and the gate of transistor 37D is connected to wiring GL3.

[0533] In the pixel circuit 15D shown in Figure 23A, by making transistor 37D conductive, the source and gate of transistor 37B become at the same potential, making transistor 37B non-conductive. This allows the current flowing to the light-emitting element 61 to be forcibly interrupted. Such a pixel circuit is suitable when using a display method that alternates between display periods and off periods. It is also possible to make transistor 37C conductive at the same time as making transistor 37D conductive.

[0534] Figure 23A shows an example configuration in which a p-channel transistor is used for transistor 37B, but the present invention is not limited to this. In addition to transistor 37B, one or more p-channel transistors can also be used for transistors 37A, 37C, and 37D.

[0535] As shown in the pixel circuit 15D in Figure 23B, an n-channel transistor can be used for the transistor 37B. The pixel circuit 15D shown in Figure 23B has a configuration in which the transistor 37D is added to the pixel circuit 15B shown in Figure 22D.

[0536] The pixel 17 shown in Figures 23C and 23D has a pixel circuit 15E and a light-emitting element 61. The pixel circuit 15E mainly differs from the pixel circuit 15D shown in Figures 23A and 23B in that it has a capacitive element 39A. The pixel circuit 15E has transistors 37A, 37B, 37C, 37D, a capacitive element 39, and a capacitive element 39A. The pixel circuit 15E is a 4Tr2C type pixel circuit having four transistors and two capacitive elements.

[0537] The pixel circuit 15E shown in Figure 23C has a configuration in which a capacitive element 39A is added to the pixel circuit 15D shown in Figure 23A. One electrode of the capacitive element 39A is connected to one electrode of the source and drain of transistor 37B, and the other electrode is connected to the gate of transistor 37B. Capacitive elements 39 and 39A each function as retaining capacitors. The region where the other electrode of the source and drain of transistor 37D, one electrode of the source and drain of transistor 37A, the other electrode of the capacitive element 39, the other electrode of the capacitive element 39A, and the gate of transistor 37B are connected functions as node FN.

[0538] As shown in the pixel circuit 15E in Figure 23D, an n-channel transistor can be used for the transistor 37B. The pixel circuit 15E shown in Figure 23D has a configuration in which a capacitive element 39A is added to the pixel circuit 15D shown in Figure 23B. One electrode of the capacitive element 39A is connected to wiring ANO, and the other electrode is connected to the gate of transistor 37B.

[0539] The pixel 17 shown in Figure 24A has a pixel circuit 15F and a light-emitting element 61. The pixel circuit 15F has transistors 37A, 37B, 37C, 37D, 37E, 37F and a capacitive element 39. The pixel circuit 15F is a 6Tr1C type pixel circuit having six transistors and one capacitive element.

[0540] The anode of the light-emitting element 61 is connected to one of the source and drain of transistor 37C, one of the source and drain of transistor 37F, and one electrode of the capacitive element 39. The other source and drain of transistor 37F is connected to one of the source and drain of transistor 37A, and one of the source and drain of transistor 37B. The gate of transistor 37B is connected to one of the source and drain of transistor 37E, and the other electrode of the capacitive element 39. The other source and drain of transistor 37B is connected to the other source and drain of transistor 37E, and one of the source and drain of transistor 37D. The region where the gate of transistor 37B, one of the source and drain of transistor 37E, and the other electrode of the capacitive element 39 are connected functions as node FN.

[0541] The source and the other drain of transistor 37A are connected to wiring SL, and the gate is connected to wiring GL1. The source and the other drain of transistor 37D are connected to wiring ANO, and the gate is connected to wiring GL2. The gate of transistor 37F is connected to wiring GL3. The gate of transistor 37E is connected to wiring GL4. The source and the other drain of transistor 37C are connected to wiring V0, and the gate is connected to wiring GL4. The cathode of the light-emitting element 61 is connected to wiring VCOM.

[0542] Figure 24A shows an example configuration in which n-channel transistors are used for transistors 37A to 37F. For example, a Si transistor can be used for transistor 37B, which functions as a drive transistor, and OS transistors can be used for transistors 37A and 37C to 37F. In particular, it is preferable to use an OS transistor for transistor 37E in order to reliably hold the image signal supplied to node FN.

[0543] A back gate can be provided for some or all of the transistors included in the pixel circuit. When a back gate is provided, it can be configured to receive the same signal as the gate, or to receive a different signal from the gate.

[0544] As shown in Figure 24B, transistor 37B can be configured to have a back gate. The back gate of transistor 37B can be connected to the gate of transistor 37B, or to either the source or drain of transistor 37B. As shown in Figure 24B, the reliability can be improved by connecting the back gate of transistor 37B to either the source or drain of transistor 37B. Alternatively, the back gate of transistor 37B can be connected to the gate of transistor 37B. This allows for a larger on-current of transistor 37B.

[0545] Figure 25A shows a pixel circuit 15F using a p-channel transistor for transistor 37B. The pixel circuit 15F shown in Figure 25A differs from the pixel circuit 15F shown in Figure 24A in the connections of transistor 37A, transistor 37E, and the capacitive element 39. In the pixel circuit 15F shown in Figure 25A, one source and drain of transistor 37A is connected to the other source and drain of transistor 37B, and one source and drain of transistor 37D. One electrode of the capacitive element 39 is connected to the other source and drain of transistor 37D. The other sourc...

Claims

1. A display device comprising a circuit section and a display section, wherein the circuit section has a region overlapping with the display section, the circuit section comprises a first transistor, a second transistor, a first insulating layer, and a second insulating layer, the display section comprises a third transistor, the first transistor has a first semiconductor layer, the second transistor has a second semiconductor layer, the third transistor has a third semiconductor layer, the first insulating layer is located on the first semiconductor layer, the second semiconductor layer is located on the first insulating layer, the second insulating layer is located on the second semiconductor layer, the third semiconductor layer is located on the second insulating layer, the first semiconductor layer has polycrystalline silicon, and the second and third semiconductor layers each have indium oxide.

2. The display device according to claim 1, wherein the second semiconductor layer and the third semiconductor layer each have crystal grains, and the particle size of the crystal grains is 0.3 μm or larger.

3. The display device according to claim 1, wherein the second semiconductor layer and the third semiconductor layer each comprise a first metal oxide layer, a second metal oxide layer on the first metal oxide layer, and a third metal oxide layer on the second metal oxide layer, and the second metal oxide layer has a region in which the hydrogen concentration is higher than that of the first metal oxide layer and the third metal oxide layer, respectively.

4. In claim 3, the second metal oxide layer has a hydrogen concentration of 5 × 10 ２０ atoms / cm ３ The above 5 x 10 ２１ atoms / cm ３ A display device having the following regions, wherein the first metal oxide layer and the third metal oxide layer each have regions in which the hydrogen concentration is 1 / 100 or more and 1 / 8 or less of the hydrogen concentration in the second metal oxide layer.

5. The display device according to claim 3, wherein the second metal oxide layer has regions with a lower film density than the first metal oxide layer and the third metal oxide layer, respectively.

6. The display device according to claim 3, wherein the thickness of the second metal oxide layer is greater than the thickness of the first metal oxide layer and the thickness of the third metal oxide layer, respectively.

7. The display device according to claim 3, wherein the thickness of the second metal oxide layer is 1 nm or more and 30 nm or less, and the thicknesses of the first metal oxide layer and the third metal oxide layer are each 0.5 nm or more and 10 nm or less.

8. A display device according to any one of claims 1 to 7, wherein one or both of the first semiconductor layer and the second semiconductor layer have a region that overlaps with the third semiconductor layer.

9. A display device according to any one of claims 1 to 7, wherein the first insulating layer is an organic insulating layer, and the second insulating layer is an organic insulating layer.

10. A display device according to any one of claims 1 to 7, wherein the first insulating layer is an inorganic insulating layer and the second insulating layer is an organic insulating layer.

11. A display device according to any one of claims 1 to 7, wherein the circuit section is located between the substrate and the display section, and the substrate is translucent.

12. The display device according to claim 11, wherein the substrate is a glass substrate.

13. A display device according to any one of claims 1 to 7, comprising a substrate, wherein the circuit section is located between the substrate and the display section, and the substrate is flexible.

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