Display panel and manufacturing method therefor, and display device

Abstract

The present disclosure provides a display panel and a manufacturing method therefor, and a display device. The display panel comprises a base substrate and a plurality of sub-pixels disposed on the base substrate; each sub-pixel comprises a sub-pixel driving circuit and a transparent anode layer coupled to each other, and the transparent anode layer is located on the side of the sub-pixel driving circuit facing away from the base substrate; at least part of the sub-pixels further comprises a distributed Bragg reflector and a reflective layer, the distributed Bragg reflector is located between the transparent anode layer and the base substrate, and the reflective layer is located on the side of the distributed Bragg reflector facing the base substrate.

Description

Display panel and its manufacturing method, display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display panel, a method for manufacturing the same, and a display device. Background Technology

[0002] With the continuous development of display technology, the application fields of display products are becoming increasingly wide, which in turn puts forward higher requirements for the performance of display products in all aspects. Taking Organic Light-Emitting Diode (OLED) display products as an example, with the diversified expansion of OLED display product application fields, the demand for high-end OLED display products is growing rapidly, thus placing higher demands on the display brightness performance of OLED display products. Summary of the Invention

[0003] The purpose of this disclosure is to provide a display panel, a method for manufacturing the same, and a display device.

[0004] To achieve the above objectives, this disclosure provides the following technical solution:

[0005] A first aspect of this disclosure provides a display panel, comprising: a substrate and a plurality of sub-pixels disposed on the substrate, each sub-pixel including a sub-pixel driving circuit coupled to a transparent anode layer, the transparent anode layer being located on the side of the sub-pixel driving circuit facing away from the substrate; at least some of the sub-pixels further comprising:

[0006] A distributed Bragg reflector, wherein the distributed Bragg reflector is located between the transparent anode layer and the substrate.

[0007] A reflective layer is located on the side of the distributed Bragg mirror facing the substrate.

[0008] Optionally, the reflective layer is coupled to a fixed voltage signal input terminal.

[0009] Optionally, the display panel includes a display area and a peripheral area surrounding the display area; the fixed voltage signal input terminal is located in the peripheral area; the reflective layers included in different sub-pixels are coupled to form a whole reflective layer, and the whole reflective layer is coupled to the fixed voltage signal input terminal.

[0010] Optionally, in at least some of the sub-pixels, the transparent anode layer is coupled to the sub-pixel driving circuit through the reflective layer.

[0011] Optionally, in at least a portion of the sub-pixels, the reflective layer is coupled to the sub-pixel driving circuit via a first via, the first via penetrating an insulating layer located between the reflective layer and the sub-pixel driving circuit; the transparent anode layer is coupled to the reflective layer via a second via, the second via penetrating the distributed Bragg mirror; the orthographic projection of the second via on the substrate does not overlap with the orthographic projection of the first via on the substrate.

[0012] Optionally, in at least some of the sub-pixels, the reflective layer is coupled to the sub-pixel driving circuit through a first via, the first via penetrating an insulating layer located between the reflective layer and the sub-pixel driving circuit;

[0013] The orthographic projection of the distributed Bragg reflector on the substrate is located inside the orthographic projection of the transparent anode layer on the substrate, and also inside the orthographic projection of the reflective layer on the substrate; the transparent anode layer overlaps with the reflective layer around the periphery of the distributed Bragg reflector.

[0014] Optionally, the sub-pixel driving circuit includes a driving transistor and a storage capacitor, wherein the first plate of the storage capacitor is coupled to the gate of the driving transistor, and the second plate of the storage capacitor is coupled to the second electrode of the driving transistor; the second electrode of the driving transistor is coupled to the transparent anode layer.

[0015] The reflective layer is coupled to the gate of the driving transistor, and the orthographic projection of the reflective layer on the substrate overlaps at least partially with the orthographic projection of the transparent anode layer on the substrate.

[0016] Optionally, the reflective layer is reused as the first electrode plate, and the transparent anode layer is reused as the second electrode plate.

[0017] Optionally, the gate of the driving transistor is reused as the first electrode plate, and the second electrode plate is disposed in the same layer and with the same material as the second gate metal layer in the display panel.

[0018] Optionally, the display panel includes sub-pixels of multiple colors, and at least one color sub-pixel includes the distributed Bragg reflector and the reflective layer.

[0019] Optionally, the display panel includes sub-pixels of multiple colors, and the distributed Bragg reflectors of different colors have different refractive indices.

[0020] Optionally, the display panel includes sub-pixels of multiple colors, and at least some of the sub-pixels of different colors include distributed Bragg reflectors of different thicknesses.

[0021] Optionally, the display panel includes red sub-pixels, green sub-pixels, and blue sub-pixels; the thickness of the distributed Bragg reflector included in the red sub-pixel is greater than the thickness of the distributed Bragg reflector included in the green sub-pixel; the thickness of the distributed Bragg reflector included in the green sub-pixel is greater than the thickness of the distributed Bragg reflector included in the blue sub-pixel.

[0022] Optionally, the display panel includes red sub-pixels, green sub-pixels, and blue sub-pixels; the thickness of the distributed Bragg reflector included in the red sub-pixel is greater than the thickness of the distributed Bragg reflector included in the green sub-pixel; the green sub-pixel and the blue sub-pixel include the same distributed Bragg reflector.

[0023] Optionally, the reflective layer may include a transparent film layer or a metallic reflective layer.

[0024] Optionally, the reflective layer includes a transparent film layer and a metal reflective layer stacked together, with the metal reflective layer located between the transparent film layer and the transparent anode layer.

[0025] Based on the above-described display panel technical solution, a second aspect of this disclosure provides a display device including the above-described display panel.

[0026] Based on the above-described display panel technical solution, a third aspect of this disclosure provides a method for manufacturing a display panel, the method comprising the step of fabricating at least some sub-pixels on a substrate, the step specifically including:

[0027] Fabricate sub-pixel driving circuits on a substrate.

[0028] A reflective layer is fabricated on the side of the sub-pixel driving circuit that faces away from the substrate.

[0029] A distributed Bragg reflector is fabricated on the side of the reflective layer facing away from the substrate.

[0030] A transparent anode layer is fabricated on the side of the distributed Bragg reflector facing away from the substrate, and the transparent anode layer is coupled to the sub-pixel driving circuit.

[0031] Optionally, the manufacturing method specifically includes:

[0032] A reflective material layer is deposited to form a reflective layer, and a patterning process is performed on the reflective material layer to form the reflective layer;

[0033] A distributed Bragg reflector layer is deposited to form a distributed Bragg reflector layer, and a patterning process is performed on the distributed Bragg reflector layer to form the distributed Bragg reflector mirror.

[0034] A transparent anode material layer is deposited and patterned to form the transparent anode layer.

[0035] Optionally, the manufacturing method specifically includes:

[0036] Deposition forms a reflective material layer;

[0037] A distributed Bragg reflector layer is deposited to form a distributed Bragg reflector layer, and a patterning process is performed on the distributed Bragg reflector layer to form the distributed Bragg reflector mirror.

[0038] A transparent anode material layer is deposited, and a patterning process is performed to simultaneously form the reflective layer and the transparent anode layer. Attached Figure Description

[0039] The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this disclosure, illustrate exemplary embodiments of the present disclosure and are used to explain the disclosure, but do not constitute an undue limitation of the disclosure. In the drawings:

[0040] Figure 1 is a first cross-sectional schematic diagram of three color sub-pixels in a display panel provided in an embodiment of this disclosure;

[0041] Figures 2 to 6 are schematic diagrams of the fabrication process of the blue sub-pixels in the structure corresponding to Figure 1;

[0042] Figure 7 is a second cross-sectional schematic diagram of the three color sub-pixels in the display panel provided in an embodiment of this disclosure;

[0043] Figure 8 is a third cross-sectional schematic diagram of the three color sub-pixels in the display panel provided in the embodiment of this disclosure;

[0044] Figure 9 is a fourth cross-sectional schematic diagram of the three color sub-pixels in the display panel provided in the embodiment of this disclosure;

[0045] Figure 10 is a fifth cross-sectional schematic diagram of the three color sub-pixels in the display panel provided in the embodiment of this disclosure;

[0046] Figure 11 is a sixth cross-sectional schematic diagram of the three color sub-pixels in the display panel provided in the embodiment of this disclosure;

[0047] Figure 12 is a seventh cross-sectional schematic diagram of the three color sub-pixels in the display panel provided in the embodiment of this disclosure;

[0048] Figure 13 is an eighth cross-sectional schematic diagram of the three color sub-pixels in the display panel provided in the embodiment of this disclosure;

[0049] Figure 14 is a schematic diagram of the circuit principle of the sub-pixel driving circuit provided in the embodiment of this disclosure. Detailed Implementation

[0050] To further illustrate the display panel, its manufacturing method, and the display device provided in the embodiments of this disclosure, a detailed description is provided below with reference to the accompanying drawings.

[0051] Currently, higher requirements are being placed on the display brightness performance of display products. Therefore, how to improve the display brightness of display products has become an urgent technical problem to be solved.

[0052] Please refer to Figures 8 to 13. This disclosure provides a display panel, including: a substrate 10 and a plurality of sub-pixels disposed on the substrate 10. Each sub-pixel includes a sub-pixel driving circuit (e.g., including TFT1 and TFT2) coupled to each other and a transparent anode layer (e.g., a transparent anode layer Ano-R for a red sub-pixel, a transparent anode layer Ano-G for a green sub-pixel, and a transparent anode layer Ano-B for a blue sub-pixel). The transparent anode layer is located on the side of the sub-pixel driving circuit facing away from the substrate 10. At least some of the sub-pixels further include:

[0053] Distributed Bragg reflectors (e.g., distributed Bragg reflectors DBR-R included in red subpixels, distributed Bragg reflectors DBR-G included in green subpixels, and distributed Bragg reflectors DBR-B included in blue subpixels), wherein the distributed Bragg reflectors are located between the transparent anode layer and the substrate 10.

[0054] A reflective layer 30 is located on the side of the distributed Bragg mirror facing the substrate 10.

[0055] It should be noted that Figures 1 to 13 also illustrate: light-shielding layer LS, first buffer layer BUF1, first active layer Poly, first gate insulating layer GI1, first gate metal layer Gate1, second gate insulating layer GI2, second gate metal layer Gate2, second buffer layer BUF2, second active layer IGZO, third gate insulating layer GI3, third gate metal layer Gate3, interlayer insulating layer ILD, source / drain metal layer SD, planarization layer PLN, and pixel boundary layer PDL.

[0056] For example, the display panel further includes a pixel delimiting layer (PDL), which defines a plurality of pixel opening areas, each of which corresponds to a sub-pixel and is the effective light-emitting area of ​​the corresponding sub-pixel.

[0057] For example, the sub-pixel includes a sub-pixel driving circuit and a light-emitting element. The light-emitting element includes a transparent anode layer, a light-emitting functional layer, and a cathode layer sequentially stacked along a direction away from the substrate 10. The transparent anode layer is coupled to the sub-pixel driving circuit and receives a driving signal provided by the sub-pixel driving circuit. The light-emitting functional layer realizes the light-emitting function under the combined action of the transparent anode layer and the cathode layer. For example, the cathode layer included in each light-emitting element can be formed as a single, integral cathode layer.

[0058] For example, the orthographic projection of the pixel opening area corresponding to the sub-pixel on the substrate 10 is located inside the orthographic projection of the transparent anode layer included in the sub-pixel on the substrate 10; the orthographic projection of the pixel opening area corresponding to the sub-pixel on the substrate 10 is located inside the orthographic projection of the light-emitting functional layer included in the sub-pixel on the substrate 10; and the orthographic projection of the pixel opening area corresponding to the sub-pixel on the substrate 10 is located inside the orthographic projection of the cathode layer included in the sub-pixel on the substrate 10.

[0059] For example, at least some of the sub-pixels also include a Distributed Bragg Reflector (DBR), which is used to reflect light of a specific wavelength. It consists of multiple alternating layers of materials with different refractive indices, forming an optical structure that causes interference of light waves at specific wavelengths, thereby achieving efficient reflection. By using DBRs of different thicknesses and parameters for sub-pixels of different colors, the reflectivity of the DBR to the light emitted by its corresponding sub-pixel can be increased to over 99%.

[0060] For example, the distributed Bragg reflector is located on the side of the sub-pixel driving circuit facing away from the substrate 10; the orthographic projection of the pixel opening area corresponding to the sub-pixel on the substrate 10 is located inside the orthographic projection of the distributed Bragg reflector included in the sub-pixel on the substrate 10.

[0061] For example, at least some of the sub-pixels also include a reflective layer 30, which has a reflectivity of more than 91% in the visible light band, for example, between 91% and 97%, but is not limited thereto. The reflective layer 30 is used to reflect light passing through the distributed Bragg mirror.

[0062] For example, the reflective layer 30 is located on the side of the sub-pixel driving circuit that faces away from the substrate 10; the orthographic projection of the pixel opening area corresponding to the sub-pixel on the substrate 10 is located inside the orthographic projection of the reflective layer 30 included in the sub-pixel on the substrate 10.

[0063] It is worth noting that since the sub-pixel includes both the distributed Bragg reflector and the reflective layer 30, the light emitted by the sub-pixel is reflected not only by the distributed Bragg reflector but also by the reflective layer 30. Therefore, the thickness of the distributed Bragg reflector in each sub-pixel can be appropriately reduced, thereby reducing the step difference between different sub-pixels.

[0064] As can be seen from the specific structure of the display panel described above, in the display panel provided in this embodiment, at least some sub-pixels include distributed Bragg reflectors and a reflective layer 30. The reflective layer 30, the distributed Bragg reflectors, and the transparent anode layer are stacked sequentially along a direction away from the substrate 10. The orthographic projection of the pixel opening area corresponding to the sub-pixel onto the substrate 10 is located inside the orthographic projection of the distributed Bragg reflector onto the substrate 10, and inside the orthographic projection of the reflective layer 30 onto the substrate 10. This arrangement enables the distributed Bragg reflector and the reflective layer 30 to achieve a reflectivity of over 99% for the light emitted by their respective sub-pixels, thereby effectively improving the brightness of the display panel, reducing the power consumption of the display panel, and extending the service life of the display panel.

[0065] Meanwhile, the sub-pixels are configured to include a transparent anode layer, so that the light reflected by the distributed Bragg reflector and the reflective layer 30 can pass through the transparent anode layer to a greater extent, further improving the light efficiency of the display panel.

[0066] As shown in Figure 8, in some embodiments, the reflective layer 30 is coupled to a fixed voltage signal input terminal.

[0067] For example, the fixed voltage signal input to the fixed voltage signal input terminal may include a common voltage signal, but is not limited to this.

[0068] For example, at least some of the sub-pixels include the reflective layer 30, which is coupled to the fixed voltage signal input terminal.

[0069] For example, the display panel includes a display area and a peripheral area surrounding the display area; the fixed voltage signal input terminal is located in the peripheral area; the reflective layers 30 included in different sub-pixels are coupled to form a whole reflective layer 30, and the whole reflective layer 30 is coupled to the fixed voltage signal input terminal. For example, the reflective layers 30 included in different sub-pixels are formed into a single structure, but it is not limited to this.

[0070] For example, after fabricating the multiple sub-pixel driving circuits, a planarization layer is fabricated that completely covers the multiple sub-pixel driving circuits; then a reflective material layer is deposited and patterned using a patterning process to form the reflective layer 30.

[0071] More specifically, the patterning process includes the following steps: a photoresist layer is formed on the side of the reflective material layer facing away from the substrate 10; the photoresist layer is exposed using a mask to form a photoresist retention area and a photoresist removal area. The photoresist retention area corresponds to the area where the reflective layer 30 is located, and the photoresist removal area corresponds to other areas besides the area where the reflective layer 30 is located. The photoresist in the photoresist removal area is removed by development, and the photoresist in the photoresist retention area is retained. The reflective material layer is etched using the photoresist in the photoresist retention area as a mask to form the reflective layer 30. Finally, the remaining photoresist is removed.

[0072] For example, the reflective layer 30 can be made of a highly reflective metallic material, such as Ag metal, Al metal, etc., but is not limited to this.

[0073] The above-described configuration couples the reflective layer 30 to the fixed voltage signal input terminal, making the reflective layer 30 a shielding layer with a fixed voltage. This shields the crosstalk between the signal lines below it and the transparent anode layer, thereby effectively improving the stability of the sub-pixel driving circuit.

[0074] As shown in Figures 1 to 8, in some embodiments, in at least a portion of the sub-pixels, the transparent anode layer is coupled to the sub-pixel driving circuit through a via through the distributed Bragg mirror and the planarization layer PLN.

[0075] As shown in Figures 1 to 7, when the transparent anode layer is coupled to the sub-pixel driving circuit in the above manner, the specific fabrication process of the sub-pixel is as follows:

[0076] As shown in Figure 2, after fabricating an array of multiple sub-pixel driving circuits on the substrate 10, a planarization layer PLN is fabricated, which covers the multiple sub-pixel driving circuits.

[0077] As shown in Figures 2 and 3, a reflector material layer DBR-B', which is included in the blue sub-pixel, is deposited on the side of the planarization layer PLN facing away from the substrate 10. Then, a via is made through the reflector material layer DBR-B' and the planarization layer PLN using a mask. This via exposes the connection terminal 22 of the sub-pixel driving circuit included in the blue sub-pixel. It is worth noting that this via can be formed into a via structure using a single mask; alternatively, two masks can be used to form two connected sub-vias, i.e., one sub-via penetrates the planarization layer and the other sub-via penetrates the distributed Bragg mirror. In the case of using two masks, each sub-via corresponds to one mask.

[0078] As shown in Figure 4, a transparent anode material layer Ano-B' is deposited to form a blue sub-pixel, and the transparent anode material layer Ano-B' is coupled to the connection terminal 22 of the sub-pixel driving circuit through the via.

[0079] As shown in Figure 5, the transparent anode material layer Ano-B' is patterned using a mask to form the transparent anode layer Ano-B included in the blue sub-pixel.

[0080] As shown in Figure 6, the transparent anode layer Ano-B included in the blue sub-pixel is used as a mask to pattern the reflector material layer DBR-B', forming the distributed Bragg reflector DBR-B included in the blue sub-pixel.

[0081] The above steps complete the fabrication of the distributed Bragg reflector and transparent anode layer on the blue sub-pixel. The fabrication steps for the distributed Bragg reflector and transparent anode layer in the red and green sub-pixels are the same as those for the blue sub-pixel. The fabrication order of the distributed Bragg reflector and transparent anode layer in the three sub-pixels can be adjusted.

[0082] As shown in Figures 9 to 12, in some embodiments, in at least some of the sub-pixels, the transparent anode layer is coupled to the sub-pixel driving circuit through the reflective layer 30.

[0083] For example, the transparent anode layer is not directly coupled to the sub-pixel driving circuit, but is indirectly coupled to the sub-pixel driving circuit through the reflective layer 30.

[0084] The above configuration connects the transparent anode layer and the sub-pixel driving circuit through the intermediate reflective layer 30, avoiding the large step difference formed by the transparent anode layer directly connecting to the lower sub-pixel driving circuit. This not only improves the stability of the electrical connection but also helps to reduce the difficulty of the manufacturing process.

[0085] As shown in Figure 9, in some embodiments, in at least a portion of the sub-pixels, the reflective layer 30 is coupled to the sub-pixel driving circuit through a first via, the first via penetrating an insulating layer located between the reflective layer 30 and the sub-pixel driving circuit; the transparent anode layer is coupled to the reflective layer 30 through a second via, the second via penetrating the distributed Bragg mirror; the orthographic projection of the second via on the substrate 10 does not overlap with the orthographic projection of the first via on the substrate 10.

[0086] For example, the insulating layer includes a planarization layer, but is not limited to this.

[0087] When creating sub-pixels with the above connection method, the following two methods can be used:

[0088] Method 1: After fabricating the planarization layer, firstly fabricate the first via corresponding to each sub-pixel (such as red sub-pixel, green sub-pixel, and blue sub-pixel) through the planarization layer; then deposit a reflective material layer, which is coupled to the corresponding sub-pixel driving circuit through the first via; perform a patterning process on the reflective material layer to form the reflective layer 30 included in each sub-pixel; then fabricate the distributed Bragg reflector and transparent anode layer included in each sub-pixel.

[0089] Method 2: After fabricating the planarization layer, firstly, a first via hole is fabricated through the planarization layer corresponding to each sub-pixel (e.g., red, green, and blue sub-pixels). Then, a reflective material layer is deposited, which is coupled to the corresponding sub-pixel driving circuit through the first via hole. Next, a blue sub-pixel including a distributed Bragg mirror with a second via hole is fabricated. Then, a transparent anode material layer is deposited, which is coupled to the reflective material layer through the second via hole. The transparent anode material layer and the reflective material layer are patterned simultaneously in a single patterning process to form the transparent anode layer and the reflective layer 30 in the blue sub-pixel. The reflective layer 30, distributed Bragg mirror, and transparent anode layer on the red and green sub-pixels are also fabricated using the same steps. This method saves on the number of masks compared to the first method.

[0090] The above configuration connects the transparent anode layer and the sub-pixel driving circuit through the intermediate reflective layer 30, avoiding the large step difference formed by the transparent anode layer directly connecting to the lower sub-pixel driving circuit. This not only improves the stability of the electrical connection but also helps to reduce the difficulty of the manufacturing process.

[0091] As shown in Figure 10, in some embodiments, in at least a portion of the sub-pixels, the reflective layer 30 is coupled to the sub-pixel driving circuit through a first via, the first via penetrating an insulating layer located between the reflective layer 30 and the sub-pixel driving circuit; the orthographic projection of the distributed Bragg reflector on the substrate 10 is located inside the orthographic projection of the transparent anode layer on the substrate 10, and also inside the orthographic projection of the reflective layer 30 on the substrate 10; the transparent anode layer overlaps with the reflective layer 30 around the periphery of the distributed Bragg reflector.

[0092] For example, the orthographic projection of the edge portion of the transparent anode layer on the substrate 10 surrounds the orthographic projection of the distributed Bragg reflector on the substrate 10; the orthographic projection of the edge portion of the reflective layer 30 on the substrate 10 surrounds the orthographic projection of the distributed Bragg reflector on the substrate 10.

[0093] When fabricating the sub-pixels with the above connection method, after depositing the reflective material layer, the reflective material layer is not patterned first. Instead, a mirror material layer is directly deposited. Then, the mirror material layer is patterned using a mask to form the distributed Bragg mirror. Note that there is no need to form a via through the distributed Bragg mirror here. Then, a transparent anode material layer is deposited. The transparent anode material layer and the reflective material layer are etched in one step using a mask to form the transparent anode layer and the reflective layer 30. The transparent anode layer overlaps with the reflective layer 30 around the distributed Bragg mirror.

[0094] The above configuration connects the transparent anode layer and the sub-pixel driving circuit through the intermediate reflective layer 30, avoiding the large step difference formed by the transparent anode layer directly connecting to the lower sub-pixel driving circuit. This not only improves the stability of the electrical connection but also simplifies the process and reduces the manufacturing difficulty.

[0095] As shown in Figures 13 and 14, in some embodiments, the sub-pixel driving circuit includes a driving transistor M3 (i.e., TFT1) and a storage capacitor Cst. The first plate of the storage capacitor Cst is coupled to the gate 21 of the driving transistor M3, and the second plate of the storage capacitor Cst is coupled to the second electrode 22 of the driving transistor M3. The second electrode 22 of the driving transistor M3 is coupled to the transparent anode layer.

[0096] The reflective layer 30 is coupled to the gate 21 of the driving transistor M3, and the orthographic projection of the reflective layer 30 on the substrate 10 at least partially overlaps with the orthographic projection of the transparent anode layer on the substrate 10.

[0097] For example, the reflective layer 30 and the gate 21 of the driving transistor M3 are electrically connected through a via that penetrates the insulating layer between the reflective layer 30 and the gate of the driving transistor M3.

[0098] For example, as shown in FIG14, the sub-pixel driving circuit includes a driving transistor M3, a storage capacitor Cst, a data writing transistor M1, and a sensing transistor M2; the first terminal of the driving transistor M3 is coupled to the power signal input terminal, the gate of the driving transistor M3 (i.e., the first node N1) is coupled to the second terminal of the data writing transistor M1, the gate of the data writing transistor M1 is coupled to the scan signal input terminal Gate, and the first terminal of the data writing transistor M1 is coupled to the data signal input terminal Data; the second terminal of the driving transistor M3 is coupled to the transparent anode layer (i.e., the second node N2) of the light-emitting element, and the cathode layer of the light-emitting element receives the VSS signal; the gate of the sensing transistor M2 is coupled to the scan signal input terminal Gate, the first terminal of the sensing transistor M2 is coupled to the sensing signal input terminal SENS, and the second terminal of the sensing transistor M2 is coupled to the transparent anode layer; the first plate of the storage capacitor Cst is coupled to the gate of the driving transistor M3, and the second plate of the storage capacitor Cst is coupled to the second terminal of the driving transistor M3.

[0099] It should be noted that in source-following sub-pixel driving circuits, such as the aforementioned 3T1C (including 3 transistors and 1 capacitor) source-following circuit, a storage capacitor Cst exists between the transparent anode layer and the gate of the driving transistor M3. When the first and second gate metal layers are used to form the plates of the storage capacitor, the area of ​​the storage capacitor Cst is small when the PPI of the display panel is high, resulting in an excessively small capacitance value. Furthermore, since the storage capacitor Cst is located in a relatively central position on the driving backplane, it is more susceptible to crosstalk from signals from other layers, causing adverse effects.

[0100] In the display panel provided in the above embodiment, the reflective layer 30 is coupled to the gate of the driving transistor M3. The orthographic projection of the reflective layer 30 on the substrate 10 overlaps at least partially with the orthographic projection of the transparent anode layer on the substrate 10, thereby forming an auxiliary capacitor structure between the reflective layer 30 and the transparent anode layer. On the one hand, this auxiliary capacitor structure is equivalent to increasing the size of the storage capacitor. On the other hand, this auxiliary capacitor structure is located relatively above the driving backplate (i.e., on the side away from the substrate 10), and is relatively far away from other signal layers, so it is less affected by crosstalk and makes the circuit more resistant to interference.

[0101] In some embodiments, the reflective layer 30 is reused as the first electrode plate, and the transparent anode layer is reused as the second electrode plate.

[0102] The above configuration can remove the plates of the storage capacitor Cst formed by the second gate metal layer, that is, only the capacitor structure formed by the reflective layer 30 and the transparent anode layer is used as the storage capacitor Cst. This not only ensures the storage function of the storage capacitor Cst, but also helps to save costs.

[0103] In some embodiments, the gate of the driving transistor M3 is reused as the first electrode plate, and the second electrode plate is disposed in the same layer and with the same material as the second gate metal layer in the display panel.

[0104] The above configuration allows the sub-pixel to include both a storage capacitor Cst and an auxiliary capacitor structure, which can further improve the capacitance value of the storage capacitor Cst in the sub-pixel and ensure the storage performance of the storage capacitor Cst.

[0105] As shown in Figures 11 and 12, in some embodiments, the display panel includes sub-pixels of multiple colors, and at least one color sub-pixel includes the distributed Bragg reflector and the reflective layer 30.

[0106] For example, the display panel includes a plurality of red sub-pixels, a plurality of green sub-pixels, and a plurality of blue sub-pixels. At least one of the red, green, and blue sub-pixels includes the distributed Bragg reflector and the reflective layer 30.

[0107] The above configuration method can flexibly set whether each sub-pixel includes the distributed Bragg reflector and the reflective layer 30 according to the actual light emission requirements of various color sub-pixels, which can better improve the light reflectivity and thus better improve the light effect of the display panel.

[0108] In some embodiments, the display panel includes sub-pixels of multiple colors, and the distributed Bragg reflectors of different colors have different refractive indices.

[0109] The above configuration method can flexibly adjust the refractive index of the distributed Bragg reflector included in each sub-pixel according to the actual light emission requirements of various color sub-pixels, which can better improve the light reflectivity and thus better improve the light effect of the display panel.

[0110] As shown in Figures 1, 8 to 10, in some embodiments, the display panel includes sub-pixels of multiple colors, and at least some of the sub-pixels of different colors include distributed Bragg reflectors of different thicknesses.

[0111] For example, the display panel includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel; the thickness of the distributed Bragg reflector included in the red sub-pixel is greater than the thickness of the distributed Bragg reflector included in the green sub-pixel; the thickness of the distributed Bragg reflector included in the green sub-pixel is greater than the thickness of the distributed Bragg reflector included in the blue sub-pixel.

[0112] For example, the display panel includes red sub-pixels, green sub-pixels, and blue sub-pixels; the thickness of the distributed Bragg reflector included in the red sub-pixel is greater than the thickness of the distributed Bragg reflector included in the green sub-pixel; the green sub-pixel and the blue sub-pixel include the same distributed Bragg reflector. It should be noted that since the structure and thickness of the distributed Bragg reflectors in the green and blue sub-pixels are relatively similar, the distributed Bragg reflectors included in the green sub-pixel and the distributed Bragg reflectors in the blue sub-pixel can be formed as the same type. This allows the reflective layer 30, the distributed Bragg reflector, and the transparent anode layer in the green and blue sub-pixels to be formed simultaneously in the same manufacturing process, thus eliminating the need for a separate manufacturing process for the reflective layer 30, the distributed Bragg reflector, and the transparent anode layer corresponding to one color sub-pixel, effectively simplifying the display panel manufacturing process and reducing manufacturing costs.

[0113] The above configuration method can flexibly adjust the thickness of the distributed Bragg reflector included in each sub-pixel according to the actual light emission requirements of various color sub-pixels, which can better improve the light reflectivity and thus better improve the light effect of the display panel.

[0114] In some embodiments, the reflective layer 30 includes a transparent film layer 302 or a metal reflective layer 301.

[0115] As shown in Figures 11 and 12, in some embodiments, the reflective layer 30 includes a transparent film layer 302 and a metal reflective layer 301 stacked together, with the metal reflective layer 301 located between the transparent film layer 302 and the transparent anode layer.

[0116] For example, the transparent film layer 302 includes an ITO layer, and the metal reflective layer 301 includes an Ag film layer, but is not limited thereto.

[0117] For example, the reflective layer 30 is formed in sub-pixels of various colors; the distributed Bragg reflector can be formed in only one color sub-pixel, or only two color sub-pixels, or of course, in sub-pixels of various colors. Setting the distributed Bragg reflector to be formed in only one color sub-pixel or only two color sub-pixels helps to save on mask elements.

[0118] When the reflective layer 30 includes a transparent film layer 302 and a metal reflective layer 301 stacked together, after the planarization layer and the vias penetrating the planarization layer are fabricated, a transparent material layer, a metal reflective material layer, and a mirror material layer can be continuously deposited. The transparent material layer is coupled to the sub-pixel driving circuit through the vias. Then, the mirror material layer is patterned through a patterning process to form a distributed Bragg mirror. Next, a transparent anode material layer is deposited. Then, the transparent anode material layer, the metal reflective material layer, and the transparent layer are patterned simultaneously through a patterning process to form a transparent anode layer, a metal reflective layer 301, and a transparent film layer 302. The transparent anode layer overlaps with the metal reflective layer 301 around the periphery of the distributed Bragg mirror.

[0119] This disclosure also provides a display device, including the display panel provided in the above embodiments.

[0120] For example, the display panel includes an organic light-emitting diode (OLED) display panel, and the display device includes an OLED display device, but is not limited thereto.

[0121] It should be noted that the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes flexible circuit boards, printed circuit boards, and backplanes.

[0122] In the display panel provided in the above embodiments, at least some sub-pixels include distributed Bragg reflectors and reflective layers 30. The reflective layer 30, the distributed Bragg reflectors, and the transparent anode layer are sequentially stacked along a direction away from the substrate 10. The orthographic projection of the pixel opening area corresponding to the sub-pixel onto the substrate 10 is located inside the orthographic projection of the distributed Bragg reflector onto the substrate 10, and also inside the orthographic projection of the reflective layer 30 onto the substrate 10. This arrangement allows the distributed Bragg reflector and the reflective layer 30 to achieve a reflectivity of over 99% for the light emitted by their respective sub-pixels, thereby effectively improving the brightness of the display panel, reducing power consumption, and extending the lifespan of the display panel. Simultaneously, the inclusion of a transparent anode layer in the sub-pixels allows light reflected by the distributed Bragg reflector and the reflective layer 30 to penetrate the transparent anode layer to a greater extent, further improving the luminous efficiency of the display panel.

[0123] The display device provided in this disclosure, when including the above-described display panel, also has the above-described beneficial effects, which will not be repeated here.

[0124] This disclosure also provides a method for manufacturing a display panel, used to manufacture the display panel provided in the above embodiments. The manufacturing method includes the step of manufacturing at least some sub-pixels on a substrate 10, specifically including:

[0125] A sub-pixel driving circuit is fabricated on the substrate 10;

[0126] A reflective layer 30 is formed on the side of the sub-pixel driving circuit that faces away from the substrate 10.

[0127] A distributed Bragg reflector is fabricated on the side of the reflective layer 30 facing away from the substrate 10;

[0128] A transparent anode layer is fabricated on the side of the distributed Bragg reflector facing away from the substrate 10, and the transparent anode layer is coupled to the sub-pixel driving circuit.

[0129] In the display panel manufactured using the method provided in this embodiment, at least some sub-pixels include a distributed Bragg reflector and a reflective layer 30. The reflective layer 30, the distributed Bragg reflector, and the transparent anode layer are sequentially stacked along a direction away from the substrate 10. The orthographic projection of the pixel opening area corresponding to the sub-pixel onto the substrate 10 is located inside the orthographic projection of the distributed Bragg reflector onto the substrate 10, and also inside the orthographic projection of the reflective layer 30 onto the substrate 10. This arrangement allows the distributed Bragg reflector and the reflective layer 30 to achieve a reflectivity of over 99% for the light emitted by their respective sub-pixels, thereby effectively improving the brightness of the display panel, reducing power consumption, and extending the lifespan of the display panel. Furthermore, in the display panel manufactured using the method provided in this embodiment, the sub-pixels include a transparent anode layer, allowing light reflected by the distributed Bragg reflector and the reflective layer 30 to penetrate the transparent anode layer to a greater extent, further improving the luminous efficiency of the display panel.

[0130] As shown in Figures 1 to 13, in some embodiments, the manufacturing method specifically includes:

[0131] A reflective material layer is deposited to form a reflective material layer, and a patterning process is performed on the reflective material layer to form the reflective layer 30;

[0132] A distributed Bragg reflector layer is deposited to form a distributed Bragg reflector layer, and a patterning process is performed on the distributed Bragg reflector layer to form the distributed Bragg reflector mirror.

[0133] A transparent anode material layer is deposited and patterned to form the transparent anode layer.

[0134] The above embodiments are applicable to the case where the transparent anode layer is directly coupled to the sub-pixel driving circuit, and also applicable to the case where the transparent anode layer is coupled to the sub-pixel driving circuit through the reflective layer 30. In the case of the transition, it is applicable to the case of the transition through the first via and the second via, as well as the case of the connection around the distributed Bragg mirror.

[0135] As shown in Figures 9 to 12, in some embodiments, the manufacturing method specifically includes:

[0136] Deposition forms a reflective material layer;

[0137] A distributed Bragg reflector layer is deposited to form a distributed Bragg reflector layer, and a patterning process is performed on the distributed Bragg reflector layer to form the distributed Bragg reflector mirror.

[0138] A transparent anode material layer is deposited, and a patterning process is performed to simultaneously form the reflective layer 30 and the transparent anode layer.

[0139] The above embodiments are applicable to the case where the transparent anode layer is coupled to the sub-pixel driving circuit through the reflective layer 30, and are applicable to the case where it is coupled through the first via and the second via, as well as the case where it is overlapped around the distributed Bragg mirror.

[0140] It should be noted that, in the embodiments of this disclosure, "same layer" can refer to film layers located on the same structural layer. Alternatively, for example, film layers located on the same layer can be layer structures formed by using the same film deposition process to form a specific pattern, and then patterning the film layer using the same photomask through a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0141] In the various method embodiments of this disclosure, the sequence numbers of each step are not intended to limit the order of the steps. For those skilled in the art, any changes in the order of the steps are within the scope of protection of this disclosure without any creative effort.

[0142] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0143] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connection,” “coupled,” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0144] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0145] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0146] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display panel, comprising: A substrate and a plurality of sub-pixels disposed on the substrate, wherein each sub-pixel includes a sub-pixel driving circuit coupled to it and a transparent anode layer, the transparent anode layer being located on the side of the sub-pixel driving circuit facing away from the substrate; At least some of the sub-pixels also include: A distributed Bragg reflector, wherein the distributed Bragg reflector is located between the transparent anode layer and the substrate. A reflective layer is located on the side of the distributed Bragg mirror facing the substrate.

2. The display panel according to claim 1, wherein, The reflective layer is coupled to a fixed voltage signal input terminal.

3. The display panel according to claim 2, wherein, The display panel includes a display area and a peripheral area surrounding the display area; the fixed voltage signal input terminal is located in the peripheral area; the reflective layers included in different sub-pixels are coupled to form a whole reflective layer, and the whole reflective layer is coupled to the fixed voltage signal input terminal.

4. The display panel according to claim 1, wherein, In at least a portion of the sub-pixels, the transparent anode layer is coupled to the sub-pixel driving circuit via the reflective layer.

5. The display panel according to claim 4, wherein, In at least a portion of the sub-pixels, the reflective layer is coupled to the sub-pixel driving circuit via a first via, the first via penetrating an insulating layer located between the reflective layer and the sub-pixel driving circuit; The transparent anode layer is coupled to the reflective layer through a second via, which penetrates the distributed Bragg reflector. The orthographic projection of the second via on the substrate does not overlap with the orthographic projection of the first via on the substrate.

6. The display panel according to claim 4, wherein, In at least a portion of the sub-pixels, the reflective layer is coupled to the sub-pixel driving circuit via a first via, the first via penetrating an insulating layer located between the reflective layer and the sub-pixel driving circuit; The orthographic projection of the distributed Bragg reflector on the substrate is located inside the orthographic projection of the transparent anode layer on the substrate, and also inside the orthographic projection of the reflective layer on the substrate; the transparent anode layer overlaps with the reflective layer around the periphery of the distributed Bragg reflector.

7. The display panel according to claim 1, wherein, The sub-pixel driving circuit includes a driving transistor and a storage capacitor. The first plate of the storage capacitor is coupled to the gate of the driving transistor, and the second plate of the storage capacitor is coupled to the second electrode of the driving transistor. The second electrode of the driving transistor is coupled to the transparent anode layer. The reflective layer is coupled to the gate of the driving transistor, and the orthographic projection of the reflective layer on the substrate overlaps at least partially with the orthographic projection of the transparent anode layer on the substrate.

8. The display panel according to claim 7, wherein, The reflective layer is reused as the first electrode plate, and the transparent anode layer is reused as the second electrode plate.

9. The display panel according to claim 7, wherein, The gate of the driving transistor is reused as the first electrode plate, and the second electrode plate is disposed in the same layer and with the same material as the second gate metal layer in the display panel.

10. The display panel according to any one of claims 1 to 9, wherein, The display panel includes sub-pixels of multiple colors, and at least one color sub-pixel includes the distributed Bragg reflector and the reflective layer.

11. The display panel according to any one of claims 1 to 9, wherein, The display panel includes sub-pixels of various colors, and the distributed Bragg reflectors of different colors have different refractive indices.

12. The display panel according to any one of claims 1 to 9, wherein, The display panel includes sub-pixels of multiple colors, and at least some of the sub-pixels of different colors include distributed Bragg reflectors of different thicknesses.

13. The display panel according to claim 12, wherein, The display panel includes red sub-pixels, green sub-pixels, and blue sub-pixels; the thickness of the distributed Bragg reflector included in the red sub-pixel is greater than the thickness of the distributed Bragg reflector included in the green sub-pixel; the thickness of the distributed Bragg reflector included in the green sub-pixel is greater than the thickness of the distributed Bragg reflector included in the blue sub-pixel.

14. The display panel according to claim 12, wherein, The display panel includes red sub-pixels, green sub-pixels, and blue sub-pixels; the thickness of the distributed Bragg reflector included in the red sub-pixel is greater than the thickness of the distributed Bragg reflector included in the green sub-pixel; the green sub-pixel and the blue sub-pixel include the same distributed Bragg reflector.

15. The display panel according to any one of claims 1 to 9, wherein, The reflective layer includes a transparent film layer or a metallic reflective layer.

16. The display panel according to any one of claims 1 to 9, wherein, The reflective layer includes a transparent film layer and a metal reflective layer stacked together, with the metal reflective layer located between the transparent film layer and the transparent anode layer.

17. A display device comprising a display panel as claimed in any one of claims 1 to 16.

18. A method for manufacturing a display panel, used to manufacture a display panel as described in any one of claims 1 to 16, the method comprising the step of manufacturing at least a portion of sub-pixels on a substrate, the step specifically comprising: Fabricate sub-pixel driving circuits on a substrate. A reflective layer is fabricated on the side of the sub-pixel driving circuit that faces away from the substrate. A distributed Bragg reflector is fabricated on the side of the reflective layer facing away from the substrate. A transparent anode layer is fabricated on the side of the distributed Bragg reflector facing away from the substrate, and the transparent anode layer is coupled to the sub-pixel driving circuit.

19. The method for manufacturing a display panel according to claim 18, wherein, The manufacturing method specifically includes: A reflective material layer is deposited to form a reflective layer, and a patterning process is performed on the reflective material layer to form the reflective layer; A distributed Bragg reflector layer is deposited to form a distributed Bragg reflector layer, and a patterning process is performed on the distributed Bragg reflector layer to form the distributed Bragg reflector mirror. A transparent anode material layer is deposited and patterned to form the transparent anode layer.

20. The method for manufacturing a display panel according to claim 18, wherein, The manufacturing method specifically includes: Deposition forms a reflective material layer; A distributed Bragg reflector layer is deposited to form a distributed Bragg reflector layer, and a patterning process is performed on the distributed Bragg reflector layer to form the distributed Bragg reflector mirror. A transparent anode material layer is deposited, and a patterning process is performed to simultaneously form the reflective layer and the transparent anode layer.

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