Display method and display device

Abstract

The present disclosure relates to the technical field of display, and provides a display method and a display device. In the display method of the present disclosure, the physical resolution of a display panel is M1×N1. The display method comprises: a mainboard converts first raw image data sent by a graphics card into first image data, and sends the first image data to a timing controller, wherein the resolution of the first image data is M2×N2, and N2:N1=a:b≤1; and the timing controller provides P clock signals to a gate driving circuit in a display panel, and provides a data control signal to a source driving circuit, wherein P=i×b. The gate driving circuit gates different rows of sub-pixels of the display panel on the basis of the P clock signals; the source driving circuit writes, on the basis of the data control signal, N2 rows of display data in the first image data row by row into the different rows of sub-pixels other than a (j×b)-th row of sub-pixels in a scanning sequence; and display data of a (b×j-1)-th row of sub-pixels and display data of a (b×j+1)-th row of sub-pixels are written into the (j×b)-th row of sub-pixels, wherein j is a positive integer greater than or equal to 1, and (b×j+1)≤N1.

Description

Display method and display device Technical Field

[0001] This disclosure belongs to the field of display technology, and specifically relates to a display method and a display device. Background Technology

[0002] The current performance improvements in gaming monitors primarily involve simultaneous increases in resolution and refresh rate, resulting in a better user experience. However, this simultaneous increase inevitably leads to a rapid decrease in pixel charging time. Although this can be addressed by adjusting panel manufacturing processes, changing design materials (A-SI → Oxide), and using ICs with stronger driving capabilities, the issue of insufficient pixel charging will still persist. Furthermore, with the simultaneous increase in refresh rate and resolution, supporting such high monitor specifications also requires simultaneous improvements in the graphics card and scaler board to deliver excellent display performance. This often leads to increased consumer spending and impacts market sales. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art, and to provide a display method and display device.

[0004] This disclosure provides a display method applied to a display device, the display device including a graphics card, a motherboard, a timing controller, and a display panel; the physical resolution of the display panel is M1×N1; the display method includes:

[0005] The motherboard converts the first raw image data sent by the graphics card into first image data and sends it to the timing controller; the resolution of the first image data is M2×N2; N2:N1=a:b≤1;

[0006] The timing controller provides P clock signals to the gate driving circuit in the display panel and data control signals to the source driving circuit; P = i × b; i is a positive integer greater than or equal to 1; the gate driving circuit selects each row of sub-pixels of the display panel according to the P clock signals, and the source driving circuit, according to the data control signals, writes the N2 row of display data in the first image data line by line for each row of sub-pixels except for the j × b row, in the scanning order; and writes the display data of the b × j-1 and b × j+1 row sub-pixels of the j × b row sub-pixels; j is a positive integer greater than or equal to 1, and b × j+1 ≤ N1.

[0007] Wherein, the start time of the effective level of the (k+1)th clock signal is earlier than the end time of the effective level of the kth clock signal; K ranges from 1 to P-1;

[0008] Of the P clock signals, except for the b×j-th clock signal, the phase difference between the start times of the effective levels of adjacent clock signals is 1H1, the phase difference between the start times of the effective levels of the b×j-th and b×j-1-th clock signals is A, and the phase difference between the start times of the effective levels of the b×j+1-th and b×j-th clock signals is B; A+B=H1; where H1 is the phase difference between the start times of two adjacent effective levels of the data control signal.

[0009] Wherein, the phase difference between the start time of the effective level of the b×j-th and b×j-1-th clock signals is H1 / 2, and the phase difference between the start time of the effective level of the b×j+1-th and b×j-th clock signals is H1 / 2.

[0010] The clock signal provided by the timing controller to the gate driving circuit and the data control signal provided to the source driving circuit satisfy the following:

[0011] Except for the sub-pixels in the j×b row, the termination time of the data writing signal from the source driving circuit to the sub-pixel is earlier than the termination time of the effective level of the gate driving signal loaded on the sub-pixel.

[0012] The clock signal provided by the timing controller to the gate driving circuit and the data control signal provided to the source driving circuit satisfy the following:

[0013] For sub-pixels except those in the j×b row, the phase difference between the termination time of the data signal written to the sub-pixel by the source driving circuit and the termination time of the effective level of the gate driving signal loaded on the sub-pixel is H1 / 2, where H1 is the phase difference between the start times of two adjacent effective levels of the data control signal.

[0014] The clock signal provided by the timing controller to the gate drive circuit satisfies the following condition: the time during which the gate drive signals loaded on the sub-pixels of adjacent rows are simultaneously at an effective level is not less than 2H1, where H1 is the phase difference between the start times of two adjacent effective levels of the data control signal.

[0015] Wherein, when a:b=3:4 and P=4i; except for the 4e-th clock signal, the phase difference of the start time of the effective level of each of the other clock signals is 1H1; e takes a positive integer from 1 to i; H1 is the phase difference of the start time of two adjacent effective levels of the data control signal; the phase difference of the start time of the effective level of the 4e-th and 4e-1-th clock signals is H1 / 2.

[0016] Wherein, when a:b=2:3 and P=3i; except for the 3e-th clock signal, the phase difference of the start time of the effective level of each of the other clock signals is 1H1; e takes a positive integer from 1 to i; H1 is the phase difference of the start time of two adjacent effective levels of the data control signal; the phase difference of the start time of the effective level of the 3e-th and 3e-1-th clock signals is H1 / 2.

[0017] Wherein, the duty cycle of the effective level of the clock signal is 50%, and the duration of the effective level of the clock signal is 3H1; where H1 is the phase difference between the start times of two adjacent effective levels of the data control signal.

[0018] Wherein, M1 is equal to M2.

[0019] The display method further includes:

[0020] The graphics card receives a display mode selection instruction, and when the display mode selection instruction is a first display mode, the graphics card sends the received first raw image data to the motherboard; the resolution of the first raw image data is M3×N3; M3 < M2;

[0021] The motherboard converts the first raw image data sent by the graphics card into first image data, including:

[0022] The motherboard performs horizontal interpolation on the first original image data to obtain the first image data.

[0023] The display method further includes: receiving a display mode selection instruction, and when the display mode selection instruction is a second display mode, the graphics card sends the received second raw image data to the motherboard;

[0024] The motherboard converts the second original image data into second image data; the resolution of the second image data is M4×N4; N4:N1=1:2; the refresh rate of the second image data is greater than the refresh rate of the first image data;

[0025] The timing controller provides multiple clock signals to the gate driving circuit in the display panel and data control signals to the source driving circuit;

[0026] The gate driving circuit selects each row of sub-pixels of the display panel according to the plurality of clock signals, and the source driving circuit writes the second image data line by line to the sub-pixels located in even-numbered rows according to the data control signal, and writes the display data of the two adjacent sub-pixels located in even-numbered rows to the sub-pixels in odd-numbered rows; or,

[0027] The gate driving circuit selects each row of sub-pixels of the display panel according to the plurality of clock signals, and the source driving circuit writes the second image data line by line to the sub-pixels located in odd-numbered rows according to the data control signal, and writes the display data of the two adjacent sub-pixels located in odd-numbered rows to the sub-pixels in even-numbered rows.

[0028] In the second display mode, the start times of the effective levels of the multiple clock signals are sequentially separated by 1H2, where H2 is half the phase difference between the start times of two adjacent effective levels of the data control signal.

[0029] In the second display mode, the effective level of the clock signal has a duration of 4H2 and a duty cycle of 50%; the duration for which adjacent row sub-pixels are simultaneously enabled by the multiple clock signals is 3H2.

[0030] This disclosure provides a display device including a graphics card, a motherboard, a gate driving circuit, a source driving circuit, and a display panel; the physical resolution of the display panel is M1×N1.

[0031] The motherboard is configured to convert the first raw image data sent by the graphics card into first image data and send it to the timing controller; the resolution of the first image data is M2×N2; N2:N1=a:b<1;

[0032] The timing controller is configured to provide P clock signals to the gate driving circuit in the display panel and to provide data control signals to the source driving circuit; P = i × b; i is a positive integer greater than or equal to 1; the gate driving circuit selects each row of sub-pixels of the display panel according to the P clock signals, and the source driving circuit, according to the data control signals, writes the N2 row of display data in the first image data line by line according to the scanning order for each row of sub-pixels except for the j × b row; and writes the display data of the b × j-1 row and the b × j+1 row of sub-pixels into the j × b row of sub-pixels; j is a positive integer greater than or equal to 1, and b × j+1 ≤ N1. Attached Figure Description

[0033] Figure 1 is a schematic diagram of a display device provided in an embodiment of this disclosure.

[0034] Figures 2A and 2B are example structural diagrams of the gate drive circuit provided in the embodiments of this disclosure.

[0035] Figure 3 is a signal timing diagram of a display method according to an embodiment of the present disclosure.

[0036] Figure 4 is a flowchart of the display method according to an embodiment of this disclosure.

[0037] Figure 5 is a timing diagram of the display method according to an embodiment of the present disclosure.

[0038] Figure 6 is a flowchart of the display method according to an embodiment of this disclosure.

[0039] Figure 7 is a timing diagram of a display method according to an embodiment of the present disclosure in a second display mode.

[0040] Figure 8 is another timing diagram of the display method of this disclosure in a second display mode. Detailed Implementation

[0041] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0042] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0043] Figure 1 is a schematic diagram of a display device provided in an embodiment of the present disclosure; as shown in Figure 1, the display device 100 includes a display panel, the display panel including a plurality of sub-pixels arranged in an M1×N1 array, wherein N1 and M1 are both integers greater than 1.

[0044] The display device 100 may further include a gate driving circuit 10, which is connected to a plurality of sub-pixels. The gate driving circuit 10 can be connected to N1 rows of sub-pixels respectively via multiple gate signal lines extending along a first direction (x-direction in FIG1). For example, it can be connected to the first row of sub-pixels via a first gate signal line to provide a first gate driving signal G1 to the first row of sub-pixels, and connected to the second row of sub-pixels via a second gate signal line to provide a second gate driving signal G2 to the second row of sub-pixels, and so on. The first row of sub-pixels turns on in response to receiving the first gate driving signal G1, the second row of sub-pixels turns on in response to receiving the second gate driving signal G2, and so on.

[0045] In some embodiments, the gate driving circuit 10 can scan N11 rows of sub-pixels one or more rows at a time. For example, the gate driving circuit 10 can scan one row of sub-pixels at a time, such as sequentially generating N1 gate driving signals G1, G2, ... GN to sequentially turn on the first row of sub-pixels, the second row of sub-pixels P, ... the N1th row of sub-pixels P. The gate driving circuit 10 can also scan two or more rows of sub-pixels P at a time. For example, the gate driving circuit 10 can simultaneously generate a first gate driving signal G1 and a second gate driving signal G2 to simultaneously turn on the first row of sub-pixels and the second row of sub-pixels, then the gate driving circuit 10 can simultaneously generate a third gate driving signal G3 and a fourth gate driving signal G4 to simultaneously turn on the third row of sub-pixels and the fourth row of sub-pixels, and so on. In some embodiments, the gate driving circuit 10 can scan the N1 rows of sub-pixels at least one row interval to sequentially turn on the sub-pixels of some rows. For example, the gate drive circuit 10 can sequentially turn on odd-numbered rows of sub-pixels (e.g., sequentially turn on the first row of sub-pixels, the third row of sub-pixels, the fifth row of sub-pixels, and so on), or sequentially turn on even-numbered rows of sub-pixels (e.g., sequentially turn on the second row of sub-pixels, the fourth row of sub-pixels, the sixth row of sub-pixels, and so on).

[0046] The display device 100 may further include a source driving circuit 20, which is connected to a plurality of sub-pixels. For example, the source driving circuit 20 may be connected to the M1 column of sub-pixels P via multiple data lines extending along a second direction (y direction in FIG1). For example, the source driving circuit 20 may be connected to the first column of sub-pixels via a first data line to provide a first data signal D1 to the first column of sub-pixels, and to the second column of sub-pixels via a second data line to provide a second data signal D2 to the second column of sub-pixels, and so on.

[0047] For example, when the first row of sub-pixels is enabled, the source driving circuit 20 can provide M1 data signals D11, D12, ..., D1M to the M1 sub-pixels of the first row via M1 data lines respectively; when the second row of sub-pixels is enabled, the source driving circuit 20 can provide M1 data signals D21, D22, ..., D2M1 to the M1 sub-pixels of the second row via multiple data lines respectively, and so on. Of course, the embodiments of this disclosure are not limited to this, and will be further described in detail below.

[0048] In some embodiments, the display device 100 may further include a graphics card 50, a motherboard 40, and a timing controller 30. Specifically, the motherboard 40 may be a Scalar motherboard 40. The graphics card 50 is used for image formation, and the motherboard 40 is used for data transmission. For example, the graphics card 50 transmits image data to the motherboard 40, and the motherboard 40 sends the image data to the timing controller 30.

[0049] The timing controller 30 is connected to the gate drive circuit 10 and the source drive circuit 20, and can provide relevant control signals to the gate drive circuit 10 and the source drive circuit 20. For example, the timing controller 30 can provide a data control signal TP to the source drive circuit 20, and the source drive circuit 20 can output data signals for each row under the control of the data control signal TP. The timing controller 30 can also provide other control signals to the source drive circuit 20, including but not limited to row data start signals, data synchronization signals, data inversion signals, etc. The timing controller 30 can also provide various control signals to the gate drive circuit 10, including but not limited to frame start signals, clock signals, etc. required by the gate drive circuit 10. In this disclosure, it is assumed that the effective level of each signal is high and the corresponding ineffective level is low.

[0050] Figures 2A and 2B illustrate example structural diagrams of the gate driving circuit according to embodiments of the present disclosure. As shown in Figures 2A and 2B, the gate driving circuit includes multiple cascaded shift registers GOA1, GOA2, ..., GOAN. For example, for an ultra-high definition (QHD: resolution 2560×1440) display panel, the horizontal pixel count is 2560 and the vertical pixel count is 1440. If each pixel contains multiple sub-pixels arranged horizontally, the display panel includes 1440 rows of sub-pixels. In the case where the display panel contains 1440 rows of sub-pixels and each shift register corresponds to one row of sub-pixels, the gate driving circuit can include 1440 shift registers.

[0051] Figure 2A shows the shift register units GOA1 to GOA9 from the first to the ninth stage. As shown in Figure 2A, STV1 is the frame start signal. When the gate drive circuit is connected to 8 CLKs, the input terminals of the shift register units GOA1 to GOA4 from the first to the fourth stage can be connected to the frame start signal terminal STV1. After the fourth stage shift register unit GOA4, the input terminal of the nth stage shift register unit GOAn is connected to the output terminal of the (n-4)th stage shift register unit GOA(n-4), where 5 ≤ n ≤ N. For example, the output of GOA1 is connected to the input of GOA5, the output of GOA2 is connected to the input of GOA6, the output of GOA3 is connected to the input of GOA7, the output of G4 is connected to the input of GOA8, the output of G5 is connected to the input of GOA9, and so on. The reset terminal RST of the nth stage shift register unit GOAn is connected to the output terminal OUT of the (n+4)th stage shift register unit GOA(n+4), where 1 ≤ n ≤ N-4. Figure 2B shows the last-stage shift register unit GOA1440 and the virtual shift register unit (Dummy GOA). As shown in Figure 2B, the last four rows of GOA can be reset through four rows of Dummy GOA. For example, Dummy GOA1 (Dum1) resets GOA1437, Dummy GOA2 (Dum2) resets GOA1438, and so on. Each Dummy GOA can be reset through STV1.

[0052] It should be noted that the above example only uses the connection of the reset terminal RST of the nth-stage shift register unit GOAn to the output terminal OUT of the (n+4)th-stage shift register unit GOA(n+4). In some examples, the reset terminal RST of the nth-stage shift register unit GOAn can also be connected to the output terminal OUT of the (n+4)th-stage shift register unit GOA(n+5), where 1 ≤ n ≤ N-5. Correspondingly, the gate drive circuit includes 5 dummy GOAs. The last 5 rows of GOAs can be reset using these 5 dummy GOAs. For example, dummy GOA1 (Dum1) resets GOA1436, dummy GOA2 (Dum2) resets GOA1437, and so on. In other words, the setting of the dummy GOAs can be flexibly configured according to the reset relationship between the GOAs. The gate drive circuits shown in Figures 2A and 2B employ eight clock signals CLK1 to CLK8. The clock signal terminal CLK of the first-stage shift register unit GOA1 is connected to receive the first clock signal CLK1; the clock signal terminal CLK of the second-stage shift register unit GOA2 is connected to receive the second clock signal CLK2, and so on. The clock signal terminal CLK of the eighth-stage shift register unit GOA8 is connected to receive the eighth clock signal CLK8. Similarly, the ninth to sixteenth-stage shift register units GOA9 to GOA16 are connected to receive the first to eighth clock signals CLK1 to CLK8, respectively.

[0053] Each shift register unit GOA1, GOA2, ..., GOAN can generate an output signal as a gate drive signal (or gate scan signal) at its output OUT under the control of its clock signal CLK and input signals. For example, the first-stage shift register unit GOA1 generates a first gate drive signal G1, the second-stage shift register unit GOA2 generates a second gate drive signal G2, and so on. By cascading, the gate drive signal generated by one-stage shift register unit can be shifted relative to the gate drive signal generated by another-stage shift register unit.

[0054] The above is merely an illustrative example of a display device according to an embodiment of this disclosure. The structure of the display device according to this disclosure is not limited thereto, and other structures may be used as needed. For example, the display device may be a display device based on liquid crystal display (LCD) technology, or a display device based on organic light-emitting diode (OLED) display technology. The gate driving circuit of the display device may adopt a different cascading method than that shown in Figures 2A and 2B. For example, it may adopt 10 or 12 clock signals cascaded in different ways.

[0055] Figure 3 is a signal timing diagram of a display method according to an embodiment of this disclosure; the signal timing of Figure 3 will be described below using the display devices of Figures 1, 2A, and 2B as examples. As shown in Figure 3, during the display of each frame of image, under the control of clock signals CLK1 to CLK8, the gate driving circuit 10 sequentially generates a first gate driving signal G1, a second gate driving signal G2, a third gate driving signal G3, and a fourth gate driving signal G4 at preset time intervals, and so on. The phase difference between the start times of the data signals written to two adjacent row sub-pixels is H. In Figure 3, the effective level duration of each gate driving signal is, for example, 4H.

[0056] For the first row of sub-pixels, during time periods T1 to T4, the first gate drive signal G1 is high, causing the first row of sub-pixels to be in the on state. The length of each time period T1 to T4 is H, meaning the first sub-pixel is on for 4H seconds. During time period T4, the first high-level pulse of the data control signal TP arrives, thereby controlling the source drive circuit 20 to apply the data signal (also called the first row data signal) DATA1 for the first row of sub-pixels to the on-state first row of sub-pixels. The first row data signal DATA1 may include M1 data signals D11, D12, ..., D1M for the M1 sub-pixels of the first row, respectively. Data signal D11 is provided to the first column of the first row of sub-pixels, data signal D12 is provided to the second column of the first row of sub-pixels, ..., data signal D1M is provided to the M1th column of the first row of sub-pixels.

[0057] Similarly, for the second row of sub-pixels, during time periods T2 to T5, the second gate drive signal G2 is high, causing the second row of sub-pixels to be in the on state. During time period T5, the second high-level pulse of the data control signal TP arrives, thereby controlling the source drive circuit 20 to apply the data signal (also called the second row data signal) DATA2 for the second row of sub-pixels to the on-state second row of sub-pixels. The second row data signal DATA2 may include M1 data signals D21, D22, ..., D2M for the M1 sub-pixels of the second row, respectively. Data signal D21 is provided to the first column of the second row of sub-pixels, data signal D22 is provided to the second column of the second row of sub-pixels, ..., data signal D2M1 is provided to the M1th column of the second row of sub-pixels. This process can be repeated for other rows of sub-pixels.

[0058] According to the above image frame, the refresh rate of the QHD display panel is 180Hz. Increasing the refresh rate of the QHD display panel from 180Hz to 240Hz achieves a 4 / 3x increase. Specifically, when the graphics card 50 receives the original image data (2560*1440*180Hz) and adjusts it to 1920*1080*240Hz, after processing by the motherboard 40 Scalar and outputting 2560*1080*240Hz, the timing controller 30 receives the image data. Since 2560*1440*180 = 2560*1080*240, its receiving bandwidth remains unchanged. This achieves a refresh rate increase from 180Hz to 240Hz; however, because the timing controller 30 actually receives 1080 lines of display data, while the display panel has 1440 physical sub-pixel lines, this results in missing display data on the display panel. To address this issue, this disclosure provides the following technical solution.

[0059] This disclosure provides a display method, which can also be applied to the display device shown in FIG1. ​​The physical resolution of the display panel is M1×N1, as shown in FIG4. The display method includes:

[0060] S10, the motherboard 40 converts the first raw image data sent by the graphics card 50 into first image data and sends it to the timing controller 30; the resolution of the first image data is M2×N2; N2:N1=a:b≤1.

[0061] Specifically, in the display method of this embodiment, the refresh rate of the first image data is higher than the normal refresh rate of the display device. For example, the normal refresh rate of the display panel is 180Hz, the refresh rate of the first image data is 240Hz, the physical resolution of the display panel is M1×N1=2560×1440, and the resolution of the first image data is M2×N2=2560×1080. Correspondingly, N2:N1=3:4, that is, a=3, b=4.

[0062] S20 and timing controller 30 provide P clock signals to the gate driving circuit 10 in the display panel and data control signals to the source driving circuit 20; P = i × b; i is a positive integer greater than or equal to 1. The gate driving circuit 10 selects each row of sub-pixels in the display panel according to the P clock signals, and the source driving circuit 20, according to the data control signals, writes the N2 row of display data in the first image data line by line according to the scanning order for each row of sub-pixels except for the j × b row; and writes the display data of the b × j-1 row and the b × j+1 row of sub-pixels into the j × b row of sub-pixels; j is a positive integer greater than or equal to 1, and j × b+1 ≤ N1.

[0063] In other words, the data written to each sub-pixel except for the j×b-th row in the display panel is the actual display data in the first image data. However, the display data written to the j×b-th row sub-pixel is the interpolation of the display data of the two adjacent rows of sub-pixels above and below it. In this way, each sub-pixel on the display panel has display data written to it, and the j×b-th row sub-pixel is written with the interpolation of the display data of the two adjacent rows of sub-pixels above and below it. This avoids the problem of display abnormalities caused by excessive differences between the display of the interpolated row sub-pixel and the adjacent row sub-pixels.

[0064] Specifically, taking a=3 and b=4 in step S10 as an example, if i is 2, then P=8, which means that the timing controller 30 generates 8 clock signals, namely CLK1 to CLK8. At this time, the 8 clock signals generated by the timing controller 30, as well as the data control signals, can control all sub-pixels except the 3j+1th row (e.g., the 4th, 8th, 12th...) to be written with real display data. For the 3j+1th row sub-pixel, the display data of the adjacent upper and lower rows of sub-pixels is interpolated for display. For example, the 4th row sub-pixel is charged by mixing the display data written by the third and fifth row sub-pixels.

[0065] It should be noted that, in the above example, the number of clock signals is not limited to 8; it can be a multiple of 4, such as 4, 8, or 12 clock signals. Furthermore, in the example above, taking the resolution of the first image data M2×N2=2560×1080 as an example, and filling 2560×1080 data points onto a display panel with a physical resolution of M1×N1=2560×1440, if the resolution of the first image data M2×N2=2560×1440 were to be filled onto a display panel with a physical resolution of M1×N1=3840×2160, then N2:N1=2:3, that is, a=2, b=3. In this case, the display data on the display panel needs to be filled every two rows, meaning that the sub-pixels in the 3rd, 6th, 9th… rows need to be charged by mixing the display data of their adjacent upper and lower sub-pixels. This requires that the number of clock signals generated by the timing controller 30 at this time be a multiple of 3, such as 6, 9, 12 clock signals, and so on, which will not be listed here.

[0066] In some examples, the start time of the high level of the (k+1)th clock signal is earlier than the end time of the high level of the kth clock signal; K ranges from 1 to P-1; among the P clock signals, except for the b×jth clock signal, the phase difference between the start times of the effective levels of adjacent clock signals is 1H1, the phase difference between the start times of the effective levels of the b×jth and b×j-1th clock signals is A, and the phase difference between the start times of the effective levels of the b×j+1th and b×jth clock signals is B; A+B=H1; H1 is the phase difference between the start times of the two adjacent effective levels of the data control signal. For example, the phase difference between the start times of the high levels of the b×jth and b×j-1th clock signals is H1 / 2, and the phase difference between the start times of the high levels of the b×j+1th and b×jth clock signals is H1 / 2. Specifically, taking a=3, b=4, i=2, and P=8 as an example; except for the 4e-th clock signal, the phase difference of the start time of the effective level of each of the other clock signals is 1H1; e is a positive integer of 1 and 2; H1 is the phase difference of the start time of two adjacent effective levels of the data control signal; the phase difference of the start time of the effective level of the 4e-th and 4e-1-th clock signals is H1 / 2. Of course, in this embodiment, the phase difference of the start time of the high level of the b×j-th and b×j-1-th clock signals can also be H1 / 3, the phase difference of the start time of the high level of the b×j+1-th and b×j-th clock signals can be 2H1 / 3, etc., which will not be listed here.

[0067] Since the clock signal determines the output of the gate driving circuit 10, the clock signal is at a high level during the output phase of the gate driving circuit 10. At this time, the gate driving signal output by the gate driving circuit 10 is also at a high level. Therefore, the start time of the high level of the (k+1)th clock signal is earlier than the end time of the high level of the kth clock signal. In other words, two adjacent rows of sub-pixels have a period of time when they are turned on at the same time. They can be pre-charged before the sub-pixel data is written to improve the charging efficiency of the sub-pixels. In this embodiment, except for the 4th and 8th clock signals, the phase difference between the start times of the high level of adjacent clock signals is 1H1, the phase difference between the start times of the high level of the 4th and 3rd clock signals is H1 / 2, and the phase difference between the start times of the high level of the 4th and 5th clock signals is H1 / 2. That is, the start times of the high level signals of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, the fifth clock signal CLK5, the sixth clock signal CLK6, and the seventh clock signal CLK7 are successively 1H1 apart, the phase difference between the start times of the high level of the fourth clock signal CLK4 and the third clock signal CLK3 is H1 / 2, and the phase difference between the start times of the high level of the fifth clock signal CLK5 and the fourth clock signal CLK4 is H1 / 2. In this way, it is ensured that the sub-pixel of the 3j+1th row uses the display data of the adjacent upper and lower row sub-pixels for mixed charging.

[0068] In some examples, the clock signal provided by the timing controller 30 to the gate driving circuit 10, and the data control signal provided to the source driving circuit 20, satisfy the following condition: for sub-pixels except for the j×b-th row, the termination time of the data writing signal from the source driving circuit 20 to the sub-pixel is earlier than the termination time of the high level of the gate driving signal loaded on the sub-pixel. In this way, it is ensured that the j×b-th row sub-pixel is charged by the display data of the adjacent sub-pixels.

[0069] In one example, the clock signal provided by the timing controller 30 to the gate drive circuit 10 and the data control signal provided to the source drive circuit 20 satisfy the following: for sub-pixels except the j×b-th row, the phase difference between the termination time of the data signal written by the source drive circuit 20 to the sub-pixel and the termination time of the high level of the gate drive signal loaded on the sub-pixel is H1 / 2, where H1 is the phase difference between the start times of two adjacent high levels of the data control signal.

[0070] In some examples, the clock signal provided by the timing controller 30 to the gate drive circuit 10 satisfies the following condition: the gate drive signals loaded on the sub-pixels of adjacent rows are simultaneously at a high level for a duration of not less than 2H1, where H1 is the phase difference between the start times of two adjacent high levels of the data control signal. For example, the duty cycle of the high-level signal of each clock signal is 50%, the high-level clock can be 3H1, and the corresponding low-level duration is also 3H1. In this case, the gate drive signals loaded on the sub-pixels of adjacent rows are simultaneously at a high level for a duration of not less than 2H1.

[0071] To better illustrate the display method of the display panel for receiving the first image data in the embodiments of this disclosure, the display method of the embodiments of this disclosure will be described using the example of the gate driving circuit 10 of the display panel being controlled by 8 clock signals.

[0072] Referring to Figure 5, the timing controller 30 provides eight clock signals, CLK1 to CLK8, to the gate drive circuit 10. The duty cycle of the high-level signal of each clock signal is 50%, and the high-level clock can be 3H1, with the corresponding low-level duration also being 3H1. The start times of the high-level signals of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, the fifth clock signal CLK5, the sixth clock signal CLK6, and the seventh clock signal CLK7 are sequentially separated by 1H1. The phase difference between the start times of the high-level signals of the fourth clock signal CLK4 and the third clock signal CLK3 is H1 / 2, and the phase difference between the start times of the high-level signals of the fifth clock signal CLK5 and the fourth clock signal CLK4 is H1 / 2. The phase difference between the start time of each data row of the data control signal written by the timing controller 30 to the source drive circuit 20 and the end time of the high level of the gate drive signal of the corresponding sub-pixel row is 3H1 / 4, and the phase difference between the end time of each data row of the data control signal written by the timing controller 30 to the source drive circuit 20 and the end time of the high level of the gate drive signal of the corresponding sub-pixel row is H1 / 2. In this case, sub-pixel row 1 is charged by data row 1, sub-pixel row 2 is charged by data row 2, sub-pixel row 3 is charged by data row 3, sub-pixel row 4 is charged by data rows 3 and 4, sub-pixel row 5 is charged by data row 4, sub-pixel row 6 is charged by data row 5, sub-pixel row 7 is charged by data row 6, sub-pixel row 8 is charged by data rows 6 and 7, and so on.

[0073] In some examples, referring to FIG6, the display method in this embodiment further includes receiving a display mode selection instruction before performing the above steps, and when the display mode selection instruction is a first display mode, the graphics card 50 sends the received first raw image data to the motherboard 40; the resolution of the first raw image data is M3×N3; M3 < M2. The motherboard 40 converts the first raw image data sent by the graphics card 50 into first image data, including: the motherboard 40 performs horizontal interpolation processing on the first raw image data to obtain the first image data.

[0074] It should be noted that the display device in this embodiment supports multiple display modes. For example, the display device includes a normal display mode, where the resolution of the image data is the same as the resolution of the display panel. In this mode, the data of each sub-pixel row and data row correspond one-to-one, and the display data written to each sub-pixel is real data. The display device also includes a first display mode. When a display mode selection instruction is received from the user to select the first display mode, the graphics card 50 sends the received first original image data to the motherboard 40. The resolution of the first original image data is M3×N3; M3 < M2. The motherboard 40 performs horizontal interpolation processing on the first original image data to obtain the first image data. For example, in the first display mode, the resolution of the first original image data is M3×N3 = 1920×1080, and the refresh rate is 240Hz. The motherboard 40 performs horizontal interpolation processing on the first original image data to obtain the first image data, M2×N2 = 2560×1080, and the refresh rate is 240Hz.

[0075] In some examples, referring to FIG6, the display method of this disclosure embodiment includes not only the above steps, but also the display method of this disclosure embodiment embodiment may include: receiving a display mode selection instruction, and when the indicated mode selection instruction is a second display mode, the graphics card 50 sends the received second raw image data to the motherboard 40.

[0076] The motherboard converts 40 pairs of original second image data into second image data; the resolution of the second image data is M4×N4; N4:N1 = 1:2; the refresh rate of the second image data is greater than the refresh rate of the first image data. For example, the resolution of the second image data is M4×N4 = 2560×720, and the refresh rate is 360Hz.

[0077] The specific steps of the motherboard 40 converting the second original image data into second image data include the motherboard 40 performing horizontal interpolation processing on the second original image data to obtain the second image data. For example, if the resolution of the second original image data is 1280*720 and the refresh rate is 360Hz, the motherboard 40 performs horizontal interpolation processing on the second original image data to obtain the second image data with a resolution of 2560*720 and a refresh rate of 360Hz.

[0078] The timing controller 30 provides multiple clock signals to the gate drive circuit 10 in the display panel and provides data control signals to the source drive circuit 20.

[0079] The gate driving circuit 10 selects each row of sub-pixels of the display panel according to multiple clock signals, and the source driving circuit 20 writes the second image data line by line to the sub-pixels located in even-numbered rows according to the data control signal, and writes the display data of the two adjacent sub-pixels located in even-numbered rows to the sub-pixels located in odd-numbered rows; or, the gate driving circuit 10 selects each row of sub-pixels of the display panel according to multiple clock signals, and the source driving circuit 20 writes the second image data line by line to the sub-pixels located in odd-numbered rows according to the data control signal, and writes the display data of the two adjacent sub-pixels located in odd-numbered rows to the sub-pixels located in even-numbered rows.

[0080] In the second display mode, the refresh rate is higher than that of the first display mode, and twice that of the normal display mode. The data row of the second image data in the second display mode is half the number of sub-pixel rows on the display panel. In this mode, by controlling the data control signal generated by the timing controller 30, the source drive circuit 20 writes real data to the sub-pixels located in odd-numbered rows, and charges the sub-pixels in even-numbered rows using a mixed charging method with the sub-pixels in the upper and lower rows. Alternatively, the source drive circuit 20 writes real data to the sub-pixels in even-numbered rows, and charges the sub-pixels in odd-numbered rows using a mixed charging method with the sub-pixels in the upper and lower rows. This method reduces image quality loss.

[0081] In some examples, in the second display mode, the start times of the effective levels of multiple clock signals are sequentially separated by 1H2, where H2 is half the phase difference between the start times of two adjacent effective levels of the data control signal. The duration of the effective level of the clock signal is 4H2, and the duty cycle of the effective level of the clock signal is 50%; the duration for which multiple clock signals satisfy the condition that adjacent row sub-pixels are simultaneously on is 3H2.

[0082] To make the display method in the second display mode of this disclosure clearer, the following detailed explanation is provided in conjunction with the timing diagram shown in Figure 7.

[0083] The timing controller 30 provides eight clock signals, CLK1 to CLK8, to the gate drive circuit 10. The duty cycle of the high-level signal of each clock signal is 50%, and the high-level clock duration is 4H2, with a corresponding low-level duration of 4H2. The start times of the high-level signals of the first clock signal CLK1, second clock signal CLK2, third clock signal CLK3, fourth clock signal CLK4, fifth clock signal CLK5, sixth clock signal CLK6, seventh clock signal CLK7, and eighth clock signal CLK8 are sequentially 1H2 apart. The phase difference between the start time of each data row of the data control signal written by the timing controller 30 to the source drive circuit 20 and the end time of the high-level gate drive signal of the corresponding sub-pixel row (odd-numbered rows) is 5H2 / 3, and the phase difference between the end time of each data row of the data control signal written by the timing controller 30 to the source drive circuit 20 and the end time of the high-level gate drive signal of the corresponding sub-pixel row is 4H2 / 3. In this case, subpixel row 1 is charged by data row 1, subpixel row 2 is charged by both data rows 1 and 2, subpixel row 3 is charged by data row 2, subpixel row 4 is charged by both data rows 2 and 3, subpixel row 5 is charged by data row 3, subpixel row 6 is charged by both data rows 3 and 4, subpixel row 7 is charged by data row 4, subpixel row 8 is charged by both data rows 4 and 5, and so on. That is, for odd-numbered rows of subpixels, the actual display data is written, while for even-numbered rows of subpixels, the display data from the adjacent rows above and below is used for filling. Similarly, referring to Figure 8, subpixel row 1 is charged by data row 1, subpixel row 2 is charged by data row 1, subpixel row 3 is charged by both data rows 1 and 2, subpixel row 4 is charged by data row 2, subpixel row 5 is charged by both data rows 2 and 3, subpixel row 6 is charged by data row 3, subpixel row 7 is charged by both data rows 3 and 4, subpixel row 8 is charged by data row 4, and so on. In this case, except for the first row of subpixels, even-numbered rows of subpixels are written with actual display data, while odd-numbered rows of subpixels are filled with a mixture of display data from the adjacent upper and lower rows of subpixels.

[0084] Referring again to Figure 1, this embodiment of the present disclosure also provides a graphics card 50, a motherboard 40, a gate driving circuit 10, a source driving circuit 20, and a display panel; the physical resolution of the display panel is M1×N1. The motherboard 40 is configured to convert the first raw image data sent by the graphics card 50 into first image data and send it to a timing controller 30; the resolution of the first image data is M2×N2; N2:N1 = a:b < 1. The timing controller 30 is configured to provide P clock signals to the gate driving circuit 10 in the display panel and to provide data control signals to the source driving circuit 20; P = i × b; i is a positive integer greater than or equal to 1; the gate driving circuit 10 selects each row of sub-pixels of the display panel according to the P clock signals, and the source driving circuit 20, according to the data control signals, writes the N2 rows of display data in the first image data line by line for each row of sub-pixels except for the j × b row, in the scanning order; and writes the display data of the b × j-1 and b × j+1 rows of sub-pixels of the j × b row of sub-pixels; j is a positive integer greater than or equal to 1, and b × j+1 ≤ N1.

[0085] The display device in the embodiments of this disclosure can be any device such as a mobile phone, tablet computer, laptop computer, e-book, game console, television, digital photo frame, navigator, etc., or any combination of display device and hardware. The embodiments of this disclosure do not limit this.

[0086] It should be noted that, for clarity and brevity, this disclosure does not show all the constituent units of the electronic device 1. To achieve the necessary functions of the electronic device, those skilled in the art can provide and set other constituent units (not shown) according to specific needs, and this disclosure does not limit this.

[0087] For a description of the relevant electronic device 1 and its technical effects, please refer to the description of the frequency divider provided in the embodiments of this disclosure, which will not be repeated here.

[0088] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A display method applied to a display device, the display device comprising a graphics card, a motherboard, a timing controller, and a display panel; The physical resolution of the display panel is M1×N1; the display method includes: The motherboard converts the first raw image data sent by the graphics card into first image data and sends it to the timing controller; the resolution of the first image data is M2×N2; N2:N1=a:b≤1; The timing controller provides P clock signals to the gate driving circuit in the display panel and data control signals to the source driving circuit; P = i × b; i is a positive integer greater than or equal to 1; the gate driving circuit selects each row of sub-pixels of the display panel according to the P clock signals, and the source driving circuit, according to the data control signals, writes the N2 row of display data in the first image data line by line for each row of sub-pixels except for the j × b row, in the scanning order; and writes the display data of the b × j-1 and b × j+1 row sub-pixels of the j × b row sub-pixels; j is a positive integer greater than or equal to 1, and b × j+1 ≤ N1.

2. The display method according to claim 1, wherein, The start time of the effective level of the (k+1)th clock signal is earlier than the end time of the effective level of the kth clock signal; K ranges from 1 to P-1. Of the P clock signals, except for the b×j-th clock signal, the phase difference between the start times of the effective levels of adjacent clock signals is 1H1, the phase difference between the start times of the effective levels of the b×j-th and b×j-1-th clock signals is A, and the phase difference between the start times of the effective levels of the b×j+1-th and b×j-th clock signals is B; A+B=H1; H1 is the phase difference between the start times of two adjacent effective levels of the data control signal.

3. The display method according to claim 1, wherein, The phase difference between the start times of the effective levels of the b×j-th and b×j-1-th clock signals is H1 / 2, and the phase difference between the start times of the effective levels of the b×j+1-th and b×j-th clock signals is H1 / 2.

4. The display method according to claim 1, wherein, The clock signal provided by the timing controller to the gate drive circuit and the data control signal provided to the source drive circuit satisfy the following: Except for the sub-pixels in the j×b row, the termination time of the data writing signal from the source driving circuit to the sub-pixel is earlier than the termination time of the effective level of the gate driving signal loaded on the sub-pixel.

5. The display method according to claim 4, wherein, The clock signal provided by the timing controller to the gate drive circuit and the data control signal provided to the source drive circuit satisfy the following: For sub-pixels except those in the j×b row, the phase difference between the termination time of the data signal written to the sub-pixel by the source driving circuit and the termination time of the effective level of the gate driving signal loaded on the sub-pixel is H1 / 2, where H1 is the phase difference between the start times of two adjacent effective levels of the data control signal.

6. The display method according to claim 1, wherein, The clock signal provided by the timing controller to the gate driving circuit satisfies the following condition: the time during which the gate driving signals loaded on the sub-pixels of adjacent rows are simultaneously at an effective level is not less than 2H1, where H1 is the phase difference between the start times of two adjacent effective levels of the data control signal.

7. The display method according to claim 1, wherein, When a:b = 3:4 and P = 4i; except for the 4e-th clock signal, the phase difference of the start time of the effective level of each of the other clock signals is 1H1; e is a positive integer from 1 to i; H1 is the phase difference of the start time of two adjacent effective levels of the data control signal; the phase difference of the start time of the effective level of the 4e-th and 4e-1-th clock signals is H1 / 2.

8. The display method according to claim 1, wherein, When a:b = 2:3 and P = 3i; except for the 3e-th clock signal, the phase difference of the start time of the effective level of each of the other clock signals is 1H1; e is a positive integer from 1 to i; H1 is the phase difference of the start time of two adjacent effective levels of the data control signal; the phase difference of the start time of the effective level of the 3e-th and 3e-1-th clock signals is H1 / 2.

9. The display method according to claim 1, wherein, The duty cycle of the effective level of the clock signal is 50%, and the duration of the effective level of the clock signal is 3H1; where H1 is the phase difference between the start times of two adjacent effective levels of the data control signal.

10. The display method according to any one of claims 1-9, wherein, M1 is equal to M2.

11. The display method according to any one of claims 1-9, wherein, Also includes: The graphics card receives a display mode selection instruction, and when the display mode selection instruction is a first display mode, the graphics card sends the received first raw image data to the motherboard; the resolution of the first raw image data is M3×N3. M3 < M2; The motherboard converts the first raw image data sent by the graphics card into first image data, including: The motherboard performs horizontal interpolation on the first original image data to obtain the first image data.

12. The display method according to claim 11, wherein, Also includes: The graphics card receives a display mode selection instruction, and when the display mode selection instruction is the second display mode, the graphics card sends the received second raw image data to the motherboard; The motherboard converts the second original image data into second image data; the resolution of the second image data is M4×N4; N4:N1=1:2; the refresh rate of the second image data is greater than the refresh rate of the first image data; The timing controller provides multiple clock signals to the gate driving circuit in the display panel and data control signals to the source driving circuit; The gate driving circuit selects each row of sub-pixels of the display panel according to the plurality of clock signals, and the source driving circuit writes the second image data line by line to the sub-pixels located in even-numbered rows according to the data control signal, and writes the display data of the two adjacent sub-pixels located in even-numbered rows to the sub-pixels in odd-numbered rows. or, The gate driving circuit selects each row of sub-pixels of the display panel according to the plurality of clock signals, and the source driving circuit writes the second image data line by line to the sub-pixels located in odd-numbered rows according to the data control signal, and writes the display data of the two adjacent sub-pixels located in odd-numbered rows to the sub-pixels in even-numbered rows.

13. The display method according to claim 12, wherein, In the second display mode, the start times of the effective levels of the plurality of clock signals are sequentially separated by 1H2, where H2 is half the phase difference between the start times of two adjacent effective levels of the data control signal.

14. The display method according to claim 13, wherein, In the second display mode, the effective level of the clock signal has a duration of 4H2, and the duty cycle of the effective level of the clock signal is 50%; the duration for which the multiple clock signals satisfy that adjacent row sub-pixels are simultaneously turned on is 3H2.

15. A display device comprising a graphics card, a motherboard, a gate driving circuit, a source driving circuit, and a display panel; wherein the physical resolution of the display panel is M1×N1; The motherboard is configured to convert the first raw image data sent by the graphics card into first image data and send it to the timing controller; the resolution of the first image data is M2×N2; N2:N1=a:b<1; The timing controller is configured to provide P clock signals to the gate driving circuit in the display panel and to provide data control signals to the source driving circuit. P = i × b; i is a positive integer greater than or equal to 1; the gate driving circuit selects each row of sub-pixels of the display panel according to the P clock signals, and the source driving circuit writes the N2 rows of display data in the first image data line by line according to the scanning order for each row of sub-pixels except for the j × b row according to the data control signal. Write the sub-pixel of row j×b into the display data of sub-pixels of rows b×j-1 and b×j+1; j is a positive integer greater than or equal to 1, and b×j+1≤N1.

Images