Semiconductor device and manufacturing method therefor
By introducing a barrier modulation layer and a sacrificial layer into gallium nitride semiconductor devices, the problem of low two-dimensional electron gas concentration was solved, and high-performance enhancement-mode devices were fabricated.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- INNOSCIENCE (SUZHOU) SEMICON CO LTD
- Filing Date
- 2025-08-01
- Publication Date
- 2026-07-09
AI Technical Summary
The low concentration of two-dimensional electron gas in gallium nitride semiconductor devices affects device performance.
In gallium nitride semiconductor devices, a barrier modulation layer and a sacrificial layer are introduced. The barrier modulation layer is used to protect the barrier layer and modulate the energy band. Its thickness is smaller than that of the barrier layer. The sacrificial layer is used to protect the barrier modulation layer. The concentration of two-dimensional electron gas is controlled by etching.
This increases the concentration of two-dimensional electron gas in semiconductor devices, ensuring the formation of enhancement-mode devices, avoiding the loss of the barrier modulation layer during etching, and improving device performance.
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Figure CN2025112115_09072026_PF_FP_ABST
Abstract
Description
Semiconductor devices and their fabrication methods
[0001] This application claims priority to Chinese Patent Application No. 202411959955.X, filed on December 30, 2024, and Chinese Patent Application No. 202510881234.X, filed on June 27, 2025, the entire contents of which are incorporated herein by reference. Technical Field
[0002] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for fabricating the same. Background Technology
[0003] Semiconductor devices, such as enhancement-mode high electron mobility transistors (HEMTs), have important applications in modern electronics.
[0004] In gallium nitride (GaN) semiconductor devices, a two-dimensional electron gas is typically formed by a barrier layer and a channel layer to create a conductive channel. However, the concentration of the two-dimensional electron gas in GaN semiconductor devices in related technologies is relatively low, and the performance of the semiconductor devices needs to be improved. Summary of the Invention
[0005] This application provides a semiconductor device and a method for fabricating the same, to improve the electrical performance of the semiconductor device.
[0006] According to one aspect of this application, a semiconductor device is provided, the semiconductor device comprising:
[0007] The substrate, channel layer, and barrier layer are stacked sequentially.
[0008] A barrier modulation layer is located on the side of the barrier layer away from the substrate. The barrier modulation layer is used to protect the barrier layer and modulate the energy band. The thickness of the barrier modulation layer is less than the thickness of the barrier layer.
[0009] A sacrificial layer is located on the side of the barrier modulation layer away from the substrate, and the sacrificial layer is used to protect the barrier modulation layer;
[0010] A doped group III-V semiconductor layer is located on the side of the sacrificial layer away from the substrate; the orthogonal projection of the doped group III-V semiconductor layer on the substrate overlaps the orthogonal projection of the sacrificial layer on the substrate.
[0011] The gate is located on the side of the doped III-V semiconductor layer away from the substrate.
[0012] Optionally, the semiconductor device further includes:
[0013] The source electrode is located on the side of the barrier layer away from the substrate;
[0014] The drain is located on the side of the barrier layer away from the substrate;
[0015] The orthogonal projection of the gate electrode onto the substrate is located between the orthogonal projections of the source electrode onto the substrate and the orthogonal projections of the drain electrode onto the substrate.
[0016] Optionally, the barrier modulation layer covers the entire barrier layer; the source is located on the side of the barrier modulation layer away from the substrate; the drain is located on the side of the barrier modulation layer away from the substrate.
[0017] Alternatively, the barrier modulation layer exposes the portion of the barrier layer corresponding to the source and the drain; the source is in contact with the barrier layer; and the drain is in contact with the barrier layer.
[0018] Optionally, the semiconductor device further includes a passivation layer covering the gate and the barrier modulation layer exposed by the sacrificial layer.
[0019] Optionally, the thickness of the barrier modulation layer is less than one-quarter of the thickness of the barrier layer.
[0020] Optionally, the thickness of the barrier modulation layer is less than the thickness of the sacrificial layer; the thickness of the sacrificial layer is less than the thickness of the barrier layer.
[0021] Optionally, the thickness of the barrier modulation layer ranges from 0.3 nm to 1.5 nm; and / or, the thickness of the sacrificial layer ranges from 1 nm to 5 nm.
[0022] Optionally, the thickness of the doped III-V semiconductor layer is greater than or equal to 100 nm; and / or, the thickness of the barrier layer ranges from 8 nm to 15 nm.
[0023] Optionally, the etching rate of the sacrificial layer is greater than the etching rate of the doped III-V semiconductor layer; the etching rate of the sacrificial layer is less than the etching rate of the barrier modulation layer.
[0024] Optionally, the material of the barrier modulation layer includes AlN; or, the material of the barrier modulation layer includes Al x Ga 1-x N(x>0.5), and the Al component content in the barrier modulation layer is greater than the Al component content in the barrier layer.
[0025] Optionally, the material of the sacrificial layer includes AlGaN; and / or, the material of the doped III-V semiconductor layer includes p-type doped GaN.
[0026] According to another aspect of this application, a method for fabricating a semiconductor device is provided, for fabricating the semiconductor device as described above, characterized in that the method for fabricating the semiconductor device includes:
[0027] Provide substrate;
[0028] A channel layer, a barrier layer, a barrier modulation layer, a sacrificial material layer, and a doped III-V group semiconductor layer are sequentially stacked on the substrate.
[0029] The doped III-V semiconductor layer and the sacrificial material layer are etched to form the doped III-V semiconductor layer and the sacrificial layer.
[0030] The technical solution of this application embodiment uses a semiconductor device comprising a substrate, a channel layer, and a barrier layer stacked sequentially; a barrier modulation layer located on the side of the barrier layer away from the substrate, which protects the barrier layer and modulates the energy band; the thickness of the barrier modulation layer is less than the thickness of the barrier layer; a sacrificial layer located on the side of the barrier modulation layer away from the substrate, which protects the barrier modulation layer; a doped III-V semiconductor layer located on the side of the sacrificial layer away from the substrate; the orthogonal projection of the doped III-V semiconductor layer on the substrate covers the orthogonal projection of the sacrificial layer on the substrate; and a gate located on the side of the doped III-V semiconductor layer away from the substrate. By setting a relatively thin barrier modulation layer, the two-dimensional electron gas concentration of the semiconductor device can be increased, and the formation of an enhancement-mode device can be ensured. In addition, by setting a sacrificial layer, it can be ensured that the relatively thin barrier modulation layer will not be completely etched during the etching process, thereby ensuring that the semiconductor device has a high two-dimensional electron gas concentration.
[0031] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description
[0032] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0033] Figure 1 is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application;
[0034] Figure 2 is a schematic diagram of the structure of another semiconductor device provided in an embodiment of this application;
[0035] Figure 3 is a schematic diagram of the structure of another semiconductor device provided in an embodiment of this application;
[0036] Figure 4 is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application;
[0037] Figures 5 and 6 are schematic diagrams of the product structure formed by the main steps of the semiconductor device fabrication method provided in the embodiments of this application. Detailed Implementation
[0038] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.
[0039] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0040] Figure 1 is a schematic diagram of a semiconductor device provided in an embodiment of this application. Referring to Figure 1, the semiconductor device includes: a substrate 11, a channel layer 13, and a barrier layer 14 stacked sequentially; the semiconductor device also includes a barrier modulation layer 15, which is located on the side of the barrier layer 14 away from the substrate 11, and is used to protect the barrier layer 14 and modulate the energy band; and the thickness of the barrier modulation layer 15 is less than the thickness of the barrier layer 14; a sacrificial layer 16, which is located on the side of the barrier modulation layer 15 away from the substrate 11, and is used to protect the barrier modulation layer 15; a doped III-V semiconductor layer 17, located on the side of the sacrificial layer 16 away from the substrate 11; the orthogonal projection of the doped III-V semiconductor layer 17 on the substrate 11 covers the orthogonal projection of the sacrificial layer 16 on the substrate 11; and a gate 18, located on the side of the doped III-V semiconductor layer 17 away from the substrate 11.
[0041] Specifically, the semiconductor device in this embodiment can be an enhancement-mode high electron mobility transistor. The substrate 11 serves to support the semiconductor device and provide insulation; the substrate 11 can be a silicon carbide substrate, a silicon substrate, a sapphire substrate, a diamond substrate, or a silicon nitride substrate, etc. The channel layer 13 and the barrier layer 14 form a heterojunction, and a two-dimensional electron gas is formed at the interface between the channel layer 13 and the barrier layer 14, thereby generating a conductive channel using the two-dimensional electron gas. The doped III-V semiconductor layer 17 is located between the gate 18 and the barrier layer 14 of the semiconductor device. The doped III-V semiconductor layer 17 can deplete the two-dimensional electron gas below the gate 18, thereby causing the semiconductor device to exhibit normally-off characteristics. When a suitable bias voltage is applied between the gate and source of the semiconductor device, the conductive channel reforms, thereby turning on the semiconductor device. The performance of the barrier layer 14 has a significant impact on the concentration of the two-dimensional electron gas. The polarization intensity of the barrier modulation layer 15 is much greater than that of the barrier layer 14. Therefore, adding the barrier modulation layer 15 to the semiconductor device will increase the concentration of the two-dimensional electron gas. However, the doped III-V semiconductor layer 17 has a limited ability to deplete the two-dimensional electron gas. Therefore, it is more difficult to achieve enhancement mode in the semiconductor device after adding the barrier modulation layer 15.
[0042] Furthermore, for regions where a two-dimensional electron gas needs to be generated in the off-state (such as the region corresponding to the gate and source, and the region corresponding to the gate and drain), a barrier modulation layer 15 is provided. The barrier modulation layer 15 can modulate the energy band to increase the concentration of the two-dimensional electron gas, thereby reducing the resistance of the semiconductor device. In other words, the semiconductor device needs to increase the concentration of the two-dimensional electron gas, but it also needs to ensure that enhancement mode can be achieved. In this embodiment, the thickness of the barrier modulation layer 15 is limited, that is, the thickness of the barrier modulation layer 15 is set to be less than the thickness of the barrier layer 14. The thinner thickness of the barrier modulation layer 15 can both increase the concentration of the two-dimensional electron gas and avoid the two-dimensional electron gas concentration being too high, which would prevent enhancement mode from being achieved. In addition, the stress of the barrier modulation layer 15 is relatively large. If it is too thick during the growth process, it will result in large lattice stress, or even relaxation, which will affect the performance of the barrier layer 14. In this embodiment, the thickness of the barrier modulation layer 15 is set to be relatively thin, which can avoid the stress of the barrier modulation layer 15 during the growth process from affecting the barrier layer 14.
[0043] In semiconductor devices, the barrier layer 14 is relatively thin, and in this embodiment, the barrier modulation layer 15 is even thinner, while the doped III-V semiconductor layer is relatively thick. Therefore, during the etching of the doped III-V semiconductor layer, if the doped III-V semiconductor layer is over-etched, the barrier modulation layer 15 is at high risk of being completely over-etched. Therefore, this embodiment further includes a sacrificial layer 16. The etching rate of the sacrificial layer 16 is greater than the etching rate of the doped III-V semiconductor layer, but less than the etching rate of the barrier modulation layer 15. Furthermore, the polarization intensity of the sacrificial layer 16 is less than that of the barrier modulation layer 15. For example, the sacrificial layer 16 is defined as being formed by etching a sacrificial material layer, and the doped III-V semiconductor layer is formed by etching a doped III-V semiconductor material layer. When etching a doped III-V semiconductor layer, if over-etching occurs, the sacrificial material layer will be etched away first, thereby protecting the subsequent barrier modulation layer 15 and preventing the excessively thin barrier modulation layer 15 from being etched.
[0044] The technical solution of this embodiment employs a semiconductor device comprising a substrate, a channel layer, and a barrier layer stacked sequentially; a barrier modulation layer located on the side of the barrier layer away from the substrate, which protects the barrier layer and modulates the energy band; the thickness of the barrier modulation layer is less than the thickness of the barrier layer; a sacrificial layer located on the side of the barrier modulation layer away from the substrate, which protects the barrier modulation layer; a doped III-V semiconductor layer located on the side of the sacrificial layer away from the substrate; the orthographic projection of the doped III-V semiconductor layer on the substrate overlaps the orthographic projection of the sacrificial layer on the substrate; and a gate located on the side of the doped III-V semiconductor layer away from the substrate. By setting a relatively thin barrier modulation layer, the two-dimensional electron gas concentration of the semiconductor device can be increased, while ensuring the formation of an enhancement-mode device. Furthermore, by setting a sacrificial layer, it can be ensured that the relatively thin barrier modulation layer is not completely etched during the etching process, thereby ensuring that the semiconductor device has a high two-dimensional electron gas concentration.
[0045] Optionally, continuing to refer to FIG1, the semiconductor device further includes: a source 19 located on the side of the barrier layer 14 away from the substrate 11; a drain 20 located on the side of the barrier layer away from the substrate 11; and a gate 18 with its orthogonal projection on the substrate 11 located between the orthogonal projections of the source 19 and the drain 20 on the substrate 11.
[0046] Specifically, an ohmic contact can be formed between the gate 18 and the doped III-V semiconductor layer 17; an ohmic contact can be formed between the source 19 and the barrier layer 14; and an ohmic contact can be formed between the drain 20 and the barrier layer 14. In the off state, the two-dimensional electron gas below the gate 18 is depleted by the doped III-V semiconductor layer 17, thus blocking the conductive channel between the source 19 and the drain 20. In the on state, that is, when a suitable bias voltage is applied between the gate 18 and the source 19, the conductive channel below the gate 18 reforms, and current can then flow between the source 19 and the drain 20. The source 19 can be titanium, aluminum, or an alloy thereof; the drain 20 can be titanium, aluminum, or an alloy thereof. The gate 18 can be nickel, gold, or an alloy thereof.
[0047] Optionally, continuing to refer to FIG1, the semiconductor device further includes a buffer layer 12 located between the substrate 11 and the channel layer 13. The buffer layer 12 can alleviate the problem of lattice mismatch between the substrate 11 and the channel layer 13. In some embodiments, the buffer layer 12 may be a GaN layer, etc. The channel layer 13 may be one or more of GaN, AlGaN, and InGaN layers. The doped III-V semiconductor layer 17 is, for example, a p-type doped GaN layer.
[0048] Alternatively, continuing to refer to FIG1, in some embodiments, the barrier modulation layer 15 exposes portions of the barrier layer 14 corresponding to the source 19 and the drain 20; the source 19 is in contact with the barrier layer 14; and the drain 20 is in contact with the barrier layer 14.
[0049] Specifically, in this embodiment, the barrier modulation layer 15 covers the portion of the barrier layer 14 corresponding to the doped III-V semiconductor layer 17, the portion of the barrier layer 14 corresponding to the doped III-V semiconductor layer 17 between the source 19, and the portion of the barrier layer 14 corresponding to the III-V semiconductor layer 17 between the drain 20.
[0050] Optionally, in some other embodiments, as shown in FIG2, FIG2 is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present application. In this embodiment, the barrier modulation layer 15 covers the entire barrier layer 14; the source 19 is located on the side of the barrier modulation layer 15 away from the substrate 11; and the drain 20 is located on the side of the barrier modulation layer 15 away from the substrate 11.
[0051] Specifically, in this embodiment, a barrier modulation layer 15 is provided to completely cover the barrier layer 14, and the bottom surface of the source 19 and the bottom surface of the drain 20 are in contact with the barrier modulation layer 15. This eliminates the need for etching the barrier modulation layer, thus avoiding the impact on the interface morphology and thickness of the barrier layer 14 caused by over-etching into the area between the gate 18 and the source 19 during etching of the barrier modulation layer 15. It also avoids the impact on the interface morphology and thickness of the barrier layer 14 caused by over-etching into the area between the gate 18 and the drain 20 during etching of the barrier modulation layer 15.
[0052] Optionally, Figure 3 is a schematic diagram of another semiconductor device provided in an embodiment of this application. Referring to Figure 3, the semiconductor device further includes a passivation layer 21 covering the gate 18, and a barrier modulation layer 15 exposed by the sacrificial layer 16.
[0053] Specifically, in this embodiment, since the barrier modulation layer 15 is not completely etched, and when the sacrificial layer 16 is formed, the portion of the sacrificial material layer other than the sacrificial layer 16 is etched. That is, the barrier modulation layer 15 is in contact with the passivation layer 21. In some embodiments, the surface materials of the two in contact are the same; for example, both the barrier modulation layer 15 and the passivation layer 21 are AlN, forming an AlN-AlN interface with good quality. In related technologies, the barrier layer 14 and the passivation layer 21 are in contact. The barrier layer 14 is generally chosen to be AlGaN, and the passivation layer 21 is also generally chosen to be AlN, forming an AlGaN-AlN interface. During the etching of AlGaN, the N element in AlGaN is selectively etched, and the Ga surface easily forms dangling bonds. When exposed to air, the surface is easily oxidized to form Ga-O bonds. Therefore, the surface of the barrier layer 14 and the passivation layer 21 in related technologies has a large number of Ga-O bonds, resulting in more interface defects. In other embodiments, the material of the barrier modulation layer 15 includes Al... x Ga 1-xThe content of Al in the barrier modulation layer 15 is greater than that in the barrier layer 14, and the content of Al in the barrier modulation layer 15 is greater than that in the barrier layer 14. In other words, the barrier modulation layer 15 uses AlGaN with a high Al content. AlN or AlGaN with a high Al content has a larger band gap, which modulates the energy band and effectively prevents two-dimensional electrons in the channel from transitioning to the surface of the barrier modulation layer 15 away from the substrate 11 and being captured by surface defects. That is, the configuration in this embodiment increases the concentration of two-dimensional electrons in the channel through the barrier modulation layer 15. Simultaneously, when the size of the barrier modulation layer 15 is fixed, if the Al content is high, the Ga content will be relatively low, resulting in fewer Ga-O bonds on the surface of the barrier modulation layer 15 and the passivation layer 21. This also optimizes the interface between the barrier modulation layer 15 and the passivation layer 21. In summary, the barrier modulation layer in this embodiment not only modulates the energy band but also optimizes the interface between the barrier modulation layer 15 and the passivation layer 21 when the semiconductor device includes a passivation layer.
[0054] Optionally, in some embodiments, the thickness of the barrier modulation layer 15 is less than one-quarter of the thickness of the barrier layer 14.
[0055] Specifically, if the barrier modulation layer 15 is too thick, the concentration of the two-dimensional electron gas will be too high, making it more difficult to form an enhancement-mode device. In this embodiment, the thickness of the barrier modulation layer 15 is very thin compared to the thickness of the barrier layer 14. The barrier modulation layer 15 can enhance the concentration of the two-dimensional electron gas without making it excessive. Furthermore, because the barrier modulation layer 15 is relatively thin compared to the barrier layer 14, the stress during the growth of the barrier modulation layer 15 can affect the performance of the barrier layer 14. Optionally, the thickness of the barrier modulation layer 15 can be one-sixth, one-seventh, or one-eighth of the thickness of the barrier layer 14.
[0056] Optionally, in some embodiments, the thickness of the barrier modulation layer 15 is less than the thickness of the sacrificial layer 16; the thickness of the sacrificial layer 16 is less than the thickness of the barrier layer 14.
[0057] Specifically, the thickness of the sacrificial layer 16 is greater than the thickness of the barrier modulation layer 15, which ensures that the barrier modulation layer 15 will not be etched away when etching the doped III-V semiconductor layer. At the same time, the thickness of the sacrificial layer 16 is less than the thickness of the barrier layer 14, which makes the sacrificial layer 16 have a smaller impact on the two-dimensional electron gas concentration, avoiding the sacrificial layer 16 from excessively increasing the two-dimensional electron gas concentration and making it difficult to form an enhancement mode.
[0058] Optionally, the sum of the thicknesses of the sacrificial layer 16 and the barrier modulation layer 15 is less than the thickness of the barrier layer 14. The overall thinner sacrificial layer 16 and barrier modulation layer 15 are more conducive to the migration of holes in the doped III-V semiconductor layer 17 to the barrier layer 14, thereby consuming the two-dimensional electron gas, which is more conducive to the formation of enhancement-mode devices.
[0059] Optionally, in some embodiments, the thickness of the barrier modulation layer 15 ranges from 0.3 nm to 1.5 nm. Optionally, it can be 0.3 nm, 0.5 nm, 0.7 nm, 0.9 nm, 1.1 nm, 1.3 nm, or 1.5 nm, etc.
[0060] Optionally, in some embodiments, the thickness of the sacrificial layer 16 ranges from 1 nm to 5 nm. Optionally, it can be 1 nm, 2 nm, 3 nm, 4 nm, or 5 nm, etc.
[0061] Optionally, in some embodiments, the thickness of the barrier layer 14 ranges from 8 nm to 15 nm. Optionally, it can be 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, or 15 nm, etc.
[0062] Optionally, in some embodiments, the etching rate of the sacrificial layer 16 is greater than the etching rate of the doped III-V semiconductor layer, and the etching rate of the sacrificial layer 16 is less than the etching rate of the barrier modulation layer 15 when etching the doped III-V semiconductor layer.
[0063] Specifically, because the etching rate of the sacrificial material layer is lower than that of the doped III-V semiconductor layer, when etching the doped III-V semiconductor layer, the doped III-V semiconductor layer is first etched at a faster rate to form the doped III-V semiconductor layer. When etching reaches the sacrificial material layer, the etching rate slows down, but is still faster than the etching rate of the barrier modulation layer 15. Therefore, the etching rate can be slowed down to avoid completely etching the barrier modulation layer 15, while also avoiding an etching rate that is too slow to remove the sacrificial material layer and expose the portion of the barrier modulation layer. In other words, the arrangement in this embodiment ensures that even when the barrier modulation layer 15 is relatively thin, the etching stop point when etching the doped III-V semiconductor layer is also located at the barrier modulation layer 15.
[0064] In some embodiments, the etching rate of the barrier modulation layer 15 is lower than that of the doped III-V semiconductor layer; the barrier modulation layer 15 can also serve as an etch stop structure for the doped III-V semiconductor layer. In other words, the combined structure of the sacrificial layer 16 and the barrier modulation layer 15 can be understood as an etch stop layer for the doped III-V semiconductor layer. The barrier modulation layer 15 has a large polarization intensity, which can increase the two-dimensional electron gas concentration; the sacrificial layer 16 increases the overall thickness of the etch stop layer, but does not significantly increase the two-dimensional electron gas concentration like the barrier modulation layer 15. Therefore, it can be understood that the sacrificial layer only effectively increases the thickness of the barrier modulation layer 15, without increasing its ability to increase the two-dimensional electron gas concentration. Furthermore, it ensures that the barrier modulation layer 15 is not completely etched when etching the doped III-V semiconductor layer.
[0065] Optionally, the etching gas for etching the doped III-V semiconductor layer 17 includes a chlorine-based etching gas doped with oxygen (O) or fluorine (F).
[0066] Specifically, aluminum in the barrier modulation layer 15 reacts with oxygen (O) in the etching gas to form dense and non-volatile Al2O3, and aluminum in the barrier modulation layer 15 reacts with fluorine (F) in the etching gas to form dense and non-volatile AlF3. This results in the etching rate of the etching gas on the doped III-V semiconductor layer 17 and the sacrificial layer 16 being greater than the etching rate on the barrier modulation layer 15.
[0067] Optionally, in some embodiments, the thickness of the doped III-V semiconductor layer 17 may be greater than or equal to 100 nm.
[0068] Optionally, in some embodiments, the sacrificial layer 16 may be a p-type doped semiconductor material layer. For example, it may be p-type InN. In this embodiment, the sacrificial layer 16 not only protects the barrier modulation layer 15, but also consumes the increased two-dimensional electron gas concentration caused by the setting of the barrier modulation layer 15, thereby enabling the doped III-V semiconductor layer to consume the two-dimensional electron gas below the gate, thus forming an enhancement-mode device.
[0069] Alternatively, in some other embodiments, the material of the sacrificial layer 16 may be AlGaN.
[0070] Based on the same concept, this application also provides a method for fabricating a semiconductor device, as shown in Figure 4. Figure 4 is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application. The method for fabricating the semiconductor device is used to fabricate the semiconductor device provided in any embodiment of this application. The method for fabricating the semiconductor device includes:
[0071] Step S110: Provide a substrate;
[0072] Step S120: A channel layer, a barrier layer, a barrier modulation layer, a sacrificial material layer, and a doped III-V group semiconductor layer are sequentially stacked on the substrate.
[0073] Specifically, Figures 5 and 6 are schematic diagrams of the product structure formed corresponding to the main steps of the semiconductor device fabrication method provided in the embodiments of this application. As shown in Figure 5, a buffer layer 12, a channel layer 13, a barrier layer 14, a barrier modulation layer 15, a sacrificial material layer 161, and a doped III-V group semiconductor layer 171 can be epitaxially formed on a substrate 11 first. The sacrificial material layer 161 is subsequently used to form a sacrificial layer, and the doped III-V group semiconductor layer is subsequently used to form a doped III-V group semiconductor layer.
[0074] Step S130: Etch the doped III-V semiconductor layer and the sacrificial material layer to form the doped III-V semiconductor layer and the sacrificial layer.
[0075] Specifically, as shown in Figure 6, the doped III-V semiconductor layer 171 can be etched using a chlorine-based etching gas containing oxygen (O) or fluorine (F) dopant. Furthermore, the gate 18 can be used as a mask to retain the portion of the doped III-V semiconductor layer 171 located below the gate 18, i.e., retaining the doped III-V semiconductor layer 171. The doped III-V semiconductor layer 171 is much thicker than the sacrificial material layer 161, and etching will over-etch into the sacrificial material layer 161. By setting the etching rate of the sacrificial material layer to be lower than the etching rate of the barrier modulation layer 15, etching can be ensured to stop at the barrier modulation layer 15. Furthermore, by setting a thinner barrier modulation layer, the two-dimensional electron gas concentration of the semiconductor device can be increased, and enhancement-mode devices can be formed. Additionally, by setting a sacrificial layer, it can be ensured that the thinner barrier modulation layer is not completely etched during the etching process, thereby ensuring that the semiconductor device has a high two-dimensional electron gas concentration.
[0076] Understandably, a source and a drain can then be formed to create the semiconductor device shown in Figure 2.
[0077] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this application can be achieved, and this is not limited herein.
[0078] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.
Claims
1. A semiconductor device, comprising: The substrate, channel layer, and barrier layer are stacked sequentially. A barrier modulation layer is located on the side of the barrier layer away from the substrate. The barrier modulation layer is used to protect the barrier layer and modulate the energy band. The thickness of the barrier modulation layer is less than the thickness of the barrier layer. A sacrificial layer is located on the side of the barrier modulation layer away from the substrate, and the sacrificial layer is used to protect the barrier modulation layer; A doped group III-V semiconductor layer is located on the side of the sacrificial layer away from the substrate; the orthogonal projection of the doped group III-V semiconductor layer on the substrate overlaps the orthogonal projection of the sacrificial layer on the substrate. The gate is located on the side of the doped III-V semiconductor layer away from the substrate.
2. The semiconductor device according to claim 1, further comprising: The source electrode is located on the side of the barrier layer away from the substrate; The drain is located on the side of the barrier layer away from the substrate; The orthogonal projection of the gate electrode onto the substrate is located between the orthogonal projections of the source electrode onto the substrate and the orthogonal projections of the drain electrode onto the substrate.
3. The semiconductor device according to claim 2, wherein, The barrier modulation layer covers the entire surface of the barrier layer; the source electrode is located on the side of the barrier modulation layer away from the substrate; the drain electrode is located on the side of the barrier modulation layer away from the substrate. Alternatively, the barrier modulation layer exposes the portion of the barrier layer corresponding to the source and the drain; the source is in contact with the barrier layer; and the drain is in contact with the barrier layer.
4. The semiconductor device of claim 1, further comprising a passivation layer covering the gate and the barrier modulation layer exposed by the sacrificial layer.
5. The semiconductor device according to claim 1, wherein, The thickness of the barrier modulation layer is less than one-quarter of the thickness of the barrier layer.
6. The semiconductor device according to claim 1, wherein, The thickness of the barrier modulation layer is less than the thickness of the sacrificial layer; the thickness of the sacrificial layer is less than the thickness of the barrier layer.
7. The semiconductor device according to claim 5 or 6, wherein, The thickness of the barrier modulation layer ranges from 0.3 nm to 1.5 nm; and / or the thickness of the sacrificial layer ranges from 1 nm to 5 nm.
8. The semiconductor device according to claim 1, wherein, The thickness of the doped III-V semiconductor layer is greater than or equal to 100 nm; and / or the thickness of the barrier layer ranges from 8 nm to 15 nm.
9. The semiconductor device according to claim 1, wherein, The etching rate of the sacrificial layer is greater than that of the doped III-V semiconductor layer; the etching rate of the sacrificial layer is less than that of the barrier modulation layer.
10. The semiconductor device according to claim 1, wherein, The material of the barrier modulation layer includes AlN; or, the material of the barrier modulation layer includes Al x Ga 1-x N(x>0.5), and the Al component content in the barrier modulation layer is greater than the Al component content in the barrier layer.
11. The semiconductor device according to claim 1, wherein, The material of the sacrificial layer includes AlGaN; and / or, the material of the doped III-V semiconductor layer includes p-type doped GaN.
12. A method for fabricating a semiconductor device, used to fabricate the semiconductor device according to any one of claims 1-11, the method comprising: Provide substrate; A channel layer, a barrier layer, a barrier modulation layer, a sacrificial material layer, and a doped III-V group semiconductor layer are sequentially stacked on the substrate. The doped III-V semiconductor layer and the sacrificial material layer are etched to form the doped III-V semiconductor layer and the sacrificial layer.