Semiconductor device and manufacturing method therefor, and electronic device

Abstract

The present application provides a semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device comprises a semiconductor substrate, a first epitaxial layer, a second epitaxial layer, and a passive element. The first epitaxial layer is located on the semiconductor substrate, the surface of the side of the first epitaxial layer away from the semiconductor substrate is provided with a first recess and a second recess, the first recess is located in an active region, and the second recess is located in a passive region. The second epitaxial layer comprises a first doped semiconductor structure and a second doped semiconductor structure, at least a part of the first doped semiconductor structure is located in the first recess, and at least a part of the second doped semiconductor structure is located in the second recess. In a thickness direction of the semiconductor substrate, the projection of the passive element does not completely overlap the projection of the second doped semiconductor structure. In the present application, the passive element can be made to avoid the pattern of the second epitaxial layer, so as to reduce the impact of the flatness of the second epitaxial layer on the passive element, thereby improving the performance of the passive element in the semiconductor device.

Description

A semiconductor device, its fabrication method and electronic device

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411988590.3, filed with the State Intellectual Property Office of the People's Republic of China on December 30, 2024, entitled "A Semiconductor Device, Method of Manufacturing Thereof and Electronic Equipment", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of radio frequency device technology, and more particularly to a semiconductor device, its manufacturing method, and an electronic device. Background Technology

[0004] GaN-based high electron mobility transistors (HEMTs) are used as radio frequency front-end devices, offering significant advantages such as high output power and high efficiency. During fabrication, secondary epitaxial growth processes are employed to create the source or drain electrodes, reducing the resistivity of ohmic contacts in HEMT devices and effectively improving their output power and efficiency. The ease of secondary epitaxial growth is closely related to the duty cycle of the growth region on the wafer surface. A higher duty cycle results in better uniformity and doping uniformity of the secondary epitaxial film; therefore, large-area growth is typically performed outside the channel region.

[0005] However, due to the high concentration of doping in the secondary epitaxial growth process, the material in the growth region will have high density of voids and other significant dislocations. Furthermore, protrusions and spikes will appear at the boundary between the growth region and the non-growth region, resulting in poor surface smoothness of the secondary epitaxial film and affecting the performance of passive components such as capacitors and inductors formed subsequently. Summary of the Invention

[0006] This application provides a semiconductor device, its fabrication method, and an electronic device to improve the performance of passive components such as capacitors and inductors in HEMT devices.

[0007] In a first aspect, embodiments of this application provide a semiconductor device. The semiconductor device in embodiments of this application may include an active region and a passive region. The active region may be a region in the semiconductor device that has transistors. For example, the source, drain, gate and other structures in the semiconductor device may be disposed in the active region. The passive region may be a region in the semiconductor device that has passive components such as capacitors and inductors.

[0008] The semiconductor device provided in this application embodiment may include: a semiconductor substrate, a first epitaxial layer, a second epitaxial layer, and a passive element. The first epitaxial layer is located on the semiconductor substrate, and has a first groove and a second groove on its surface facing away from the semiconductor substrate. The first groove is located within an active region, and the second groove is located within a passive region. The second epitaxial layer may include a first semiconductor doped structure and a second semiconductor doped structure, with at least a portion of the first semiconductor doped structure located within the first groove and at least a portion of the second semiconductor doped structure located within the second groove. The passive element is located on the side of the first epitaxial layer facing away from the semiconductor substrate, within a passive region, and the projection of the passive element does not completely overlap with the projection of the second semiconductor doped structure in the thickness direction of the semiconductor substrate.

[0009] In the semiconductor device provided in this application embodiment, a first groove and a second groove are provided on the surface of the first epitaxial layer. The first groove is located in the active region, and the second groove is located in the passive region. During the fabrication of the second epitaxial layer using a secondary epitaxial growth process, the first semiconductor doped structure in the second epitaxial layer can grow within the first groove, and the second semiconductor doped structure can grow within the second groove, preventing the formation of patterns in other areas of the second epitaxial layer. This allows subsequently formed passive components to avoid the patterns in the second epitaxial layer, reducing the impact of the flatness of the second epitaxial layer on the passive components and improving the performance of passive components in the semiconductor device. For example, this can improve the uniformity of the dielectric layer thickness in a capacitor, enhance the consistency of the capacitor's capacitance value, and increase the capacitor's yield.

[0010] In one possible implementation, the projections of the passive element and the second semiconductor doped structure can be non-overlapping along the thickness direction of the semiconductor substrate. This allows the passive element to completely avoid the pattern of the second epitaxial layer, preventing the flatness of the second epitaxial layer from affecting the passive element. In another possible implementation, the projections of the passive element and the second semiconductor doped structure can partially overlap along the thickness direction of the semiconductor substrate. This reduces the overlap area between the passive element and the pattern of the second epitaxial layer, thus mitigating the impact of the flatness of the second epitaxial layer on the passive element.

[0011] In the embodiments of this application, the passive components can be resistors, capacitors, or inductors. In specific implementations, the number and types of passive components in the semiconductor device can be reasonably set according to actual needs. Furthermore, according to actual needs, all passive components in the semiconductor device can be set to avoid the second groove, or a portion of the passive components in the semiconductor device can be set to avoid the second groove; no limitation is made here.

[0012] In specific configurations, the surface of the first semiconductor doped structure (or the second semiconductor doped structure) may be lower than the surface of the first epitaxial layer; alternatively, the surface of the first semiconductor doped structure (or the second semiconductor doped structure) may be substantially flush with the surface of the first epitaxial layer; or alternatively, the surface of the first semiconductor doped structure (or the second semiconductor doped structure) may be higher than the surface of the first epitaxial layer. In practical implementation, the heights of the first and second semiconductor doped structures can be reasonably set according to actual needs, and are not limited here. For example, the first semiconductor doped structure (or the second semiconductor doped structure) may include gallium nitride (GaN) material doped with a high concentration of N-type impurities, and the doping elements may include Si, Ge, In, etc., with a doping concentration greater than or equal to 1e⁻¹. 19 / cm 3 This allows the contact resistivity of semiconductor devices to be less than or equal to 0.1 Ω·mm.

[0013] In this embodiment, the transistor in the semiconductor device may include a source, a drain, and a gate located in the active region. The source (or drain) may include a first semiconductor doped structure and a contact structure, with the contact structure located on the side of the first semiconductor doped structure facing away from the semiconductor substrate. By providing a heavily doped first semiconductor doped structure in the first groove of the first epitaxial layer, the barrier width between the semiconductor and the metal can be reduced, which is beneficial for reducing the ohmic contact resistivity of the semiconductor device. The contact structure may include a metallic material such as titanium (Ti), and the contact structure can serve as a reactant in the ohmic contact of the semiconductor device.

[0014] In one possible implementation, the first epitaxial layer may include a channel layer and a barrier layer, with the barrier layer located on the side of the channel layer facing away from the semiconductor substrate. A first groove extends from the surface of the first epitaxial layer facing away from the semiconductor substrate into the interior of the channel layer, and a second groove extends from the surface of the first epitaxial layer facing away from the semiconductor substrate into the interior of the channel layer. The bottom of the first groove is located inside the channel layer, allowing the first semiconductor doped structure to directly contact the channel layer, thereby reducing the contact resistance between the source (or drain) and the first epitaxial layer. During the fabrication process, annealing can be performed at a relatively low temperature (e.g., in the range of 200°C to 500°C), which can form a good and reliable ohmic contact.

[0015] During the operation of a semiconductor device, a two-dimensional electron gas is generated at the interface between the channel layer and the barrier layer. The region in this interface where the two-dimensional electron gas exists is the channel region, which is located within the aforementioned active region. The gate is located at a position corresponding to the channel region. In the thickness direction of the semiconductor substrate, the projection of the first groove does not overlap with the projection of the channel region, that is, the projection of the gate does not overlap with the projection of the first semiconductor doped structure.

[0016] In this embodiment, by forming a second groove in the first epitaxial layer in the passive region and forming a second semiconductor doped structure in the second groove, the pattern area of ​​the second epitaxial layer can be increased. For example, in the thickness direction of the semiconductor substrate, the ratio of the sum of the projected areas of the first and second semiconductor doped structures to the projected area of ​​the first epitaxial layer can be less than or equal to 15%. Thus, during the fabrication of the second epitaxial layer using a secondary epitaxial growth process, epitaxial material can be grown in both the regions containing the first and second grooves, resulting in a larger growth area and a higher-quality second epitaxial layer. This leads to a lower contact resistance between the source (or drain) and the first epitaxial layer. Furthermore, passive components in the passive region are positioned away from the second groove, thereby reducing the impact of the flatness of the second epitaxial layer on the passive components. Therefore, the semiconductor device provided in this embodiment can reduce the impact on the performance of passive components without affecting the quality of the second epitaxial layer. In specific configurations, the number, size, and position of the first and second grooves can be reasonably set according to actual needs.

[0017] In one possible implementation, the semiconductor device may further include: a first dielectric layer and a first interconnect structure. The first dielectric layer is located on the side of the first epitaxial layer opposite to the semiconductor substrate, and a first via is provided in the first dielectric layer. In the thickness direction of the semiconductor substrate, the first via overlaps with a first groove. At least a portion of the first interconnect structure is located within the first via, and the first interconnect structure is electrically connected to a contact structure. That is, the first interconnect structure can be electrically connected to a source (or drain), serving to bring out the source (or drain). In a specific configuration, the first interconnect structure may be located on the side of the contact structure opposite to the semiconductor substrate. In some cases, the first interconnect structure is in contact with the contact structure, but the first interconnect structure and the first semiconductor doped structure are not in contact; that is, the first semiconductor doped structure is covered by the contact structure, and the first interconnect structure is connected to the first semiconductor doped structure through the contact structure. In other cases, a portion of the first interconnect structure is in contact with the contact structure, and a portion is in contact with the first semiconductor doped structure. That is, the first semiconductor doped structure is not completely covered by the contact structure, and the first semiconductor doped structure can be directly connected to the first interconnect structure.

[0018] In some embodiments of this application, a first dielectric layer covers a second semiconductor doped structure, and passive components are located on the side of the first dielectric layer facing away from the semiconductor substrate. That is, the passive components are separated from the second semiconductor doped structure by the first dielectric layer, preventing the second semiconductor doped structure from affecting the function of the passive components. Furthermore, the passive components are also separated from the first epitaxial layer by the first dielectric layer, ensuring that the passive components are insulated from the first epitaxial layer.

[0019] In some other embodiments of this application, the semiconductor device may further include: a second dielectric layer located on the side of the first dielectric layer facing away from the semiconductor substrate. The second dielectric layer may cover the surface of the first interconnect structure facing away from the semiconductor substrate. In this way, the first interconnect structure can be kept insulated from the conductive components above it through the second dielectric layer, and the second dielectric layer may also serve to protect the first interconnect structure.

[0020] In some cases, when the passive component is a resistor or inductor, it can be located between the first dielectric layer and the second dielectric layer. This allows the passive component to be insulated from other conductive components through the first and second dielectric layers. When the passive component is a resistor, the semiconductor device may further include a second interconnect structure electrically connected to the resistor, and this second interconnect structure may be located between the first and second dielectric layers.

[0021] In other cases, when the passive component is a capacitor, the capacitor may include a first electrode and a second electrode stacked together, with the second electrode located on the side of the first electrode facing away from the semiconductor substrate. The first electrode may be located between a first dielectric layer and a second dielectric layer, and the second electrode may be located on the side of the second dielectric layer facing away from the semiconductor substrate. That is, the second dielectric layer can be reused as the dielectric layer in the capacitor, thereby making the structure of the semiconductor device more compact.

[0022] Secondly, embodiments of this application also provide a method for fabricating a semiconductor device. The method for fabricating a semiconductor device provided in embodiments of this application may include:

[0023] Step 1: Using the first epitaxial process, a first epitaxial layer is formed on the semiconductor substrate.

[0024] Step 2: A mask layer is formed on the first epitaxial layer. The mask layer is patterned so that it covers the channel region of the active region and at least a portion of the passive region. The location of the passive region covered by the mask layer can be the area where passive components such as capacitors, inductors, and resistors will be formed. The mask layer can cover part or all of the capacitor region, resistor region, or inductor region. Then, using the mask layer as a shield, the first epitaxial layer is etched to form a first groove and a second groove on the surface of the first epitaxial layer. After forming the first groove and the second groove, the mask layer is removed.

[0025] In this embodiment, the mask layer covers the channel region of the active area, protecting it from damage caused by the etching process. Furthermore, the mask layer covers at least a portion of the passive area, specifically the non-growth area for the subsequent second epitaxial process. This facilitates the formation of passive components that avoid the pattern of the second epitaxial layer. In specific implementations, the ratio of the total area of ​​the mask layer pattern to the total area of ​​the first epitaxial layer is less than or equal to 85%, and the ratio of the sum of the areas of the first and second grooves formed on the surface of the first epitaxial layer to the total area of ​​the first epitaxial layer is less than or equal to 15%. In the subsequent second epitaxial process, epitaxial material can be grown in the areas containing the first and second grooves, resulting in a larger growth area and a higher quality second epitaxial layer. Since the first and second grooves are fabricated using the same etching process, their depths are essentially equal.

[0026] In one possible implementation, insulating materials such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON) can be used to fabricate the mask layer, which may include one or more insulating films.

[0027] Step 3: Form a second epitaxial layer using a second epitaxial process; the second epitaxial layer may include a first semiconductor doped structure and a second semiconductor doped structure; at least a portion of the first semiconductor doped structure is located in a first groove, and at least a portion of the second semiconductor doped structure is located in a second groove.

[0028] During the second epitaxial process, in order to ensure that the formed first semiconductor doped structure fills the first groove and minimizes the contact resistance between the source (or drain) and the first epitaxial layer, the formed first semiconductor doped structure is typically made slightly higher than the surface of the first epitaxial layer. Of course, in some cases, the surface of the first semiconductor doped structure can be substantially flush with the surface of the first epitaxial layer; or, the surface of the first semiconductor doped structure can be lower than the surface of the first epitaxial layer. The height of the first semiconductor doped structure can be reasonably set according to actual needs. Since the first and second semiconductor doped structures are fabricated using the same epitaxial process, their heights are essentially equal.

[0029] In one possible implementation, gallium nitride (GaN) material doped with a high concentration of N-type impurities can be used to fabricate the second epitaxial layer. The doping elements can include Si, Ge, In, etc., with a doping concentration greater than or equal to 1e. 19 / cm 3 This allows the contact resistivity of semiconductor devices to be less than or equal to 0.1 Ω·mm.

[0030] Step 4: Form passive components within the passive region above the first epitaxial layer; the projection of the passive component does not completely overlap with the projection of the second semiconductor doped structure in the thickness direction of the semiconductor substrate. For example, the passive component may include resistors, capacitors, inductors, etc.

[0031] In the semiconductor device fabrication method provided in this application embodiment, a mask layer is formed on a first epitaxial layer, and the pattern of the mask layer covers the channel region of the active region and at least a portion of the passive region. The pattern-covered area of ​​the mask layer is the non-growth area of ​​the subsequent second epitaxial process. This facilitates the formation of passive components that avoid the pattern of the second epitaxial layer, reduces the impact of the flatness of the second epitaxial layer on the passive components, and improves the performance of the passive components in the semiconductor device.

[0032] Thirdly, embodiments of this application also provide an electronic device, which may include any of the semiconductor devices and circuit boards mentioned in the first aspect above, wherein the semiconductor device is electrically connected to the circuit board. The semiconductor devices in these embodiments can effectively improve the performance of passive components such as capacitors and inductors; therefore, the electronic device including this semiconductor device has better electrical performance. Attached Figure Description

[0033] Figure 1 is a schematic diagram of the structure of the electronic device provided in an embodiment of this application;

[0034] Figure 2 is a schematic diagram of the structure of the semiconductor device provided in an embodiment of this application;

[0035] Figure 3 is a flowchart of the method for fabricating a semiconductor device provided in an embodiment of this application;

[0036] Figures 4 to 8 are schematic diagrams of the structure corresponding to each step in the manufacturing method provided in the embodiments of this application.

[0037] Reference numerals: 100 - Electronic device; 101 - Semiconductor device; 102 - Circuit board; 20 - Semiconductor substrate; 21 - First epitaxial layer; 211 - Channel layer; 212 - Barrier layer; 213 - Insertion layer; 214 - Buffer layer; 215 - Cap layer; 22 - Second epitaxial layer; 22a - First semiconductor doped structure; 22b - Second semiconductor doped structure; 23 - Passive component; 23R - Resistor; 23L - Inductor; 23C - Capacitor; 24 - Contact structure; 251 - First dielectric layer; 252 - Second dielectric layer; 261 - First interconnect structure; 262 - Second interconnect structure; 27 - Mask layer; C1 - First electrode; C2 - Second electrode; S - Source; D - Drain; G - Gate; U1 - First groove; U2 - Second groove; A - Active region; B - Passive region; T - First via; M - Mark; Q - Channel region. Detailed Implementation

[0038] In the fabrication process of high electron mobility transistors (HEMTs), secondary epitaxial growth is used to create the source or drain electrodes. This reduces the resistivity of the ohmic contacts in HEMTs, effectively improving their output power and efficiency. The ease of secondary epitaxial growth is closely related to the duty cycle of the growth region on the wafer surface. A higher duty cycle results in better uniformity and doping uniformity of the secondary epitaxial film; therefore, large-area growth is typically performed outside the channel region. However, due to the high concentration (typically 1e) in secondary epitaxial growth processes... 19 / cm 3 Doping (both left and right) can cause high-density voids and other significant dislocations in the growth region. Furthermore, protrusions and spikes may appear at the boundary between the growth and non-growth regions, resulting in poor surface smoothness of the secondary epitaxial film. This negatively impacts the performance of subsequently formed passive components such as capacitors and inductors. For example, it can reduce the yield of passive components like capacitors, which require high flatness; it can also cause significant fluctuations in the uniformity of the dielectric layer thickness in capacitors, leading to capacitance deviations or even capacitor failure; and poor flatness in passive components can also result in higher RF losses in HEMT devices.

[0039] Based on this, in order to improve the performance of passive components such as capacitors and inductors in HEMT devices, embodiments of this application provide a semiconductor device, its fabrication method, and an electronic device. The semiconductor device provided in this application can be a high electron mobility transistor (HEMT) device; exemplarily, the semiconductor device provided in this application can be a GaN-based HEMT device. Of course, in some cases, the semiconductor device provided in this application can also be other types of transistor devices, and this application does not limit its application.

[0040] The semiconductor device provided in this application can be applied to various types of electronic devices, such as mobile phones, tablets, laptops, and other portable terminal devices. Specifically, the semiconductor device provided in this application can be applied to radio frequency (RF) application devices; for example, it can be used as an RF front-end device. Because the resistivity of the ohmic contacts in this semiconductor device is low, it can be applied to low-voltage (≤15V) RF application devices.

[0041] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.

[0042] It should be noted that the accompanying drawings in this application are for illustrative purposes only and do not represent actual scale. The same reference numerals in the accompanying drawings denote the same or similar structures, and therefore, repeated descriptions of them will be omitted.

[0043] The terms describing position and direction used in this application, such as "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," are merely illustrative examples based on the orientation or positional relationships shown in the accompanying drawings. They are intended solely for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Changes may be made as needed, and all such changes are included within the scope of protection of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0044] Figure 1 is a schematic diagram of the structure of the electronic device provided in the embodiment of this application. The left side of Figure 1 is a top view of the electronic device, and the right side of Figure 1 is a cross-sectional view of the top view of the electronic device at the dashed line AA'. As shown in Figure 1, the electronic device 100 provided in the embodiment of this application may include a semiconductor device 101 and a circuit board 102, with the semiconductor device 101 and the circuit board 102 electrically connected. The semiconductor device 101 in the embodiment of this application can effectively improve the performance of passive components such as capacitors and inductors. Therefore, the electronic device 100 including the semiconductor device 101 has better electrical performance. Figure 1 uses a mobile phone as an example for illustration. When the electronic device 100 is another device, the position, shape, size, etc. of the semiconductor device 101 and the circuit board 102 in the electronic device 100 can be reasonably set according to actual needs.

[0045] Figure 2 is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application. As shown in Figure 2, the semiconductor device 101 in this embodiment may include an active region A and a passive region B. The active region A may be a region in the semiconductor device 101 that has a transistor. For example, the source, drain, gate and other structures in the semiconductor device 101 may be disposed in the active region A. The passive region B may be a region in the semiconductor device 101 that has passive components 23 such as capacitors and inductors.

[0046] The semiconductor device 101 provided in this application embodiment may include: a semiconductor substrate 20, a first epitaxial layer 21, a second epitaxial layer 22, and a passive element 23. The first epitaxial layer 21 is located on the semiconductor substrate 20, and has a first groove U1 and a second groove U2 on its surface facing away from the semiconductor substrate 20. The first groove U1 is located in an active region A, and the second groove U2 is located in a passive region B. The second epitaxial layer 22 may include a first semiconductor doped structure 22a and a second semiconductor doped structure 22b. At least a portion of the first semiconductor doped structure 22a is located in the first groove U1, and at least a portion of the second semiconductor doped structure 22b is located in the second groove U2. The passive element 23 is located on the side of the first epitaxial layer 21 facing away from the semiconductor substrate 20. The passive element 23 is located in the passive region B, and in the thickness direction of the semiconductor substrate 20, the projection of the passive element 23 does not completely overlap with the projection of the second semiconductor doped structure 22b.

[0047] In the semiconductor device 101 provided in this application embodiment, a first groove U1 and a second groove U2 are provided on the surface of the first epitaxial layer 21. The first groove U1 is located in the active region A, and the second groove U2 is located in the passive region B. During the fabrication of the second epitaxial layer 22 using a secondary epitaxial growth process, the first semiconductor doped structure 22a in the second epitaxial layer 22 can grow in the first groove U1, and the second semiconductor doped structure 22b can grow in the second groove U2. Other areas will not form the pattern of the second epitaxial layer 22. In this way, the passive components 23 formed subsequently can avoid the pattern of the second epitaxial layer 22, reducing the impact of the flatness of the second epitaxial layer 22 on the passive components 23, thereby improving the performance of the passive components 23 in the semiconductor device 101. For example, this can improve the thickness uniformity of the dielectric layer in a capacitor, improve the consistency of the capacitor value, and improve the yield of the capacitor.

[0048] In one possible implementation, the projection of the passive element 23 and the projection of the second semiconductor doped structure 22b can be non-overlapping along the thickness direction of the semiconductor substrate 20. This allows the passive element 23 to completely avoid the pattern of the second epitaxial layer 22, preventing the flatness of the second epitaxial layer 22 from affecting the passive element 23. In another possible implementation, the projection of the passive element 23 and the projection of the second semiconductor doped structure 22b can partially overlap along the thickness direction of the semiconductor substrate 20. This reduces the overlap area between the passive element 23 and the pattern of the second epitaxial layer 22, thus reducing the impact of the flatness of the second epitaxial layer 22 on the passive element 23.

[0049] In this embodiment, the passive element 23 can be a resistor 23R, a capacitor 23C, or an inductor 23L. Figure 2 illustrates an example where the semiconductor device 101 includes three passive elements 23: a resistor 23R, a capacitor 23C, and an inductor 23L. In actual implementation, the number and type of passive elements 23 in the semiconductor device 101 can be reasonably set according to actual needs. Figure 2 illustrates an example where each passive element 23 in the semiconductor device 101 avoids the position of the second groove U2. In actual implementation, some passive elements 23 in the semiconductor device 101 can also be set to avoid the position of the second groove U2. This can be set according to actual needs and is not limited here.

[0050] In specific configurations, the surface of the first semiconductor doped structure 22a (or the second semiconductor doped structure 22b) may be lower than the surface of the first epitaxial layer 21; alternatively, the surface of the first semiconductor doped structure 22a (or the second semiconductor doped structure 22b) may be substantially flush with the surface of the first epitaxial layer 21; or alternatively, the surface of the first semiconductor doped structure 22a (or the second semiconductor doped structure 22b) may be higher than the surface of the first epitaxial layer 21. In specific implementations, the heights of the first semiconductor doped structure 22a and the second semiconductor doped structure 22b can be reasonably set according to actual needs, and are not limited here. For example, the first semiconductor doped structure 22a (or the second semiconductor doped structure 22b) may include gallium nitride (GaN) material doped with a high concentration of N-type impurities, and the doping elements may include Si, Ge, In, etc., with a doping concentration greater than or equal to 1e⁻¹. 19 / cm 3 In this way, the contact resistivity of the semiconductor device 101 can be less than or equal to 0.1 Ω·mm.

[0051] In this embodiment, the transistor in the semiconductor device 101 may include a source S, a drain D, and a gate G located in the active region A. The source S (or drain D) may include a first semiconductor doped structure 22a and a contact structure 24, with the contact structure 24 located on the side of the first semiconductor doped structure 22a facing away from the semiconductor substrate 20. By providing a heavily doped first semiconductor doped structure 22a in the first groove U1 of the first epitaxial layer 21, the barrier width between the semiconductor and the metal can be reduced, which is beneficial for reducing the ohmic contact resistivity of the semiconductor device 101. The contact structure 24 may include a metallic material such as titanium (Ti), and the contact structure 24 can serve as a reactant in the ohmic contact of the semiconductor device 101.

[0052] In one possible implementation, the first epitaxial layer 21 may include a channel layer 211 and a barrier layer 212, with the barrier layer 212 located on the side of the channel layer 211 facing away from the semiconductor substrate 20. A first groove U1 extends from the surface of the first epitaxial layer 21 facing away from the semiconductor substrate 20 into the interior of the channel layer 211, and a second groove U2 extends from the surface of the first epitaxial layer 21 facing away from the semiconductor substrate 20 into the interior of the channel layer 211. The bottom of the first groove U1 is located inside the channel layer 211, allowing the first semiconductor doped structure 22a to directly contact the channel layer 211, thereby reducing the contact resistance between the source S (or drain D) and the first epitaxial layer 21. During the fabrication process, annealing can be performed at a relatively low temperature (e.g., in the range of 200°C to 500°C), which can form a good and reliable ohmic contact.

[0053] During the operation of semiconductor device 101, a two-dimensional electron gas is generated at the interface between channel layer 211 and barrier layer 212. The region in this interface where the two-dimensional electron gas exists is the channel region, which is located within the aforementioned active region A. The gate G is located at a position corresponding to the channel region. In the thickness direction of semiconductor substrate 20, the projection of the first groove U1 does not overlap with the projection of the channel region, that is, the projection of the gate G does not overlap with the projection of the first semiconductor doped structure 22a.

[0054] In this embodiment, by forming a second groove U2 in the first epitaxial layer 21 of the passive region B, and forming a second semiconductor doped structure 22b in the second groove U2, the pattern area of ​​the second epitaxial layer 22 can be increased. Exemplarily, in the thickness direction of the semiconductor substrate 20, the ratio of the sum of the projected areas of the first semiconductor doped structure 22a and the second semiconductor doped structure 22b to the projected area of ​​the first epitaxial layer 21 can be less than or equal to 15%. Thus, during the fabrication of the second epitaxial layer 22 using a secondary epitaxial growth process, epitaxial material can be grown in the regions where the first groove U1 and the second groove U2 are located. The larger area of ​​the growth region results in a higher quality second epitaxial layer 22, thereby reducing the contact resistance between the source S (or drain D) and the first epitaxial layer 21. Furthermore, the passive element 23 in the passive region B is positioned away from the second groove U2. For example, in Figure 2, the wavy line indicates poor flatness of the film layer. It can be clearly seen from Figure 2 that there is no pattern of the second epitaxial layer 22 below the passive element 23, thereby reducing the impact of the flatness of the second epitaxial layer 22 on the passive element 23. Therefore, the semiconductor device 101 provided in this application embodiment can reduce the impact on the performance of the passive element 23 without affecting the quality of the second epitaxial layer 22. In specific settings, the number, size, and position of the first groove U1 and the second groove U2 can be reasonably set according to actual needs.

[0055] In specific implementations, the first epitaxial layer 21 in this embodiment may further include: an insertion layer 213, a buffer layer 214, and a cap layer 215. The insertion layer 213 may be located between the channel layer 211 and the barrier layer 212, the buffer layer 214 may be located between the channel layer 211 and the semiconductor substrate 20, and the cap layer 215 may be located on the side of the barrier layer 212 facing away from the semiconductor substrate 20. The layers in the first epitaxial layer 21 are illustrated here as examples. In specific implementations, the layers in the first epitaxial layer 21 can be reasonably arranged according to actual needs, and no limitation is made here. In one possible implementation, the semiconductor substrate 20 may include a high-resistivity semiconductor material. For example, the semiconductor substrate 20 may include silicon (Si), silicon carbide (SiC), gallium nitride (GaN), or sapphire materials with high resistivity. The channel layer 211 may include gallium nitride (GaN), and the barrier layer 212 may include aluminum gallium nitride (AlGaN) or indium gallium nitride (InGaN). The insertion layer 213 may include aluminum nitride (AlN) material. The buffer layer 214 may include gallium nitride (GaN) material. The cap layer 215 may include gallium nitride (GaN) material. The materials of each film layer in the semiconductor substrate 20 and the first epitaxial layer 21 are illustrated here. In some cases, other materials may be used for each film layer in the first epitaxial layer 21, which is not limited here.

[0056] Referring again to Figure 2, in one possible implementation, the semiconductor device 101 may further include a first dielectric layer 251 and a first interconnect structure 261. The first dielectric layer 251 is located on the side of the first epitaxial layer 21 facing away from the semiconductor substrate 20, and a first via T is provided in the first dielectric layer 251. In the thickness direction of the semiconductor substrate 20, the first via T and the first groove U1 have an overlapping area. At least a portion of the first interconnect structure 261 is located within the first via T, and the first interconnect structure 261 is electrically connected to the contact structure 24. That is, the first interconnect structure 261 can be electrically connected to the source S (or drain D), and can serve to bring out the source S (or drain D). In a specific configuration, the first interconnect structure 261 may be located on the side of the contact structure 24 facing away from the semiconductor substrate 20. In some cases, such as at the drain D location in Figure 2, the first interconnect structure 261 is in contact with the contact structure 24, but the first interconnect structure 261 and the first semiconductor doped structure 22a are not in contact. That is, the first semiconductor doped structure 22a is covered by the contact structure 24, and the first interconnect structure 261 is connected to the first semiconductor doped structure 22a through the contact structure 24. In other cases, such as at the source S location in Figure 2, a portion of the first interconnect structure 261 is in contact with the contact structure 24, and a portion is in contact with the first semiconductor doped structure 22a. That is, the first semiconductor doped structure 22a is not completely covered by the contact structure 24, and the first semiconductor doped structure 22a can be directly connected to the first interconnect structure 261.

[0057] In some embodiments of this application, the first dielectric layer 251 covers the second semiconductor doped structure 22b, and the passive element 23 is located on the side of the first dielectric layer 251 facing away from the semiconductor substrate 20. That is, the passive element 23 is separated from the second semiconductor doped structure 22b by the first dielectric layer 251, preventing the second semiconductor doped structure 22b from affecting the function of the passive element 23. Furthermore, the passive element 23 is also separated from the first epitaxial layer 21 by the first dielectric layer 251, which keeps the passive element 23 insulated from the first epitaxial layer 21.

[0058] In a specific implementation, the first dielectric layer 251 may include multiple dielectric films. At least one dielectric film in the first dielectric layer 251 shifts the side of the film layer where the gate G is located that is close to the semiconductor substrate 20, while the remaining dielectric films in the first dielectric layer 251 are located on the side of the film layer where the gate G is located that is away from the semiconductor substrate 20, thereby playing the role of adjusting the stress at the location of the gate G.

[0059] In some other embodiments of this application, the semiconductor device 101 may further include a second dielectric layer 252 located on the side of the first dielectric layer 251 facing away from the semiconductor substrate 20. The second dielectric layer 252 may cover the surface of the first interconnect structure 261 facing away from the semiconductor substrate 20. In this way, the first interconnect structure 261 can be kept insulated from the conductive components above through the second dielectric layer 252, and the second dielectric layer 252 may also protect the first interconnect structure 261.

[0060] In some cases, when the passive element 23 is a resistor 23R or an inductor 23L, the passive element 23 can be located between the first dielectric layer 251 and the second dielectric layer 252. In this way, the passive element 23 can be insulated from other conductive components through the first dielectric layer 251 and the second dielectric layer 252. When the passive element 23 is a resistor 23R, the semiconductor device 101 may further include a second interconnect structure 262, which is electrically connected to the resistor 23R, and the second interconnect structure 262 can be located between the first dielectric layer 251 and the second dielectric layer 252.

[0061] In other cases, when the passive component 23 is a capacitor 23C, the capacitor 23C may include a first electrode C1 and a second electrode C2 stacked together, with the second electrode C2 located on the side of the first electrode C1 facing away from the semiconductor substrate 20. The first electrode C1 may be located between the first dielectric layer 251 and the second dielectric layer 252, and the second electrode C2 may be located on the side of the second dielectric layer 252 facing away from the semiconductor substrate 20. That is, the second dielectric layer 252 can be reused as the dielectric layer in the capacitor 23C, thereby making the structure of the semiconductor device 101 more compact.

[0062] Based on the same technical concept, this application also provides a method for fabricating a semiconductor device. Figure 3 is a flowchart of the method for fabricating a semiconductor device provided in this application, and Figures 4 to 8 are schematic diagrams of the structures corresponding to each step in the fabrication method provided in this application. As shown in Figure 3, the method for fabricating a semiconductor device provided in this application may include:

[0063] S301. Referring to Figure 4, a first epitaxial layer 21 is formed on the semiconductor substrate 20 using a first epitaxial process.

[0064] In one possible implementation, the semiconductor substrate 20 may include a silicon (Si) material, a silicon carbide (SiC) material, a gallium nitride (GaN) material, or a sapphire material with high resistivity. Step S301 may specifically include forming a channel layer 211 on the semiconductor substrate 20 and forming a barrier layer 212 on the channel layer 211. Exemplarily, the channel layer 211 may be formed using gallium nitride (GaN) material, and the barrier layer 212 may be formed using aluminum gallium nitride (AlGaN) material or indium gallium nitride (InGaN) material. In some embodiments, before forming the barrier layer 212, an insertion layer 213 may be formed on the channel layer 211; for example, the insertion layer 213 may be formed using aluminum nitride (AlN) material. In other embodiments, before forming the channel layer 211, a buffer layer 214 may be formed on the semiconductor substrate 20; for example, the buffer layer 214 may be formed using gallium nitride (GaN) material. After the barrier layer 212 is formed, a cap layer 215 can also be formed after the barrier layer 212. For example, the cap layer 215 can be formed using gallium nitride (GaN) material.

[0065] After the first epitaxial layer 21 is formed, the first epitaxial layer 21 can be etched to form a mark M at the edge of the first epitaxial layer 21.

[0066] S302. Referring to Figure 5, a mask layer 27 is formed on the first epitaxial layer 21. The mask layer 27 is patterned so that it covers the channel region Q of the active region A and at least a portion of the passive region B. The location of the passive region B covered by the mask layer 27 can be the region where passive components such as capacitors, inductors, and resistors will be formed. The mask layer 27 can cover part or all of the capacitor region, resistor region, and inductor region. Then, using the mask layer 27 as a shield, the first epitaxial layer 21 is etched to form a first groove U1 and a second groove U2 on the surface of the first epitaxial layer 21. After forming the first groove U1 and the second groove U2, the mask layer 27 is removed to obtain the structure shown in Figure 6.

[0067] In this embodiment, the mask layer 27 covers the channel region Q of the active region A, protecting the channel region Q from damage caused by the etching process. Furthermore, the mask layer 27 covers at least a portion of the passive region B, and the area covered by the mask layer 27 is the non-growth area for the subsequent second epitaxial process. This facilitates the formation of passive components that avoid the pattern of the second epitaxial layer. In specific implementations, the ratio of the total area of ​​the mask layer 27 pattern to the total area of ​​the first epitaxial layer 21 is less than or equal to 85%, and the ratio of the sum of the areas of the first groove U1 and the second groove U2 formed on the surface of the first epitaxial layer 21 to the total area of ​​the first epitaxial layer 21 is less than or equal to 15%. In the subsequent second epitaxial process, epitaxial material can be grown in the areas where the first groove U1 and the second groove U2 are located. The larger area of ​​the growth region results in a higher quality second epitaxial layer 22. Since the first groove U1 and the second groove U2 are fabricated using the same etching process, their depths are essentially equal.

[0068] In one possible implementation, the mask layer 27 can be formed using thin film deposition methods such as metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), sputtering, and evaporation. The mask layer 27 can be fabricated using insulating materials such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON), and may include one or more insulating thin films.

[0069] S303. Referring to FIG7, a second epitaxial layer 22 is formed using a second epitaxial process. The second epitaxial layer 22 may include a first semiconductor doped structure 22a and a second semiconductor doped structure 22b. At least a portion of the first semiconductor doped structure 22a is located in the first groove U1, and at least a portion of the second semiconductor doped structure 22b is located in the second groove U2.

[0070] During the second epitaxial process, in order to ensure that the formed first semiconductor doped structure 22a fills the first groove U1 and minimizes the contact resistance between the source (or drain) and the first epitaxial layer 21, the formed first semiconductor doped structure 22a is typically made slightly higher than the surface of the first epitaxial layer 21. Of course, in some cases, the surface of the first semiconductor doped structure 22a can be substantially flush with the surface of the first epitaxial layer 21; or, the surface of the first semiconductor doped structure 22a can be lower than the surface of the first epitaxial layer 21. The height of the first semiconductor doped structure 22a can be reasonably set according to actual needs. Since the first semiconductor doped structure 22a and the second semiconductor doped structure 22b are fabricated using the same epitaxial process, their heights are essentially equal.

[0071] In one possible implementation, gallium nitride (GaN) material doped with a high concentration of N-type impurities can be used to fabricate the second epitaxial layer 22. The doping elements can include Si, Ge, In, etc., and the doping concentration is greater than or equal to 1e 19 / cm 3 In this way, the contact resistivity of the semiconductor device 101 can be less than or equal to 0.1 Ω·mm.

[0072] For example, the second epitaxial process may include thin film deposition processes such as MOCVD, MBE, PECVD, LPCVD, ALD, sputtering, and evaporation.

[0073] After step S303, referring to FIG8, a contact structure 24 is formed at the location of the first semiconductor doped structure 22a on the second epitaxial layer 22 to form a source S or a drain D. Then, each film layer in the first dielectric layer 251 and the gate G are formed.

[0074] S304. Continuing to refer to Figure 8, a passive element 23 is formed in the passive region B above the first epitaxial layer 21; in the thickness direction of the semiconductor substrate 20, the projection of the passive element 23 does not completely overlap with the projection of the second semiconductor doped structure 22b.

[0075] In one possible implementation, the first dielectric layer 251 covers the second semiconductor doped structure 22b, and the passive element 23 can be formed on the first dielectric layer 251. In this way, the passive element 23 is separated from the second semiconductor doped structure 22b by the first dielectric layer 251, preventing the second semiconductor doped structure 22b from affecting the function of the passive element 23. Furthermore, the passive element 23 is also separated from the first epitaxial layer 21 by the first dielectric layer 251, ensuring that the passive element 23 and the first epitaxial layer 21 remain insulated.

[0076] For example, passive component 23 may include components such as resistor 23R, capacitor 23C, and inductor 23L.

[0077] In addition, the manufacturing method in the embodiments of this application may also include steps such as forming a first interconnect structure 261, a second interconnect structure 262, and a second dielectric layer 252.

[0078] In the semiconductor device fabrication method provided in this application embodiment, a mask layer 27 is formed on the first epitaxial layer 21, and the pattern of the mask layer 27 covers the channel region of the active region A and at least a portion of the passive region B. The pattern-covered area of ​​the mask layer 27 is the non-growth area of ​​the subsequent second epitaxial process. This facilitates the formation of passive components that avoid the pattern of the second epitaxial layer 22, reduces the impact of the flatness of the second epitaxial layer 22 on the passive component 23, and improves the performance of the passive component 23 in the semiconductor device 101.

[0079] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0080] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of the embodiments of this application. Therefore, if these modifications and variations to the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

Claims

1. A semiconductor device, characterized in that, include: Semiconductor substrate; A first epitaxial layer is located on the semiconductor substrate, and the first epitaxial layer has a first groove and a second groove on the surface of the first epitaxial layer facing away from the semiconductor substrate; the semiconductor device includes an active region and a passive region, the first groove is located in the active region, and the second groove is located in the passive region; The second epitaxial layer includes a first semiconductor doped structure and a second semiconductor doped structure; at least a portion of the first semiconductor doped structure is located within the first groove, and at least a portion of the second semiconductor doped structure is located within the second groove. A passive element is located on the side of the first epitaxial layer away from the semiconductor substrate; the passive element is located within the passive region, and the projection of the passive element in the thickness direction of the semiconductor substrate does not completely overlap with the projection of the second semiconductor doped structure.

2. The semiconductor device as claimed in claim 1, characterized in that, In the thickness direction of the semiconductor substrate, the projection of the passive element and the projection of the second semiconductor doped structure do not overlap; or, in the thickness direction of the semiconductor substrate, the projection of the passive element and the projection of the second semiconductor doped structure partially overlap.

3. The semiconductor device as described in claim 1 or 2, characterized in that, The semiconductor device further includes: a first dielectric layer, a contact structure, and a first interconnect structure; The first dielectric layer is located on the side of the first epitaxial layer away from the semiconductor substrate. The first dielectric layer has a first through-hole. In the thickness direction of the semiconductor substrate, the first through-hole and the first groove have an overlapping area. The contact structure is located on the side of the first semiconductor doped structure opposite to the semiconductor substrate, at least a portion of the first interconnect structure is located within the first via, and the first interconnect structure is electrically connected to the contact structure.

4. The semiconductor device as described in claim 3, characterized in that, The first interconnect structure is located on the side of the contact structure opposite to the semiconductor substrate; The first interconnect structure is in contact with the contact structure, and the first interconnect structure is not in contact with the first semiconductor doped structure; or, a portion of the first interconnect structure is in contact with the contact structure, and a portion is in contact with the first semiconductor doped structure.

5. The semiconductor device as described in claim 3 or 4, characterized in that, The first dielectric layer covers the second semiconductor doped structure, and the passive element is located on the side of the first dielectric layer away from the semiconductor substrate.

6. The semiconductor device as claimed in claim 5, characterized in that, The semiconductor device further includes: a second dielectric layer located on the side of the first dielectric layer opposite to the semiconductor substrate, the second dielectric layer covering the surface of the first interconnect structure opposite to the semiconductor substrate; The passive component is a resistor or an inductor, and the passive component is located between the first dielectric layer and the second dielectric layer.

7. The semiconductor device as claimed in claim 5, characterized in that, The semiconductor device further includes: a second dielectric layer located on the side of the first dielectric layer opposite to the semiconductor substrate, the second dielectric layer covering the surface of the first interconnect structure opposite to the semiconductor substrate; The passive component is a capacitor, which includes a first electrode and a second electrode stacked together, wherein the second electrode is located on the side of the first electrode away from the semiconductor substrate. The first electrode is located between the first dielectric layer and the second dielectric layer, and the second electrode is located on the side of the second dielectric layer opposite to the semiconductor substrate.

8. The semiconductor device according to any one of claims 1 to 7, characterized in that, In the thickness direction of the semiconductor substrate, the ratio of the sum of the projected areas of the first semiconductor doped structure and the second semiconductor doped structure to the projected area of ​​the first epitaxial layer is less than or equal to 15%.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that, The first epitaxial layer includes a channel layer and a barrier layer; the barrier layer is located on the side of the channel layer opposite to the semiconductor substrate. The first groove extends from the surface of the first epitaxial layer away from the semiconductor substrate to the interior of the channel layer, and the second groove extends from the surface of the first epitaxial layer away from the semiconductor substrate to the interior of the channel layer.

10. An electronic device, characterized in that, include: The semiconductor device and circuit board according to any one of claims 1 to 9, wherein the semiconductor device is electrically connected to the circuit board.

11. A method for fabricating a semiconductor device, characterized in that, include: A first epitaxial layer is formed on a semiconductor substrate using a first epitaxial process; A mask layer is formed on the first epitaxial layer, and the mask layer is patterned so that the mask layer covers the channel region of the active region and covers at least a portion of the passive region; Using the mask layer as a shield, the first epitaxial layer is etched to form a first groove and a second groove on the surface of the first epitaxial layer; A second epitaxial layer is formed using a second epitaxial process; the second epitaxial layer includes a first semiconductor doped structure and a second semiconductor doped structure; at least a portion of the first semiconductor doped structure is located within the first groove, and at least a portion of the second semiconductor doped structure is located within the second groove; Passive components are formed in the passive region above the first epitaxial layer; In the thickness direction of the semiconductor substrate, the projection of the passive element does not completely overlap with the projection of the second semiconductor doped structure.

12. The manufacturing method as described in claim 11, characterized in that, The ratio of the total area of ​​the mask layer pattern to the total area of ​​the first epitaxial layer is less than or equal to 85%.

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