Clock synchronization method and apparatus

Abstract

The present application relates to the technical field of communications, and provides a clock synchronization method and apparatus. The clock synchronization method can be applied to a first network device, and the first network device can be a network device located at an intermediate node in a clock synchronization network. The method comprises: on the basis of an acquired reset signal, switching an operation mode from a first mode to a second mode, wherein the first mode is a joint mode in which a transparent clock mode and an ordinary clock mode are simultaneously operated, and the second mode is an independent mode in which only the transparent clock mode is operated; and when the operation mode is the second mode, if a clock packet is received, forwarding the clock packet. In the present application, two clock synchronization modes, i.e., a joint mode and an independent mode, are deployed for a first network device, so that when the first network device is reset, a clock link does not need to be re-established for a third network device of the first network device, thereby ensuring, when the first network device is reset, that a downstream network device of the first network device can continue to operate normally.

Description

Clock synchronization method and device

[0001] This application claims priority to Chinese Patent Application No. 202411999317.0, filed with the Chinese Patent Office on December 31, 2024, entitled "Clock Synchronization Method and Apparatus", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communication technology, and in particular to a clock synchronization method and apparatus. Background Technology

[0003] In wireless networks, Precision Time Protocol (PTP) can be used to synchronize clocks between network devices. Network devices using PTP can operate in various modes, including Transparent Clock (TC) and Boundary Clock (BC). For example, in a PTP cascading scenario (where multiple PTP-enabled network devices are connected sequentially), an intermediate device running in BC mode can exchange packets with its upstream and downstream devices to synchronize their clocks. An intermediate device running TC mode, however, does not synchronize its clock with its upstream and downstream devices; it only forwards packets between its upstream and downstream devices and measures the forwarding latency.

[0004] To prevent downstream devices from malfunctioning due to the reset of an intermediate device in a PTP cascade scenario, the current clock synchronization method for intermediate devices is to default to BC mode and switch to TC mode upon reset. However, after the intermediate device switches to TC mode, the clock link between the downstream device and the intermediate device is broken. The downstream device needs to interact with the upstream device of the intermediate device to establish a link, and this link establishment process takes time. Therefore, the current clock synchronization method still causes downstream devices to malfunction for a period of time. Thus, ensuring the continued normal operation of downstream devices when an intermediate device resets has become a pressing technical problem to be solved. Summary of the Invention

[0005] This application provides a clock synchronization method and apparatus that can ensure the continuous normal operation of downstream devices when an intermediate device in a multi-cascaded network is reset.

[0006] In a first aspect, this application provides a clock synchronization method, which can be applied to a first network device; the method includes: switching the operating mode from a first mode to a second mode based on an acquired reset signal; and forwarding the clock message if a clock message is received when the operating mode is the second mode.

[0007] In this context, the first network device can be a network device located at an intermediate node in the clock synchronization network in a PTP cascading scenario; in the clock synchronization network, the network device located at the preceding node of the first network device (i.e., the network device upstream of the first network device) is the second network device of the first network device; in the clock synchronization network, the network device located at the following node of the first network device (i.e., the network device downstream of the first network device) is the third network device of the first network device.

[0008] The first network device is pre-configured with two clock synchronization modes (i.e., the operating modes in this application): a first mode and a second mode. The first mode is a combined mode that simultaneously operates a transparent clock mode and an ordinary clock (OC) mode, while the second mode is an independent mode that only operates the transparent clock mode. The first network device operates in the first mode under normal circumstances; when the first network device is reset, it operates in the second mode. When operating in the ordinary clock mode, the first network device can synchronize its local clock with the clock source of the clock synchronization network; when operating in the transparent clock mode, the first network device can forward clock messages. For example, the first network device can forward clock messages between the second and third network devices, enabling the third network device to synchronize its local clock with the clock source based on the clock messages.

[0009] In the technical solution provided in this application, two clock synchronization modes are pre-configured for the first network device: a combined mode (i.e., the first mode) that simultaneously runs transparent clock mode and normal clock mode, and an independent mode (i.e., the second mode) that only runs transparent clock mode. Under normal circumstances, the first network device defaults to running both transparent clock mode and normal clock mode simultaneously. When the first network device is reset, only the normal clock mode is reset, while the transparent clock mode is retained. That is, the first network device only runs transparent clock mode upon reset (i.e., switching from the first mode to the second mode). Since the first network device normally only forwards clock messages between the third and second network devices, and uses transparent clock mode to achieve clock synchronization between the third network device's local clock and the clock source, the third network device actually achieves clock synchronization with the clock source through a clock link with the head node of the clock synchronization network (this clock link depends on the first network device's transparent clock mode). Therefore, when the first network device resets, since the transparent clock mode does not reset, the clock link between the third network device and the first node remains intact. This allows the first network device to continue forwarding clock messages between the second and third network devices, enabling the third network device to synchronize its local clock with the clock source based on these clock messages. It can be seen that this application, by deploying both federated and standalone clock synchronization modes for the first network device and switching between them as needed, eliminates the need to re-establish clock links for downstream third network devices when the first network device resets. Therefore, this application ensures the continued normal operation of downstream devices even when an intermediate device in a multi-cascaded network system resets.

[0010] In one possible implementation, the clock synchronization method provided in this application further includes: when the operating mode is the first mode, if a clock message is received, forwarding the clock message using the transparent clock mode; and using the normal clock mode, synchronizing the local clock of the first network device with the clock source based on the clock message.

[0011] Since the first mode is a combined mode that simultaneously operates transparent clock mode and normal clock mode, when the first network device is running in the first mode under normal circumstances, it can use the normal clock mode to synchronize its local clock with the clock source. This ensures that the local clock of the first network device is synchronized with the clocks of other devices in the clock synchronization network, thereby ensuring the continuous normal operation of downstream devices of the first network device.

[0012] In another possible implementation, if a clock message is received, the clock message is forwarded using a transparent clock mode, including: if a clock message is received through the first PTP port of the first network device, the clock message is forwarded through the second PTP port of the first network device using a transparent clock mode; and the local clock of the first network device is synchronized with the clock source based on the clock message, including: synchronizing the local clock of the first network device with the clock source based on the clock message received through the first PTP port.

[0013] This application allows for the deployment of two ports (i.e., a first PTP port and a second PTP port) on the first network device, with both ports configured to simultaneously support transparent clock mode and normal clock mode. This reduces the number of ports deployed on the first network device, lowering the configuration requirements for transmission equipment in the fronthaul network.

[0014] In another possible implementation, the transparent clock mode is an end-to-end transparent clock mode.

[0015] Transparent clock modes include end-to-end and point-to-point transparent clock modes. If the first network device adopts a point-to-point transparent clock mode, the path delay measurement in the entire clock synchronization network needs to be performed between each link segment. The link delay of each link between the master and slave nodes is accumulated in the clock message and transmitted level by level to the third network device. Thus, when the first network device is reset, since the path delay of each link segment needs to be measured, the third network device downstream of the first network device still needs to interact with the second network device upstream of the first network device to establish a link. Based on this, in this application, the first network device adopts an end-to-end transparent clock mode.

[0016] In another possible implementation, the clock synchronization method provided in this application further includes: performing an initialization operation based on the acquired start signal to initialize the running mode to the first mode.

[0017] In another possible implementation, after switching the operating mode from the first mode to the second mode based on the acquired reset signal, the clock synchronization method provided in this application further includes: switching the operating mode from the second mode to the first mode based on the acquired recovery signal.

[0018] In another possible implementation, the reset signal is a non-power-down type reset signal.

[0019] The technical solution provided in this application needs to support the first network device retaining the transparent clock mode during reset. However, the first network device cannot operate in transparent clock mode during power-down reset. Based on this, this application only applies to configuring the first network device to operate in the second mode when the first network device receives a non-power-down type reset signal.

[0020] In another possible implementation, the synchronous Ethernet link of the first network device is not interrupted during the second mode operation.

[0021] Since PTP is based on Ethernet transmission, the synchronous Ethernet link is the foundation for communication and interaction between network devices in the entire clock synchronization network. Therefore, when resetting the first network device, this application must not only maintain the transparent clock mode without resetting, but also ensure that the synchronous Ethernet link remains uninterrupted.

[0022] Secondly, this application provides a clock synchronization device configured in a first network device; the device includes: a mode switching module, used to switch the operating mode from a first mode to a second mode based on an acquired reset signal; the first mode is a combined mode that simultaneously operates a transparent clock mode and a normal clock mode, and the second mode is an independent mode that only operates a transparent clock mode; a transparent clock module, used to forward a clock message if a clock message is received when the operating mode is the second mode.

[0023] In one possible implementation, the clock synchronization device provided in this application further includes a normal clock module; a transparent clock module, which is further used to forward clock messages using a transparent clock mode when a clock message is received in the first operating mode; and a normal clock module, which is used to synchronize the local clock of the first network device with the clock source based on the clock message using the normal clock mode.

[0024] In another possible implementation, the transparent clock module is specifically used to: if a clock message is received through the first PTP port of the first network device, then the clock message is forwarded through the second PTP port of the first network device using the transparent clock mode; the ordinary clock module is specifically used to: synchronize the local clock of the first network device with the clock source based on the clock message received through the first PTP port.

[0025] In another possible implementation, the transparent clock mode is an end-to-end transparent clock mode.

[0026] In another possible implementation, the clock synchronization device provided in this application further includes an initialization module; the initialization module is used to perform an initialization operation based on the acquired start signal to initialize the operating mode to the first mode.

[0027] In another possible implementation, the mode switching module is also used to switch the operating mode from the second mode to the first mode based on the acquired recovery signal.

[0028] In another possible implementation, the reset signal is a non-power-down type reset signal.

[0029] In another possible implementation, the synchronous Ethernet link of the first network device is not interrupted during the second mode operation.

[0030] Thirdly, this application provides a network device including a memory and at least one processor; the memory is coupled to the processor; wherein the memory stores computer program code, the computer program code including computer instructions, and when the computer instructions are executed by the processor, the network device performs the method provided in the first aspect or any implementation thereof.

[0031] Fourthly, this application provides a computer-readable storage medium including computer instructions that, when executed on a computer, cause the computer to perform the method provided in the first aspect or any implementation thereof.

[0032] Fifthly, this application provides a computer program product that, when run on a computer, causes the computer to execute the method provided in the first aspect or any implementation thereof.

[0033] It is understood that the technical effects of the technical solutions provided in the second to fifth aspects of this application can be referred to the technical effects corresponding to the first aspect or any implementation of the first aspect, and will not be repeated here.

[0034] Based on the implementation methods provided in the above aspects, this application can be further combined to provide more implementation methods. Attached Figure Description

[0035] Figure 1 is a schematic diagram of a clock synchronization network in related technologies;

[0036] Figure 2 is a schematic diagram of another clock synchronization network in the related technology;

[0037] Figure 3 is a schematic diagram of a clock synchronization network provided in an embodiment of this application;

[0038] Figure 4 is a schematic diagram of another clock synchronization network provided in an embodiment of this application;

[0039] Figure 5 is a schematic diagram of another clock synchronization network provided in an embodiment of this application;

[0040] Figure 6 is a flowchart illustrating a clock synchronization method provided in an embodiment of this application;

[0041] Figure 7 is a schematic diagram of the connection of various network devices in a clock synchronization network provided in an embodiment of this application;

[0042] Figure 8 is a schematic diagram of the connection of various network devices in another clock synchronization network provided in an embodiment of this application;

[0043] Figure 9 is a flowchart illustrating another clock synchronization method provided in an embodiment of this application;

[0044] Figure 10 is a schematic diagram of a clock synchronization device provided in an embodiment of this application;

[0045] Figure 11 is a schematic diagram of the structure of a network device provided in an embodiment of this application. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described herein are some, but not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this application.

[0047] The terms "first," "second," etc., used in the specification, embodiments, and drawings of this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, such as including a series of steps or units. A method, apparatus, or product is not limited to the listed steps or units but may optionally include other unlisted steps or units, or optionally include other steps or units inherent to these methods, apparatus, or products.

[0048] It is understood that in this application, "at least one" means one or more, and "more than one" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can mean: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. Furthermore, terms such as "exemplary" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or implementation described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or implementations. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0049] Before describing the technical solution provided in this application in detail, the technical background of this application will be briefly introduced below.

[0050] In a wireless network, multiple network devices within the same PTP domain can synchronize their clocks using PTP. A PTP domain refers to a logical group of network devices using PTP. A physical network can be divided into multiple PTP domains, and clock synchronization between different PTP domains is independent of each other.

[0051] A port on a network device that runs PTP is called a PTP port. PTP ports can be of three types: Master port, Slave port, and Passive port. A Master port acts as an upstream port, sending clock information to its downstream counterpart, enabling clock synchronization between the downstream and upstream network devices. A Slave port provides clock information to its corresponding network device for synchronizing its local clock. A Passive port serves as a backup for the Slave port. For example, a network device containing a Master port can send clock information to the Slave ports of its downstream devices, allowing the downstream devices to synchronize their clocks based on the received clock information.

[0052] Network devices using PTP (Peripherally Transmitted Protocol) operate in several modes (i.e., clock synchronization modes), including TC (Tracking Clock), BC (Block Clock), and OC (Open Clock). In OC mode, a network device has only one PTP port. This device can act as the master node within the PTP domain, publishing clock information to downstream nodes (in this case, the PTP port is the Master port), or as the slave node, obtaining clock information from upstream nodes (in this case, the PTP port is the Slave port). In BC mode, a network device has multiple PTP ports, including multiple Master ports or Passive ports, but only one Slave port. The Slave port obtains clock information from upstream nodes, multiple Master ports publish clock information to downstream nodes, and the Passive port provides alternative clocks as backups for the Slave port. In TC mode, a network device has multiple PTP ports, but these ports have no port state (i.e., they do not function as Master, Slave, or Passive ports). This network device only processes and forwards clock messages between ports.

[0053] For example, referring to Figure 1, a schematic diagram of a clock synchronization network in a PTP cascading scenario (i.e., a scenario in which multiple network devices using PTP are connected sequentially) is shown. This clock synchronization network can be part of a communication system. As shown in Figure 1, the clock synchronization network includes network device 1, network device 2, network device 3, and network device 4. These network devices belong to the same PTP domain and can achieve clock synchronization between network devices through PTP.

[0054] Network device 1 operates in OC mode, which synchronizes its local clock with an external clock source, such as a Global Navigation Satellite System (GNSS). Network device 1's local clock serves as the Grandmaster Clock for the clock synchronization network, publishing clock information to downstream network device 2 via the Master port (denoted by M in Figure 1). Network devices 2 and 3 operate in BC mode, each with a Slave port (denoted by S in Figure 1) and a Master port. Network device 2 obtains clock information from the Master port of upstream network device 1 via its Slave port, synchronizing its local clock with that of network device 1; it can also publish clock information to downstream network device 3 via its Master port. Similarly, network device 3 obtains clock information from the Master port of upstream network device 2 via its Slave port, synchronizing its local clock with that of network device 2; and it can also publish clock information to downstream network device 4 via its Master port. Network device 4 operates in OC mode and has a Slave port. It can obtain clock information from the Master port of the upstream network device 3 through the Slave port to synchronize its local clock with the local clock of network device 3.

[0055] As can be seen, in the clock synchronization network shown in Figure 1, by using the clock synchronization method where the first and last nodes run in OC mode and the intermediate nodes run in BC mode, clock synchronization between network devices can be achieved step-by-step in a PTP cascading scenario. However, when using this clock synchronization method, if the upstream device of a network device (not the first node) is reset, the clock link between the network device and its upstream device will be broken. Therefore, the network device will be unable to synchronize with other network devices in the clock synchronization network due to the loss of its clock source, thus failing to operate normally. Specifically, within the same PTP domain, when a network device (not the first node) performs clock synchronization, it relies on the clock link between itself and its upstream device. This clock link is established by the interaction of announcement messages between the network device and its upstream device. The starting point of this clock link is the Master port of the upstream device, and the ending point is the Slave port of the network device. After the clock link is established, a relative master-slave relationship exists between the network device and its upstream device. In this master-slave relationship, the network device itself acts as the slave node, and its upstream device acts as the master node. For example, as shown in Figure 1, network device 4 relies on the clock link between itself and network device 3 (i.e., the clock link between the Master port of network device 3 and the Slave port of network device 4) for clock synchronization. When network device 3 is reset, the clock link between network device 4 and network device 3 is broken, and network device 4 will fail to operate normally due to the loss of its clock source. Based on this, related technologies provide another clock synchronization method in PTP cascading scenarios. For example, referring to Figure 2, a schematic diagram of another clock synchronization network in a PTP cascading scenario is provided.

[0056] As shown in Figure 2, the clock synchronization network includes network device 1, network device 2, network device 3, and network device 4. Network device 1 and network device 4 operate in the same OC mode as in Figure 1. Network device 2 and network device 3 operate in the same BC mode under normal conditions as in Figure 1; however, they operate in TC mode upon reset. For example, when network device 3 resets, it switches from BC mode to TC mode. The Slave port (represented by S in Figure 2) and Master port (represented by M in Figure 2) of network device 3 are set to PTP ports (no port). In this case, network device 3 can use TC mode to transparently transmit clock information between network device 2 and network device 4. Under normal circumstances, network device 4 relies on the clock link between itself and network device 3 (i.e., the clock link between the Master port of network device 3 and the Slave port of network device 4) for clock synchronization. When network device 3 is reset, its Master port is set to a portless PTP port, and the clock link between network device 4 and network device 3 is broken. Since network device 3 operates in TC mode when reset, network device 4 can establish a clock link between network device 2 and network device 4 (i.e., the clock link between the Master port of network device 2 and the Slave port of network device 4) by exchanging Announce messages with network device 3. Thus, when network device 3 is reset, network device 4 can complete clock synchronization through the clock link with network device 2.

[0057] As can be seen from Figure 2, in the clock synchronization network, by using the OC mode for the first and last nodes and the clock synchronization method where intermediate nodes switch between BC and TC modes, a clock link can be re-established for the intermediate node when its upstream node is reset. This allows the intermediate node to synchronize with other nodes in the clock synchronization network based on the re-established clock link. However, establishing a clock link takes time. Therefore, while this clock synchronization method can avoid the situation where downstream devices cannot operate normally for a long time due to the reset of a network device, it cannot solve the problem of downstream devices not operating normally for a short period of time during the re-establishment process. In other words, this clock synchronization method cannot fundamentally solve the problem in PTP cascading scenarios where the downstream devices of a network device located in an intermediate node (i.e., not a first or last node) cannot operate normally due to the reset of that network device.

[0058] To address the issue of downstream devices failing to operate normally due to the reset of a network device at an intermediate node in a PTP cascading scenario, this application provides a clock synchronization method. This method deploys two clock synchronization modes—joint mode and independent mode—for the network device at the intermediate node and switches between the two clock synchronization modes as needed, ensuring that downstream devices can continue to operate normally when the network device is reset.

[0059] The clock synchronization method provided in this application embodiment can be applied to a clock synchronization network in a PTP cascade scenario, where the clock synchronization network can be part of a communication system. Referring to Figure 3, a schematic diagram of a clock synchronization network provided in this application embodiment is shown. As shown in Figure 3, this clock synchronization network consists of multiple network devices in the communication system connected sequentially.

[0060] For example, the communication system to which the clock synchronization network in this application belongs can be a sidelink communication system, a vehicle-to-everything (V2X) system, a wireless local area network (WLAN) system, a narrowband internet of things (NB-IoT) system, a global system for mobile communications (GSM) system, an enhanced data rate for GSM evolution (EDGE) system, a wideband code division multiple access (WCDMA) system, a code division multiple access (CDMA2000) system, a time division-synchronization code division multiple access (TD-SCDMA) system, a long term evolution (LTE) system, a satellite communication system, a 5th generation (5G) mobile communication system, or a future communication network system (such as a 6th generation mobile communication system), etc.

[0061] In one possible implementation, the network device in the clock synchronization network of this application embodiment can be a device on the base station side of a communication system. The base station side can include wireless devices and wireless device controllers. The wireless devices and wireless device controllers can be network-connected through a front-haul transport network (FTN) composed of one or more transmission devices. The network device in this application embodiment can be a wireless device, a wireless device controller, or a transmission device in a front-haul network.

[0062] A radio device controller can be a network element or device with baseband signal processing capabilities, or a device that manages radio signal processing for the radio access network (RAN). The radio device controller can perform baseband signal processing functions such as coding, multiplexing, modulation, and spreading; it can also process signaling from radio devices, perform local management and remote operation and maintenance of radio devices, and provide clock synchronization for transmission or radio devices. For example, the radio device controller can be a baseband unit (BBU) (or building baseband unit) in an access network device (e.g., a base station). For instance, in an LTE system, the radio device controller can be a BBU in an evolved Node B (eNB or e-NodeB). For example, in a 5G mobile communication system, the radio device controller can be a BBU in a next-generation node B (gNB); or it can be a distributed unit (DU) in a cloud radio access network (CloudRAN) or open radio access network (O-RAN) system; or it can be a centralized unit (CU), or a combination of CU and DU. It should be understood that in practical applications and in subsequent network evolution, the radio device controller can also be other network elements or devices with baseband signal processing capabilities, or other devices with radio signal processing capabilities for managing the RAN.

[0063] Wireless devices can be radio units (RUs) in access network equipment (e.g., base stations), or other processing devices capable of processing wireless signals (e.g., intermediate frequency signals, radio frequency signals, etc.). For example, a wireless device can be a remote radio unit (RRU) or a remote radio head (RRH) in a base station. RRUs can be used for conventional outdoor coverage in macro base stations, while RRHs can be used for indoor coverage in indoor distribution systems. For instance, in 5G mobile communication systems, wireless devices can also be active antenna units (AAUs), which are processing units integrating an RRU (or RRH) and an antenna. It should be understood that in practical applications and in subsequent network evolution, wireless devices can also be other devices capable of transmitting and receiving radio frequency signals, processing radio frequency signals, or intermediate frequency signals.

[0064] Transmission equipment can be network devices used for data transmission in a fronthaul network, with each transmission device connected to the others via optical fiber or other transmission media. Transmission equipment can be network devices that integrate packet transport network (PTN) equipment, routers, switches, microwave equipment, optical transport network (OTN) equipment, and other network devices capable of message processing and data transmission.

[0065] It should be understood that in practical applications, the network devices in the clock synchronization network of this application embodiment can also be other devices of the communication system. The wireless devices, wireless device controllers and transmission devices on the base station side are only examples of network devices, and this application embodiment does not limit them.

[0066] Taking the Lower Layer Split-Configuration 2 (LLS-C2) scenario defined in the O-RAN protocol as an example, in one possible implementation, the clock synchronization network in this embodiment can be a network composed of a BBU and multiple cascaded AAUs. Referring to Figure 4, a schematic diagram of another clock synchronization network provided in this embodiment is shown. As shown in Figure 4, the first node of this clock synchronization network is the BBU, followed by multiple AAUs (such as AAU1, AAU2, and AAU3 in Figure 4). The BBU and AAUs can communicate through a fronthaul interface. For example, the fronthaul interface can be an enhanced common public radio interface (eCPRI). The eCPRI protocol is an Ethernet-based transmission protocol, so the BBU and AAUs can achieve clock synchronization through PTP (which is included in the eCPRI protocol). Additionally, multiple cascaded AAUs can also achieve clock synchronization through PTP. In other words, each network device in the clock synchronization network shown in Figure 4 can be a network device that uses PTP. This clock synchronization network can achieve clock synchronization between network devices through PTP. Among them, the BBU, as the first node in the network, can obtain clock information from GNSS and publish the clock information to AAU level by level, thereby achieving clock synchronization within the clock synchronization network.

[0067] Taking the LLS-C2 scenario as an example, in another possible implementation, the clock synchronization network in this embodiment can be a network composed of a BBU, multiple cascaded transmission devices, and an AAU. Referring to Figure 5, a schematic diagram of another clock synchronization network provided in this embodiment is shown. As shown in Figure 5, the first node of this clock synchronization network is the BBU. After the BBU, multiple transmission devices (such as switch 1, switch 2, and switch 3 in Figure 5, which form a fronthaul network) are connected sequentially. After these transmission devices, an AAU is connected. Clock synchronization between the BBU and the transmission devices, between transmission devices, and between the transmission devices and the AAU can all be achieved through PTP. That is, each network device in the clock synchronization network shown in Figure 5 can be a network device using PTP, and this clock synchronization network can achieve clock synchronization between network devices through PTP. The BBU, as the first node in the network, can obtain clock information from GNSS and publish this clock information to downstream devices level by level, thereby achieving clock synchronization within the clock synchronization network.

[0068] It should be understood that the clock synchronization networks shown in Figures 4 and 5 are merely examples. In practical applications, the clock synchronization network can also have other structural forms, and this application embodiment does not limit this. In the following description of the embodiments of this application, the clock synchronization network shown in Figure 4 will be used as an example for explanation.

[0069] Referring to Figure 6, a flowchart illustrating a clock synchronization method provided in this application embodiment is shown. This method can be applied to a first network device in the clock synchronization network shown in Figures 3, 4, or 5. The first network device can be a network device located at an intermediate node in the clock synchronization network in a PTP cascading scenario. For example, in the clock synchronization network shown in Figure 3, all network devices except those corresponding to the first and last nodes can serve as the first network device. Similarly, in the clock synchronization network shown in Figure 4, AAU1 and AAU2 can both serve as the first network device. Furthermore, in the clock synchronization network shown in Figure 5, switches 1, 2, and 3 can all serve as the first network device. As shown in Figure 6, the method includes the following steps:

[0070] S601. Based on the acquired reset signal, switch the operating mode from the first mode to the second mode.

[0071] In this embodiment, two clock synchronization modes (i.e., the operating modes in this embodiment) can be pre-configured for the first network device: a first mode and a second mode. The first mode is a combined mode that simultaneously runs a transparent clock mode and a normal clock mode, while the second mode is an independent mode that only runs the transparent clock mode. The first network device defaults to running the first mode (i.e., it runs the first mode under normal conditions). When the first network device receives a reset signal, it switches from the first mode to the second mode. That is, when the first network device resets, only the normal clock mode is reset, while the transparent clock mode is retained.

[0072] A reset signal can be a control signal used to restore the first network device to its initial state or clear a fault state. For example, a reset signal can be a signal triggered by a user pressing the reset button on the first network device according to usage requirements; alternatively, a reset signal can be a control signal triggered by software instructions during software testing or software updates of the first network device to restore it to its initial state or clear a fault state; or, a reset signal can be a control signal generated by external hardware circuitry to clear a fault state when the first network device experiences an operational fault that cannot be resolved by software reset.

[0073] In one possible implementation, the reset signal is a non-power-down type reset signal.

[0074] In this embodiment, the first network device is configured to retain a transparent clock mode upon reset. However, the first network device cannot operate in transparent clock mode during a power-down reset. Therefore, the clock synchronization method provided in this embodiment only applies to configuring the first network device to operate in the second mode when the first network device receives a non-power-down type reset signal.

[0075] When the first network device operates in the first mode, it can utilize the normal clock mode within the first mode to achieve clock synchronization between its local clock and the clock source of the clock synchronization network (e.g., GNSS in the clock synchronization network shown in Figure 4). Furthermore, it can utilize the transparent clock mode within the first mode to forward clock messages between its second and third network devices, enabling the third network device to achieve clock synchronization between its local clock and the clock source based on these clock messages. In the clock synchronization network, the network device at the preceding node of the first network device (i.e., the upstream device of the first network device) is the second network device of the first network device; the network device at the following node of the first network device (i.e., the downstream device of the first network device) is the third network device of the first network device. Taking the clock synchronization network shown in Figure 4 as an example, if the first network device is AAU1, then the second network device of the first network device is BBU, and the third network device of the first network device is AAU2.

[0076] S602. When the operating mode is the second mode, if a clock message is received, the clock message is forwarded.

[0077] When the first network device is operating in the second mode, it can forward packets between the second and third network devices using a transparent clock mode. Specifically, in the second operating mode, if the first network device receives a clock packet sent by the second network device, it forwards the clock packet to the third network device, so that the third network device can synchronize its local clock with the clock source based on the clock packet.

[0078] In this embodiment, the first network device normally uses a transparent clock mode to synchronize the local clock of the third network device with the clock source (e.g., an external GNSS clock source in Figure 4). The first network device only forwards clock messages between the third and second network devices. The third network device actually achieves clock synchronization with the clock source through a clock link with the first node of the clock synchronization network (this clock link depends on the transparent clock mode of the first network device). When the first network device is reset, since the transparent clock mode is not reset, the clock link between the third network device and the first node remains intact. Therefore, the first network device can still forward clock messages between the second and third network devices, enabling the third network device to synchronize its local clock with the clock source based on clock messages.

[0079] In one possible implementation, the clock synchronization method provided in this application embodiment may further include: when the first network device is in the first operating mode, if it receives a clock message, it forwards the clock message using a transparent clock mode; and, using a normal clock mode, it synchronizes the local clock of the first network device with the clock source based on the clock message.

[0080] If a clock message is received, the clock message is forwarded using the transparent clock mode, including: if a clock message is received from the second network device, the clock message is forwarded to the third network device using the transparent clock mode, so that the third network device can synchronize its local clock with the clock source based on the clock message.

[0081] Since the first mode is a combined mode that simultaneously operates transparent clock mode and normal clock mode, when the first network device is running in the first mode under normal circumstances, it can use the normal clock mode to synchronize its local clock with the clock source. This ensures that the local clock of the first network device is synchronized with the clocks of other devices in the clock synchronization network, thereby ensuring the continuous normal operation of downstream devices of the first network device.

[0082] Referring to Figure 7, a connection diagram of each network device in a clock synchronization network provided in this application embodiment is shown (specifically, the connection diagram of each network device in the clock synchronization network shown in Figure 4). As shown in Figure 7, the clock synchronization network includes a BBU, AAU1, AAU2, and AAU3. The BBU operates in normal clock mode (i.e., OC mode), which can synchronize its local clock with an external clock source by obtaining clock information from GNSS. The BBU's local clock can serve as the optimal clock for the clock synchronization network, and publishes clock information to the downstream AAU1 via the fronthaul network through the Master port (represented by M in Figure 7).

[0083] AAU1 has a Slave port (represented by S in Figure 7) and two portless PTP ports. Under normal circumstances, it operates simultaneously in normal clock mode and transparent clock mode (i.e., TC mode). In normal clock mode, AAU1 can receive clock messages sent by the BBU via the fronthaul network through the Slave port and synchronize its local clock with the BBU's local clock based on the received clock messages. Since the BBU's local clock is synchronized with an external clock source, AAU1's local clock is also synchronized with the external clock source. Simultaneously, AAU1 can also utilize transparent clock mode, receiving clock messages sent by the BBU via one of the portless PTP ports via the fronthaul network and transmitting the received clock messages to downstream AAU2 via the other portless PTP port via the fronthaul network. When AAU1 is reset, it only operates in transparent clock mode.

[0084] AAU2 and AAU1 have the same structure and operating mode. Under normal circumstances, AAU2 can use the ordinary clock mode to receive clock messages forwarded by AAU1 through the fronthaul network via the Slave port. A master-slave relationship exists between AAU2 and the BBU, with the BBU acting as the master node and AAU2 as the slave node. AAU1 forwards clock messages between AAU2 and the BBU. AAU2 can synchronize its local clock with the BBU's local clock based on the clock link between itself and the BBU (i.e., the clock link between the BBU's Master port and AAU2's Slave port), thus achieving clock synchronization between its local clock and an external clock source. Similar to AAU1, AAU2 can also use the transparent clock mode, receiving clock messages forwarded by AAU1 through one of its portless PTP ports via the fronthaul network, and transmitting the received clock messages to the downstream AAU3 through the other portless PTP port via the fronthaul network.

[0085] AAU3 operates in normal clock mode and can receive clock messages forwarded by AAU2 through its Slave port. A master-slave relationship also exists between AAU3 and the BBU. In this relationship, the BBU acts as the master node, and AAU3 as the slave node. AAU1 and AAU2 forward clock messages between AAU3 and the BBU. AAU3 can synchronize its local clock with the BBU's local clock based on the clock link between itself and the BBU (i.e., the clock link between the BBU's Master port and AAU3's Slave port), thereby achieving clock synchronization between its local clock and an external clock source.

[0086] Taking AAU1 as the first network device, the second network device is the BBU, and the third network device is AAU2. The clock link between AAU2 and the BBU downstream of AAU1 relies on AAU1's transparent clock mode (which requires AAU1 to forward clock messages between the BBU and AAU2). When AAU1 is reset, because AAU1's transparent clock mode is still retained, the clock link between AAU2 and the BBU will not be broken. Therefore, when AAU1 is reset, AAU2 can still achieve clock synchronization with the external clock source based on the clock messages forwarded by AAU1.

[0087] As can be seen, in the clock synchronization network shown in Figure 7, the clock link between the third network device downstream of the first network device and the first node can be maintained when the first network device is reset. This eliminates the need to re-establish the clock link for the third network device, thus preventing it from malfunctioning due to reset and re-establishment.

[0088] In one possible implementation, if a clock message is received, the clock message is forwarded using a transparent clock mode, including: if a clock message is received through the first PTP port of the first network device, the clock message is forwarded through the second PTP port of the first network device using a transparent clock mode; and the local clock of the first network device is synchronized with the clock source based on the clock message, including: synchronizing the local clock of the first network device with the clock source based on the clock message received through the first PTP port.

[0089] Specifically, if the first network device receives a clock message sent by the second network device through the first PTP port, it will use the transparent clock mode to forward the clock message to the third network device through the second PTP port.

[0090] In the clock synchronization network shown in Figure 7, the first network device needs to deploy three ports, and the transmission devices in the fronthaul network need to support transparent clock mode. In order to reduce the number of ports deployed on the first network device and reduce the configuration requirements of the transmission devices in the fronthaul network, this embodiment can deploy two ports on the first network device (i.e., the first PTP port and the second PTP port in this embodiment), and configure these two ports to support both transparent clock mode and normal clock mode simultaneously.

[0091] Referring to Figure 8, a connection diagram of each network device in another clock synchronization network provided in this application embodiment is shown (specifically, the connection diagram of each network device in the clock synchronization network shown in Figure 4). As shown in Figure 8, the clock synchronization network includes BBU, AAU1, AAU2, and AAU3. The BBU operates in normal clock mode (i.e., OC mode), which can synchronize its local clock with an external clock source by obtaining clock information from GNSS. The BBU's local clock can serve as the optimal clock for the clock synchronization network, publishing clock information to downstream AAU1 through the Master port (represented by M in Figure 8).

[0092] AAU1 has a first PTP port and a second PTP port, both configured to support both transparent clock mode and normal clock mode simultaneously. Under normal circumstances, AAU1 operates in both normal clock mode and transparent clock mode (i.e., TC mode). Specifically, when AAU1's first PTP port receives a clock message from the BBU, it can use normal clock mode to forward the clock message to the corresponding module in AAU1. This module can then synchronize AAU1's local clock with the BBU's local clock based on the received clock message. Since the BBU's local clock is synchronized with an external clock source, AAU1's local clock is also synchronized with the external clock source. Furthermore, when AAU1's first PTP port receives a clock message from the BBU, it can use transparent clock mode to forward the clock message to AAU1's second PTP port. AAU1's second PTP port can then transmit the received clock message to the downstream AAU2.

[0093] AAU2 and AAU1 have the same structure and operating mode. Under normal circumstances, when AAU2's first PTP port receives a clock message from AAU1's second PTP port, AAU2's first PTP port can use the normal clock mode to forward the clock message to the corresponding module in AAU2's normal clock mode. There is a master-slave relationship between AAU2 and the BBU. In this master-slave relationship, the BBU acts as the master node, and AAU2 acts as the slave node. AAU1 forwards clock messages between AAU2 and the BBU. When AAU2's first PTP port operates in normal clock mode, this first PTP port acts as the slave port corresponding to the BBU's master port. Therefore, AAU2 can synchronize its local clock with the BBU's local clock based on the clock link between itself and the BBU (i.e., the clock link between the BBU's master port and AAU2's first PTP port), thereby achieving clock synchronization between its local clock and an external clock source. Similar to AAU1, when the first PTP port of AAU2 receives a clock message forwarded by AAU1, it can use transparent clock mode to forward the clock message to the second PTP port of AAU2. The second PTP port of AAU2 can then transmit the received clock message to the downstream AAU3.

[0094] AAU3 operates in normal clock mode and can receive clock messages forwarded by AAU2 from the second PTP port of AAU2 through the Slave port (represented by S in Figure 8). A master-slave relationship also exists between AAU3 and the BBU. In this relationship, the BBU acts as the master node, and AAU3 as the slave node. AAU1 and AAU2 forward clock messages between AAU3 and the BBU. AAU3 can synchronize its local clock with the BBU's local clock based on the clock link between itself and the BBU (i.e., the clock link between the BBU's Master port and AAU3's Slave port), thereby achieving clock synchronization between its local clock and an external clock source.

[0095] Taking AAU1 as the first network device, BBU as the second network device, and AAU2 as the third network device, the clock link between AAU2 and BBU downstream of AAU1 relies on AAU1's transparent clock mode (clock packets are forwarded between BBU and AAU2 through the transparent clock mode of AAU1's first and second PTP ports). When AAU1 is reset, since AAU1's transparent clock mode is still retained, the clock link between AAU2 and BBU will not be broken. Therefore, when AAU1 is reset, AAU2 can still achieve clock synchronization with an external clock source based on the clock packets forwarded by AAU1's second PTP port.

[0096] As can be seen, in the clock synchronization network shown in Figure 8, the clock link between the third network device downstream of the first network device and the first node can be maintained even when the first network device is reset. Furthermore, compared to the clock synchronization network shown in Figure 7, the clock synchronization network shown in Figure 8 can reduce the number of ports deployed on the first network device and lower the configuration requirements for transmission devices in the fronthaul network (no need for the fronthaul network to support transparent clock mode).

[0097] In one possible implementation, the transparent clock mode involved in the embodiments of this application is an end-to-end transparent clock (E2E TC) mode.

[0098] Transparent clock modes include end-to-end transparent clock mode and peer-to-peer transparent clock (P2PTC) mode. If the first network device adopts the peer-to-peer transparent clock mode, the path delay measurement in the entire clock synchronization network needs to be performed between each link segment. The link delay of each link between the master and slave nodes is accumulated in the clock message and transmitted to the third network device level by level. Thus, when the first network device is reset, since the path delay of each link segment needs to be measured, the third network device downstream of the first network device still needs to interact with the second network device upstream of the first network device to establish a link. For example, taking the first network device as AAU1 in Figure 8, if AAU1 adopts the peer-to-peer transparent clock mode, then when AAU2 synchronizes with the external clock source, it also needs to refer to the link delay of the link between AAU1 and AAU2 (AAU1 as the master node and AAU2 as the slave node). Thus, when AAU1 resets, AAU2 needs to re-establish a link with the BBU to measure the path delay of the link between AAU2 and the BBU. However, when the first network device uses an end-to-end transparent clock mode, it is unnecessary to measure the path delay of each link in the clock synchronization network. The third network device achieves synchronization with the external clock source through the clock link with the first node (this clock link depends on the first network device's transparent clock mode). It can be seen that in this embodiment, only when the first network device's transparent clock mode is an end-to-end transparent clock mode can it be achieved that when the first network device resets, it is not necessary to re-establish a clock link with its downstream third network device. Therefore, in this embodiment, the first network device uses an end-to-end transparent clock mode.

[0099] In one possible implementation, when the clock message is a clock synchronization message carrying a first timestamp, a transparent clock mode is used to forward the clock message to a third network device, so that the third network device can synchronize its local clock with the clock source based on the clock message. This includes: writing a first forwarding delay of the clock synchronization message flowing through the first network device into the clock synchronization message, and forwarding the written clock synchronization message to the third network device; receiving a delay request message sent by the third network device, writing a second forwarding delay of the delay request message flowing through the first network device into the delay request message, and forwarding the written delay request message to the second network device; receiving a delay request response message sent by the second network device carrying a second timestamp and a second forwarding delay, and forwarding the delay request response message to the third network device, so that the third network device can synchronize its local clock with the clock source based on the first timestamp, the second timestamp, the first forwarding delay, and the second forwarding delay; wherein, the first timestamp corresponds to the time when the second network device sends the clock synchronization message, and the second timestamp corresponds to the time when the second network device receives the delay request message.

[0100] Referring to Figure 9, a flowchart illustrating another clock synchronization method provided in this application embodiment is shown. This method can be applied to the clock synchronization network shown in Figure 8. As shown in Figure 9, the first network device can be AAU1, the second network device can be BBU, and the third network device can be AAU2. BBU can periodically send clock synchronization messages (i.e., Sync messages) to AAU1. These Sync messages carry the time t1 (i.e., the first timestamp) at which BBU sends the Sync message. After receiving the Sync message from BBU, AAU1 can write the first forwarding delay C1 of the Sync message through AAU1 into the Sync message and forward the Sync message with C1 written to it to AAU2. After receiving the Sync message forwarded by AAU1, AAU2 can record C1 and t1 in the Sync message, and can also record the time t2 (i.e., the third timestamp) at which AAU2 receives the Sync message. Subsequently, AAU2 can send a delay request message (i.e., Delay_req message) to AAU1, and can record the time t3 (i.e., the fourth timestamp) at which the Delay_req message is sent. After receiving the Delay_req message, AAU1 can write the second forwarding delay C2 of the Delay_req message into the Delay_req message and forward the Delay_req message with C2 written to it to BBU. After receiving the Delay_req message, BBU can send a delay request response message (i.e., a Delay_resp message) to AAU1. This Delay_resp message carries the time t4 (i.e., the second timestamp) at which BBU received the Delay_req message and the second forwarding delay C2. After receiving the Delay_resp message, AAU1 directly forwards the Delay_resp message to AAU2. After receiving the Delay_resp message, AAU2 can obtain the second timestamp t4 and the second forwarding delay C2 from the Delay_resp message.

[0101] If we let D represent the path delay and offset represent the time difference between BBU and AAU2, then the path delay of the link from BBU to AAU2 is D = t2 - t1 - C1 - offset, and the path delay of the link from AAU2 to BBU is D = t4 - t3 - C2 - (-offset). Assuming the two path delays are equal, the time difference offset between BBU and AAU2 can be obtained by solving the equation t2 - t1 - C1 - offset = t4 - t3 - C2 - (-offset). Then, AAU2 can achieve time synchronization with BBU based on the time difference offset. Furthermore, in practical applications, if the two path delays are unequal, the offset can be corrected using the time difference between the two path delays.

[0102] Clock synchronization generally includes time synchronization and frequency synchronization. In this embodiment, AAU2 can also achieve frequency synchronization between its local clock and the BBU's local clock through message interaction, thereby achieving frequency synchronization between its local clock and an external clock source. Alternatively, this embodiment can also utilize synchronous Ethernet to achieve frequency synchronization between AAU2 and the BBU at the physical layer (the specific implementation method can be referred to the description in related technologies, which will not be repeated in this embodiment).

[0103] It should be understood that the method for synchronizing the local clock of the third network device with the clock source provided in the embodiments of this application is only an example. In practical applications, it can also be implemented through other message interaction methods. For example, when the second network device sends a Sync message to the first network device, it may not carry the first timestamp t1, and then send a follow-up message (i.e., a Follow_up message) carrying the first timestamp t1 to the first network device after a certain interval.

[0104] In one possible implementation, the clock synchronization method provided in this application embodiment may further include: a first network device performing an initialization operation based on the acquired start signal to initialize the operating mode to a first mode.

[0105] The start signal can be a control signal that triggers the first network device to start working.

[0106] Since the first network device includes a first mode and a second mode, and this embodiment requires the first network device to operate in the first mode under normal circumstances, this embodiment can configure the first network device to perform an initialization operation upon receiving a start signal, thereby initializing the operating mode to the first mode.

[0107] In addition, before the first network device runs the first mode, it needs to establish a clock link between the first node and the first network device by exchanging notification messages with the first node in the clock synchronization network.

[0108] In one possible implementation, after switching the operating mode from the first mode to the second mode based on the acquired reset signal, the clock synchronization method provided in this application embodiment may further include: the first network device switching the operating mode from the second mode to the first mode based on the acquired recovery signal.

[0109] The recovery signal can be an automatically triggered recovery signal that occurs after a preset duration following the receipt of the reset signal. This preset duration is related to the type of reset signal and is determined based on the duration it takes for the first network device to recover to its initial state or for the first network device to clear its fault state. Alternatively, the recovery signal can also be a control signal triggered by external hardware circuitry or software instructions.

[0110] After being reset, the first network device will resume normal operation after a period of time. To ensure that the first network device can synchronize its clock with the clock source using the normal clock mode after resuming normal operation, in this embodiment of the application, the first network device can be configured to switch its operating mode from the second mode back to the first mode when it receives a recovery signal.

[0111] In one possible implementation, the synchronous Ethernet link of the first network device is not interrupted during the second mode operation.

[0112] Since PTP is based on Ethernet transmission, the synchronous Ethernet link is the foundation for communication and interaction between network devices in the entire clock synchronization network. Therefore, in this embodiment, when the first network device is reset, it is necessary not only to maintain the transparent clock mode without resetting, but also to ensure that the synchronous Ethernet link is not interrupted.

[0113] The clock synchronization method provided in this application pre-configures two clock synchronization modes for the first network device: a combined mode (i.e., the first mode) that simultaneously runs a transparent clock mode and a normal clock mode, and an independent mode (i.e., the second mode) that only runs a transparent clock mode. Under normal circumstances, the first network device defaults to running both transparent and normal clock modes simultaneously. It can use the normal clock mode to synchronize its local clock with the clock source, and it can use the transparent clock mode to synchronize the local clock (i.e., the local clock) of the third network device with the clock source. When the first network device is reset, only the normal clock mode is reset, while the transparent clock mode is retained. That is, the first network device only runs the transparent clock mode upon reset (i.e., switching from the first mode to the second mode). Since the first network device normally only forwards clock messages between the third and second network devices, and uses the transparent clock mode to synchronize the local clock of the third network device with the clock source, the third network device actually achieves clock synchronization with the clock source through a clock link with the head node of the clock synchronization network (this clock link depends on the transparent clock mode of the first network device). Therefore, when the first network device resets, since the transparent clock mode is not reset, the clock link between the third network device and the first node remains intact. This allows the first network device to continue forwarding clock messages between the second and third network devices, enabling the third network device to synchronize its local clock with the clock source based on these clock messages. It can be seen that this embodiment deploys both federated and standalone clock synchronization modes for the first network device and switches between them as needed. This ensures that when the first network device resets, there is no need to re-establish the clock link with its downstream third network device. Therefore, this embodiment can ensure the continued normal operation of downstream devices even when one intermediate device in a multi-cascaded network setup is reset.

[0114] Furthermore, if the clock synchronization method proposed in related technologies, which involves re-establishing the clock link for the third network device when the first network device is reset, is adopted, then after the first network device recovers, the clock link of the third network device needs to be switched back to the original clock link (i.e., the clock link between the third network device and the first network device). This necessitates repeated link re-establishment during the operation of the clock synchronization network, which is detrimental to its operation and maintenance management. However, in the embodiment of this application, the clock link between the first network device and the first node is maintained continuously, eliminating the need for repeated link re-establishment. Therefore, the clock synchronization method provided in this embodiment facilitates the operation and maintenance management of the clock synchronization network.

[0115] It is understood that, in order to achieve the above functions, the first network device includes hardware and / or software modules that perform the respective functions. Referring to FIG10, a schematic diagram of a clock synchronization device provided in an embodiment of this application is shown. As shown in FIG10, when each functional module is divided according to its respective function, the clock synchronization device 1000 may include a mode switching module 1001 and a transparent clock module 1002.

[0116] The mode switching module 1001 is used to switch the operating mode from the first mode to the second mode based on the acquired reset signal; the first mode is a combined mode that runs both transparent clock mode and normal clock mode, and the second mode is an independent mode that runs only transparent clock mode; the transparent clock module 1002 is used to forward clock messages if a clock message is received when the operating mode is the second mode.

[0117] In one possible implementation, as shown in FIG10, the clock synchronization device 1000 provided in this application embodiment further includes a normal clock module 1003; a transparent clock module 1002, which is further used to forward the clock message using the transparent clock mode when the operating mode is the first mode and a clock message is received; and a normal clock module 1003, which is used to synchronize the local clock of the first network device with the clock source based on the clock message using the normal clock mode.

[0118] In another possible implementation, the transparent clock module 1002 is specifically used to: if a clock message is received through the first PTP port of the first network device, then the clock message is forwarded through the second PTP port of the first network device using the transparent clock mode; the ordinary clock module 1003 is specifically used to: synchronize the local clock of the first network device with the clock source based on the clock message received through the first PTP port.

[0119] In another possible implementation, the transparent clock mode is an end-to-end transparent clock mode.

[0120] In another possible implementation, the clock synchronization device 1000 provided in this application embodiment further includes an initialization module; the initialization module is used to perform an initialization operation based on the acquired start signal to initialize the running mode to the first mode.

[0121] In another possible implementation, the mode switching module 1001 is also used to: switch the operating mode from the second mode to the first mode based on the acquired recovery signal.

[0122] In another possible implementation, the reset signal is a non-power-down type reset signal.

[0123] In another possible implementation, the synchronous Ethernet link of the first network device is not interrupted during the second mode operation.

[0124] The clock synchronization device provided in this application embodiment is used to execute the aforementioned clock synchronization method. Taking the clock synchronization method shown in FIG6 as an example, the mode switching module 1001 can be used to execute S601 in FIG6, and the transparent clock module 1002 can be used to execute S602 in FIG6. The specific implementation process of the clock synchronization device and the corresponding beneficial effects can be referred to the relevant description of the aforementioned method embodiment, and will not be repeated here.

[0125] For example, the functions implemented by the mode switching module 1001, the transparent clock module 1002, and the ordinary clock module 1003 can all be implemented by the processor of the first network device executing program instructions.

[0126] It should be noted that the module division in Figure 10 is exemplary and only represents one logical functional division. In actual implementation, other division methods are possible. For example, two or more functions can be integrated into one module. The integrated module described above can be implemented in hardware or as a software functional module.

[0127] The clock synchronization method provided in this application can be executed by a network device (specifically, the first network device in a clock synchronization network). Referring to Figure 11, which is a schematic diagram of the structure of a network device according to an embodiment of this application, the network device may include at least one processor 1101, at least one memory 1102, at least one transceiver 1103, and one or more antennas 1104. The processor 1101, memory 1102, and transceiver 1103 are connected via a connection device, and the antenna 1104 is connected to the transceiver 1103. The connection device may include various interfaces, transmission lines, or buses, etc., and this embodiment of the application does not limit its scope.

[0128] The memory 1102 is primarily used to store software programs and data. The memory 1102 can exist independently and be connected to the processor 1101. Alternatively, the memory 1102 can be integrated with the processor 1101, for example, integrated within one or more chips. The memory 1102 can store and execute the program code involved in the embodiments of this application, and its execution is controlled by the processor 1101. The various types of computer program code being executed can also be considered as drivers for the processor 1101. It should be understood that Figure 11 only shows one memory and one processor; however, in practical applications, the network device can have multiple processors or multiple memories.

[0129] Transceiver 1103 can be used to support the reception or transmission of radio frequency signals between the network device and the terminal device. Transceiver 1103 can be connected to antenna 1104. Transceiver 1103 includes a transmitter (Tx) and a receiver (Rx). Specifically, one or more antennas 1104 can receive radio frequency signals. The receiver of transceiver 1103 is used to receive the radio frequency signals from antennas 1104 and convert the radio frequency signals into digital baseband signals or digital intermediate frequency signals, so that the aforementioned digital baseband signals or digital intermediate frequency signals are transmitted to the wireless device controller, so that the wireless device controller can perform further processing on the digital baseband signals or digital intermediate frequency signals, such as demodulation processing and decoding processing. In addition, the transmitter in transceiver 1103 is also used to receive the modulated digital baseband signals or digital intermediate frequency signals from the wireless device controller, convert the modulated digital baseband signals or digital intermediate frequency signals into radio frequency signals, and transmit the radio frequency signals through one or more antennas 1104. Specifically, the receiver can selectively perform one or more stages of downmixing and analog-to-digital conversion on the radio frequency signal to obtain a digital baseband signal or a digital intermediate frequency (IF) signal. The order of the downmixing and IF conversion processes is adjustable. Similarly, the transmitter can selectively perform one or more stages of upmixing and digital-to-analog conversion on the modulated digital baseband or IF signal to obtain a radio frequency signal. The order of these upmixing and IF conversion processes is also adjustable. Both the digital baseband signal and the digital IF signal can be collectively referred to as digital signals.

[0130] The processor 1101 is primarily used to process communication protocols and communication data, execute software programs, and process data from these software programs, for example, to support the network device in performing the actions described in the foregoing embodiments. In one possible implementation, the network device is used to execute the clock synchronization method shown in FIG6.

[0131] It should be noted that the structure shown in Figure 11 does not constitute a limitation on the network device. In addition to the components shown in Figure 11, the network device may include more or fewer components than those shown in Figure 11, or combine certain components, or have different component arrangements. For example, when the network device is an AAU, the network device may not include the memory 1102.

[0132] This application also provides a computer-readable storage medium including computer instructions that, when executed on a computer, cause the computer to perform any of the aforementioned clock synchronization methods. For example, when the computer instructions are executed on a computer, the method performed by the clock synchronization device in the above embodiments can be implemented.

[0133] This application also provides a computer program product that, when run on a computer, causes the computer to execute any of the aforementioned clock synchronization methods. For example, when the computer program product is run on a computer, it can implement the methods executed by the clock synchronization device in the above embodiments.

[0134] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A clock synchronization method, characterized in that, Applied to a first network device, the method includes: Based on the acquired reset signal, the operating mode is switched from the first mode to the second mode; the first mode is a combined mode that runs both transparent clock mode and normal clock mode simultaneously, and the second mode is an independent mode that runs only the transparent clock mode; When the operating mode is the second mode, if a clock message is received, the clock message is forwarded.

2. The method according to claim 1, characterized in that, The method further includes: When the operating mode is the first mode, if the clock message is received, the clock message is forwarded using the transparent clock mode; Using the normal clock mode, the local clock of the first network device is synchronized with the clock source based on the clock message.

3. The method according to claim 2, characterized in that, The step of forwarding the clock message using the transparent clock mode if the clock message is received includes: if the clock message is received through the first Precision Clock Protocol (PTP) port of the first network device, then forwarding the clock message through the second PTP port of the first network device using the transparent clock mode. The step of synchronizing the local clock of the first network device with the clock source based on the clock message includes: synchronizing the local clock of the first network device with the clock source based on the clock message received through the first PTP port.

4. The method according to any one of claims 1-3, characterized in that, The transparent clock mode is an end-to-end transparent clock mode.

5. The method according to any one of claims 1-4, characterized in that, The method further includes: An initialization operation is performed based on the acquired start signal to initialize the operating mode to the first mode.

6. The method according to any one of claims 1-5, characterized in that, After switching the operating mode from the first mode to the second mode based on the acquired reset signal, the method further includes: Based on the acquired recovery signal, the operating mode is switched from the second mode to the first mode.

7. The method according to any one of claims 1-6, characterized in that, The reset signal is a non-power-down type reset signal.

8. The method according to any one of claims 1-7, characterized in that, During the operation of the second mode by the first network device, the synchronous Ethernet link of the first network device is not interrupted.

9. A clock synchronization device, characterized in that, Configured in a first network device, the apparatus includes: The mode switching module is used to switch the operating mode from a first mode to a second mode based on the acquired reset signal; the first mode is a joint mode that runs both transparent clock mode and normal clock mode simultaneously, and the second mode is an independent mode that runs only the transparent clock mode; A transparent clock module is used to forward a clock message if it is received when the operating mode is the second mode.

10. The apparatus according to claim 9, characterized in that, The device also includes a standard clock module; The transparent clock module is also used to forward the clock message using the transparent clock mode when the clock message is received in the first operating mode. The normal clock module is used to synchronize the local clock of the first network device with the clock source based on the clock message using the normal clock mode.

11. The apparatus according to claim 10, characterized in that, The transparent clock module is specifically used to: if the clock message is received through the first PTP port of the first network device, then forward the clock message through the second PTP port of the first network device using the transparent clock mode; The ordinary clock module is specifically used to: synchronize the local clock of the first network device with the clock source based on the clock message received through the first PTP port.

12. The apparatus according to any one of claims 9-11, characterized in that, The transparent clock mode is an end-to-end transparent clock mode.

13. The apparatus according to any one of claims 9-12, characterized in that, The device also includes an initialization module; The initialization module is used to perform an initialization operation based on the acquired start signal to initialize the running mode to the first mode.

14. The apparatus according to any one of claims 9-13, characterized in that, The mode switching module is also used for: Based on the acquired recovery signal, the operating mode is switched from the second mode to the first mode.

15. The apparatus according to any one of claims 9-14, characterized in that, The reset signal is a non-power-down type reset signal.

16. The apparatus according to any one of claims 9-15, characterized in that, During the operation of the second mode by the first network device, the synchronous Ethernet link of the first network device is not interrupted.

17. A network device, characterized in that, include: Memory and at least one processor; The memory is coupled to the processor; wherein the memory stores computer program code, the computer program code including computer instructions, and when the computer instructions are executed by the processor, the network device performs the method as described in any one of claims 1-8.

18. A computer-readable storage medium comprising computer instructions, characterized in that, When the computer instructions are executed on the computer, the computer causes the computer to perform the method as described in any one of claims 1-8.

19. A computer program product, characterized in that, When the computer program product is run on a computer, it causes the computer to perform the method as described in any one of claims 1-8.

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