Low noise amplifier and radio frequency chip

Abstract

The present invention is applicable to the technical field of wireless communications, and particularly relates to a low noise amplifier and a radio frequency chip. The low noise amplifier comprises an input matching circuit, a bias circuit, an amplification circuit, an output matching circuit, an attenuator, and an anti-distortion gain suppression circuit. Compared with the prior art, in the present invention, by adding an anti-distortion gain suppression circuit capable of preventing distortion caused by excessive waveform amplitude to the connection between a first MOS transistor and a second MOS transistor of an amplification circuit, since the anti-distortion gain suppression circuit can effectively mitigate the linearity deterioration problem in an amplifier chain of a chip caused by excessive waveform amplitude, the low-noise amplifier can output a radio frequency signal having better linearity.

Description

A low-noise amplifier and RF chip Technical Field

[0001] This invention relates to the field of wireless communication technology, and in particular to a low-noise amplifier and radio frequency chip. Background Technology

[0002] Low-noise amplifiers (LNAs) are a crucial component of wireless communication systems, primarily used in the radio frequency (RF) front-end of wireless receivers. As the first active device in the receiver's RF front-end, the LNA plays a vital role in the performance of the receiving system. To ensure receiver sensitivity, the LNA typically needs a certain gain to amplify the weak signal received by the antenna, while effectively suppressing noise from subsequent modules, and the LNA itself also needs to have very low noise. When the system receives high-power signals from the antenna, to ensure no distortion and to prevent damage to subsequent active components, the LNA must have variable gain and extended dynamic range capabilities. Therefore, in addition to meeting system requirements for gain and noise, high linearity design is also essential for LNAs.

[0003] Existing low-noise amplifiers mainly utilize output attenuation and bias current adjustment to regulate the gain of different levels. However, this method has certain disadvantages in improving linearity. For example, while the output attenuation design allows for gain adjustment, it does not improve linearity and cannot meet the stepped IIP3 specification of communication systems. Furthermore, adjusting the bias current can cause the amplifier transistor to operate in the subthreshold region at low gain due to insufficient current, resulting in poor linearity and matching of the low-noise amplifier.

[0004] Therefore, there is an urgent need for a new low-noise amplifier and RF chip to solve the above-mentioned technical problems. Summary of the Invention

[0005] This invention provides a low-noise amplifier and an RF chip, which aims to improve the linearity of the low-noise amplifier at different gain levels.

[0006] In a first aspect, a low-noise amplifier includes an input matching circuit, a bias circuit, an amplification circuit, an output matching circuit, and a distortion-resistant gain suppression circuit.

[0007] The input terminal of the input matching circuit serves as the input terminal of the low-noise amplifier for receiving radio frequency signals, and the output terminal of the input matching circuit is connected to the first input terminal of the amplifier circuit.

[0008] The bias circuit is used to provide a bias voltage for the amplifier circuit;

[0009] The output terminal of the amplifier circuit is connected to the input terminal of the output matching circuit;

[0010] The output terminal of the output matching circuit serves as the output terminal of the low-noise amplifier.

[0011] The distortion-prevention gain suppression circuit is used to provide feedback adjustment for the gain output of the amplifier circuit at different levels, so as to improve the linearity of the amplifier circuit at different gain output levels.

[0012] Preferably, the amplification circuit includes a first MOSFET, a second MOSFET, and a first inductor; the gate of the first MOSFET serves as the first input terminal of the amplification circuit, the source of the first MOSFET is grounded after being connected in series with the first inductor, the drain of the first MOSFET is connected to the source of the second MOSFET, the gate of the second MOSFET serves as the second input terminal of the amplification circuit, and the drain of the second MOSFET serves as the output terminal of the amplification circuit; the bias circuit provides bias voltages for the first MOSFET and the second MOSFET respectively.

[0013] Preferably, the anti-distortion gain suppression circuit includes a capacitor unit, a plurality of first switches, and a plurality of first resistors; the first end of the capacitor unit is connected to the drain of the first MOS transistor and the source of the second MOS transistor respectively; the second end of the capacitor unit is connected to the first end of the plurality of first resistors respectively; the second ends of the plurality of first resistors are connected to the control terminals of the plurality of first switches one by one; and the output terminals of the plurality of first switches are interconnected and grounded.

[0014] Preferably, the anti-distortion gain suppression circuit includes a capacitor unit, a plurality of first switches, and a plurality of first resistors; the first end of the capacitor unit is connected to the drain of the second MOS transistor, the second end of the capacitor unit is connected to the first end of the plurality of first resistors respectively, the second ends of the plurality of first resistors are respectively connected to the control terminals of the plurality of first switches one by one, and the output terminals of the plurality of first switches are interconnected and connected to the gate of the first MOS transistor.

[0015] Preferably, the anti-distortion gain suppression circuit includes a capacitor unit, a plurality of first switches, and a plurality of first resistors; the first end of the capacitor unit is connected to the drain of the first MOS transistor and the source of the second MOS transistor respectively; the second end of the capacitor unit is connected to the first end of the plurality of first resistors respectively; the second end of the plurality of first resistors is connected to the control terminals of the plurality of first switches one by one; and the output terminals of the plurality of first switches are interconnected and then connected to the gate of the first MOS transistor.

[0016] Preferably, the capacitor unit includes a plurality of first capacitors and a plurality of second switches; the first ends of the plurality of first capacitors are interconnected and serve as the first ends of the capacitor unit, the second ends of the plurality of first capacitors are respectively connected to the control ends of the plurality of second switches, and the output ends of the plurality of second switches are interconnected and serve as the second ends of the capacitor unit.

[0017] Preferably, the anti-distortion gain suppression circuit further includes a second capacitor; the first end of the second capacitor is connected to the first end of the capacitor unit, and the second end of the second capacitor is connected to the output terminals of a plurality of first switches respectively.

[0018] Preferably, the bias circuit includes a filter circuit that provides a bias voltage for the second MOSFET and a current mirror circuit that provides a bias voltage for the first MOSFET. The filter circuit includes a second resistor and a fourth capacitor. The first end of the second resistor serves as the input terminal of the filter circuit and is used to connect to an external voltage source. The second end of the second resistor serves as the output terminal of the filter circuit and is connected to the gate of the second MOSFET. The first end of the fourth capacitor is connected to the second end of the second resistor, and the second end of the fourth capacitor is grounded.

[0019] Preferably, the current mirror circuit includes a third MOSFET and a third resistor; the source of the third MOSFET is grounded, the drain of the third MOSFET serves as the input terminal of the current mirror circuit for connecting to an external current source, the gate of the third MOSFET is connected to the first terminal of the third resistor and the drain of the third MOSFET respectively, and the second terminal of the third resistor serves as the output terminal of the current mirror circuit connected to the gate of the first MOSFET.

[0020] Preferably, the output matching circuit includes a third inductor, a first adjustable resistor, a fifth capacitor, and an attenuator; the first end of the first adjustable resistor is connected to the first end of the third inductor, the second end of the first adjustable resistor is connected to the second end of the third inductor, the first end of the third inductor is used to connect to an external power supply voltage, the second end of the third inductor is connected to the first end of the fifth capacitor, the first end of the fifth capacitor serves as the input terminal of the output matching circuit, the second end of the fifth capacitor is connected to the input terminal of the attenuator, and the output terminal of the attenuator serves as the output terminal of the output matching circuit.

[0021] In a second aspect, the present invention also provides a radio frequency chip, the radio frequency chip comprising a low-noise amplifier as described in any of the above embodiments.

[0022] Compared to existing technologies, this invention adds a distortion-prevention gain suppression circuit at the connection point of the first and second MOSFETs in the amplifier circuit. This circuit prevents distortion caused by excessive waveform amplitude. The distortion-prevention gain suppression circuit effectively reduces the linearity degradation problem in the chip amplification link caused by excessive waveform amplitude, thereby enabling the low-noise amplifier to output a radio frequency signal with better linearity. Furthermore, by designing the structure of the distortion-prevention gain suppression circuit, this invention allows for different gain levels and linearity improvements at different gain levels by adjusting the first switch and the first resistor in the circuit. By setting the resistance values ​​of the first resistor and the first capacitor in the capacitor unit, higher precision signal attenuation can be achieved. Attached Figure Description

[0023] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings:

[0024] Figure 1 is a schematic diagram of the circuit structure of the low-noise amplifier provided in Embodiment 1 of the present invention;

[0025] Figure 2 is a schematic diagram of the circuit structure of the low-noise amplifier provided in Embodiment 2 of the present invention;

[0026] Figure 3 is a schematic diagram of the circuit structure of the low-noise amplifier provided in Embodiment 3 of the present invention;

[0027] Figure 4 is a schematic diagram of the circuit structure of the low-noise amplifier provided in Embodiment 4 of the present invention;

[0028] Figure 5 is a schematic diagram of the circuit structure of the low-noise amplifier provided in Embodiment 5 of the present invention. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0030] Example 1

[0031] Please refer to Figure 1. The present invention provides a low-noise amplifier 100, including an input matching circuit 1, a bias circuit 2, an amplification circuit 3, an output matching circuit 4, and a distortion-prevention gain suppression circuit 5.

[0032] The input terminal of the input matching circuit 1 serves as the input terminal of the low-noise amplifier 100 for receiving radio frequency signals, and the output terminal of the input matching circuit 1 is connected to the first input terminal of the amplifier circuit 3.

[0033] The bias circuit 2 is used to provide a bias voltage for the amplifier circuit 3;

[0034] The output terminal of the amplifier circuit 3 is connected to the input terminal of the output matching circuit 4;

[0035] The output terminal of the output matching circuit 4 is connected to the output terminal of the low-noise amplifier 100.

[0036] The anti-distortion gain suppression circuit 5 is used to provide feedback adjustment for the gain output of the amplifier circuit 3 at different levels, so as to improve the linearity of the amplifier circuit 3 at different gain output levels.

[0037] In this embodiment of the invention, the amplifier circuit 3 includes a first MOSFET NM1, a second MOSFET NM2, and a first inductor L1. The gate of the first MOSFET NM1 serves as the first input terminal of the amplifier circuit 3. The source of the first MOSFET NM1 is grounded after being connected in series with the first inductor L1. The drain of the first MOSFET NM1 is connected to the source of the second MOSFET NM2. The gate of the second MOSFET NM2 serves as the second input terminal of the amplifier circuit 3, and the drain of the second MOSFET NM2 serves as the output terminal of the amplifier circuit 3. The bias circuit 2 provides bias voltages for the first MOSFET and the second MOSFET, respectively. The first inductor L1 is a source degenerate inductor used to provide input matching.

[0038] In this embodiment of the invention, the input matching circuit 1 includes a second inductor L2 and a third capacitor C3; the first end of the second inductor L2 serves as the input terminal of the input matching circuit 1, the second end of the second inductor L2 is connected to the first end of the third capacitor C3, and the second end of the third capacitor C3 serves as the output terminal of the input matching circuit 1. The third capacitor C3 is a barrier capacitor.

[0039] In this embodiment of the invention, the bias circuit 2 includes a filter circuit 21 that provides a bias voltage for the second MOSFET and a current mirror circuit 22 that provides a bias voltage for the first MOSFET. The filter circuit 21 includes a second resistor R2 and a fourth capacitor C4. The first end of the second resistor R2 serves as the input end of the filter circuit 21 and is used to connect to an external voltage source. The second end of the second resistor R2 serves as the output end of the filter circuit 21 and is connected to the gate of the second MOSFET. The first end of the fourth capacitor C4 is connected to the second end of the second resistor R2, and the second end of the fourth capacitor C4 is grounded.

[0040] In this embodiment of the invention, the current mirror circuit 22 includes a third MOSFET NM3 and a third resistor R3. The source of the third MOSFET NM3 is grounded, and the drain of the third MOSFET NM3 serves as the input terminal of the current mirror circuit 22, used to connect to an external current source. The gate of the third MOSFET NM3 is connected to both the first terminal of the third resistor R3 and the drain of the third MOSFET NM3. The second terminal of the third resistor R3 serves as the output terminal of the current mirror circuit 22, connected to the gate of the first MOSFET. The third resistor R3 is used to isolate the radio frequency and analog circuit modules, and its resistance value is set according to actual conditions to avoid introducing excessive noise.

[0041] In this embodiment of the invention, the output matching circuit 4 includes a third inductor L3, a first adjustable resistor Rbank, a fifth capacitor C5, and an attenuator 41. The first terminal of the first adjustable resistor Rbank is connected to the first terminal of the third inductor L3, and the second terminal of the first adjustable resistor Rbank is connected to the second terminal of the third inductor L3. The first terminal of the third inductor L3 is connected to an external power supply voltage VDD, and the second terminal of the third inductor L3 is connected to the first terminal of the fifth capacitor C5. The first terminal of the fifth capacitor C5 serves as the input terminal of the output matching circuit 4, and the second terminal of the fifth capacitor C5 is connected to the input terminal of the attenuator 41. The output terminal of the attenuator 41 serves as the output terminal of the output matching circuit 4. The fifth capacitor C5 is a blocking capacitor, and the third inductor L3 is a source load inductor.

[0042] In this embodiment of the invention, the anti-distortion gain suppression circuit 5 includes a capacitor unit 51, a plurality of first switches T1, and a plurality of first resistors R1. The first end of the capacitor unit 51 is connected to the drain of the first MOSFET NM1 and the source of the second MOSFET NM2, respectively. The second end of the capacitor unit 51 is connected to the first end of the plurality of first resistors R1, and the second ends of the plurality of first resistors R1 are respectively connected to the control terminals of the plurality of first switches T1. The output terminals of the plurality of first switches T1 are interconnected and grounded. The capacitor unit 51 is a first capacitor C1, with the first end of the first capacitor C1 serving as the first terminal of the capacitor unit 51, and the second end of the first capacitor C1 serving as the second terminal of the capacitor unit 51.

[0043] Specifically, the first terminal of the first capacitor C1 is connected to node netB in amplifier circuit 3. The second terminal of the first capacitor C1 is connected to multiple first resistors R1 and multiple first switches T1. Since a series switch array is added to ground at node netB, good output signal attenuation can be achieved. By adjusting the resistance values ​​of the multiple first resistors R1, different switching resistors can be used for different gain levels, thus improving linearity at different gain levels. It should be noted that the capacitance value of the first capacitor C1 cannot be too low, ideally in the pF range; otherwise, good transmission of the required frequency band signal will be impossible, which is detrimental to improving the linearity of the low-noise amplifier 100. Furthermore, the resistance value and number of the first resistors R1 and the number of first switches T1 can be set according to actual conditions. The three first resistors R1 and three first switches T1 in Figure 1 are only examples; other numbers of first resistors R1 and first switches T1 are also feasible. Adjusting the number of first resistors R1 and first switches T1 increases the gain level.

[0044] Example 2

[0045] Please refer to Figure 2. Embodiment 2 of the present invention provides a low-noise amplifier 200. The low-noise amplifier 200 of Embodiment 2 of the present invention has a basically the same circuit structure as the low-noise amplifier 100 of Embodiment 1 of the present invention, the difference being:

[0046] The anti-distortion gain suppression circuit 5 includes a capacitor unit 51, multiple first switches T1, and multiple first resistors R1. The first end of the capacitor unit 51 is connected to the drain of the second MOS transistor NM2. The second end of the capacitor unit 51 is connected to the first end of each of the multiple first resistors R1. The second ends of the multiple first resistors R1 are connected to the control terminals of the multiple first switches T1 one-to-one. The output terminals of the multiple first switches T1 are interconnected and connected to the gate of the first MOS transistor NM1. The capacitor unit 51 is a first capacitor C1, with its first end serving as the first terminal of the capacitor unit 51 and its second end serving as the second terminal of the capacitor unit 51.

[0047] Specifically, the first terminal of the first capacitor C1 is connected to node netC at the output of amplifier circuit 3. The second terminal of the first capacitor C1 is connected to the common terminal of multiple first resistors R1. Each of the multiple first resistors R1 is connected to the control terminal of a multiple first switch T1. The common terminal of the outputs of the multiple first switches T1 is connected to node netA at the input of amplifier circuit 3. By feeding the output signal back to the gate of the first MOSFET NM1, the net input signal amplitude at the input terminal can be effectively reduced, thereby improving linearity. Simultaneously, by adjusting the multiple first resistors R1 to different resistance values, different switching resistors can be used for different gain levels, achieving linearity improvement at different gain levels. It should be noted that the capacitance value of the first capacitor C1 cannot be too low, ideally in the pF range; otherwise, good transmission of the required frequency band signal will be impossible, which is detrimental to improving the linearity of the low-noise amplifier 100. Meanwhile, the resistance value and number of the first resistor R1 and the number of the first switch T1 can be set according to the actual situation. The three first resistors R1 and three first switches T1 in Figure 2 are just examples. Other numbers of first resistors R1 and first switches T1 are also feasible. The number of first resistors R1 and first switches T1 can be adjusted to increase the gain of different levels.

[0048] Example 3

[0049] Please refer to Figure 3. Embodiment 3 of the present invention provides a low-noise amplifier 300. The low-noise amplifier 300 of Embodiment 3 of the present invention has a basically the same circuit structure as the low-noise amplifier 100 of Embodiment 1 of the present invention, the difference being:

[0050] The anti-distortion gain suppression circuit 5 includes a capacitor unit 51, multiple first switches T1, and multiple first resistors R1. The first end of the capacitor unit 51 is connected to the drain of the first MOSFET NM1 and the source of the second MOSFET NM2, respectively. The second end of the capacitor unit 51 is connected to the first end of each of the multiple first resistors R1. The second ends of the multiple first resistors R1 are connected to the control terminals of the multiple first switches T1, and the output terminals of the multiple first switches T1 are interconnected and connected to the gate of the first MOSFET NM1. The capacitor unit 51 is a first capacitor C1, with its first end serving as the first terminal of the capacitor unit 51 and its second end serving as the second terminal of the capacitor unit 51.

[0051] Specifically, the first terminal of the first capacitor C1 is connected to node netB in amplifier circuit 3, and the second terminal of the first capacitor C1 is connected to the common terminal of multiple first resistors R1. Each of the multiple first resistors R1 is connected to a corresponding control terminal of a multiple first switch T1. The common terminal of the interconnected output terminals of the multiple first switches T1 is connected to node netA at the input of amplifier circuit 3. By feeding the output signal back to the gate of the first MOSFET NM1, the net input signal amplitude at the input terminal can be effectively reduced, thereby improving linearity. Simultaneously, by adjusting the multiple first resistors R1 to different resistance values, different switching resistors can be used for different gain levels, achieving linearity improvement at different gain levels. It should be noted that the capacitance value of the first capacitor C1 cannot be too low, ideally in the pF range; otherwise, good transmission of the required frequency band signal will be impossible, which is detrimental to improving the linearity of the low-noise amplifier 100. Meanwhile, the resistance value and number of the first resistor R1 and the number of the first switch T1 can be set according to the actual situation. The three first resistors R1 and three first switches T1 in Figure 3 are just examples. Other numbers of first resistors R1 and first switches T1 are also feasible. The number of first resistors R1 and first switches T1 can be adjusted to increase the gain of different levels.

[0052] Example 4

[0053] Please refer to Figure 4. Embodiment 4 of the present invention provides a low-noise amplifier 400. The low-noise amplifier 400 of Embodiment 4 of the present invention has a basically the same circuit structure as the low-noise amplifier 300 of Embodiment 3 of the present invention, the difference being:

[0054] The capacitor unit 51 includes a plurality of first capacitors C1 and a plurality of second switches T2; the first ends of the plurality of first capacitors C1 are interconnected and serve as the first ends of the capacitor unit 51, the second ends of the plurality of first capacitors C1 are respectively connected to the control ends of the plurality of second switches T2, and the output ends of the plurality of second switches T2 are interconnected and serve as the second ends of the capacitor unit.

[0055] Specifically, by adaptively adjusting multiple first capacitors C1 and multiple second switches T2, higher precision signal attenuation can be achieved according to different levels, thereby improving the linearity of the low-noise amplifier 100. It should be noted that although the number of first capacitors C1 and second switches T2 in Figure 4 is three, it does not mean that the number of first capacitors C1 and second switches T2 is limited to three. Other numbers of first capacitors C1 and second switches T2 are also feasible; different gain levels can be increased by adjusting the number of first capacitors C1 and second switches T2.

[0056] Example 5

[0057] Please refer to Figure 5. Embodiment 2 of the present invention provides a low-noise amplifier 500. The low-noise amplifier 500 of Embodiment 2 of the present invention has a basically the same circuit structure as the low-noise amplifier 300 of Embodiment 3 of the present invention, the difference being:

[0058] The anti-distortion gain suppression circuit 5 also includes a second capacitor C2; the first end of the second capacitor C2 is connected to the first end of the capacitor unit 51, and the second end of the second capacitor C2 is connected to the output ends of a plurality of first switches T1 respectively.

[0059] Specifically, the addition of the second capacitor C2 enables the anti-distortion gain suppression circuit 57 to provide higher precision signal attenuation, thereby improving the linearity of the low-noise amplifier 500.

[0060] Compared to existing technologies, this invention adds a distortion-prevention gain suppression circuit at the connection point of the first and second MOSFETs in the amplifier circuit. This circuit prevents distortion caused by excessive waveform amplitude. The distortion-prevention gain suppression circuit effectively reduces the linearity degradation problem in the chip amplification link caused by excessive waveform amplitude, thereby enabling the low-noise amplifier to output a radio frequency signal with better linearity. Furthermore, by designing the structure of the distortion-prevention gain suppression circuit, this invention allows for different gain levels and linearity improvements at different gain levels by adjusting the first switch and the first resistor in the circuit. By setting the resistance values ​​of the first resistor and the first capacitor in the capacitor unit, higher precision signal attenuation can be achieved.

[0061] Example 6

[0062] This invention also provides a radio frequency (RF) chip, which includes a low-noise amplifier as described in the above embodiments and can achieve the same technical effect. Please refer to the description in the above embodiments, which will not be repeated here.

[0063] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0064] The embodiments of the present invention have been described above with reference to the accompanying drawings. The disclosed embodiments are merely preferred embodiments of the present invention. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many equivalent changes in form without departing from the spirit and scope of the claims of the present invention, and all such changes are within the protection scope of the present invention.

Claims

1. A low-noise amplifier, characterized in that, It includes an input matching circuit, a bias circuit, an amplifier circuit, an output matching circuit, and a distortion-proof gain suppression circuit. The input terminal of the input matching circuit serves as the input terminal of the low-noise amplifier for receiving radio frequency signals, and the output terminal of the input matching circuit is connected to the first input terminal of the amplifier circuit. The bias circuit is used to provide a bias voltage for the amplifier circuit; The output terminal of the amplifier circuit is connected to the input terminal of the output matching circuit; The output terminal of the output matching circuit serves as the output terminal of the low-noise amplifier. The distortion-prevention gain suppression circuit is used to provide feedback adjustment for the gain output of the amplifier circuit at different levels, so as to improve the linearity of the amplifier circuit at different gain output levels.

2. The low-noise amplifier as described in claim 1, characterized in that, The amplifier circuit includes a first MOSFET, a second MOSFET, and a first inductor; the gate of the first MOSFET serves as the first input terminal of the amplifier circuit, the source of the first MOSFET is grounded after being connected in series with the first inductor, the drain of the first MOSFET is connected to the source of the second MOSFET, the gate of the second MOSFET serves as the second input terminal of the amplifier circuit, and the drain of the second MOSFET serves as the output terminal of the amplifier circuit; the bias circuit provides bias voltages for the first MOSFET and the second MOSFET respectively.

3. The low-noise amplifier as described in claim 2, characterized in that, The distortion-prevention gain suppression circuit includes a capacitor unit, multiple first switches, and multiple first resistors. The first end of the capacitor unit is connected to the drain of the first MOS transistor and the source of the second MOS transistor, respectively. The second end of the capacitor unit is connected to the first end of the multiple first resistors, respectively. The second ends of the multiple first resistors are connected to the control terminals of the multiple first switches one by one. The output terminals of the multiple first switches are interconnected and grounded.

4. The low-noise amplifier as described in claim 2, characterized in that, The distortion-prevention gain suppression circuit includes a capacitor unit, multiple first switches, and multiple first resistors; the first end of the capacitor unit is connected to the drain of the second MOS transistor, the second end of the capacitor unit is connected to the first end of the multiple first resistors, the second ends of the multiple first resistors are connected to the control terminals of the multiple first switches one by one, and the output terminals of the multiple first switches are interconnected and connected to the gate of the first MOS transistor.

5. The low-noise amplifier as described in claim 2, characterized in that, The distortion-prevention gain suppression circuit includes a capacitor unit, multiple first switches, and multiple first resistors. The first end of the capacitor unit is connected to the drain of the first MOS transistor and the source of the second MOS transistor, respectively. The second end of the capacitor unit is connected to the first end of the multiple first resistors, respectively. The second ends of the multiple first resistors are connected to the control terminals of the multiple first switches one by one. The output terminals of the multiple first switches are interconnected and then connected to the gate of the first MOS transistor.

6. The low-noise amplifier as described in any one of claims 3-5, characterized in that, The capacitor unit includes a plurality of first capacitors and a plurality of second switches; the first ends of the plurality of first capacitors are interconnected and serve as the first ends of the capacitor unit; the second ends of the plurality of first capacitors are respectively connected to the control ends of the plurality of second switches; and the output ends of the plurality of second switches are interconnected and serve as the second ends of the capacitor unit.

7. The low-noise amplifier as described in any one of claims 3-5, characterized in that, The distortion-prevention gain suppression circuit further includes a second capacitor; the first end of the second capacitor is connected to the first end of the capacitor unit, and the second end of the second capacitor is connected to the output ends of a plurality of first switches respectively.

8. The low-noise amplifier as described in claim 2, characterized in that, The bias circuit includes a filter circuit that provides a bias voltage for the second MOSFET and a current mirror circuit that provides a bias voltage for the first MOSFET. The filter circuit includes a second resistor and a fourth capacitor. The first end of the second resistor serves as the input terminal of the filter circuit and is used to connect to an external voltage source. The second end of the second resistor serves as the output terminal of the filter circuit and is connected to the gate of the second MOSFET. The first end of the fourth capacitor is connected to the second end of the second resistor, and the second end of the fourth capacitor is grounded.

9. The low-noise amplifier as described in claim 8, characterized in that, The current mirror circuit includes a third MOSFET and a third resistor; the source of the third MOSFET is grounded, the drain of the third MOSFET serves as the input terminal of the current mirror circuit for connecting to an external current source, the gate of the third MOSFET is connected to the first terminal of the third resistor and the drain of the third MOSFET respectively, and the second terminal of the third resistor serves as the output terminal of the current mirror circuit connected to the gate of the first MOSFET.

10. The low-noise amplifier as claimed in claim 1, characterized in that, The output matching circuit includes a third inductor, a first adjustable resistor, a fifth capacitor, and an attenuator. The first end of the first adjustable resistor is connected to the first end of the third inductor, and the second end of the first adjustable resistor is connected to the second end of the third inductor. The first end of the third inductor is used to connect to an external power supply voltage. The second end of the third inductor is connected to the first end of the fifth capacitor. The first end of the fifth capacitor serves as the input terminal of the output matching circuit. The second end of the fifth capacitor is connected to the input terminal of the attenuator. The output terminal of the attenuator serves as the output terminal of the output matching circuit.

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