Probe assembly and manufacturing method therefor, and testing apparatus

Abstract

The present disclosure belongs to the technical field of semiconductor testing. Provided are a probe assembly and a manufacturing method therefor, and a testing apparatus, which can solve the problem of poor accuracy in existing probe assemblies. The probe assembly of the present disclosure comprises a probe unit and a support unit which are arranged opposite each other, wherein the probe unit is arranged on the support unit, and comprises a first substrate and a plurality of probes located on the first substrate; the support unit comprises a second substrate and a plurality of elastic support structures located on the second substrate; and the orthographic projections of the probes on the second substrate at least partially overlap with the orthographic projections of the elastic support structures on the second substrate.

Description

Probe components, their preparation methods, and testing equipment Technical Field

[0001] This disclosure belongs to the field of semiconductor testing technology, specifically relating to a probe assembly and its preparation method and testing equipment. Background Technology

[0002] In the semiconductor manufacturing process, it is necessary to test the performance of semiconductor products at each stage to prevent defective products from flowing into the next process and affecting product quality. Typically, probes are used to input test signals into semiconductor products during testing. For example, in the manufacturing process of display panels, probes are used to input test signals to the anodes of each light-emitting device in the display panel to test whether the display panel can display normally.

[0003] Currently, the main types of probes used in the semiconductor industry include: cantilever probes, blade probes, vertical probes, micro-electro-mechanical system (MEMS) probes, and thin-film probes. Among these, thin-film probe technology, as a small-pitch, high-precision probe technology, can meet the testing needs of semiconductor devices as they move towards miniaturization and integration, and is therefore widely used. Summary of the Invention

[0004] This disclosure aims to at least solve one of the technical problems existing in the prior art, and provides a probe assembly, its preparation method, and testing equipment.

[0005] In a first aspect, embodiments of this disclosure provide a probe assembly, the probe assembly comprising: a probe unit disposed on a cartridge and a support unit; the probe unit being disposed on the support unit;

[0006] The probe unit includes: a first substrate and a plurality of probes located on the first substrate; the support unit includes: a second substrate and a plurality of elastic support structures located on the second substrate.

[0007] The orthographic projection of the probe on the second substrate at least partially overlaps with the orthographic projection of the elastic support structure on the second substrate.

[0008] In some embodiments, the probe unit further includes: a probe base and a test signal line located on the first substrate;

[0009] The probe base is located on the side of the probe closer to the first substrate;

[0010] The test signal line is connected to the probe base.

[0011] In some embodiments, the probe unit further includes a switching transistor; the switching transistor includes: a gate, a gate insulating layer, a semiconductor layer, a first electrode, and a second electrode sequentially disposed along a direction away from the first substrate; the first electrode and the second electrode are disposed in the same layer and are respectively connected to both ends of the semiconductor layer;

[0012] The second electrode is reused as the probe base.

[0013] In some embodiments, the probe unit further includes: a switch signal line located on the first substrate and intersecting with the test signal line;

[0014] The test signal line is connected to the first electrode;

[0015] The switch signal line is connected to the gate.

[0016] In some embodiments, each of the elastic support structures includes: a first support member and a second support member;

[0017] The height of the first support member is greater than the height of the second support member.

[0018] In some embodiments, the support unit further includes: an auxiliary elastic support structure located between adjacent elastic support structures;

[0019] The height of the auxiliary elastic support structure is less than the height of the elastic support structure.

[0020] In some embodiments, the probe assembly further includes: an encapsulation layer;

[0021] The encapsulation layer is located between the first substrate and the second substrate, and is disposed around the edges of the first substrate and the second substrate.

[0022] In some embodiments, the probe unit further includes: an antioxidant layer;

[0023] The antioxidant layer is located on the side of the probe opposite to the first substrate.

[0024] In some embodiments, the probe has a circular, triangular, quadrilateral, or hexagonal shape along a cross section parallel to the first substrate.

[0025] In some embodiments, the probe has a plurality of contact electrodes formed on the side opposite to the first substrate; at least some of the contact electrodes have different sizes and heights.

[0026] Secondly, embodiments of this disclosure provide a testing device, which includes the probe assembly provided above.

[0027] In some embodiments, the testing device is used to test an array of light-emitting devices; the plurality of probes are divided into a plurality of probe groups that correspond one-to-one with the light-emitting devices; each probe group is provided with a first probe and a second probe that correspond one-to-one with the anode and cathode of the light-emitting devices, respectively;

[0028] The first probe in the same probe group is connected to the anode test pad;

[0029] The second probes in the same probe group are all connected to the cathode test pads.

[0030] In some embodiments, the anode test pad and the cathode test pad are located on opposite sides of the probe group along the column direction.

[0031] In some embodiments, the first probe in each probe group is connected to the anode test pad via a switching transistor;

[0032] The first probe is connected to the second electrode of the switching transistor, the anode test pad is connected to the first electrode of the switching transistor, and the switching signal line is connected to the gate of the switching transistor.

[0033] In some embodiments, the gates of the switching transistors connected to the first probes in the same row of the probe group are all connected to the same switching signal line.

[0034] In some embodiments, the testing equipment is used to test a micro-driver chip array; the plurality of probes are divided into a plurality of probe groups that correspond one-to-one with the micro-driver chip; each probe group is provided with a third probe, a fourth probe, a fifth probe, a sixth probe and a seventh probe that correspond one-to-one with the input signal terminal, output signal terminal, power signal terminal, clock signal terminal and reset signal terminal of the micro-driver chip respectively;

[0035] In the same row, the fourth probe in the probe group of this column is connected to the seventh probe in the probe group of the previous column and the third probe in the probe group of the next column;

[0036] Each of the third probes in the first column of the probe group is connected to the starting test pad; each of the fourth probes in the last column of the probe group is connected to the output test pad via a switching transistor.

[0037] The fifth probe in each of the aforementioned probe groups is connected to the power test pad;

[0038] The sixth probe in each of the probe groups is connected to the clock test pad.

[0039] In some embodiments, the testing equipment is used to test a micro-driver chip array; the plurality of probes are divided into a plurality of probe groups that correspond one-to-one with the micro-driver chip; each probe group is provided with a third probe, a fourth probe, a fifth probe, a sixth probe, and a seventh probe that correspond one-to-one with the input signal terminal, output signal terminal, power signal terminal, clock signal terminal, and reset signal terminal of the micro-driver chip;

[0040] The fourth probe in the probe group in the same column is connected to the seventh probe in the probe group in the previous row and the third probe in the probe group in the next row;

[0041] Each of the third probes in the probe group described in the first row is connected to the starting test pad; each of the fourth probes in the probe group described in the last row is connected to the output test pad via a switching transistor.

[0042] The fifth probe in each of the aforementioned probe groups is connected to the power test pad;

[0043] The sixth probe in each of the probe groups is connected to the clock test pad.

[0044] In some embodiments, the testing device further includes: a scan driving circuit; the scan driving circuit is located on the first substrate and disposed on one side of the probe group along the row direction, or on one side of the probe group along the column direction;

[0045] The scanning drive circuit is connected to each of the switch signal lines and is configured to provide switch control signals to each of the switch signal lines one by one according to a preset timing sequence.

[0046] In some embodiments, the scan driving circuit includes: a plurality of shift registers; the shift registers include: an input sub-circuit, a reset sub-circuit, and an output sub-circuit;

[0047] The input sub-circuit is configured to control the voltage of the pull-up node in response to an input signal;

[0048] The reset sub-circuit is configured to reset the voltage of the pull-up node using a power supply signal in response to a reset signal.

[0049] The output sub-circuit is configured to output a clock signal in response to the voltage of the pull-up node, or to output a power signal in response to a reset signal.

[0050] In some embodiments, the input sub-circuit includes: a first transistor; the reset sub-circuit includes: a second transistor; and the output sub-circuit includes: a third transistor, a storage capacitor, and a fourth transistor.

[0051] The gate and first electrode of the first transistor are connected to the input signal line, and the second electrode is connected to the pull-up node; the gate of the second transistor is connected to the reset signal line, the first electrode is connected to the power signal line, and the second electrode is connected to the pull-up node; the gate of the third transistor is connected to the pull-up node, the first electrode is connected to the clock signal line, and the second electrode is connected to the output signal line; one end of the storage capacitor is connected to the pull-up node, and the other end is connected to the output signal line; the gate of the fourth transistor is connected to the reset signal line, the first electrode is connected to the power signal line, and the second electrode is connected to the output signal line.

[0052] In some embodiments, the input signal lines in the shift register of this level are connected to the output signal lines in the shift register of the previous level;

[0053] The reset signal line in the shift register of this stage is connected to the output signal line in the shift register of the next stage.

[0054] Thirdly, this disclosure provides a method for preparing a probe assembly, used to prepare the probe assembly as described above, the method comprising:

[0055] Multiple probes are formed on the first substrate to form a probe unit;

[0056] Multiple elastic support structures are formed on the second substrate to form support units;

[0057] The probe unit and the support unit are bonded together to form a probe assembly; the orthographic projection of the probe on the second substrate at least partially overlaps with the orthographic projection of the elastic support structure on the second substrate.

[0058] In some embodiments, a plurality of probes are formed on a first substrate to form a probe unit, including:

[0059] A first substrate is formed on a support substrate;

[0060] Using a patterning process, a pattern defining layer is formed on the side of the first substrate opposite to the supporting substrate; the pattern defining layer is provided with a plurality of first probe openings;

[0061] A seed layer is formed within the area defined by the first probe opening of the pattern defining layer;

[0062] Using a patterning process, an insulating layer is formed on the side of the pattern defining layer opposite to the first substrate; the insulating layer is provided with a plurality of second probe openings; the orthographic projection of the second probe openings on the first substrate at least partially overlaps with the orthographic projection of the first probe openings on the first substrate;

[0063] Multiple probes are formed within the area defined by the first probe opening and the second probe opening using an electroplating process;

[0064] The insulating layer is removed to expose the plurality of probes.

[0065] In some embodiments, a pattern defining layer is formed on the side of the first substrate opposite to the supporting substrate using a patterning process, and the process further includes:

[0066] Using a patterning process, a probe base and a test signal line are formed on the first substrate; the probe base is located on the side of the probe closer to the first substrate; the test signal line is connected to the probe base.

[0067] In some embodiments, the probe unit and the support unit are bonded together to form a probe assembly, including:

[0068] A removable encapsulation layer is formed at the edge of the first substrate;

[0069] A transfer substrate is attached to the side of the removable encapsulation layer opposite to the first substrate.

[0070] Peel off the support substrate;

[0071] An encapsulation layer is formed at the edge of the second substrate;

[0072] Using the transfer substrate, the first substrate and the second substrate are bonded together through the encapsulation layer;

[0073] The transfer substrate is peeled off, and the removable encapsulation layer is removed. Attached Figure Description

[0074] Figure 1 is a schematic diagram of an exemplary probe assembly.

[0075] Figure 2 is a schematic diagram of the structure of a probe assembly provided in an embodiment of this disclosure.

[0076] Figure 3 is a schematic diagram of another probe assembly provided in an embodiment of this disclosure.

[0077] Figure 4 is a schematic diagram of another probe assembly provided in an embodiment of this disclosure.

[0078] Figure 5 is a schematic diagram of another probe assembly provided in an embodiment of this disclosure.

[0079] Figure 5A is a top view of a probe in a probe assembly provided in an embodiment of this disclosure.

[0080] Figure 6 is a schematic diagram of an exemplary light-emitting device array.

[0081] Figure 7 is a schematic diagram of the structure of a testing device provided in an embodiment of this disclosure.

[0082] Figure 8 is a schematic diagram of another testing device provided in an embodiment of this disclosure.

[0083] Figure 9 is a schematic diagram of an exemplary micro-driver chip array.

[0084] Figure 10 is a schematic diagram of the structure of another testing device provided in an embodiment of this disclosure.

[0085] Figure 11 is a schematic diagram of another testing device provided in an embodiment of this disclosure.

[0086] Figure 12 is a schematic diagram of a scanning drive circuit provided in an embodiment of this disclosure.

[0087] Figure 13 is a schematic diagram of the shift register in the scan drive circuit shown in Figure 12.

[0088] Figure 14 is a schematic flowchart of a method for preparing a probe assembly according to an embodiment of this disclosure.

[0089] Figure 15 is a schematic flowchart of a probe unit fabrication method.

[0090] Figures 16a to 16h are schematic diagrams of the intermediate structures during the fabrication process of the probe unit.

[0091] Figures 17a to 17c are schematic diagrams of the intermediate structure during the fabrication process of the support unit.

[0092] Figure 18 is a schematic diagram of the process of bonding a probe unit and a support unit to a box.

[0093] Figures 19a to 19f are schematic diagrams of the intermediate structure during the bonding process of the probe unit and the support unit to the box. Detailed Implementation

[0094] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. The components of the embodiments of this disclosure described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed disclosure, but merely represents selected embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure. Without conflict, the various embodiments of this disclosure and the features in the embodiments can be combined with each other.

[0095] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising,” “including,” or “including,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0096] In this disclosure, "multiple or several" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0097] It should be noted that the transistors used in the embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Since the source and drain of the transistors are symmetrical, there is no distinction between them. In the embodiments of this disclosure, to distinguish the source and drain of the transistor, one electrode is called the first electrode, and the other electrode is called the second electrode. Furthermore, transistors can be classified into N-type transistors and P-type transistors according to their characteristics. The following embodiments are based on N-type transistors. When using an N-type transistor, the first electrode is the source, and the second electrode is the drain. When a high-level signal is input to the gate, the source and drain electrodes are turned on; the opposite is true for P-type transistors. It is conceivable that using a P-type transistor is something that those skilled in the art can easily conceive of without creative effort, and therefore it is within the scope of protection of the embodiments of this disclosure. Moreover, the power signal line in the embodiments of this disclosure can specifically be a low-level power signal line, which can provide a low-level power signal.

[0098] Figure 1 is a schematic diagram of an exemplary probe assembly. As shown in Figure 1, the probe assembly includes: a first substrate 101 and a plurality of probes 102 located on the first substrate 101; the probe assembly also includes: a probe base 103 located on the first substrate 101 and a test signal line 104; the probe base 103 is located on the side of the probes 102 closer to the first substrate 101; the test signal line 104 is connected to the probe base 103. The probe base 103 is made of metal material, which provides stable support for the probes 102 on it while transmitting the test signal in the test signal line 104.

[0099] During the testing process, multiple probes 102 can be connected to the pads to be tested. External testing equipment can transmit test signals to probes 102 through test signal lines 104, and then transmit test signals to the pads to be tested through probes 102. This allows the semiconductor products to be tested, preventing defective products from flowing into the next process and affecting product quality.

[0100] For example, in the fabrication process of a display panel, probes are used to input test signals to the anodes of each light-emitting device in the display panel to test whether the display panel can display normally. The light-emitting devices can specifically be Organic Light-Emitting Diodes (OLEDs), Micro-LEDs, Quantum Dot Light-Emitting Diodes (QLEDs), etc. In this disclosure and the following description, Micro-LEDs will be used as an example. Because the display panel has a large area, the anodes of each light-emitting device are not necessarily on the same plane, but have a certain step difference. During the test, the probes 102 in the probe assembly cannot contact and connect with the anodes of all light-emitting devices, resulting in some probes 102 being disconnected from the anodes of the light-emitting devices. This can easily cause the test signal to not be directly transmitted to the corresponding anode, affecting the test yield and reducing the test accuracy.

[0101] To at least solve one of the above-mentioned technical problems, this disclosure provides a probe assembly, its preparation method, and testing equipment. The following will describe in further detail the probe assembly, its preparation method, and testing equipment provided in this disclosure in conjunction with the accompanying drawings and specific embodiments.

[0102] In a first aspect, the present disclosure provides a probe assembly. FIG2 is a schematic diagram of the structure of a probe assembly provided in the present disclosure. As shown in FIG2, the probe assembly includes: a probe unit 10 and a support unit 20 disposed on a housing; the probe unit 10 is disposed on the support unit 20; the probe unit 10 includes: a first substrate 101 and a plurality of probes 102 located on the first substrate 101; the support unit 20 includes: a second substrate 201 and a plurality of elastic support structures 202 located on the second substrate 201; the orthographic projection of the probes 102 on the second substrate 201 and the orthographic projection of the elastic support structures 202 on the second substrate 201 at least partially overlap.

[0103] The first substrate 101 can be a single-layer or multi-layer structure, and can be made of flexible materials such as polyimide (PI), which has good bending and tensile resistance. In the embodiments of this disclosure, the first substrate 101 adopts a single-layer structure. The first substrate 101 can effectively support the multiple probes 102 on it, which can prevent the probe assembly from breaking due to stress during bending, stretching, and twisting, thus avoiding poor circuit breaking. In practical applications, the first substrate 101 can be patterned, removing some areas of the substrate 101, such as areas where no probes 102 are provided, and areas where test signal lines 104 and switch signal lines 106 are not subsequently provided, so that the thin film probe as a whole does not interfere with each other when deformed.

[0104] The probe 102 can be a single-layer or multi-layer structure, and can be made of materials with good electrical conductivity, such as metals or metal alloys. For example, the material of the probe 102 can be selected from metals such as copper (Cu), aluminum (Al), nickel (Ni), gold (Au), palladium (Pd), platinum (Pt), tungsten (W), and radium (Ra), or alloys such as copper (Cu) alloys, beryllium copper (BeCu), and tungsten (W) alloys. In practical applications, multiple probes 102 are all of equal height, which ensures the flatness of the probe assembly surface.

[0105] The second substrate 201 can be a single-layer or multi-layer structure, and can be made of flexible materials such as polyimide (PI) or rigid materials such as glass or metal. In the embodiments of this disclosure, the second substrate 201 adopts a double-layer structure, one layer being a glass substrate and the other layer being a PI substrate, with the PI substrate located on the glass substrate. This can effectively support the elastic structure 202 and other structures on it.

[0106] The elastic support structure 202 can be a single-layer or multi-layer structure, and its material can be made of elastic materials such as polydimethylsiloxane (PDMS), silicone, acrylate, and epoxy resin. The elastic support structure 202 can be a full-surface support layer, with a size greater than or equal to the size of the area where each probe 102 is located. Alternatively, the elastic support structure 202 can be a patterned support layer; for example, the orthographic projection of the probe 102 on the second substrate 201 at least partially overlaps with the orthographic projection of the elastic support structure 202 on the second substrate 201, thus enabling the elastic support structure 202 to support the probe 102.

[0107] In the probe assembly provided in this embodiment, when not under testing, the elastic support structure 202 is in a non-compressed state. All elastic support structures 202 have the same height, and the heights of the probes 102 supported on them are also equal, resulting in a relatively flat probe assembly surface and ensuring surface smoothness. During testing, some elastic support structures 202 can deform under external force and enter a compressed state, allowing each probe 102 to be at a different height. This accommodates the step differences on the surface of the semiconductor product under test, ensuring that each probe 102 can contact and connect with the pads under test. This prevents some probes 102 from being disconnected from the pads, ensuring that test signals are transmitted to the corresponding test pads. Therefore, this improves test yield and accuracy. Meanwhile, under the action of external force, the probe 102 will be displaced to remove or destroy the oxide layer, impurities and other film layers on the pad to be tested that affect the electrical connection, thereby ensuring that each probe 102 is in contact with and connected to the pad to be tested, thereby further improving the test yield and improving the test accuracy.

[0108] In some embodiments, as shown in FIG2, the probe unit 10 further includes: a probe base 103 and a test signal line 104 located on a first substrate 101; the probe base 103 is located on the side of the probe 102 close to the first substrate 101; the test signal line 104 is connected to the probe base 103.

[0109] The probe base 103 can be a single-layer or multi-layer structure, and can be made of materials with good electrical conductivity, such as metals or metal alloys. For example, the material of the probe base 103 can be selected from metals such as copper (Cu), aluminum (Al), molybdenum (Mo), and titanium (Ti), or alloys such as copper (Cu) alloys and beryllium copper (BeCu). The projected area of ​​the probe base 103 on the first substrate 101 is larger than the projected area of ​​the probe 102 on the first substrate 101. The probe base 103 can effectively support the probe 102 and prevent the probe 102 from piercing the first substrate 101 under external force. Simultaneously, the probe base 103 is connected to the test signal line 104 and has good electrical conductivity, allowing the test signal transmitted in the test signal line 104 to be transmitted to the probe 102 via the probe base 103.

[0110] The test signal line 104 can be made of the same material and using the same process as the probe base 103, which can reduce the number of process steps, reduce the difficulty of the process, save the manufacturing cost, and ensure the effective connection between the test signal line 104 and the probe base 103, reduce the contact resistance, and ensure the effective transmission of the test signal line.

[0111] Figure 3 is a schematic diagram of another probe assembly provided in an embodiment of this disclosure. As shown in Figure 3, the probe unit 10 further includes a switching transistor. The switching transistor includes: a gate 1051, a gate insulating layer 1052, a semiconductor layer 1053, a first electrode 1054, and a second electrode 1055 sequentially disposed along a direction away from the first substrate 101. The first electrode 1054 and the second electrode 1055 are disposed in the same layer and are respectively connected to both ends of the semiconductor layer 1053. The second electrode 1055 is multiplexed as a probe base 103. The probe unit 10 further includes: a switching signal line 106 located on the first substrate 101 and intersecting with the test signal line 104. The test signal line 104 is connected to the first electrode 1054. The switching signal line 106 is connected to the gate 1051.

[0112] The first electrode 1054 can be the source of a switching transistor, and the second electrode 1055 can be the drain of a switching transistor. Test signal line 104 is connected to the source, and switching signal line 106 is connected to the gate 1051. When the signal transmitted by switching signal line 106 is an enable signal (high-level or low-level signal, depending on the type of switching transistor), the source and drain are connected through semiconductor layer 1053. The test signal transmitted by test signal line 104 passes through the source, semiconductor layer 1053, and drain, and is transmitted to probe 102 to test the pad to be tested. The second electrode 1055 can be reused as probe base 103, eliminating the need for separate probe base fabrication, reducing process steps, and saving fabrication costs. It also reduces the number of film layers and the thickness of the probe assembly. Furthermore, the probe unit 10 can integrate test devices such as switching transistors to directly provide test signals to the pad to be tested, reducing investment in test equipment and lowering test costs.

[0113] It is understandable that, in addition to integrating the aforementioned switching transistors, the probe unit 10 can also integrate other test devices, such as resistors and capacitors. The integration principle is similar to that described above and will not be detailed here.

[0114] Figure 4 is a schematic diagram of another probe assembly provided in an embodiment of the present disclosure. As shown in Figure 4, each elastic support structure 202 includes: a first support member 2021 and a second support member 2022; the height of the first support member 2021 is greater than the height of the second support member 2022.

[0115] Each elastic support structure 202 can be composed of two support members with different heights, namely a first support member 2021 and a second support member 2022, wherein the height of the first support member 2021 is greater than the height of the second support member 2022. The first support member 2021 and the second support member 2022 are aligned with the two ends of the probe 102, respectively. During the downward pressing of the probe 102, due to the certain height difference between the first support member 2021 and the second support member 2022, the probe 102 can undergo a certain displacement not only in the vertical direction but also in the horizontal direction. This allows the probe 102 to remove or destroy oxide layers, impurities, and other films on the pads to be tested that affect electrical connections. This further ensures that each probe 102 contacts and connects with the pads to be tested, thereby further improving the test yield and accuracy.

[0116] Figure 5 is a schematic diagram of another probe assembly provided in an embodiment of the present disclosure. As shown in Figure 5, the support unit 20 further includes an auxiliary elastic support structure 203 located between adjacent elastic support structures 202; the height of the auxiliary elastic support structure 203 is less than the height of the elastic support structure 202.

[0117] The height of the auxiliary elastic support structure 203 is less than the height of the elastic support structure 202. During the pressing process of the probe 102, the auxiliary elastic support structure 203 can provide further support for the probe unit 10, avoid damage to the probe unit 10 due to excessive external force, and improve the structural stability of the probe assembly.

[0118] In some embodiments, as shown in Figures 2 to 4, the probe assembly further includes an encapsulation layer 30; the encapsulation layer 30 is located between the first substrate 101 and the second substrate 201, and is disposed around the edges of the first substrate 101 and the second substrate 201.

[0119] The encapsulation layer 30 can be made of adhesive materials such as epoxy resin, acrylic, silicone, polysulfide, butyl, and polyurethane. The encapsulation layer 30 can bond the probe unit 10 and the support unit 20 together to form an integral probe assembly, ensuring the structural stability of the probe assembly.

[0120] In some embodiments, the probe unit 10 further includes an antioxidant layer (not shown in the figure); the antioxidant layer is located on the side of the probe 102 away from the first substrate 101.

[0121] The anti-oxidation layer can be made of a metal material with anti-oxidation properties, such as gold (Au), tungsten (W), zirconium (Zr), etc. The anti-oxidation layer can cover the side of probe 102 away from the first substrate 101, which can prevent the probe 102 from oxidizing and affecting the connection between probe 102 and the pad to be tested, thereby improving the transmission effect of test signals and improving test accuracy.

[0122] In practical applications, the shape of the probe 102 along the cross section parallel to the first substrate 101 can be circular, triangular, quadrilateral or hexagonal, or it can be an irregular shape such as S-shaped. It can be set according to actual needs, and will not be listed one by one here.

[0123] In some embodiments, FIG5A is a top view of a probe in a probe assembly provided in this disclosure. As shown in FIG5A, a plurality of contact electrodes 1020 are formed on the side of the probe 102 away from the first substrate 101; at least some of the contact electrodes 1020 have different sizes and heights.

[0124] Taking a scenario with three contact electrodes 1020 as an example, each contact electrode 1020 has a different size and height. Under the action of external force, each contact electrode 1020 in the probe 102 will undergo a certain displacement, causing the probe 102 to remove or destroy oxide layers, impurities, and other films affecting electrical connection on the pad to be tested. This further ensures that each probe 102 contacts and connects with the pad to be tested, thereby further improving the test yield and accuracy. It is understandable that the size and height of each contact electrode 1020 can also be the same. Although this cannot achieve the same effect of removing or destroying oxide layers, impurities, and other films affecting electrical connection on the pad to be tested, it can still increase the stability of the contact between each contact electrode 1020 and the pad to be tested, which can improve the test yield and accuracy to a certain extent.

[0125] Secondly, this disclosure provides a testing apparatus that includes a probe assembly as provided in any of the above embodiments.

[0126] Figure 6 is a schematic diagram of an exemplary light-emitting device array. As shown in Figure 6, the light-emitting device array includes multiple light-emitting devices 601; each light-emitting device 601 includes an anode 6011 and a cathode 6012. When an anode signal is input to the anode 6011 and a cathode signal is input to the cathode 6012, it can emit light to realize the display function. It should be noted that the light-emitting device 601 can specifically be a Micro-LED.

[0127] The testing equipment provided in this embodiment can be used to test the light-emitting device array shown in FIG6. FIG7 is a schematic diagram of the structure of a testing equipment provided in this embodiment. As shown in FIG7, multiple probes 102 are divided into multiple probe groups G that are arranged one-to-one with the light-emitting device 601; each probe group G is provided with a first probe 1021 and a second probe 1022 that are respectively arranged one-to-one with the anode 6011 and the cathode 6012 of the light-emitting device 601; the first probes 1021 in the same column of probe group G are all connected to the anode test pad 701; the second probes 1022 in the same column of probe group G are all connected to the cathode test pad 702.

[0128] In practical applications, multiple light-emitting devices 601 can be arranged in an array to form a light-emitting device array. Correspondingly, multiple probes 102 can be divided into multiple probe groups G. Each probe group G is provided with two probes 102, namely the first probe 1021 and the second probe 1022. The first probe 1021 and the second probe 1022 in each probe group G can provide anode test signals and cathode test signals to the anode 6011 and cathode 6012 of each light-emitting device 601, respectively, so as to simultaneously test each light-emitting device 601 in the light-emitting device array, so as to meet the testing of high-density, large-scale integrated light-emitting device arrays.

[0129] In the testing equipment, all first probes 1021 within the same probe group G can be shorted together by a common test signal line 104, the end of which can be connected to the anode test pad 701. Similarly, all second probes 1022 within the same probe group G are also shorted together by another independent test signal line 104, the end of which can be connected to the cathode test pad 702.

[0130] During testing, a single anode test pad 701 and its corresponding test signal line 104 can be used to simultaneously provide an anode test signal to the first probe 1021 in the probe group G; simultaneously, a single cathode test pad 702 and its corresponding test signal line 104 can be used to simultaneously provide a cathode test signal to the second probe 1022 in the probe group G. This significantly reduces the number of independent test signal lines 104 required between adjacent first probes 1021 and adjacent second probes 1022, reserving more space for the first probes 1021 and second probes 1022. This not only optimizes the signal transmission path and reduces circuit complexity, but also effectively reduces the possibility of mutual interference between different test signal lines 104, thereby helping to improve the testing efficiency and accuracy of the testing equipment.

[0131] It should be noted that since the first probes 1021 in the same column probe group G are shorted together, and the second probes 1022 in the same column probe group G are shorted together, when one or more light-emitting devices 601 in the light-emitting device array malfunction, further testing can be carried out by observation or taking pictures to accurately test the yield, brightness, color and other performance of the corresponding light-emitting device 601.

[0132] In some embodiments, as shown in FIG6, the anode test pad 701 and the cathode test pad 702 are located on opposite sides of the probe group G along the column direction.

[0133] In the structural layout of the anode test pad 701 and the cathode test pad 702, the anode test pad 701 and the cathode test pad 702 are respectively arranged on both sides of the probe group G along the column direction, that is, they are in opposite positions. This opposing arrangement ensures that there is sufficient physical distance between the two test pads with different polarities, thereby effectively preventing electrical short circuits that may be caused by excessive distance. In addition, this layout also helps to achieve clearer signal isolation during testing, reduce cross-interference, and improve the integrity and stability of test signals. This not only enhances the safety of the test equipment, but also provides a layout basis for subsequent high-density, high-parallelism testing, further ensuring test accuracy and long-term operational stability.

[0134] Figure 8 is a schematic diagram of another test device provided in an embodiment of this disclosure. As shown in Figure 8, the first probe 1021 in each probe group G is connected to the anode test pad 701 through the switching transistor TFT; the first probe 1021 is connected to the second electrode of the switching transistor TFT, the anode test pad 701 is connected to the first electrode of the switching transistor TFT, and the switching signal line 106 is connected to the gate of the switching transistor TFT.

[0135] The test equipment shown in Figure 8 differs from that shown in Figure 7 in that, in the test equipment shown in Figure 7, the first probes 1021 in the same probe group G are shorted together, and the second probes 1022 in the same probe group G are shorted together. Although this allows for precise testing of the yield, brightness, and chromaticity of the corresponding light-emitting device 601, it cannot perform current-voltage characteristic testing (IV testing) or current-voltage-brightness comprehensive testing (IVL testing) of the corresponding light-emitting device 601. In the test equipment shown in Figure 8, multiple switching transistors (TFTs) are added to the test equipment shown in Figure 7. The first probe 1021 is connected to the second electrode of the switching transistor TFT, the anode test pad 701 is connected to the first electrode of the switching transistor TFT, and the switching signal line 106 is connected to the gate of the switching transistor TFT. Since the first probe 1021 in each probe group G is connected to the anode test pad 701 through the switching transistor TFT, the anode test signal can be independently input to each first probe 1021 in a time-division manner. Therefore, the current-voltage characteristic test (IV test) and the current-voltage-brightness comprehensive test (IVL test) of the corresponding light-emitting device 601 can be realized, thereby further improving the test efficiency and test accuracy of the test equipment.

[0136] In some embodiments, as shown in FIG8, the gates of the switching transistors TFTs connected to the first probe 1021 in the same row of probe group G are all connected to the same switching signal line 106.

[0137] In the same row of probe groups G, the gates of the switching transistors (TFTs) connected to each first probe 1021 are all connected to the same switching signal line 106. With the aid of an external scanning drive circuit, the switching on and off of each first probe 1021 and its corresponding test signal line 104 in the same row of probe groups G can be synchronously controlled via this single switching signal line 106, thereby enabling current-voltage characteristic testing (IV testing) and current-voltage-brightness comprehensive testing (IVL testing) of the corresponding light-emitting device 601. This reduces the number of switching signal lines 106 required between different row of probe groups G, thus freeing up more physical layout space for the first probe 1021 and the second probe 1022. Therefore, it not only simplifies the wiring structure and reduces the overall circuit complexity but also effectively suppresses mutual interference between different switching signal lines 106, ensuring the integrity and stability of the test signal during transmission, and further improving the overall efficiency of the testing equipment and the accuracy of the test data.

[0138] Figure 9 is a schematic diagram of an exemplary micro-driver chip array. As shown in Figure 9, the micro-driver chip array includes multiple micro-driver chips 901. Each micro-driver chip 901 includes an input signal terminal 9011, an output signal terminal 9012, a power signal terminal 9013, a clock signal terminal 9014, and a reset signal terminal 9015. When the corresponding signals are input to the above signal terminals, it can operate to realize the driving function. It should be noted that the micro-driver chip 901 can specifically be a chip used to drive Micro-LEDs.

[0139] The testing equipment provided in this disclosure can be used to test the micro-driver chip array shown in FIG9. FIG10 is a schematic diagram of the structure of another testing equipment provided in this disclosure. As shown in FIG10, multiple probes 102 are divided into multiple probe groups G corresponding to the micro-driver chip 901; each probe group G is provided with a third probe 1023, a fourth probe 1024, a fifth probe 1025, a sixth probe 1026, and a seventh probe 1027 respectively corresponding to the input signal terminal 9011, output signal terminal 9012, power signal terminal 9013, clock signal terminal 9014, and reset signal terminal 9015 of the micro-driver chip 901; in the same row The fourth probe 1024 in the current probe group G is connected to the seventh probe 1027 in the previous probe group G and the third probe 1023 in the next probe group G; each of the third probes 1023 in the first probe group G is connected to the starting test pad STV; each of the fourth probes 1024 in the last probe group G is connected to the output test pad Output through the switching transistor TFT; each of the fifth probes 1025 in each probe group G is connected to the power test pad VSS; and each of the sixth probes 1026 in each probe group G is connected to the clock test pad CK.

[0140] In practical applications, multiple micro-driver chips 901 can be arranged in an array to form a micro-driver chip array. Correspondingly, multiple probes 102 can be divided into multiple probe groups G. Each probe group G is provided with five probes 102, namely the third probe 1023, the fourth probe 1024, the fifth probe 1025, the sixth probe 1026, and the seventh probe 1027. The third probe 1023, the fourth probe 1024, the fifth probe 1025, the sixth probe 1026, and the seventh probe 1027 in each probe group G can provide input signals, output signals, power signals, clock signals, and reset signals to the input signal terminal 9011, output signal terminal 9012, power signal terminal 9013, clock signal terminal 9014, and reset signal terminal 9015 of each micro-driver chip 901, respectively, so as to test each micro-driver chip 901 in the micro-driver chip array and meet the testing requirements of high-density, large-scale integrated micro-driver chip arrays.

[0141] In the test equipment, probe groups G in adjacent columns of the same row can be cascaded. Specifically, the fourth probe 1024 in the current column of probe group G in the same row is connected to the seventh probe 1027 in the previous column of probe group G and the third probe 1023 in the next column of probe group G; each third probe 1023 in the first column of probe group G is connected to the starting test pad STV; each fourth probe 1024 in the last column of probe group G is connected to the output test pad Output through the switching transistor TFT; each fifth probe 1025 in each probe group G is connected to the power test pad VSS; and each sixth probe 1026 in each probe group G is connected to the clock test pad CK.

[0142] During testing, the starting test pad STV, power test pad VSS, clock test pad CK, and corresponding test signal lines 104 can be used to provide input test signals, power test signals, and clock test signals to the third probe 1023, fifth probe 1025, and sixth probe 1026 in each probe group G, respectively, so that the micro-driver chip 901 can work. Since the probe groups G in adjacent columns of the same row can be cascaded, the micro-driver chips 901 in adjacent columns of the same row can also be cascaded. The output signal of this column can be used as the reset signal of the previous column to provide a reset test signal for the seventh probe 1027. At the same time, the output signal transmitted by the output test pad Output connected to the fourth probe 1024 in the last column of probe group G can be detected to test whether the micro-driver chips 901 in each row are normal. This significantly reduces the number of independent test signal lines 104 required between adjacent probes 102, reserving more space for each probe 102. This not only optimizes the signal transmission path and reduces circuit complexity, but also effectively reduces the possibility of mutual interference between different test signal lines 104, thereby helping to improve the testing efficiency and accuracy of the testing equipment.

[0143] Each fourth probe 1024 in the last column probe group G is connected to the output test pad Output via a switching transistor TFT. With the help of an external scanning drive circuit, the switching transistor TFT is turned on and off row by row through the corresponding switching signal line 106 to control the conduction and disconnection between the fourth probe 1024 in the last column probe group G and the output test pad Output, so as to test the micro-driver chip 901 in each row.

[0144] Figure 11 is a schematic diagram of another test device provided in an embodiment of this disclosure. As shown in Figure 11, multiple probes 102 are divided into multiple probe groups G, each corresponding to a micro-driver chip 901. Each probe group G is provided with a third probe 1023, a fourth probe 1024, a fifth probe 1025, a sixth probe 1026, and a seventh probe 1027, each corresponding to an input signal terminal 9011, an output signal terminal 9012, a power signal terminal 9013, a clock signal terminal 9014, and a reset signal terminal 9015 of the micro-driver chip 901. (The last sentence appears to be incomplete and possibly refers to a different configuration.) The fourth probe 1024 in the probe group G of the middle row is connected to the seventh probe 1027 in the probe group G above and the third probe 1023 in the probe group G below; each of the third probes 1023 in the first probe group G is connected to the starting test pad STV; each of the fourth probes 1024 in the last probe group G is connected to the output test pad Output through the switching transistor TFT; each of the fifth probes 1025 in each probe group G is connected to the power test pad VSS; and each of the sixth probes 1026 in each probe group G is connected to the clock test pad CK.

[0145] The test device shown in Figure 11 differs from the test device shown in Figure 10 in that the probe groups G in adjacent columns of the same row in the test device shown in Figure 10 can be cascaded together. The working process of the test device shown in Figure 11, where probe groups G in adjacent rows of the same column can be cascaded together, is basically the same as that of the test device in Figure 10, and will not be described again here.

[0146] In the actual testing process, the micro-driver chip array can first be tested using the testing equipment shown in Figure 10. This test can quickly identify the specific row location of the faulty chip. Subsequently, the same array is tested again using the testing equipment shown in Figure 11, thereby accurately locating the column location of the faulty chip. Based on the row and column information determined by the two tests, combined with the cross-sectional location method, the specific micro-driver chip 901 in the micro-driver chip array that is faulty can be accurately identified. This step-by-step testing strategy not only significantly reduces the scope of fault diagnosis but also significantly reduces the time and resources required for full inspection. While improving the accuracy of test coverage, it further optimizes the overall testing efficiency and equipment utilization.

[0147] Since relying on an external scanning drive circuit to control the on and off of each switching transistor TFT row by row is costly, the scanning drive circuit can be integrated into the testing equipment.

[0148] In some embodiments, the test device further includes: a scan driving circuit (not shown in the figure); the scan driving circuit is located on the first substrate 101 and disposed on one side of the probe group G along the row direction or on one side of the probe group G along the column direction; the scan driving circuit G is connected to each switch signal line 106 and is configured to provide switch control signals to each switch signal line 106 one by one according to a preset timing sequence.

[0149] The scan drive circuit can sequentially provide switch control signals to each switch signal line 106 according to a preset timing logic, thereby realizing row-by-row or column-by-column selection and testing. The scan drive circuit can be directly integrated on the first substrate 101 of the test equipment, which not only helps to simplify the overall structure of the test equipment and reduce the number of external connections and components, but also significantly reduces the assembly and manufacturing costs of the test equipment, improves the compactness and reliability of the test equipment, and thus reduces test costs while ensuring test accuracy.

[0150] Figure 12 is a schematic diagram of a scan driving circuit provided in an embodiment of this disclosure. As shown in Figure 12, the scan driving circuit includes multiple shift registers (G0 to G3). Figure 13 is a schematic diagram of the shift register in the scan driving circuit shown in Figure 12. As shown in Figure 13, the shift register includes an input sub-circuit 1301, a reset sub-circuit 1302, and an output sub-circuit 1303. The input sub-circuit 1301 is configured to control the voltage of the pull-up node PU in response to an input signal. The reset sub-circuit 1302 is configured to reset the voltage of the pull-up node PU in response to a reset signal using a power supply signal. The output sub-circuit 1303 is configured to output a clock signal in response to the voltage of the pull-up node PU, or output a power supply signal in response to a reset signal.

[0151] Specifically, the input sub-circuit 1301 includes a first transistor M1; the reset sub-circuit 1302 includes a second transistor M2; and the output sub-circuit 1303 includes a third transistor M3, a storage capacitor C, and a fourth transistor M4. The gate and first electrode of the first transistor M1 are connected to the input signal line Input, and the second electrode is connected to the pull-up node PU. The gate of the second transistor M2 is connected to the reset signal line Reset, the first electrode is connected to the power signal line VSS, and the second electrode is connected to the pull-up node PU. The gate of the third transistor M3 is connected to the pull-up node PU, the first electrode is connected to the clock signal line CLK, and the second electrode is connected to the output signal line Output(N). One end of the storage capacitor C is connected to the pull-up node PU, and the other end is connected to the output signal line Output(N). The gate of the fourth transistor M4 is connected to the reset signal line Reset, the first electrode is connected to the power signal line, and the second electrode is connected to the output signal line Output(N). The input signal line Input in this stage shift register is connected to the output signal line Output(N-1) in the previous stage shift register; the reset signal line Reset in this stage shift register is connected to the output signal line Output(N+1) in the next stage shift register.

[0152] When the input signal is high, the voltage of the pull-up node PU is pulled high, and the third transistor M3 is turned on under the control of the pull-up node PU to output the clock signal. When the reset signal is high, the voltage of the pull-up node PU is pulled low, and the fourth transistor M4 is turned on under the control of the reset signal to output the power signal.

[0153] Thirdly, this disclosure provides a method for preparing a probe assembly, which is used to prepare a probe assembly as provided in any of the above embodiments. Figure 14 is a schematic flowchart of a method for preparing a probe assembly provided in this disclosure. As shown in Figure 14, the method for preparing a probe assembly includes the following steps S601 to S603.

[0154] S601, a plurality of probes are formed on the first substrate to form a probe unit.

[0155] S602, multiple elastic support structures are formed on the second substrate to form support units.

[0156] S603, the probe unit and the support unit are bonded together to form a probe assembly; the orthographic projection of the probe on the second substrate at least partially overlaps with the orthographic projection of the elastic support structure on the second substrate.

[0157] Figure 15 is a schematic flowchart of a probe unit fabrication method. Figures 16a to 16h are schematic diagrams of intermediate structures during the probe unit fabrication process. The fabrication process of the probe unit will be described in further detail below with reference to Figures 15, 16a to 16h.

[0158] As shown in Figure 15, step S601 above forms a plurality of probes on the first substrate to form a probe unit, specifically including steps S6011 to S6017 below.

[0159] S6011, a first substrate is formed on a support substrate.

[0160] As shown in Figure 16a, the support substrate 100 can be made of rigid materials such as glass, which can support other film layers formed on it. Flexible materials such as polyimide (PI) can be coated on the support substrate 100, and a first substrate 101 can be formed by curing processes such as heating and baking.

[0161] S6012 uses a patterning process to form a probe base and a test signal line on a first substrate; the probe base is located on the side of the probe closer to the first substrate; the test signal line is connected to the probe base.

[0162] As shown in Figure 16b, a buffer layer 101a is formed by depositing silicon nitride (SiN) and silicon oxide (SiO) on the first substrate 101 to improve the bonding strength of subsequent film layers. The buffer layer 101a in the bending area is removed by exposure and etching to prevent poor open circuitry during bending. It should be noted that the bending area can be the region where a flexible circuit board needs to be connected and bent.

[0163] As shown in Figure 16c, a metal material layer is deposited on the buffer layer 101a. By exposure and etching, part of the metal material layer is removed to form the probe base 103 and the test signal line 104.

[0164] S6013, using a patterning process, a pattern defining layer is formed on the side of the first substrate away from the support substrate; the pattern defining layer is provided with a plurality of first probe openings.

[0165] As shown in Figure 16d, a photoresist layer is deposited on the film layer where the probe base 103 and the test signal line 104 are located. The photoresist layer is exposed, developed and etched using a mask to form multiple first probe openings at the corresponding positions to form a pattern limiting layer 102a.

[0166] S6014, a seed layer is formed in the area defined by the first probe opening of the pattern defining layer.

[0167] As shown in Figure 16e, copper metal is deposited in the area defined by the first probe opening of the pattern definition layer 102a to form a seed layer 102b.

[0168] S6015, using a patterning process, an insulating layer is formed on the side of the pattern definition layer away from the first substrate; the insulating layer is provided with a plurality of second probe openings; the orthographic projection of the second probe openings on the first substrate at least partially overlaps with the orthographic projection of the first probe openings on the first substrate.

[0169] As shown in Figure 16f, an insulating layer 102c is formed by depositing materials such as silicon nitride (SiN) and silicon oxide (SiO) on the pattern-defined layer 102a. The insulating layer 102c is then exposed, developed, and etched using a mask to form multiple second probe openings at corresponding positions. The second probe openings and the first probe openings at least partially overlap.

[0170] S6016 utilizes an electroplating process to form multiple probes within the area defined by the first probe opening and the second probe opening.

[0171] As shown in Figure 16g, copper metal is electroplated on the seed layer 102b, so that the copper metal grows into a probe 102 with a certain height.

[0172] S6017 removes the insulating layer to expose multiple probes.

[0173] As shown in Figure 16h, the insulating layer 102c is removed, exposing multiple probes 102.

[0174] Figures 17a to 17c are schematic diagrams of the intermediate structure during the fabrication process of the support unit. The fabrication process of the support unit will be described in further detail below with reference to Figures 17a to 17c.

[0175] As shown in Figure 17a, the second substrate 201 can be made of a double-layer structure, one layer being a glass substrate and the other layer being a PI substrate. Flexible materials such as polyimide (PI) can be coated on the glass substrate, and the second substrate 201 can be formed by curing processes such as heating and baking.

[0176] As shown in Figure 17b, a photoresist layer 201a is deposited on the second substrate 201 to increase the adhesion performance of other films on the second substrate 201.

[0177] As shown in Figure 17c, elastic materials such as polydimethylsiloxane (PDMS) are deposited on the photoresist layer 201a, and multiple elastic support structures 202 are formed through exposure and etching processes.

[0178] Figure 18 is a schematic diagram of the process of bonding the probe unit and the support unit to the box. Figures 19a to 19f are schematic diagrams of the intermediate structure during the bonding process of the probe unit and the support unit to the box. The bonding process of the probe unit and the support unit to the box will be described in further detail below with reference to Figures 18 and 19a to 19f.

[0179] As shown in Figure 18, step S603 above, which involves attaching the probe unit and the support unit to the box to form a probe assembly, specifically includes steps S6031 to S6036.

[0180] S6031, a removable encapsulation layer is formed at the edge of the first substrate.

[0181] As shown in FIG19a, a removable encapsulation layer 301 is formed at the edge of the first substrate 101, and the height of the removable encapsulation layer 301 is higher than the height of the probe 102.

[0182] S6032, a transfer substrate is attached to the side of the detachable encapsulation layer away from the first substrate.

[0183] As shown in FIG19b, the transfer substrate 302 is attached to the first substrate 101 using a removable encapsulation layer 301 to facilitate the transfer of the probe unit 10.

[0184] S6033, peel off the support substrate.

[0185] As shown in Figure 19c, in order to increase the overall flexibility of the probe unit 10, the support substrate 100 can be peeled off, and only the first substrate 101 is used to support the probe 102 on it.

[0186] S6034, an encapsulation layer is formed at the edge of the second substrate.

[0187] As shown in Figure 19d, an encapsulation layer 30 is formed at the edge of the second substrate 201 using adhesive materials such as sealant, epoxy resin, acrylic, silicone, polysulfide, butyl, polyurethane, etc.

[0188] S6035 utilizes a transfer substrate to bond the first substrate and the second substrate together via an encapsulation layer.

[0189] As shown in Figure 19e, the first substrate 101 and the second substrate 201 are bonded together through the encapsulation layer 30 by moving the probe unit 10 using the transfer substrate 302.

[0190] S6036, peel off the transfer substrate and remove the removable encapsulation layer.

[0191] As shown in Figure 19f, the transfer substrate 302 is peeled off and the removable encapsulation layer 301 is removed to complete the bonding of the probe unit 10 and the support unit 20, forming an integral probe assembly.

[0192] It should be noted that the dimensions of layers and regions may be exaggerated in the accompanying drawings for clarity. Furthermore, it is understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or there may be intermediate layers. Additionally, it is understood that when an element or layer is referred to as being "below" another element or layer, it can be directly below the other element, or there may be more than one intermediate layer or element. Furthermore, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or there may be more than one intermediate layer or element. Similar reference numerals throughout indicate similar elements.

[0193] In the several embodiments provided in this disclosure, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the positions of the components shown are only logical functional positions, and in actual implementation, they may be arranged in other positions.

[0194] In this disclosure, the use of terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refers to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of this specification. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0195] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A probe assembly, wherein, The probe assembly includes: a probe unit and a support unit disposed on the housing; the probe unit is disposed on the support unit; The probe unit includes: a first substrate and a plurality of probes located on the first substrate; the support unit includes: a second substrate and a plurality of elastic support structures located on the second substrate. The orthographic projection of the probe on the second substrate at least partially overlaps with the orthographic projection of the elastic support structure on the second substrate.

2. The probe assembly according to claim 1, wherein, The probe unit further includes: a probe base and a test signal line located on the first substrate; The probe base is located on the side of the probe closer to the first substrate; The test signal line is connected to the probe base.

3. The probe assembly according to claim 2, wherein, The probe unit further includes a switching transistor; the switching transistor includes a gate, a gate insulating layer, a semiconductor layer, a first electrode, and a second electrode arranged sequentially along the direction away from the first substrate; the first electrode and the second electrode are arranged in the same layer and are respectively connected to both ends of the semiconductor layer; The second electrode is reused as the probe base.

4. The probe assembly according to claim 3, wherein, The probe unit further includes: a switch signal line located on the first substrate and intersecting with the test signal line; The first electrode is connected to the test signal line; The gate is connected to the switch signal line.

5. The probe assembly according to claim 1, wherein, Each of the aforementioned elastic support structures includes: a first support member and a second support member; The height of the first support member is greater than the height of the second support member.

6. The probe assembly according to claim 1, wherein, The support unit further includes: an auxiliary elastic support structure located between adjacent elastic support structures; The height of the auxiliary elastic support structure is less than the height of the elastic support structure.

7. The probe assembly according to claim 1, wherein, The probe assembly further includes: an encapsulation layer; The encapsulation layer is located between the first substrate and the second substrate, and is disposed around the edges of the first substrate and the second substrate.

8. The probe assembly according to claim 1, wherein, The probe unit further includes: an antioxidant layer; The antioxidant layer is located on the side of the probe opposite to the first substrate.

9. The probe assembly according to claim 1, wherein, The probe has a circular, triangular, quadrilateral, or hexagonal shape in the cross-section parallel to the first substrate.

10. The probe assembly according to claim 1, wherein, The probe has multiple contact electrodes formed on the side opposite to the first substrate; at least some of the contact electrodes have different sizes and heights.

11. A testing device, wherein, The testing equipment includes the probe assembly as described in any one of claims 1 to 10.

12. The testing equipment according to claim 11, wherein, The testing equipment is used to test the array of light-emitting devices; the multiple probes are divided into multiple probe groups that correspond one-to-one with the light-emitting devices; each probe group is provided with a first probe and a second probe that correspond one-to-one with the anode and cathode of the light-emitting device, respectively; The first probe in the same probe group is connected to the anode test pad; The second probes in the same probe group are all connected to the cathode test pads.

13. The testing equipment according to claim 12, wherein, The anode test pad and the cathode test pad are located on opposite sides of the probe group along the column direction.

14. The testing equipment according to claim 12, wherein, The first probe in each probe group is connected to the anode test pad via a switching transistor; The first probe is connected to the second electrode of the switching transistor, the anode test pad is connected to the first electrode of the switching transistor, and the switching signal line is connected to the gate of the switching transistor.

15. The testing apparatus according to claim 14, wherein, The gates of the switching transistors connected to the first probes in the same row of the probe group are all connected to the same switching signal line.

16. The testing apparatus according to claim 11, wherein, The testing equipment is used to test micro-driver chip arrays; The probes are divided into multiple probe groups that correspond one-to-one with the micro-driver chip; each probe group is provided with a third probe, a fourth probe, a fifth probe, a sixth probe, and a seventh probe that correspond one-to-one with the input signal terminal, output signal terminal, power signal terminal, clock signal terminal, and reset signal terminal of the micro-driver chip. In the same row, the fourth probe in the probe group of this column is connected to the seventh probe in the probe group of the previous column and the third probe in the probe group of the next column; Each of the third probes in the first column of the probe group is connected to the starting test pad; each of the fourth probes in the last column of the probe group is connected to the output test pad via a switching transistor. The fifth probe in each of the aforementioned probe groups is connected to the power test pad; The sixth probe in each of the probe groups is connected to the clock test pad.

17. The testing apparatus according to claim 11, wherein, The testing equipment is used to test micro-driver chip arrays; The probes are divided into multiple probe groups that correspond one-to-one with the micro-driver chip; each probe group is provided with a third probe, a fourth probe, a fifth probe, a sixth probe, and a seventh probe that correspond one-to-one with the input signal terminal, output signal terminal, power signal terminal, clock signal terminal, and reset signal terminal of the micro-driver chip. In the same column, the fourth probe in the probe group of this row is connected to the seventh probe in the probe group of the previous row and the third probe in the probe group of the next row; Each of the third probes in the probe group described in the first row is connected to the starting test pad; each of the fourth probes in the probe group described in the last row is connected to the output test pad via a switching transistor. The fifth probe in each of the aforementioned probe groups is connected to the power test pad; The sixth probe in each of the probe groups is connected to the clock test pad.

18. The testing apparatus according to any one of claims 15 to 17, wherein, The testing equipment further includes: a scanning drive circuit; the scanning drive circuit is located on the first substrate and disposed on one side of the probe group along the row direction, or on one side of the probe group along the column direction; The scanning drive circuit is connected to each of the switch signal lines and is configured to provide switch control signals to each of the switch signal lines one by one according to a preset timing sequence.

19. The testing apparatus according to claim 18, wherein, The scan driving circuit includes: multiple shift registers; each shift register includes: an input sub-circuit, a reset sub-circuit, and an output sub-circuit; The input sub-circuit is configured to control the voltage of the pull-up node in response to an input signal; The reset sub-circuit is configured to reset the voltage of the pull-up node using a power supply signal in response to a reset signal. The output sub-circuit is configured to output a clock signal in response to the voltage of the pull-up node, or to output a power signal in response to a reset signal.

20. The testing apparatus according to claim 19, wherein, The input sub-circuit includes a first transistor; the reset sub-circuit includes a second transistor; the output sub-circuit includes a third transistor, a storage capacitor, and a fourth transistor. The gate and first electrode of the first transistor are connected to the input signal line, and the second electrode is connected to the pull-up node; the gate of the second transistor is connected to the reset signal line, the first electrode is connected to the power signal line, and the second electrode is connected to the pull-up node; the gate of the third transistor is connected to the pull-up node, the first electrode is connected to the clock signal line, and the second electrode is connected to the output signal line; one end of the storage capacitor is connected to the pull-up node, and the other end is connected to the output signal line; the gate of the fourth transistor is connected to the reset signal line, the first electrode is connected to the power signal line, and the second electrode is connected to the output signal line.

21. The testing apparatus according to claim 20, wherein, The input signal lines in the shift register described in this stage are connected to the output signal lines in the shift register described in the previous stage. The reset signal line in the shift register of this stage is connected to the output signal line in the shift register of the next stage.

22. A method for preparing a probe assembly, used to prepare the probe assembly as described in any one of claims 1 to 10, wherein, The method for preparing the probe assembly includes: Multiple probes are formed on the first substrate to form a probe unit; Multiple elastic support structures are formed on the second substrate to form support units; The probe unit and the support unit are bonded together to form a probe assembly; the orthographic projection of the probe on the second substrate at least partially overlaps with the orthographic projection of the elastic support structure on the second substrate.

23. The method for preparing the probe assembly according to claim 22, wherein, Multiple probes are formed on a first substrate to form a probe unit, including: A first substrate is formed on a support substrate; Using a patterning process, a pattern defining layer is formed on the side of the first substrate opposite to the supporting substrate; the pattern defining layer is provided with a plurality of first probe openings; A seed layer is formed within the area defined by the first probe opening of the pattern defining layer; Using a patterning process, an insulating layer is formed on the side of the pattern defining layer opposite to the first substrate; the insulating layer is provided with a plurality of second probe openings; the orthographic projection of the second probe openings on the first substrate at least partially overlaps with the orthographic projection of the first probe openings on the first substrate; Multiple probes are formed within the area defined by the first probe opening and the second probe opening using an electroplating process; The insulating layer is removed to expose the plurality of probes.

24. The method for preparing the probe assembly according to claim 23, wherein, Using a patterning process, a pattern defining layer is formed on the side of the first substrate opposite to the supporting substrate, and prior to this, the process further includes: Using a patterning process, a probe base and a test signal line are formed on the first substrate; the probe base is located on the side of the probe closer to the first substrate; the test signal line is connected to the probe base.

25. The method for preparing the probe assembly according to claim 23, wherein, The probe unit and the support unit are bonded together to form a probe assembly, comprising: A removable encapsulation layer is formed at the edge of the first substrate; A transfer substrate is attached to the side of the removable encapsulation layer opposite to the first substrate. Peel off the support substrate; An encapsulation layer is formed at the edge of the second substrate; Using the transfer substrate, the first substrate and the second substrate are bonded together through the encapsulation layer; The transfer substrate is peeled off, and the removable encapsulation layer is removed.

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