Epitaxy method from a nucleation layer

Abstract

The invention relates to an epitaxy method from a nucleation layer. A stack (1) is provided comprising, stacked along a so-called stacking direction (Z), a substrate (10), preferably made of silicon, an insulating layer (20), and a semiconductor-based layer, referred to as a nucleation layer (30). The insulating layer (20) having a portion not covered by the nucleation layer (30), referred to as an exposed portion (25). A roughening of at least a part of the exposed portion (25) of the insulating layer, referred to as a roughened part (26), is then carried out, and then an epitaxy is performed from the nucleation layer (30).

Description

[0001] "Epitaxial process from a nucleation layer"

[0002] TECHNICAL FIELD OF THE INVENTION

[0003] The present invention relates to the fields of microelectronics and optoelectronics. It concerns an epitaxial process using a thin film deposited on a substrate, for example, a thin film of indium phosphide (InP) on a silicon (Si) substrate. The present invention can be used, in particular, for the fabrication of microelectronic or optoelectronic components. Its particularly advantageous applications include high-frequency devices, photonics (3D detection, health monitoring, etc.), and shortwave infrared (SWIR) image sensors.

[0004] STATE OF THE ART

[0005] Components based on III-V materials, particularly indium phosphide (InP), are increasingly used in microelectronics and optoelectronics. They can be manufactured using various processes.

[0006] The current commercial solution involves manufacturing components directly on a bulk InP substrate and then packaging them into chips. In some technology applications, these chips are subsequently transferred to a silicon substrate. A more economically and environmentally friendly approach is to deposit a thin layer of InP onto a silicon wafer, forming an InPOSi substrate, and then grow the components directly on this thin layer. This approach offers numerous advantages. For example, the laser systems fabricated in this way exhibit low-loss evanescent optical coupling with the photonic silicon of the circuits. They can also be manufactured using dense integration to improve chip performance and reduce manufacturing costs.More generally, when this approach is implemented using Smart Cut™ technology, it reduces manufacturing costs. The bulk InP material from which the InP thin layer is derived can be recycled after bonding and separation. Since InP is an expensive material (approximately €700 per 100 mm diameter wafer), material recycling is a significant advantage. Furthermore, by using paved InPOSi structures, it is possible to create much larger substrates, which is not the case with a bulk InP substrate, as these substrates currently have a maximum diameter of 150 mm.

[0007] InPOSi substrates can thus be divided into two categories:

[0008] • InPOSi substrates obtained by full-plate InP transfer (only applicable to small InP bulk substrates, i.e., those with a diameter of 150 mm or less). The substrate thus obtained is illustrated in Figures 1A (top view) and 1B (cross-sectional view). • InPOSi substrates obtained by discontinuous transfer of InP chips from a pseudo-donor substrate. The InP chips typically form a tiling pattern on the Si substrate, as illustrated in Figures 2A and 2B.

[0009] In both configurations, the InP film generally does not extend to the very edge of the Si wafer. This is due to the presence of bevels at the periphery of the substrates and is characteristic of layer transfer techniques based on the molecular bonding of substrates (wafer bonding), of which Smart Cut™ technology is a part. As illustrated in Figures 1A, 1B, 2A, and 2B, a dielectric ring 25 with a width on the order of a few millimeters (usually 1 to 3 mm) extends at the periphery. Furthermore, in the case of an InPOSi substrate with InP tiling, the dielectric is also visible between the InP chips.

[0010] During the epitaxial step performed using the InPOSi substrate, the presence of inactive areas at the periphery and possibly between the InP chips can generate a SAG (selective area growth) effect, i.e., selective growth of the epitaxial cells. This is particularly the case with MOCVD (Metal Organic Chemical Vapor Deposition) chemical vapor deposition techniques using metal-organic precursors. Indeed, two precursor diffusion regimes contribute to the variation in the deposition rate: gas-phase diffusion and surface diffusion, represented by arrows labeled 2 and 3 respectively in Figure 3. These diffusion phenomena cause a variation in the growth rate because both diffusions are dependent on the precursor concentration.As a result, the deposited thicknesses are greater in the vicinity of the dielectric zone, thus resulting in an overthickness 45 in the vicinity of this zone (see figure 3).

[0011] It is also noted that vapor-phase diffusion 2 has a diffusion length much greater than surface diffusion 3 (several hundred microns versus a few micrometers). These diffusion lengths depend on the epitaxial conditions (epitaxial temperature, gas flow rate, pressure, etc.), the desired epitaxial stacking (nature of materials, layer thickness, total stacking thickness, etc.), and also the size of the dielectric mask. Thus, although both phenomena are present, they operate at different scales: surface diffusion 3 dominates in the immediate vicinity of the mask, while vapor-phase diffusion 2 becomes predominant as one moves away from the mask.

[0012] In the intended applications, the SAG effect is a drawback. It induces overgrowth of epitaxial growth at the InP edge, and even variations in composition. The use of these areas for manufacturing functional components is not possible, which significantly reduces the wafer's usable surface area. This is exacerbated for tiled structures such as those illustrated in Figures 2A and 2B, where the SAG effect occurs even between the InP chips.

[0013] Moreover, for strong epitaxies, the SAG effect will be amplified and may lead to delaminations, crystalline defects, cracks and / or variations in composition, prohibiting the use of the InPOSi substrate.

[0014] The object of the invention is thus to minimize or even eliminate the SAG effect during epitaxy.

[0015] SUMMARY OF THE INVENTION

[0016] To achieve this objective, a first aspect of the invention relates to an epitaxial process from a nucleation layer comprising the following steps: • providing a stack comprising, stacked along a so-called stacking direction:

[0017] • a support, preferably made of silicon,

[0018] • a layer based on a first electrically insulating material, called the insulating layer, and

[0019] • a layer based on a semiconductor, called the nucleation layer, preferably based on an III-V material, the insulating layer completely separating the nucleation layer from the substrate, the insulating layer having a portion not covered by the nucleation layer, called the exposed portion.

[0020] The process preferably also includes the following steps:

[0021] • to roughen at least part of the exposed portion of the insulating layer, known as the roughened portion,

[0022] • perform an epitaxy from the nucleation layer.

[0023] Rugosification is configured to promote nucleation at the rugosified zone during epitaxy and thus reduce a selective growth effect of epitaxy between the nucleation layer and the exposed portion of the insulating layer.

[0024] The roughened part is located at the level of the crown, at the edge of the wafer, and possibly, in the case of a stack obtained by transferring semiconductor chips, between these chips.

[0025] Roughening the roughened area allows for greater nucleation in that zone. By promoting this nucleation, growth during the epitaxial stage is homogenized, both in terms of thickness and composition of the epitaxial layer. The epitaxial layer thus exhibits a less pronounced increase in thickness than in the previous stage, or even a virtually constant thickness. Furthermore, the composition of the epitaxial layer shows less variation. The SAG effect is therefore reduced.

[0026] Thanks to the process according to the invention, unusable areas for the production of devices are thus reduced or even eliminated.

[0027] A second aspect of the invention relates to a stacking comprising, stacked according to a so-called stacking direction:

[0028] • a support, preferably made of silicon,

[0029] • a layer based on a first electrically insulating material, called the insulating layer, the insulating layer having a portion, called the roughened part, having an RMS roughness greater than or equal to 0.30 nm, preferably greater than or equal to 0.40 nm

[0030] • a semiconductor-based layer, called the nucleation layer, preferably based on an III-V material, with the insulating layer completely separating the nucleation layer from the substrate,

[0031] • a layer based on an epitaxial semiconductor, called the epitaxial layer, extending above the nucleation layer and the roughened portion. The advantages described with reference to the process according to the first aspect of the invention apply mutatis mutandis to the stacking according to the second aspect of the invention.

[0032] BRIEF DESCRIPTION OF THE FIGURES

[0033] The aims, objects, features and advantages of the invention will become clearer from the detailed description of an embodiment thereof, which is illustrated by the following accompanying drawings in which:

[0034] Figures 1A and 1B represent a substrate obtained by full-plate transfer of a semiconductor thin film onto a support.

[0035] Figures 2A and 2B represent a substrate obtained by transferring a thin semiconductor film in the form of a plurality of chips onto a support.

[0036] Figure 3 illustrates the SAG effect occurring during the epitaxy of a thin film near a dielectric layer.

[0037] Figures 4A to 4E illustrate a first embodiment of the present invention in which the final epitaxy is carried out from a continuous nucleation layer.

[0038] Figures 5A to 5E illustrate a second embodiment of the present invention in which the final epitaxy is carried out from a plurality of nucleation chips that are disjoint from each other.

[0039] Figures 6A to 6C illustrate an example of achieving the roughening of the oxide layer by depositing a rough layer on the insulating layer.

[0040] Figures 7A and 7B illustrate the increase in roughness through the deposition of a rough layer on the insulating layer.

[0041] Figures 8A and 8B illustrate the reduction of the excess thickness of the epitaxial layer near the insulating layer thanks to the prior deposition of a rough layer on the insulating layer.

[0042] Figures 9A and 9B illustrate an example of achieving the roughening of the oxide layer by creating grooves in the latter.

[0043] Figures 10A and 10B are explanatory diagrams illustrating the increase in nucleation at the level of inactive areas and thus the reduction of the SAG effect thanks to the present invention.

[0044] Figures 11 A to 11 C illustrate the roughening of the support and the transfer of roughness to the insulating layer formed on the support.

[0045] The drawings are provided as examples and are not intended to limit the scope of the invention. They are schematic representations of the principle intended to facilitate understanding of the invention and are not necessarily to scale with practical applications. In particular, the dimensions are not representative of reality.

[0046] DETAILED DESCRIPTION OF THE INVENTION

[0047] Before proceeding with a detailed review of embodiments of the invention, optional features that may be used in combination or alternatively are listed below:

[0048] Advantageously, the roughening step is configured to impart an RMS roughness of 0.30 nm or greater to the roughened part, and preferably 0.40 nm or greater. Preferably, the roughening step is configured to impart an RMS roughness of 0.50 nm or greater, preferably 60 nm, preferably 80 nm, or even 1 µm. When the roughening step is implemented using certain methods, such as saw structuring, the roughening step can be configured to impart an even greater RMS roughness to the roughened part, for example, 2 µm or greater, or 3 µm or greater.

[0049] Preferably, in a transverse plane substantially perpendicular to the stacking direction, the roughened part extends from the nucleation layer.

[0050] Advantageously, the roughened portion extends from the nucleation layer over a dimension L26, with L26 s 30 pm, preferably L26 s 40 pm, preferably L26 s 100 pm, for example L26 = 200 pm. L26 can typically be equal to L25, the dimension of the exposed portion.

[0051] Advantageously, the roughened part surrounds the nucleation layer, preferably entirely.

[0052] According to an advantageous example, the nucleation layer is based on an Il lV material, for example InP, GaAs or GaN.

[0053] According to one embodiment, the roughening step includes the formation, in contact with the insulating layer, of a so-called roughening layer based on a second electrically insulating material, preferably identical to the first electrically insulating material.

[0054] According to one example, the formation of the roughening layer includes the following steps:

[0055] • Apply the roughening layer to the stack,

[0056] • Remove, selectively with respect to the nucleation layer, the roughening layer in areas where it covers the nucleation layer, leaving it in place in areas where it directly covers the insulating layer.

[0057] According to an alternative example, the formation of the roughening layer is done using a photolithography process, after masking the nucleation layer.

[0058] In another embodiment, the roughening layer formation is configured so that the roughening layer extends at least partially over the nucleation layer. The roughening layer is then deposited on an area of ​​the nucleation layer extending from the exposed portion of the insulating layer. This allows for better anchoring of the nucleation layer and thus further reduces the risk of delamination during subsequent steps, particularly the epitaxial step.

[0059] As an example, the roughening step also includes the removal of the roughening layer. During the removal of the roughening layer, its roughness is transferred to the exposed portion of the underlying insulation layer. This forms the roughened portion of the insulation layer.

[0060] In one example, the second electrically insulating material is SiU2. In one embodiment, the roughening step includes a surface roughening treatment applied to at least a part of the exposed portion of the insulating layer.

[0061] According to one embodiment, the roughening step includes, in the stack supply step, the following steps:

[0062] • provide support,

[0063] • perform a surface roughening treatment applied to the substrate, then • deposit the insulating layer and the nucleation layer on the substrate.

[0064] As an example, the roughening treatment includes exposure to laser radiation.

[0065] As an example, the roughening treatment includes an ion bombardment step.

[0066] According to one example, the roughening treatment includes at least one of the following treatments: saw structuring, waterjet structuring, milling, chemical etching, plasma etching.

[0067] In one example, the support is silicon-based.

[0068] Selective etching with respect to or etching with selectivity with respect to means an etching process configured to remove a material A or a layer A from a material B or a layer B, and having an etching speed of material A greater than the etching speed of material B. Selectivity is the ratio of the etching speed of material A to the etching speed of material B. The selectivity between A and B is denoted SA:B.

[0069] It is specified that, within the framework of the present invention, the terms "on", "overcomes", "covers", "underlying", "opposite" and their equivalents do not necessarily mean "in contact with". Thus, for example, the depositing, transferring, gluing, assembling or applying a first layer on a second layer does not necessarily mean that the two layers are directly in contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it or by being separated from it by at least one other layer or at least one other element.

[0070] A layer can also be composed of several sub-layers of the same material or of different materials.

[0071] The term "III-V material" refers to a semiconductor composed of one or more elements from columns III and V of the periodic table. Elements in column III include boron, gallium, aluminum, and indium. Column V contains, for example, nitrogen, arsenic, antimony, and phosphorus. The term "II-VI material" refers to a semiconductor composed of one or more elements from columns II and VI of the periodic table, while the term "IV-IV material" refers to a semiconductor composed of at least two elements from column IV of the periodic table.

[0072] A substrate, layer, or device "based" on a material M is understood to be a substrate, layer, or device comprising only that material M, or that material M and possibly other materials, for example, alloying elements, impurities, or dopants. Thus, a material based on a material III-N may comprise a material III-N with added dopants.

[0073] A material is said to be "electrically conductive" when it exhibits an electrical conductivity preferably greater than 10 8 S / m.

[0074] A material is said to be "electrically insulating" when it has a conductivity preferably less than 10' 8 S / m or a resistivity greater than 10 8 Qm

[0075] A coordinate system, preferably orthonormal, comprising the X, Y, and Z axes is shown in Figure 6A. This coordinate system can be applied by extension to the other figures. The direction along the Z axis is typically designated as the Z-stack direction.

[0076] In this patent application, the terms thickness for a layer and height for a structure or device will be preferred. Height is measured perpendicular to the transverse plane XY. Thickness is measured in a direction normal to the principal plane of extension of the layer. Thus, a layer typically has a thickness along the Z-axis when it extends primarily along the transverse plane XY, and a projecting element, such as a trench, has a height along the Z-axis. The relative terms "on," "under," and "below" preferentially refer to positions measured along the Z-axis.

[0077] The terms "approximately", "about", "in the order of" mean "within 10%, preferably within 5%".

[0078] RMS roughness corresponds to the root mean square of the microscopic peaks and troughs measured on a surface. It is classically measured using an atomic force microscope (AFM) over a 1 pm x 1 pm field.

[0079] The process according to the invention will now be described in more detail.

[0080] A first embodiment is illustrated in figures 4A to 4E. This first embodiment uses a substrate obtained by full-plate transfer of a semiconductor layer onto a support.

[0081] The first phase of the process consists of forming a thin semiconductor film on a substrate. This first phase can notably be carried out using a Smart Cut™ process, as illustrated in Figures 4A to 4E and described in detail below.

[0082] A donor substrate 100 with a top face 101 is first provided (Figure 4A). The donor substrate 100 is based on a semiconductor material, for example, from the II-VI, II-IV (typically InP, GaN, or GaAs), or IV-IV materials. A coating 20' based on an electrically insulating material (for example, SiU2), called the dielectric coating 20', can then be deposited on the top face 101 of the donor substrate 100 (Figure 4B). Ion implantation, for example, of hydrogen ions (H+) and / or helium ions, is then carried out in the donor substrate 100 (Figure 4C). As illustrated in Figure 4D, a receiving substrate, also referred to as support 10, is then provided. This is typically a silicon substrate that has undergone thermal oxidation and thus has an oxide coating 20”. The donor substrate 100 is then bonded to the support 10 via the dielectric coating 20' and the oxide coating 20”.This assembly is achieved, for example, by hydrophilic bonding. It is possible to introduce other bonding layers between the dielectric coating 20' and the oxide coating 20”. It is also possible that there may be no intermediate bonding coating or only one of the dielectric coating 20' and the oxide coating 20”, in which case the bonding is achieved respectively between the donor substrate 100 and the oxide coating 20” or between the dielectric coating 20' and the support 10.

[0083] As illustrated by the transition from Figure 4D to Figure 4E, the donor substrate 100 then undergoes annealing, allowing its fracture at the previously performed ion implantation. This fracture leaves only a thin film of semiconductor on the support 10. The remainder of the donor substrate 100 can be retained for a further iteration of the process according to the invention.

[0084] This results in stacking 1, illustrated in Figure 4E, which therefore comprises:

[0085] • Support 10, typically silicon-based,

[0086] • An insulating layer 20 extending between the support 10 and the nucleation layer 30 and formed from a portion of the oxide coating 20” and the dielectric coating 20',

[0087] • A nucleation layer 30, corresponding to the thin film left on the support after fracture of the donor substrate 100.

[0088] As illustrated in Figure 4E, the insulating layer 20 completely separates the nucleation layer 30 and the substrate 10. This is typically achieved by manufacturing, because the oxide coating 20" typically completely covers the bonding face of the substrate 10 (see Figures 4D and 4E) and / or the dielectric coating 20' typically completely covers the top face 101 of the donor substrate 100 (see Figures 4B to 4D).

[0089] The nucleation layer 30 has a thickness e3o measured along the stacking direction Z. e3o is typically less than or equal to 5 pm.

[0090] Alternatively, stack 1 can be obtained using a conventional disassembly technique (not shown). In this variant, the donor substrate 100 is not implanted and then fractured. After bonding to the support 10 via the dielectric coating 20' and optionally the oxide coating 20", the donor substrate 100 undergoes, for example, mechanical thinning by grinding and / or a CMP (chemical-mechanical polishing) step to thin it to the desired thickness e3os. Stack 1 is then obtained.

[0091] Regardless of the method used to obtain the stacking 1, in a completely conventional manner, the nucleation layer 30 has lateral dimensions smaller than those of the insulating layer 20 and the support 10. Thus, in the transverse plane XY, the insulating layer 20 extends beyond the nucleation layer 30. In other words, the insulating layer 20 has a portion 25 not covered by the nucleation layer 30. This portion is called the exposed portion 25. It extends over a dimension L25 from the nucleation layer 30. In the conventional case where the insulating layer 20 and the nucleation layer 30 each have a substantially circular shape in the transverse plane XY, the exposed portion 25 extends radially around the nucleation layer 30 and completely surrounds it. The L25 dimension is then measured radially around the nucleation layer 30.L25 is for example greater than or equal to 500 pm, for example greater than or equal to 1 mm or even 5 mm.

[0092] At this stage, various treatments can be carried out as appropriate (cleaning, heat treatment, CMP, ...) in order to prepare the nucleation layer 30 for epitaxy.

[0093] In the case of the Smart Cut™ process, a CMP step can be performed to remove the fracture zone, i.e. the area at which the ions had been implanted and the fracture of the donor substrate 100 took place.

[0094] The invention provides at this stage for roughening at least part of the exposed portion 25, referred to as the roughened portion 26. The roughening step will be described further.

[0095] A second embodiment is illustrated in Figures 5A to 5E. This second embodiment uses a substrate obtained by transferring a semiconductor layer in the form of a plurality of chips onto a support.

[0096] This second embodiment is particularly advantageous in that it is compatible with supports 10 with a diameter of 200 mm as well as 300 mm.

[0097] First, a pseudo-donor substrate is provided, comprising a support 1000 surmounted by a discontinuous donor substrate 100, forming a plurality of donor chips 150 (Figure 5A). The discontinuous donor substrate 100, and therefore the donor chips 150, are based on a semiconductor material, for example, taken from materials II-VI, III-V (typically InP), or IV-IV.

[0098] A coating 20' based on an electrically insulating material (e.g., SiO2), called the dielectric coating 20', can then be deposited onto the donor chips 150 (Figure 5B). This coating is optional. In the case of a Smart Cut™ process, ion implantation, for example of hydrogen ions H+ and / or helium ions, is then carried out in the donor substrate 100 (Figure 5C). As illustrated in Figure 5D, a receiving substrate, also referred to as the support 10, is then provided. As in the first embodiment, this is typically a silicon substrate, possibly coated with an oxide coating 20". The donor chips 150 are then bonded to the support 1000 via the dielectric coating 20' and the oxide coating 20". This bonding is achieved, for example, by hydrophilic bonding. It is possible to introduce other bonding layers, for example between the dielectric coating 20' and the oxide coating 20”.

[0099] As illustrated by the transition from Figure 5D to Figure 5E, the donor chips 150 then undergo thermal annealing, allowing them to fracture at the previously ion-implanted location. This fracture leaves only a thin, discontinuous, semiconducting film on the substrate 10, thus forming a plurality of semiconductor chips. The remaining donor chips 150 can be retained for a further iteration of the process according to the invention.

[0100] This results in the stacking arrangement 1 illustrated in figure 5E, comprising:

[0101] • Support 10, typically silicon-based,

[0102] • An insulating layer 20 extending between the support 10 and the nucleation layer 30 and formed from a portion of the oxide coating 20” and the dielectric coating 20',

[0103] • A nucleation layer 30, corresponding to the discontinuous thin film left on the support after fracture of the donor chips 150. The nucleation layer 30 is thus formed from a plurality of semiconductor chips 35. As illustrated in Figure 5E, the insulating layer 20 completely separates the nucleation layer 30 and the substrate 10. This is typically achieved by manufacturing, since the oxide coating 20" typically completely covers the bonding face of the substrate 10 (see Figures 5D and 5E) and / or the dielectric coating 20' typically completely covers the upper faces of the donor chips 150 (see Figures 5B to 5D).

[0104] Semiconductor chips 35 have a dimension ho. In the case of square-shaped chips in the transverse XY plane, ho corresponds to their side, ho is typically greater than or equal to 0.3 cm, for example approximately equal to 1 cm.

[0105] The semiconductor chips 35 are also spaced at an interchip distance dinter. dj n ter is typically greater than or equal to 100 pm, for example approximately equal to 250 pm.

[0106] As in the first embodiment, alternatively, stack 1 can be obtained by a conventional disassembly technique (not shown). In this variant, the donor chips 150 are not implanted and then fractured. After bonding to the support 10 via the dielectric coating 20' and optionally the oxide coating 20", the donor substrate 100 undergoes mechanical thinning, for example by milling and / or a CMP (chemical-mechanical polishing) step to reduce it to the desired thickness e3o. Stack 1 is then obtained.

[0107] As in the first embodiment, before carrying out an epitaxial step to form an epitaxial layer 40 from the nucleation layer 30, the invention provides for carrying out a roughening to limit or even eliminate the SAG effect.

[0108] Several roughening techniques that can be used within the framework of the present invention will now be described with reference to figures 6A to 11C.

[0109] The objective of these various roughening techniques is to form the roughened portion 26 of the insulating layer 30. This roughened portion 26 extends over a dimension L26 from the nucleation layer 30. In the typical case where the insulating layer 20 and the nucleation layer 30 each have a substantially circular shape in the transverse XY plane, the roughened portion 26 extends radially around the nucleation layer 30 and completely surrounds it. The dimension L26 is then measured radially around the nucleation layer 30.

[0110] According to a first example illustrated by Figures 6A to 6C, roughening is achieved by depositing a layer with advantageous roughness, designated the roughening layer 27, onto the exposed portion 25. Figure 6A is an enlargement of Figure 4E or Figure 5E at the level of the exposed portion 25 of the insulating layer 20. Figures 6B and 6C illustrate the formation of the roughening layer 27 on the exposed portion 25. In the figures, the roughening layer 27 is deposited across the entire width of the exposed portion 25, and the roughened portion 26 therefore corresponds to the entire exposed portion 25 (L26 is then equal to L25), but it is understood that the roughening layer can be deposited on only a portion of the exposed portion 25. The roughened portion 26 corresponds in all cases to the portion of the exposed portion 25 covered by the roughening layer 27.

[0111] Furthermore, in the case of a discontinuous nucleation layer 30, the derugosification layer 27 can be deposited at the level of the portions of the insulating layer 20 apparent between the semiconductor chips 35.

[0112] The roughening layer 27 is based on a second electrically insulating material, typically a dielectric material such as SiC>2.

[0113] The roughening layer 27 is advantageously formed by plasma-enhanced chemical vapor deposition (PECVD). The roughening layer 27 can initially be deposited directly onto the exposed portion 25 and onto the nucleation layer 30 (Figure 6B). The portion of the roughening layer 27 covering the nucleation layer 30 can then be removed by an HF deoxidation step (Figure 6C). Since the selectivity of the SiC>2 removal chemistry relative to 1'1 nP is very high, it is advantageous to opt for a SiC>2-based roughening layer 27 when the nucleation layer 30 is InP-based. Good selectivity between the material of the roughening layer 27 and that of the nucleation layer 30 allows the roughening layer 27 to be deposited in a full plate manner and to avoid certain photolithography and etching steps.This reduces the number of steps to be taken and therefore the complexity and cost of the process.

[0114] However, it is also possible to deposit the nucleation layer through a lithography mask so as to deposit it only on the exposed part 25 (transition from figure 6A to figure 6C directly).

[0115] The roughening layer 27 has a thickness 627 measured along the stacking direction Z. When the roughening layer 27 extends only over the exposed part 25, 627 is typically configured so that the rough area of ​​the roughening layer 27 is substantially level with the upper face 31 of the nucleation layer 30.

[0116] It is also possible to retain a portion of the roughening layer 27 deposited on the nucleation layer 30. Typically, the roughening layer 27 then overlaps the nucleation layer 30 over a width of 10 to 30 µm from the exposed portion 25 of the insulating layer 20 (width typically measured radially in the transverse XY plane). Depositing and retaining the roughening layer 27 on a portion of the nucleation layer 30 creates an additional anchoring effect for the nucleation layer 30, which helps to limit or even prevent delamination during subsequent steps, particularly during the epitaxial step. In this particular example, the roughening layer 27 is preferably continuous. Thus, the portion of the roughening layer 27 overlapping the insulating layer 20 and the portion overlapping the nucleation layer 27 are continuous. This allows for better anchoring of the nucleation layer 30.

[0117] The roughening layer 27 thus deposited exhibits a significantly higher roughness than the exposed portion 25, which has generally undergone a CMP step. The roughening layer 27 therefore roughens the exposed portion 25, thereby facilitating nucleation during epitaxy.

[0118] Figures 7A and 7B are reproductions of images obtained by atomic force microscopy (AFM) illustrating the increase in roughness following the PECVD deposition of SiC>2 on the exposed area 25. Figure 7A shows the surface of the exposed area 25 before deposition of the roughening layer 27. The exposed area 25 underwent a CMP step and thus exhibits a very low RMS roughness of 0.15 nm. Figure 7B is centered on the same area, this time after deposition of the roughening layer 27 and deoxidation. The RMS roughness has more than doubled, increasing to 0.41 nm.

[0119] Epitaxy was then performed on these same samples. Figures 8A and 8B, illustrating the results obtained, are images obtained by optical microscopy. It was observed that when epitaxy is performed on a sample without a roughening layer 27 (Figure 8A), the thickness in the vicinity of the insulating layer (14.38 pm) is significantly greater than that observed when a roughening layer 27 is deposited (8.56 pm, Figure 8B). These experimental results demonstrate the reduction of the SAG effect by roughening the exposed area 25.

[0120] According to another example, the roughening layer 27 deposited on the exposed part 25 is removed after its deposition by non-selective etching with respect to the insulating layer 20. The removal etching then allows the roughness of the roughening layer 27 to be transferred to the exposed part 25, thus forming the roughened part 26 directly on the insulating layer 20.

[0121] This embodiment allows, for example, the full-plate deposition and subsequent removal of the roughening layer 27, which, provided that materials with adequate selectivity are selected, eliminates the need for any photolithography step. This reduces the number of steps required and therefore the complexity and cost of the process.

[0122] According to another example, the roughening layer 27 does not have the advantageous roughness when it is deposited but undergoes a surface treatment allowing its roughening after its deposition on the exposed part 25. This surface treatment can be taken from those described below with reference to a directed roughening of the exposed part 25.

[0123] It is possible to roughen the exposed part 25 in other ways. For example, it is possible to carry out a surface treatment that roughens at least part of the exposed part 25, thus forming the roughened part 26.

[0124] Several surface treatments are possible for this purpose.

[0125] As illustrated, a laser treatment is performed on the exposed area 25. In this example, the laser locally melts the first electrically insulating material (typically SiCh), thus roughening the exposed area 25. The laser beam is applied to the exposed area 25 according to a predetermined map, enabling the desired roughening. Advantageously, the laser used is a nanosecond laser.

[0126] In another example, the surface treatment is ion bombardment, for example using localized ion beams. During bombardment, the nucleation layer 30 can be protected by a resin or a hard mask (for example a layer of SiC>2 or SiN) produced by prior photolithography steps.

[0127] In another example, the exposed portion is roughened by a mechanical surface treatment. Possible treatments include sawing, waterjet cutting, and milling. In each of these cases, a series of grooves is formed in the exposed portion 25, typically to a depth of a few tens of micrometers. Figures 9A and 9B are photographs showing the result of roughening an insulating layer 20 by creating grooves 10 µm deep. The grooves can, if necessary, penetrate the entire thickness of the insulating layer 20 or even cut into part of the underlying layer. Figure 9B, in particular, illustrates the area at the edge of the plate, where the substrate 10, the insulating layer 20, and the nucleation layer 30 are visible.

[0128] The exposed area can also be roughened using an etching process, possibly combined with one or more masking steps. For example, networks of dots or lines, or even grids, can be created on the surface of the exposed area. This can involve chemical etching or plasma etching.

[0129] Advantageously, the nucleation layer 30 is protected during any surface treatment, for example by a resin or a hard mask (for example a layer of SiU2 or SiN). Any mask that was used to protect the nucleation layer is then removed by an H F process.

[0130] It is then possible to carry out a CMP or chemical cleaning step to reduce the defect induced by the roughing step by mechanical treatment.

[0131] Samples were roughened by saw structuring, and then epitaxial growth was performed from the nucleation layer. The wafer edges were then analyzed, and the following results were obtained: thanks to saw roughening, the thickness of the epitaxial layer 40 near the insulating layer was reduced from 12 µm to 8.5 µm. This demonstrates a reduction in the SAG effect.

[0132] Figures 10A and 10B are diagrams explaining more precisely the increase in nucleation at the level of the insulating layer due to its roughening.

[0133] Figure 10A illustrates the stack obtained after epitaxy on a prior art stack. It can be seen that the insulating layer 20 is particularly smooth and therefore only allows a very low density of crystals to grow. These two factors result in a high concentration of growth at the edge of the nucleation layer 30.

[0134] Figure 10B illustrates the stack obtained after epitaxy on a stack according to the present invention, which has undergone roughening of the insulating layer 20. This roughening allows for better adhesion and therefore better crystal growth during epitaxy. Furthermore, roughening typically makes the lateral edge of the nucleation layer 30 more abrupt. These two characteristics help to homogenize the thickness of the epitaxial layer.

[0135] The various surface treatments presented above for roughening the exposed part 25 of the insulating layer 20 can be used alone or in combination.

[0136] In an alternative embodiment, the surface roughening treatment is applied to the substrate 10 rather than to the insulating layer 20. Indeed, during the formation of the insulating layer 20 on the substrate 10, the roughness of the substrate 10 is transferred to the insulating layer 20. Figures 11A to 11C illustrate this roughness transfer: Figure 11A shows the substrate 10 alone, Figure 11B the roughening of its upper surface 11, and finally Figure 11C the formation of the insulating layer 20, for example, by oxidation. It can be seen that the upper surface 21 of the insulating layer 20, opposite the upper surface 11 of the substrate 10, is roughened at the points where it overlaps the roughened portions of the substrate 10.

[0137] Thus, surface treatment can, for example, be carried out:

[0138] • in the case of a full plate nucleation layer 30:

[0139] before the support provision step 10 illustrated in Figure 6D, or

[0140] just before the epitaxial stage,

[0141] • in the case of a nucleation layer 30 in the form of a plurality of nucleation chips 150

[0142] before the support provision step 10 illustrated in Figure 7D, or

[0143] just before the epitaxial stage.

[0144] When the roughening of the insulating layer 20 is performed by laser, it is particularly advantageous to carry out this step before the transfer of the semiconductor layer. This increases the process safety level. Furthermore, it has been proven that the topology created by laser structuring is very well transferred from the substrate 10 to the insulating layer 20 during oxidation. Good results have been obtained, for example, by structuring the substrate 10 with a laser with a power of 1.9 J / cm². 2 .

[0145] It appears from the various embodiments described above that the present invention offers an effective solution for reducing the SAG effect. It thus enables the fabrication of high-quality stacks over a larger area, which can be used to manufacture microelectronic and optoelectronic components.

[0146] The invention is not limited to the embodiments previously described and extends to all embodiments covered by the invention.

Claims

DEMANDS 1. Epitaxial process from a nucleation layer comprising the following steps: • provide a stacking (1) comprising, stacked along a so-called stacking direction (Z): a support (10), a layer based on a first electrically insulating material, called the insulating layer (20), and a semiconductor-based layer, called the nucleation layer (30), the insulating layer (20) completely separating the nucleation layer (30) from the substrate (10), the insulating layer (20) having a portion not covered by the nucleation layer (30), called the exposed portion (25), • to roughen at least part of the exposed portion (25) of the insulating layer, referred to as the roughened portion (26), • carry out an epitaxy from the nucleation layer (30), the rugosification being configured to promote during epitaxy nucleation at the rugosified part (26) and thus reduce a selective growth effect of the epitaxy between the nucleation layer (30) and the exposed portion (25) of the insulating layer (20).

2. A method according to the preceding claim in which the roughening step is configured to give the roughened part an RMS roughness greater than or equal to 0.40 nm.

3. A method according to any one of the preceding claims wherein, in a transverse plane (XY) substantially perpendicular to the stacking direction (Z), the roughened part (26) extends from the nucleation layer (30).

4. Method according to the preceding claim in which the roughened part (26) extends from the nucleation layer (30) over a dimension l_26, with l_26 s 30 pm, preferably l_26 s 40 pm, preferably l_26 s 100 pm, for example l_26 = 200 pm.

5. A method according to any one of the preceding claims, wherein the roughened portion (26) surrounds the nucleation layer (30), preferably entirely.

6. A method according to any one of the preceding claims, wherein the nucleation layer is InP-based.

7. A method according to any one of the preceding claims in which the roughening step comprises the formation, in contact with the insulating layer, of a so-called roughening layer (27) based on a second electrically insulating material, preferably identical to the first electrically insulating material.

8. Method according to the preceding claim wherein the formation of the roughening layer (27) is configured so that the roughening layer (27) extends at least partially over the nucleation layer (30).

9. A method according to any one of claims 7 and 8 wherein the second electrically insulating material is SiC>2.

10. A method according to any one of claims 7 to 9 wherein the roughening step further comprises the removal of the roughening layer (27).

11. A method according to any one of claims 1 to 6 wherein the roughening step comprises a surface roughening treatment applied to at least a part of the exposed portion of the insulating layer.

12. A method according to any one of claims 1 to 6, wherein the roughening step comprises, in the stacking supply step, the following steps: • provide support, • perform a surface roughening treatment applied to the substrate, then • deposit the insulating layer and the nucleation layer onto the support.

13. A method according to any one of claims 11 and 12, wherein the roughening treatment comprises exposure to laser radiation.

14. A method according to any one of claims 11 to 13 wherein the roughening treatment comprises an ion bombardment step.

15. A method according to any one of claims 11 to 14 in which the roughening treatment comprises at least one of the following treatments: saw structuring, water jet structuring, milling, chemical etching, plasma etching.

16. A method according to any one of the preceding claims, wherein the support is silicon-based.

17. A stack (1) comprising, stacked along a so-called stacking direction (Z): • a support (10), • a layer based on a first electrically insulating material, called the insulating layer (20), the insulating layer (20) having a portion, called the roughened part (26), having an RMS roughness greater than or equal to 0.40 nm, • a semiconductor-based layer, called the nucleation layer (30), the insulating layer (20) completely separating the nucleation layer (30) from the substrate (10), • a layer based on an epitaxial semiconductor, called the epitaxial layer (40), extending above the nucleation layer (30) and the roughened part (26).

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