System and method for logical core distribution for processing data packets

Abstract

SYSTEM AND METHOD FOR LOGICAL CORE DISTRIBUTION FOR PROCESSING DATA PACKETS 5 Disclosed are a system (200) and a method (500) for logical core distribution for processing data packets received at a Network Interface Card (NIC) (220) of a multi- core processing system (200). The method (500) includes receiving input including a start ID of a logical core among multiple logical cores of processors (230, 232) of the multi-core processing system (200), a number of receive (Rx) queues of the NIC, 10 and a number of stream queues. Further, the method (500) includes determining, based on the number of Rx queues and the number of streaming queues included in the received input, a number of logical cores required for processing the data packets associated with processing tasks to be processed in parallel, and assigning the determined number of logical cores for at least one packet processing task based on 15 a processing overhead associated with the packet processing tasks.

Description

SYSTEM AND METHOD FOR LOGICAL CORE DISTRIBUTION FOR PROCESSING DATA PACKETS TECHNICAL FIELD

[0001] The embodiments of the present disclosure generally relate to the field of communication networks and systems. More particularly, the present disclosure relates to a system and a method for logical core distribution for processing data packets received at a Network Interface Card (NIC) of a multi-core device.BACKGROUND OF THE INVENTION

[0002] The subject matter disclosed in the background section should not be assumed or construed to be prior art merely due to its mention in the background section. Similarly, any problem statement mentioned in the background section or its association with the subject matter of the background section should not be assumed or construed to have been previously recognized in the prior art.

[0003] In the field of telecommunications, with increase in demand for high-speed data communication, the ability to process data packets efficiently is crucial, particularly in environments such as data centers, cloud computing platforms and high-speed networking applications. Packet processing in high-speed network environments involves multiple tasks, such as capturing packets from hardware interfaces, preprocessing data, appending metadata, and distributing packets across processing streams for further analysis. These tasks must often be performed simultaneously, with each requiring variable computational resources based on the volume of incoming packets. To this end, systems for processing the data packets are required to handle a huge volume of data in real time to meet the demands of the networking applications, and ensure seamless communication. The processing of the data packets at such level of performance requires optimal utilization of available Central Processing Unit (CPU) cores, which is a significant challenge.

[0004] Heretofore, existing data processing systems rely on static allocation of the CPU cores i.e., assigning specific cores to handle specific tasks. The static allocation of the CPU cores results in underutilization or overutilization of some CPU cores, leading to wastage of resources, delays, and performance issues. Further, owing to uncontrolled distribution of the CPU cores for packet processing tasks, network administrators struggle to balance the workloads across the cores effectively. This workload imbalance becomes more pronounced in large communication environments with numerous processing units.

[0005] Furthermore, the existing data processing systems require extensive manual intervention and complex configurations to accommodate additional workloads, further adding to unsuitability for dynamic and rapidly evolving network environments. Moreover, the existing data processing systems are not user friendly, and the network administrators are required to manually configure and monitor allocation of the cores using complicated tools and scripts. This manual intervention increases the likelihood of configuration errors and reduces operational efficiency and the delays of such systems.

[0006] Moreover, in network environments where traffic load varies unpredictably, the inability of the existing data processing systems to redistribute tasks among the available cores in real time leads to inefficient resource utilization and degraded system performance. This inflexibility undermines the overall reliability and responsiveness of the system.

[0007] In view of the aforementioned challenges associated with the existing data processing systems, there lies a need for a system and a method using which the distribution of the cores for processing data packets can be performed efficiently.SUMMARY

[0008] The following embodiments present a simplified summary in order to provide a basic understanding of some aspects of the disclosed invention. This summary is not an extensive overview, and it is not intended to identify key / criticalelements or to delineate the scope thereof. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is presented later.

[0009] In an embodiment, a method for logical core distribution for processing data packets in a multi-core system is disclosed. The method comprises obtaining, by a Network Interface Card (NIC) from a network, the data packets associated with a plurality of tasks to be processed in parallel. Further, the method comprises receiving, by an input reception module via a User Interface (UI), an input including an identifier (ID) of a starting logical core among a plurality of logical cores of a plurality of processors of the multi-core system, a number of receive (Rx) queues of the NIC, and a number of streaming queues. Furthermore, the method comprises determining, by one or more processors based on the number of Rx queues and the number of streaming queues included in the received input, a number of logical cores required for processing the obtained data packets. Thereafter, the method comprises assigning, by the one or more processors, the determined number of logical cores for at least one task among the plurality of tasks based on a processing overhead associated with each task.

[0010] In one or more aspects, the plurality of tasks includes one or more of a packet acquisition task, a metadata addition task, a traffic segregation task, a packet streaming task, and a storage unit assignment task for storing streaming packets. The method further comprises setting, by the one or more processors, the starting logical core as a current logical core based on the ID of the starting logical core.

[0011] In one or more aspects, for assigning the determined number of logical cores for the at least one task, the method comprises determining, by the one or more processors for each of the determined number of logical cores, whether a first predefined condition is fulfilled. The first pre-defined condition is fulfilled when a value of the ID of the current logical core is less than a sum of a value of the ID of the starting logical core and the number of Rx queues. Further, based on a determination that the first pre-defined condition is fulfilled, the method comprisesassigning, by the one or more processors, the current logical core for performing the packet acquisition task for a first port of the NIC.

[0012] In one or more aspects, for assigning the determined number of logical cores for the at least one task, the method further comprises determining, by the one or more processors for remaining number of the logical cores among the plurality of logical cores for which the at least one task is yet to be assigned, whether a second pre-defined condition is fulfilled when the first pre-defined condition is unfulfilled. The second pre-defined condition is fulfilled when the value of the ID of the current logical core is less than the sum of the value of the ID of the starting logical core and twice the number of Rx queues. Further, based on a determination that the second pre-defined condition is fulfilled, the method comprises assigning, by the one or more processors, the current logical core for performing the packet acquisition task for a second port of the NIC.

[0013] In one or more aspects, for assigning the determined number of logical cores for the at least one task, the method further comprises determining, by the one or more processors for the remaining number of the logical cores among the plurality of logical cores for which the at least one task is yet to be assigned, whether a third pre-defined condition is fulfilled when the second pre-defined condition is unfulfilled. The third pre-defined condition is fulfilled when the value of the ID of the current logical core is less than the sum of the value of the ID of the starting logical core and thrice the number of Rx queues. Further, based on a determination that the third pre-defined condition is fulfilled, the method comprises assigning, by the one or more processors, the current logical core for performing the metadata addition task.

[0014] In one or more aspects, for assigning the determined number of logical cores for the at least one task, the method further comprises determining, by the one or more processors for the remaining number of the logical cores among the plurality of logical cores for which the at least one task is yet to be assigned, whether a fourth pre-defined condition is fulfilled when the third pre-defined condition is unfulfilled.The fourth pre-defined condition is fulfilled when the value of the ID of the current logical core is less than the sum of the value of the ID of the starting logical core and four times the number of Rx queues. Further, based on a determination that the fourth pre-defined condition is fulfilled, the method comprises assigning, by the one or more processors, the current logical core for performing the traffic segregation task.

[0015] In one or more aspects, for assigning the determined number of logical cores for the at least one task, the method further comprises determining, the one or more processors for the remaining number of the logical cores among the plurality of logical cores for which the at least one task is yet to be assigned, whether a fifth predefined condition is fulfilled when the fourth pre-defined condition is unfulfilled. The fifth pre-defined condition is fulfilled when the value of the ID of the current logical core is less than the sum of the value of the ID of the starting logical core, four times the number of Rx queues, and the number of stream queues. Further, based on a determination that the fifth pre-defined condition is fulfilled, the method comprises assigning, by the one or more processors, the current logical core for performing the packet streaming task.

[0016] In one or more aspects, for assigning the determined number of logical cores for the at least one task, the method further includes determining, for the remaining number of the logical cores among the plurality of logical cores for which the at least one task is yet to be assigned, whether a sixth pre-defined condition is fulfilled when the fifth pre-defined condition is unfulfilled. The sixth pre-defined condition is fulfilled when the value of the ID of the current logical core is less than the sum of the value of the ID of the starting logical core, four times the number of Rx queues, and twice the number of stream queues. Further, based on a determination that the sixth pre-defined condition is fulfilled, the method includes assigning the current logical core for performing the storage unit assignment task.

[0017] In one or more aspects, each of the value of the identifier of the current logical core and the value of the identifier of the starting logical core corresponds to a numeric or integer value of core ID.

[0018] According to another aspect of the present disclosure, a system for logical core distribution for processing data packets is disclosed. The system includes a Network Interface Card (NIC), one or more processors including a plurality of logical cores, and an input reception module. The one or more processors are communicatively coupled to the NIC and the input reception module. The NIC is configured to obtain, from a network, the data packets associated with a plurality of tasks to be processed in parallel. The input reception module is configured to receive, via a User Interface (UI), an input including an identifier (ID) of a starting logical core among the plurality of logical cores, a number of receive (Rx) queues of the NIC, and a number of streaming queues. The one or more processors are configured to determine, based on the number of Rx queues and the number of streaming queues included in the received input, a number of logical cores required for processing the data packets associated with a plurality of tasks to be processed in parallel. Further, the one or more processors are configured to assign the determined number of logical cores for at least one task among the plurality of tasks based on a processing overhead associated with each task.

[0019] According to another aspect of the present disclosure, a computer program product for logical core distribution for processing data packets in a multi-core system is disclosed. The computer program product comprises computer-executable instructions that are stored on a non-transitory computer-readable medium and that, when executed by at least one processor performs operations that comprise obtaining, at a Network Interface Card (NIC) from a network, the data packets associated with a plurality of tasks to be processed in parallel. The operations further comprise receiving, via a User Interface (UI), an input including an identifier (ID) of a starting logical core among a plurality of logical cores of a plurality of processors of the multi-core system, a number of receive (Rx) queues of the NIC, and a number of streaming queues. Furthermore, the operations comprisedetermining, based on the number of Rx queues and the number of streaming queues, a number of logical cores required for processing the obtained data packets. Thereafter, the operations comprise assigning the determined number of logical cores for at least one task among the plurality of tasks based on a processing overhead associated with each task.BRIEF DESCRIPTION OF DRAWINGS

[0020] Various embodiments disclosed herein will become better understood from the following detailed description when read with the accompanying drawings. The accompanying drawings constitute a part of the present disclosure and illustrate certain non-limiting embodiments of inventive concepts. Further, components and elements shown in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present disclosure. For the purpose of consistency and ease of understanding, similar components and elements are annotated by reference numerals in the exemplary drawings.

[0021] FIG. 1 illustrates an example block diagram depicting a network environment for a user device to access a multi-core processing system, in accordance with an embodiment of the present disclosure.

[0022] FIG. 2 illustrates an example diagram of the multi-core processing system, in accordance with an embodiment of the present disclosure.

[0023] FIG. 3 illustrates an example diagram depicting processing of data packets through a network stack of the multi-core processing system, in accordance with an embodiment of the present disclosure.

[0024] FIG. 4 illustrates a process flow depicting operational steps for logical core distribution for processing the data packets, in accordance with an embodiment of the present disclosure.

[0025] FIG. 5 illustrates a flowchart depicting a method for the logical core distribution for processing the data packets, in accordance with an embodiment of the present disclosure.

[0026] FIG. 6 illustrates an exemplary computer system in which or with which embodiments of the present disclosure may be implemented.DETAILED DESCRIPTION OF THE INVENTION

[0027] Inventive concepts of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which examples of one or more embodiments of inventive concepts are shown. Inventive concepts may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Further, the one or more embodiments disclosed herein are provided to describe the inventive concept thoroughly and completely, and to fully convey the scope of each of the present inventive concepts to those skilled in the art. Furthermore, it should be noted that the embodiments disclosed herein are not mutually exclusive concepts. Accordingly, one or more components from one embodiment may be tacitly assumed to be present or used in any other embodiment.

[0028] The following description presents various embodiments of the present disclosure. The embodiments disclosed herein are presented as teaching examples and are not to be construed as limiting the scope of the present disclosure. The present disclosure should in no way be limited to the illustrative implementations, drawings, and techniques illustrated below, including the exemplary design and implementation illustrated and described herein, but may be modified, omitted, or expanded upon without departing from the scope of the present disclosure.

[0029] The following description contains specific information pertaining to embodiments in the present disclosure. The detailed description uses the phrases “in some embodiments” or “some implementations” which may each refer to one or more or all of the same or different embodiments or implementations. The term“some” as used herein is defined as “one, or more than one, or all.” Accordingly, the terms “one,” “more than one,” “more than one, but not all” or “all” would all fall under the definition of “some.” In view of the same, the terms, for example, “in an embodiment” or “in an implementation” refers to one embodiment or one implementation and the term, for example, “in one or more embodiments” refers to “at least one embodiment, or more than one embodiment, or all embodiments ”. Further, the term, for example, “in one or more implementations” refers to “at least one implementation, or more than one implementation, or all implementations.

[0030] The term “comprising,” when utilized, means “including, but not necessarily limited to;” it specifically indicates open-ended inclusion in the so-described one or more listed features, elements in a combination, unless otherwise stated with limiting language. Furthermore, to the extent that the terms “includes,” “has,” “have,” “contains,” and other similar words are used in either the detailed description, such terms are intended to be inclusive in a manner similar to the term “comprising.”

[0031] In the following description, for the purposes of explanation, various specific details are set forth in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent, however, that embodiments of the present disclosure may be practiced without these specific details. Several features described hereafter can each be used independently of one another or with any combination of other features.

[0032] The description provided herein discloses exemplary embodiments only and is not intended to limit the scope, applicability, or configuration of the present disclosure. Rather, the foregoing description of the exemplary embodiments will provide those skilled in the art with an enabling description for implementing any of the exemplary embodiments. Specific details are given in the following description to provide a thorough understanding of the embodiments. However, it may be understood by one of the ordinary skilled in the art that the embodiments disclosed herein may be practiced without these specific details.

[0033] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein the description, the singular forms "a", "an", and "the" include plural forms unless the context of the invention indicates otherwise.

[0034] The terminology and structure employed herein are for describing, teaching, and illuminating some embodiments and their specific features and elements and do not limit, restrict, or reduce the scope of the present disclosure. Accordingly, unless otherwise defined, all terms, and especially any technical and / or scientific terms, used herein may be taken to have the same meaning as commonly understood by one having ordinary skill in the art.

[0035] An object of the present disclosure is to provide a multi-core processing system and a method using which logical core distribution can be performed efficiently for processing data packets received from a network. Another object of the present disclosure is to provide a system and a method that can reduce complexity in management of logical cores for processing the data packets by providing a refined and optimized control to a user of the multi-core processing system. Yet another object of the present disclosure is to provide a system and a method that can ensure optimal distribution processing load across cores of multiple processors of the multi-core processing system.

[0036] The “multi-core processing system” refers to a computing device or a processing device that integrates two or more independent processing cores within a single physical package (such as a CPU). Each processing core is capable of executing instructions and performing computations independently, enabling parallel processing for multi -threaded applications.

[0037] The term “logical core” refers to an addressable execution context within processors (e.g., a CPU core or a hardware thread) identified by a core Identifier (ID). The logical core is used to denote scheduling or assignment granularity for tasks associated with the multi -threaded applications. Each logical core has the coreID in form of a numeric value or an integer value that uniquely references the logical core within the multi-core processing system.

[0038] Further, “Receive (Rx) queue” refers to a queue (or queue pair) on a Network Interface Card (NIC) through which incoming packets are delivered to the host. The number of Rx queues is an input parameter used in pre-defined conditions and in determining the number of logical cores required for performing the tasks associated with the multi -threaded applications.

[0039] The term “streaming queue” refers to a queue construct used for packet streaming operations (e.g., forwarding / transmitting / stream -processing). The number of streaming queues is an input parameter used for determining requirement of the logical cores for performing the packet streaming operations.

[0040] Embodiments of the present disclosure will be described below in detail with reference to the accompanying drawings. FIG. 1 through FIG. 6, discussed below, and the one or more embodiments used to describe the principles of the present disclosure are by way of illustration only and should not be construed in any way to limit the scope of the present disclosure. Those skilled in the art will understand that the principles of the present disclosure may be implemented in any suitably arranged system or device.

[0041] FIG. 1 illustrates an example block diagram depicting a network environment 100 for one or more user devices (102a-102n) to access a multi-core processing system 200, in accordance with an embodiment of the present disclosure. The network environment 100 comprises one or more clients 102a- 102 n (also generally referred to as “local machine(s) 102”, or “user device(s) 102”) in communication with the multi-core processing system 200 (also generally referred to “multi-core device 200”) via one or more networks 104, 104' (generally referred to as “network 104”). In some embodiments, the user device 102 communicates with the multi-core processing system 200 via a gateway 106.

[0042] The user device 102 refers to any endpoint computing apparatus operated directly or indirectly by a user and configured to originate, receive, render, or otherwise interact with data packets that are processed by the multi-core processing system 200 via the network 104 and, in some embodiments, via the gateway 106. In one or more embodiments, the user device 102 may include, but not limited to, a processing circuitry (e.g., CPU, GPU, DSP, embedded controller, SoC, FPGA), a memory / storage (volatile and non-volatile), communication interfaces (wired or wireless, e.g., Ethernet, Wi-Fi, cellular, Bluetooth, optical, or other physical / virtual interfaces) for exchanging the data packets with the network 104, power subsystem (battery, mains, or energy harvesting), and user interface (UI) components.

[0043] Examples of the user device 102 may include, but are not limited to, portable handheld electronic devices such as a mobile phone, a tablet, a laptop, a smart watch etc., or fixed electronic devices such as a desktop computer, a computing device, etc. In some aspects of the present disclosure, the user device 102 may include an application console (not shown) to execute a computer-executable software application (hereinafter interchangeably referred to as ‘computer application’) installed / operated on the user device 102.

[0044] The “UI blocks” shown within user devices 102a, 102b, 102ninFIG. 1 refers to any combination of hardware and / or software elements on the user device 102 that presents information to the user and accepts user inputs, to enable control over applications where the data packets are distributed across multiple logical cores of the multi-core processing system 200.

[0045] The network 104 and / or the network 104' can be a local-area network (LAN), such as a company Intranet, a metropolitan area network (MAN), or a wide area network (WAN), such as the Internet or the World Wide Web. In one embodiment, network 104' may be a private network and network 104 may be a public network. In some embodiments, network 104 may be a private network and network 104' a public network. In another embodiment, networks 104 and 104' may both be private networks. In some embodiments, the user device 102 may be locatedat service provider center of operation and may be communicating via a WAN connection over the network 104 to the multi-core processing system located at a data processing center.

[0046] The network 104 and / or 104' be any type and / or form of network and may include, but not limited to, a point-to-point network, a broadcast network, a wide area network, a local area network, a telecommunications network, a data communication network, a computer network, a wireless network, a wired network, and the like. In some embodiments, the network 104 may comprise a wireless link, such as an infrared channel or satellite band. The topology of the network 104 and / or 104' may be a bus, star, or ring network topology. The network 104 and / or 104' and network topology may be of any such network or network topology as known to those ordinarily skilled in the art capable of supporting the operations described herein.

[0047] The gateway 106 between the networks 104 and 104' may be referred to as an interface unit, and may be located on the network 104. In other embodiments, the gateway 106 may be located on the network 104'. In another embodiment, a plurality of gateways may be deployed on the networks 104 and 104’. In other embodiments, the gateway may be located at any point in the network or network communications path between the user device 102 and the multi-core processing system 200.

[0048] Although FIG. 1 illustrates one example of the network environment 100, where the various networks are shown between the user device 102 and the multi -core processing system 200, the user device 102 and the multi-core processing system 200 may utilize the same network 104.

[0049] FIG. 2 illustrates an example diagram of the multi-core processing system 200, in accordance with an embodiment of the present disclosure. As illustrated in FIG. 1, the multi-core processing system 200 includes a network 210, a Network Interface Card (NIC) 220, one or more processors (230, 232), an input reception module 215, and a system memory 240. The multiple processors (230, 232) are communicatively coupled to the NIC 220 and the input reception module 215.

[0050] The network 210 may be any high-speed network, such as an Ethernet-based Local Area Network (LAN)AVide Area Network (WAN) capable of supporting multiple data packet flows concurrently. The network 210 may transmit data packets from various sources such as user devices, servers, or edge devices. The data packets may represent a wide range of traffic types, including streaming data, control signals, and application specific payloads.

[0051] The NIC 220 is a hardware component configured to establish or form a connection between the multi-core processing system 200 and the network 210. The NIC 220 obtains data packets associated with tasks to be performed in parallel from the network 210 and performs low-level processing, and transfers the data packets after low level processing to the system's memory 240 for further operations. The NIC 220 is connected to each of the processors (230, 232) such that an interrupt is created in the processors (230, 232) for each data packet received from the network 210. The processors (230, 232) are configured to distribute each data packet received from the network 210 to one of the cores 0 through core N based on processor load where the packet is processed until the packets reaches the destination application / services 1 through N.

[0052] Each of the processors (230, 232) includes a plurality of cores (core 0, core 1, ..., core N), optionally the cores 0 through core N within each processor (230, 232) have a shared cache memory (236, 238) as well as each of the cores 0 through core N has its own respective cache memory (mo, Mi, ... , Mn), respectively. The term “core” and “logical core” has the same meaning and are used interchangeably without deviating from the scope of the present disclosure. For symmetric multiprocessing the system memory 240 is shared such that any processor (230, 232) can access any data in system memory 240.

[0053] The input reception module 215 is configured to receive, via the UI, an input including an Identifier (ID) of a starting logical core among the plurality of logical cores, a number of receive (Rx) queues of the NIC 220, and a number of streaming queues.

[0054] Although FIG. 2 illustrates one example of the multi-core processing system 200, various changes may be made to FIG. 2. For example, the multi-core processing system 200 may include any number of processors in any suitable arrangement, without deviating from the scope of the present disclosure. Further, various components in FIG. 2 may be combined, further subdivided, or omitted and additional components may be added according to particular needs.

[0055] FIG. 3 illustrates an example diagram depicting processing of data packets through a network stack 300 of the multi-core processing system 200, in accordance with an embodiment of the present disclosure. As shown in FIG. 3, the NIC 220 includes multiple physical ports (e.g., port 0 and port 1) for redundancy and scalability. Both the ports are bonded together to ensure seamless failover and balanced traffic handling. When one port (port 0) is active and processing incoming data packets (Pi through Pn), the other port (port 1) may remain in standby to provide uninterrupted packet reception in case of failure.

[0056] In an embodiment, when the incoming data packets arrive at the NIC 220, port 0 (active port) may initially handles the incoming data traffic. However, in case of failure or excessive load on the port 0, port 1 may handle the incoming data traffic. Once packets are received through either port 0 or port 1, the data packets are transferred into designated receiving (Rx) queues (Rx 0, Rx 1, ..., Rx N) corresponding to the logical cores (cores 0 through core N) for further processing. Each Rx queue is mapped to a specific processing task or task group among multiple tasks for processing the data packets. The multiple tasks may include, but not limited to, a packet acquisition task, a metadata addition task, a traffic segregation task corresponding to streaming instances, and a storage unit assignment task for storing streaming packets.

[0057] Further, the data packets are segmented into smaller units and are stored in an appropriate Rx queue based on predefined rules, such as, but not limited to, packet type, source address, service priority, and the like. The Rx queues mayoperate in a First-In-First-Out (FIFO) manner to ensure that the packets are processed in order they are received from the network 210.

[0058] In an embodiment, the processors (230, 232) receive, via a user interface, input data including a start Identifier (ID) of a starting logical core (LCORE START ID) among the logical cores 0 through N of the processors (230, 232), a number of Rx queues (NO RX QUEUES) of the NIC 220, and a number of streaming queues (NO STREAM QUEUES). Further, based on the number of Rx queues and the number of streaming queues included in the received input, the processors (230, 232) determines a number of logical cores required for processing the data packets associated with a plurality of tasks to be processed in parallel. In a non-limiting example, the plurality of tasks includes the packet acquisition task, the metadata addition task, the traffic segregation task, the packet streaming task, and the storage unit assignment task for storing streaming packets.

[0059] In one or more embodiments, the packet acquisition task may correspond to operations that bind the logical cores to receive the data packets from the ports or Rx queues of the NIC 220, including dequeuing, basic validation, and hand-off to subsequent tasks. Further, the metadata addition task corresponds to operations that annotate packets with metadata (e.g., timestamps, flow IDs, QoS tags) required for downstream segregation, stream generation, or storage assignments. Furthermore, the traffic segregation task corresponds to operations that classify or route the data packets into flows or service classes (e.g., per Rx queue, per tenant, per policy) to prepare them for streaming operations or storage assignments. The packet streaming task corresponds to operations that stream packets (e.g., forward to egress, publish to streaming processors, or transmit to external endpoints) via streaming queues. Furthermore, the storage unit assignment task corresponds to operations that allocate or assign storage resources (e.g., buffers, files, or database entries) for storing the streaming packets.

[0060] More specifically, the processors (230, 232) determine the number of logical cores based on the number of Rx queues and the number of streaming queues utilizing a predefined calculation criterion. The predefined calculation criterioncomprises multiple predefined conditions for determining the number of logical cores required for performing each processing task.

[0061] In an embodiment, the processors (230, 232) distribute or assign the determined number of logical cores for each of the plurality of tasks, respectively, based on a processing overhead associated with each task. The processing overhead may be referred to a measure (e.g., CPU cycles, latency, throughput impact) representing a computational load of each task. The processing overhead is utilized by the processors (230, 232) to assign the determined number of logical cores to the tasks proportionate to their overhead.

[0062] The processors (230, 232) assign the logical cores for each processing task when a corresponding predefined condition for a corresponding processing task is fulfilled. In a non-limiting example, the processors (230, 232) may assign a set of logical cores dynamically to handle metadata addition based on packet volume when the predefined condition corresponding to the metadata addition task is fulfilled. The addition of metadata may correspond to addition of information such as timestamps, source / destination identification, and processing flags to the data packets in the Rx queues. In another non-limiting example, the processors (230, 232) may distribute another set of logical cores to segregate traffic into multiple streams or groups.

[0063] In an embodiment, the processors (230, 232) may forward the data packets appended with the metadata to multiple streaming instances 1 through N in accordance with hash values. In a non-limiting example, the processors (230, 232) may categorize or segregate the data packets based on their attributes, such as protocol type, priority level, or intended destination, and thereafter may forward the data packets to multiple stream instances 1 through N (as shown in FIG. 3).

[0064] FIG. 4 illustrates a process flow 400 (also referred to as “method 400”) depicting operational steps for logical core distribution for processing the data packets received at the NIC 220 of the multi-core processing system 200, in accordance with an embodiment of the present disclosure. The process flow 400comprises a series of operation steps 402 through 430 performed by the processors (230, 232) of the multi-core processing system 200.

[0065] At step 402, the processors (230, 232) receives, via one of the port 0 or port 1 of the NIC 220, the data packets that are arrived at the multi-core processing system 200 via the network 210.

[0066] At step 404, the processors (230, 232) receive, via the UI of the user device 102, the input data including the start ID of the starting logical core (LCORE_START_ID) of the multi-core processing system 200, the number of Rx queues (NO_RX_QUEUES) of the NIC 220, and the number of streaming queues (NO_STREAM_QUEUES) for logical core distribution to process the received data packets. The input data may be provided by a network administrator or a system operator responsible for configuring the multi-core processing system 200. For example, the administrator may enter values such as LCORE_START_ID = 2, NO_RX_QUEUES = 8, and NO_STREAM_QUEUES = 4 via the UI of the user device 102 to initiate logical core distribution.

[0067] At step 406, the processors (230, 232) start the core distribution processing for distributing the logical cores 0 through N for the received data packets. In particular, the processors (230, 232) calls each logical core among the logical cores 0 through N in a range of LCORE_START_ID to LCORE_END_ID for the core distribution processing. The LCORE_END_ID may be derived or identified using equation (1) as given below:LCORE_END_ID = LCORE_START_ID + 4*NO_RX_QUEUES + 2*NO_STREAM_QUEUES ... (l)The equation as disclosed above is fixed in terms of its structure, however, the resulting value or output varies dynamically based on the input data provided by the network administrator or the system operator. For example, if the administrator changes the number of Rx queues or streaming queues, the computed LCORE END ID will be adjusted accordingly. This ensures flexibility in handling different traffic scenarios while maintaining consistency of the calculation method.

[0068] At step 408, the processors (230, 232) set the starting logical core as a current logical core based on the ID of the starting logical core. Further, at step 408, the processors (230, 232) determine, for each of the logical cores 0 through N, whether a value of the identifier of current logical core is less than a sum of a value of the identifier of starting logical core and the number of Rx queues. For instance, the processors (230, 232) check whether a first pre-defined condition is fulfilled by comparing the value of the identifier of the current logical core with a sum of the value of the identifier of the starting logical core and the number of Rx queues. In a non-limiting example, the value of the identifier of the current logical core and the value of the identifier of the starting logical core corresponds to the numeric or the integer value of the core ID.

[0069] If, at step 408, it is determined that the value of the identifier of the current logical core is less than the sum of the value of the identifier of the starting logical core and the number of Rx queues (i.e., if the first pre-defined condition is fulfilled), then the processors (230, 232) assign the current logical core for performing the packet acquisition task for port 0 (i.e., first port) of the NIC 220 (at step 420). In particular, the first pre-defined condition is fulfilled when the core ID of the current logical core < the core ID of the starting logical core + number of Rx queues.

[0070] Further, if at step 408, it is determined that the value of the identifier of the current logical core is equal to or greater than the sum of the value of the identifier of the starting logical core and the number of Rx queues (i.e., when the first predefined condition is unfulfilled), the flow of the method 400 proceeds to step 410.

[0071] At step 410, the processors (230, 232) determine, for remaining number of the logical cores among the logical cores 0 through N for which any processing task is not assigned or is yet to be assigned, whether the value of the identifier of the current logical core is less than the sum of the value of the identifier of the starting logical core and twice the number of Rx queues (i.e., whether second predefined condition is fulfilled). For instance, if, at step 410, it is determined that the value of the identifier of the current logical core is less than the sum of the value of theidentifier of the starting logical core and twice the number of Rx queues (i.e., determination that the second predefined condition is fulfilled), the processors (230, 232) assign the current logical core for performing the packet acquisition task for port 1 (i.e., second port) of the NIC 220 (at step 422). In particular, the second predefined condition is fulfilled when the core ID (current) < cored ID (starting) + 2 x number_of_Rx_queues.

[0072] Further, if at step 410, if it is determined that the value of the identifier of the current logical core is equal to or greater than the sum of the value of the identifier of the starting logical core and twice the number of Rx queues (i.e., when the second pre-defined condition is unfulfilled), the flow of the method 400 proceeds to step 412.

[0073] At step 412, the multi-core processing system 200 determines, for the remaining number of the logical cores among the logical cores 0 through N for which the at least one task is yet to be assigned, whether the value of the identifier of the current logical core is less than the sum of the value of the identifier of the starting logical core and thrice the number of Rx queues (i.e., whether third predefined condition is fulfilled). If, at step 418, it is determined that the value of the identifier of the current logical core is less than the sum of the value of the identifier of the starting logical core and thrice the number of Rx queues (i.e., determination that the third predefined condition is fulfilled), the processors (230, 232) assign the current logical core to perform addition of the metadata to the data packets stored in the Rx queue (at step 424). In particular, the third predefined condition is fulfilled when the core ID (current) < core ID (starting) + 3 x number_of_Rx_queues .

[0074] Further, if at step 412, it is determined that the value of the identifier of the current logical core is equal to or greater than the sum of the value of the identifier of the starting logical core and thrice the number of Rx queues (i.e., determination that the third predefined condition is unfulfilled), the flow of the method 400 proceeds to step 414.

[0075] At step 414, the processors (230, 232) determine, for the remaining number of the logical cores among the logical cores 0 through N for which the at least one task is yet to be assigned, whether the value of the identifier of the current logical core is less than the sum of the value of the identifier of the starting logical core and four times the number of Rx queues (i.e., whether fourth predefined condition is fulfilled). If, at step 414, it is determined that the value of the identifier of the current logical core is less than the sum of the value of the identifier of the starting logical core and four times the number of Rx queues (i.e., determination that the fourth predefined condition is fulfilled), the processors (230, 232) assign the current logical core for segregating the traffic for the streaming operations (at step 426). In particular, the fourth predefined condition is fulfilled when the core ID (current) < core ID (starting) + 4 x number_of_Rx_queues.

[0076] Further, if at step 414, it is determined that the value of the identifier of the current logical core is equal to or greater than the sum of the value of the identifier of the starting logical core and four times the number of Rx queues (i.e., determination that the fourth predefined condition is unfulfilled), the flow of the method 400 proceeds to step 416.

[0077] At step 416, the processors (230, 232) determines, for the remaining number of the logical cores among the logical cores 0 through N for which the at least one task is yet to be assigned, whether the value of the identifier of the current logical core is less than the sum of the value of the identifier of the starting logical core, four times the number of Rx queues, and the number of stream queues (i.e., whether fifth predefined condition is fulfilled). If, at step 416, it is determined that the value of the identifier of the current logical core is less than the sum of the value of the identifier of the starting logical core, four times the number of Rx queues, and the number of stream queues (i.e., determination that the fifth predefined condition is fulfilled), the processors (230, 232) assign the current logical core for streaming packets for storage (at step 428). In particular, the fifth predefined condition is fulfilled when the core ID (current) < core ID (starting) + 4 x number_of_Rx_queues + number_of_streaming_queues.

[0078] Further, if at step 416, it is determined that the value of the identifier of the current logical core is equal to or greater than the sum of the value of the identifier of the starting logical core, four times the number of Rx queues, and the number of stream queues (i.e., determination that the fifth predefined condition is unfulfilled), the flow of the method 400 proceeds to step 418.

[0079] At step 418, the processors (230, 232) determine, for the remaining number of the logical cores among the logical cores 0 through N for which the at least one task is yet to be assigned, whether the value of the identifier of the current logical core is less than the sum of the value of the identifier of the starting logical core, four times the number of Rx queues, and twice the number of stream queues (i.e., whether sixth predefined condition is fulfilled). If, at step 418, it is determined that the value of the identifier of the current logical core is less than the sum of the value of the identifier of the starting logical core, four times the number of Rx queues, and twice the number of stream queues (i.e., determination that the sixth predefined condition is fulfilled), the processors (230, 232) assign the current logical core for assignment of the storage for streaming packets (at step 430). In particular, the when the core ID (current) < core ID (starting) + 4 x number_of_Rx_queues + 2 x number_of_streaming_queues .

[0080] Further, if at step 418, it is determined that the value of the identifier of the current logical core is not less than the sum of the value of the identifier of the starting logical core, four times the number of Rx queues, and twice the number of stream queues (i.e., determination that the sixth predefined condition is unfulfilled), the method 400 terminates.

[0081] In one or more embodiments, the first predefined condition through the sixth predefined condition as disclosed above is fixed in terms of its structure and does not change across different scenarios, however, the resulting value or the output varies dynamically based on the input data provided by the network administrator or the system operator. This variation occurs because the input parameters such as the number of Rx queues and streaming queues may differ depending on networktraffic conditions or configuration requirements. For example, if the administrator changes the number_of_Rx_queues or number_of_streaming_queues, then the determination whether the condition is fulfilled or unfulfilled will be adjusted accordingly.

[0082] FIG. 5 illustrates a flowchart depicting a method 500 for the logical core distribution for processing the data packets, in accordance with an embodiment of the present disclosure. The method 500 includes a series of operation steps 502 through 510 depicting a simplified process flow.

[0083] At step 502, the processors (230, 232) obtain, via one of the port 0 or port 1 of the NIC 220, the data packets that are arrived at the multi-core processing system 200 via the network 210. The obtained data packets are associated with the tasks such as the packet acquisition, the metadata addition, the traffic segregation, the streaming operation, and the storage assignment which are to be processed in parallel.

[0084] At step 504, the processors (230, 232) receive, via the UI of the user device 102, the input including the start ID of the starting logical core, the number of Rx queues of the NIC 220, and the number of streaming queues for the logical core distribution to process the received data packets.

[0085] At step 506, the processors (230, 232) start the core distribution processing and set the starting logical core as the current logical core based on the ID of the starting logical core.

[0086] At step 508, the processors (230, 232) determine the number of logical cores required for processing the data packets associated with the tasks to be processed in parallel.

[0087] At step 510, the processors (230, 232) assign the determined number of logical cores for at least one task to be processed in parallel based on the processing overhead associated with each task.

[0088] FIG.6 illustrates an exemplary computer system 600 in which or with which embodiments of the present disclosure may be implemented. As shown in FIG. 6, the computer system 600 may include a bus 610, a processing unit 620, a main memory 630, a Read Only Memory (ROM) 640, a storage device 650, an input device 660, an output device 670, and a communication interface 680. The bus 610 may include a path that permits communication among the other components of the computer system 600.

[0089] The processing unit 620 may include one or more processors or microprocessors which may interpret and execute stored instructions associated with one or more processes, or processing logic that implements the one or more processes. For example, the processing unit 620 may include, but is not limited to, programmable logic such as Field Programmable Gate Arrays (FPGAs) or accelerators. The processing unit 620 may include software, hardware, or a combination of software and hardware for executing the processes described herein.

[0090] The main memory 630 may include a random-access memory (RAM) or another type of dynamic storage device that may store information and, in some implementations, instructions for execution by the processing unit 620. The ROM 640 may include a ROM device or another type of static storage device (e.g., Electrically Erasable Programmable ROM (EEPROM)) that may store static information and, in some implementations, instructions for use by the processing unit 620.

[0091] The storage device 650 may include a magnetic, an optical, and / or a solid state (e.g., flash drive) recording medium and its corresponding drive. The main memory 630, the ROM 640 and the storage device 650 may each be referred to herein as a “non-transitory computer-readable medium” or a “non-transitory storage medium”. The process / methods set forth herein can be implemented as instructions that are stored in the main memory 630, the ROM 640 and / or the storage device 650 for execution by the processing unit 620.

[0092] The input device 660 may include one or more devices that permit an operator to input information to the computer system 600, such as, for example, a keypad or a keyboard, a display with a touch sensitive panel, voice recognition and / or biometric mechanisms etc. The output device 670 may include one or more devices that output information to the operator, including a display, a speaker, etc. The input device 660 and the output device 670 may, in some implementations, be implemented as a user interface (UI) that displays UI information and which receives user input via the UI. The communication interface 680 may include one or more transceivers that enable the computer system 600 to communicate with other devices and / or systems. For example, the communication interface 680 may include one or more wired or wireless transceivers for communicating via the network 210.

[0093] The computer system 600 may perform certain operations or processes, as may be described herein. The computer system 600 may perform these operations in response to the processing unit 620 executing software instructions contained in a computer-readable medium, such as the memory 630. The “computer-readable medium” may be defined as a physical or logical memory device. The logical memory device may include memory space within a single physical memory device or spread across multiple physical memory devices. The software instructions may be read into the main memory 630 from another computer-readable medium, such as the storage device 650, or from another device via the communication interface 680. The software instructions contained in the main memory 630 may cause the processing unit 620 to perform the operations or processes, as described herein. Alternatively, hardwired circuitry (e.g., logic hardware) may be used in place of, or in combination with, software instructions to implement the operations or processes, as described herein. Thus, exemplary implementations are not limited to any specific combination of hardware circuitry and software.

[0094] The configuration of components of the computer system 600 illustrated in FIG. 6 is for illustrative purposes only. Other configurations may be implemented.Therefore, the computer system 600 may include additional, fewer, and / or different components, arranged in a different configuration, than depicted in FIG. 6.

[0095] Now, referring to the technical abilities and advantageous effect of the present disclosure, the embodiments disclosed herein provides a solution for dynamically distributing or assigning the logical cores for performing real-time packet processing tasks considering variable processing overhead. As a result, efficient utilization of the logical cores of the multi-core device is ensured and complexity in management of the logical cores for processing the data packets is reduced.

[0096] The above described embodiments can be implemented at a network level of any type of high-speed network system, where ultra-fast packet processing is required to ensure optimal utilization of computational resources.

[0097] Those skilled in the art will appreciate that the methodology described herein in the present disclosure may be carried out in other specific ways than those set forth herein in the above disclosed embodiments without departing from essential characteristics and features of the present invention. The above-described embodiments are therefore to be construed in all aspects as illustrative and not restrictive.

[0098] The drawings and the forgoing description give examples of embodiments. Those skilled in the art will appreciate that one or more of the described elements may well be combined into a single functional element. Alternatively, certain elements may be split into multiple functional elements. Elements from one embodiment may be added to another embodiment. For example, orders of processes described herein may be changed and are not limited to the manner described herein. Any combination of the above features and functionalities may be used in accordance with one or more embodiments.

[0099] In the present disclosure, each of the embodiments has been described with reference to numerous specific details which may vary from embodiment to1embodiment. The foregoing description of the specific embodiments disclosed herein may reveal the general nature of the embodiments herein that others may, by applying current knowledge, readily modify and / or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications are intended to be comprehended within the meaning of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and is not limited in scope.LIST OF REFERENCE NUMERALS

[0100] The following list is provided for convenience and in support of the drawing figures and as part of the text of the specification, which describe innovations by reference to multiple items. Items not listed here may nonetheless be part of a given embodiment. For better legibility of the text, a given reference number is recited near some, but not all, recitations of the referenced item in the text. The same reference number may be used with reference to different examples or different instances of a given item. The list of reference numerals is:100 - Network environment102a, 102b - User Device104 - Network104’ - Network106 - Gateway200 - Multi-core processing system210 - Network215 - Input Reception Module220 - Network Interface Card (NIC)230, 232 - One or more processors236 - Shared Cache Memory238 - Shared Cache memory240 - System Memory300 - Network stack of the multi-core processing system400 - Process flow depicting operational steps for logical core distribution for processing the data packets received at the NIC of the multi-core processing system500 - Flowchart depicting a method 500 for the logical core distribution for processing the data packets600 - Computer System610 - Bus620 - Processing Unit630 - Main Memory640 - ROM650 - Storage Device660 - Input Device670 - Output Device680- Communication Interface

Claims

We claim:

1. A method (500) for logical core distribution for processing data packets in a multi-core system, the method (500) comprising:obtaining, by a Network Interface Card (NIC) (220) from a network (210), the data packets associated with a plurality of tasks to be processed in parallel; receiving, by an input reception module (215) via a User Interface (UI), an input including an Identifier (ID) of a starting logical core among a plurality of logical cores of a plurality of processors of the multi-core system, a number of receive (Rx) queues of the NIC (220), and a number of streaming queues;determining, by one or more processors (230, 232) based on the number of Rx queues and the number of streaming queues, a number of logical cores required for processing the obtained data packets; andassigning, by the one or more processors (230, 232), the determined number of logical cores for at least one task among the plurality of tasks based on a processing overhead associated with each task.

2. The method (500) as claimed in claim 1, whereinthe plurality of tasks includes one or more of a packet acquisition task, a metadata addition task, a traffic segregation task, a packet streaming task, and a storage unit assignment task for storing streaming packets, andthe method (500) comprises setting, by the one or more processors (230, 232), the starting logical core as a current logical core based on the ID of the starting logical core.

3. The method (500) as claimed in claim 2, wherein, for assigning the determined number of logical cores for the at least one task, the method (500) comprises:determining, by the one or more processors (230, 232) for each of the determined number of logical cores, whether a first pre-defined condition is fulfilled, wherein the first pre-defined condition is fulfilled when a value of the IDof the current logical core is less than a sum of a value of the ID of the starting logical core and the number of Rx queues; andassigning, by the one or more processors (230, 232), the current logical core for performing the packet acquisition task for a first port of the NIC 220 based on a determination that the first pre-defined condition is fulfilled.

4. The method (500) as claimed in claim 3, wherein, for assigning the determined number of logical cores for the at least one task, the method (500) comprises:determining, by the one or more processors (230, 232) for remaining number of the logical cores among the plurality of logical cores for which the at least one task is yet to be assigned, whether a second pre-defined condition is fulfilled when the first pre-defined condition is unfulfilled, wherein the second pre-defined condition is fulfilled when the value of the ID of the current logical core is less than the sum of the value of the ID of the starting logical core and twice the number of Rx queues; andassigning, by the one or more processors (230, 232), the current logical core for performing the packet acquisition task for a second port of the NIC (220) based on a determination that the second pre-defined condition is fulfilled.

5. The method (500) as claimed in claim 4, wherein, for assigning the determined number of logical cores for the at least one task, the method (500) comprises:determining, by the one or more processors (230, 232) for the remaining number of the logical cores among the plurality of logical cores for which the at least one task is yet to be assigned, whether a third pre-defined condition is fulfilled when the second pre-defined condition is unfulfilled, wherein the third pre-defined condition is fulfilled when the value of the ID of the current logical core is less than the sum of the value of the ID of the starting logical core and thrice the number of Rx queues; andassigning, by the one or more processors (230, 232), the current logical core for performing the metadata addition task based on a determination that the third pre-defined condition is fulfilled.

6. The method (500) as claimed in claim 5, wherein, for assigning the determined number of logical cores for the at least one task, the method (500) comprises:determining, by the one or more processors (230, 232) for the remaining number of the logical cores among the plurality of logical cores for which the at least one task is yet to be assigned, whether a fourth pre-defined condition is fulfilled when the third pre-defined condition is unfulfilled, wherein the fourth pre-defined condition is fulfilled when the value of the ID of the current logical core is less than the sum of the value of the ID of the starting logical core and four times the number of Rx queues; andassigning, by the one or more processors (230, 232), the current logical core for performing the traffic segregation task based on a determination that the fourth pre-defined condition is fulfilled.

7. The method (500) as claimed in claim 6, wherein, for assigning the determined number of logical cores for the at least one task, the method (500) comprises:determining, by the one or more processors (230, 232) for the remaining number of the logical cores among the plurality of logical cores for which the at least one task is yet to be assigned, whether a fifth pre-defined condition is fulfilled when the fourth pre-defined condition is unfulfilled, wherein the fifth pre-defined condition is fulfilled when the value of the ID of the current logical core is less than the sum of the value of the ID of the starting logical core, four times the number of Rx queues, and the number of stream queues; andassigning, by the one or more processors (230, 232), the current logical core for performing the packet streaming task based on a determination that the fifth predefined condition is fulfilled.

8. The method (500) as claimed in claim 7, wherein, for assigning the determined number of logical cores for the at least one task, the method (500) comprises:determining, by the one or more processors (230, 232) for the remaining number of the logical cores among the plurality of logical cores for which the at least one task is yet to be assigned, whether a sixth pre-defined condition is fulfilled when the fifth pre-defined condition is unfulfilled, wherein the sixth pre-defined condition is fulfilled when the value of the ID of the current logical core is less than the sum of the value of the ID of the starting logical core, four times the number of Rx queues, and twice the number of stream queues; andassigning, by the one or more processors (230, 232), the current logical core for performing the storage unit assignment task based on a determination that the sixth pre-defined condition is fulfilled.

9. The method (500) as claimed in claim 3, wherein each of the value of the identifier of the current logical core and the value of the identifier of the starting logical core corresponds to a numeric value or an integer value of core ID.

10. A system (200) for logical core distribution for processing data packets, the system (200) comprising:a Network Interface Card (NIC) (220) configured to obtain, from a network (210), the data packets associated with a plurality of tasks to be processed in parallel;one or more processors (230, 232) including a plurality of logical cores; and an input reception module (215) configured to receive, via a User Interface (UI), an input including an identifier (ID) of a starting logical core among the plurality of logical cores, a number of receive (Rx) queues of the NIC (220), and a number of streaming queues,wherein the one or more processors (230, 232) are communicatively coupled to the NIC (220) and the input reception module (215), and the one or more processors (230, 232) are configured to:determine, based on the number of Rx queues and the number of streaming queues, a number of logical cores required for processing the obtained data packets; andassign the determined number of logical cores for at least one task among the plurality of tasks based on a processing overhead associated with each task.

11. The system (200) as claimed in claim 10, whereinthe plurality of tasks includes one or more of a packet acquisition task, a metadata addition task, a traffic segregation task, a packet streaming task, and a storage unit assignment task for storing streaming packets, andthe one or more processors (230, 232) are configured to set the starting logical core as a current logical core based on the ID of the starting logical core.

12. The system (200) as claimed in claim 11, wherein, to assign the determined number of logical cores for the at least one task, the one or more processors (230, 232) are configured to:determine, for each of the determined number of logical cores, whether a first pre-defined condition is fulfilled, wherein the first pre-defined condition is fulfilled when a value of the ID of the current logical core is less than a sum of a value of the ID of the starting logical core and the number of Rx queues; and assign the current logical core for performing the packet acquisition task for a first port of the NIC (220) based on a determination that the first pre-defined condition is fulfilled.

13. The system (200) as claimed in claim 12, wherein, to assign the determined number of logical cores for the at least one task, the one or more processors (230, 232) are configured to:determine, for remaining number of the logical cores among the plurality of logical cores for which the at least one task is yet to be assigned, whether a second pre-defined condition is fulfilled when the first pre-defined condition is unfulfilled,wherein the second pre-defined condition is fulfilled when the value of the ID of the current logical core is less than the sum of the value of the ID of the starting logical core and twice the number of Rx queues; andassign the current logical core for performing the packet acquisition task for a second port of the NIC (220) based on a determination that the second pre-defined condition is fulfilled.

14. The system (200) as claimed in claim 13, wherein, to assign the determined number of logical cores for the at least one task, the one or more processors (230, 232) are configured to:determine, for the remaining number of the logical cores among the plurality of logical cores for which the at least one task is yet to be assigned, whether a third pre-defined condition is fulfilled when the second pre-defined condition is unfulfilled, wherein the third pre-defined condition is fulfilled when the value of the ID of the current logical core is less than the sum of the value of the ID of the starting logical core and thrice the number of Rx queues; andassign the current logical core for performing the metadata addition task based on a determination that the third pre-defined condition is fulfilled.

15. The system (200) as claimed in claim 14, wherein, to assign the determined number of logical cores for the at least one task, the one or more processors (230, 232) are configured to:determine, for the remaining number of the logical cores among the plurality of logical cores for which the at least one task is yet to be assigned, whether a fourth pre-defined condition is fulfilled when the third pre-defined condition is unfulfilled, wherein the fourth pre-defined condition is fulfilled when the value of the ID of the current logical core is less than the sum of the value of the ID of the starting logical core and four times the number of Rx queues; andassign the current logical core for performing the traffic segregation task based on a determination that the fourth pre-defined condition is fulfilled.

16. The system (200) as claimed in claim 15, wherein, to assign the determined number of logical cores for the at least one task, the one or more processors (230, 232) are configured to:determine, for the remaining number of the logical cores among the plurality of logical cores for which the at least one task is yet to be assigned, whether a fifth pre-defined condition is fulfilled when the fourth pre-defined condition is unfulfilled, wherein the fifth pre-defined condition is fulfilled when the value of the ID of the current logical core is less than the sum of the value of the ID of the starting logical core, four times the number of Rx queues, and the number of stream queues; andassign the current logical core for performing the packet streaming task based on a determination that the fifth pre-defined condition is fulfilled.

17. The system (200) as claimed in claim 16, wherein, to assign the determined number of logical cores for the at least one task, the one or more processors (230, 232) are configured to:determine, for the remaining number of the logical cores among the plurality of logical cores for which the at least one task is yet to be assigned, whether a sixth pre-defined condition is fulfilled when the fifth pre-defined condition is unfulfilled, wherein the sixth pre-defined condition is fulfilled when the value of the ID of the current logical core is less than the sum of the value of the ID of the starting logical core, four times the number of Rx queues, and twice the number of stream queues; andassigning the current logical core for performing the storage unit assignment task based on a determination that the sixth pre-defined condition is fulfilled.

18. The system (200) as claimed in claim 12, wherein each of the value of the identifier of the current logical core and the value of the identifier of the starting logical core corresponds to a numeric value or an integer value of core ID.

19. A computer program product for logical core distribution for processing data packets in a multi-core system, the computer program product comprisingcomputer-executable instructions that are stored on a non-transitory computer-readable medium and that, when executed by at least one processor performs operations comprising:obtaining, at a Network Interface Card (NIC) from a network, the data packets associated with a plurality of tasks to be processed in parallel;receiving, via a User Interface (UI), an input including an identifier (ID) of a starting logical core among a plurality of logical cores of a plurality of processors of the multi-core system, a number of receive (Rx) queues of the NIC, and a number of streaming queues;determining, based on the number of Rx queues and the number of streaming queues, a number of logical cores required for processing the obtained data packets; andassigning the determined number of logical cores for at least one task among the plurality of tasks based on a processing overhead associated with each task.

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