Method for manufacturing electronic circuit

Abstract

Disclosed is a method for manufacturing an electronic circuit. A method for manufacturing an electronic circuit of the present invention comprises the steps of: forming a first film by laminating a base film and a metal film; forming an electronic circuit pattern having a combination of a plurality of patterns corresponding to a plurality of times of punching with regard to the first film; laminating a removal film on at least one surface to form a second film; and laminating a protective film to form a third film. The step of forming an electronic circuit pattern includes the steps of: forming a first pattern corresponding to at least one part of the plurality of patterns; and forming a second pattern corresponding to at least another part of the plurality of patterns. The step of forming the second film is performed between at least two times of punching among the plurality of times of punching. According to the present invention, it is possible to quickly produce an electronic circuit without environmental pollution because no etching process or the like is included. In addition, it is possible to efficiently produce a microelectronic circuit, which was difficult to manufacture by an existing punching process, regardless of whether an island pattern or the like exists or not.

Description

Method for manufacturing electronic circuits

[0001] The present invention relates to a method for manufacturing electronic circuits that can produce electronic circuits quickly without environmental contamination by not including etching processes, and can efficiently produce micro electronic circuits that were difficult to manufacture using conventional punching processes, regardless of the presence of island patterns, etc.

[0002] Electronic circuits are used in various fields, and in line with the characteristics of electronic products becoming lighter, thinner, shorter, and smaller, electronic circuits are also becoming more sophisticated and miniaturized. In particular, when electronic circuits are used for antenna circuits or frequency filters, the circuit patterns must be configured to correspond to the target frequency response characteristics; furthermore, to transmit and receive high frequencies for the transmission of large amounts of data, electronic circuit patterns are becoming even more fine and complex.

[0003] Etching processes can be used to form increasingly miniaturized and complex electronic circuit patterns. While etching is a method also used in semiconductor production and offers the advantage of achieving high precision, it has disadvantages, such as reduced production efficiency due to the need for a certain amount of time for physicochemical reactions and significant environmental impact from wastewater.

[0004] When producing electronic circuit patterns through a punching process, very rapid product manufacturing is possible. However, forming electronic circuit patterns via punching presents challenges such as difficulty in achieving precision for fine patterns and forming island patterns, making it urgent to resolve these issues.

[0005] The present invention aims to solve the aforementioned problems and other problems. Another objective is to provide a method for manufacturing electronic circuits that can produce electronic circuits quickly without environmental contamination by not including etching processes, and can efficiently produce micro electronic circuits that were difficult to manufacture using conventional punching processes, regardless of the presence of island patterns, etc.

[0006] According to one aspect of the present invention for achieving the above or other purposes, the method comprises: a step of forming a first film by laminating a base film and a metal film; a step of forming an electronic circuit pattern by combining a plurality of patterns corresponding to a plurality of punchings on the first film; a step of forming a second film by laminating a removal film on at least one surface; and a step of forming a third film by laminating a protective film, wherein the step of forming the electronic circuit pattern comprises a step of forming a first pattern corresponding to at least one part of the plurality of patterns and a step of forming a second pattern corresponding to at least another part of the plurality of patterns, and the step of forming the second film may be performed between at least two punchings among the plurality of punchings.

[0007] The above plurality of patterns can be formed side by side with each other.

[0008] The above plurality of patterns can be formed so as not to overlap each other.

[0009] Among the plurality of patterns above, the first and second patterns may be spaced apart from each other.

[0010] The electronic circuit pattern includes an island pattern that is physically separated from another area of ​​the first film by the punching, and the plurality of patterns may correspond to at least one part and at least another part of the island pattern.

[0011] The step of forming the electronic circuit pattern is performed by a press process using a plurality of molds, and at least one of the plurality of molds has irregularities formed corresponding to at least two of the plurality of patterns so that the at least two patterns can be formed simultaneously in one region and another region of the first film.

[0012] The step of forming the electronic circuit pattern can remove areas not corresponding to the electronic circuit pattern from the first film by the plurality of punchings.

[0013] The method may further include the step of supplying the first film in one direction toward a press device forming the electronic circuit pattern.

[0014] According to another aspect of the present invention for achieving the above or other purposes, the method comprises the steps of: supplying a laminated film comprising a metal film; forming an electronic circuit by punching at least one area of ​​the supplied laminated film a plurality of times; and laminating a protective film onto the laminated film having the electronic circuit formed thereon, wherein the step of forming the electronic circuit may be performed by punching at least one of a plurality of mutually adjacent areas at a time different from at least one other to form the electronic circuit.

[0015] The method may further include a step of laminating a removal film between the die-cuts at different points in time as described above.

[0016] The step of laminating the above removal film can be performed when at least a portion of the area forming the electronic circuit is disconnected from at least another portion forming the electronic circuit by the die-cutting at different points in time.

[0017] In the electronic circuit divided line by line, the above plurality of regions may each be a group of non-adjacent lines.

[0018] The effects of the electronic circuit manufacturing method according to the present invention are described as follows.

[0019] According to at least one of the embodiments of the present invention, electronic circuits can be produced quickly without environmental contamination by not including an etching process, and there is an advantage that micro electronic circuits, which were difficult to produce using conventional punching processes, can be produced efficiently regardless of the presence of island patterns, etc.

[0020] Further scopes of the applicability of the present invention will become apparent from the following detailed description. However, since various changes and modifications within the spirit and scope of the present invention are clearly understood by those skilled in the art, specific embodiments, such as the detailed description and preferred embodiments of the present invention, should be understood as being given merely as examples.

[0021] FIG. 1 is a drawing illustrating a method for manufacturing an electronic circuit according to one embodiment of the present invention.

[0022] FIG. 2 is a drawing illustrating an electronic circuit pattern according to an electronic circuit manufacturing method according to one embodiment of the present invention.

[0023] FIG. 3 is a drawing illustrating an electronic circuit pattern according to one embodiment of the present invention.

[0024] FIG. 4 is a drawing illustrating a mold according to one embodiment of the present invention.

[0025] FIG. 5 is a diagram illustrating the process of forming an electronic circuit pattern using a mold according to one embodiment of the present invention.

[0026] FIG. 6 is a drawing illustrating a press mold according to one embodiment of the present invention.

[0027] FIGS. 7 to 13 are drawings illustrating the manufacturing process of an electronic circuit according to one embodiment of the present invention.

[0028] FIG. 14 is a drawing illustrating the shape of a mold according to one embodiment of the present invention.

[0029] Hereinafter, embodiments disclosed in this specification will be described in detail with reference to the attached drawings. Identical or similar components regardless of drawing symbols will be assigned the same reference number, and redundant descriptions thereof will be omitted. The suffixes "module" and "part" used for components in the following description are assigned or used interchangeably solely for the ease of drafting the specification and do not inherently possess distinct meanings or roles. Furthermore, in describing embodiments disclosed in this specification, if it is determined that a detailed description of related prior art could obscure the essence of the embodiments disclosed in this specification, such detailed description will be omitted. Additionally, the attached drawings are intended only to facilitate understanding of the embodiments disclosed in this specification; the technical concept disclosed in this specification is not limited by the attached drawings, and it should be understood that they include all modifications, equivalents, and substitutions that fall within the spirit and technical scope of the present invention.

[0030] Terms including ordinal numbers, such as first, second, etc., may be used to describe various components, but said components are not limited by said terms. These terms are used solely for the purpose of distinguishing one component from another.

[0031] When it is stated that one component is "connected" or "connected" to another component, it should be understood that while it may be directly connected or connected to that other component, there may also be other components in between. On the other hand, when it is stated that one component is "directly connected" or "directly connected" to another component, it should be understood that there are no other components in between.

[0032] A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0033] In this application, terms such as “comprising” or “having” are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0034] FIG. 1 is a drawing illustrating a method for manufacturing an electronic circuit according to one embodiment of the present invention.

[0035] As described herein, the electronic circuit manufacturing method according to one embodiment of the present invention can form an electronic circuit pattern constituting the electronic circuit through punching. When forming an electronic circuit pattern through punching, very fast production can be achieved compared to the case of etching, etc., by using a press process that utilizes a mold having protrusions and indentations corresponding to the electronic circuit pattern.

[0036] As illustrated in FIG. 1(a), the mold (30) may include an upper mold (31) and a lower mold (33). The mold (30) may include a punch (32) corresponding to an electronic circuit pattern. For example, this means that a punch (32) may be formed in the upper mold (31).

[0037] The film (10) can be supplied to the mold (30). The film (10) may include a base film (F1) and a metal film (F2). The base film (F1) may be a resin in the form of a thin film that is a dielectric material. The base film (F1) may be PET. The metal film (F2) may be a metal material such as copper. The metal film (F2) may be copper foil. The metal film (F2) can ultimately form an electronic circuit. That is, it means that an electronic circuit pattern forming an electronic circuit can be formed on the metal film (F2) by performing a process using the mold (30).

[0038] As illustrated in FIG. 1 (b) and (c), processing of the film (10) can be performed by a press process using a mold (30). That is, a punch (32) penetrates the film (10), and a removed area (20) can be formed in which a portion of the film (10) is cut. The area excluding the removed area (20) may remain as a remaining area (40). However, this is the result of a single punch, and the removed area (20) may be increased by subsequent punches.

[0039] FIG. 2 is a drawing illustrating an electronic circuit pattern according to an electronic circuit manufacturing method according to one embodiment of the present invention.

[0040] As described herein, according to the electronic circuit manufacturing method of one embodiment of the present invention, complex and fine electronic circuit patterns can be formed through stamping.

[0041] As shown in FIG. 2(a), when observed in the xy plane, an electronic circuit pattern may be formed on the processed film (10).

[0042] As illustrated in FIG. 2 (b) and (c), if only the metal film (F2) portion is observed, the portion cut by processing can be represented as the removed portion (20), and the portion where processing is completed can be represented as the remaining portion (40). However, this is a drawing for convenience of understanding, and the metal film (F2) where processing is completed is not separated from other parts of the film (10).

[0043] The removal section (20) may be a portion of the metal film (F2) from which a portion has been removed by multiple punchings. However, the removal section (20) is not removed in a single form as illustrated. That is, since multiple punchings proceed sequentially and a portion of the metal film (F2) is cut and detached little by little, the entire removal section (20) does not form a single intact shape. That is, Figure 2 (b) is a drawing for ease of understanding, and the removal section (20) may be in the form of metal scraps cut by multiple punchings.

[0044] The remaining portion (40) may be a metal film (F2) region that remains even after multiple punching operations. The remaining portion (40) may be an electronic circuit pattern of an electronic circuit. The remaining portion (40), which is an electronic circuit pattern, may include an island pattern (42).

[0045] The island pattern (42) may be an area where a specific pattern is not connected to another part of the metal film (F2). In other words, the island pattern (42) may be an area that is not physically connected to another part of the film (10). In other words, the island pattern (42) may refer to a residual part (40) isolated by the removal part (20). In other words, the island pattern (42) may be an area disconnected from another part forming an electronic circuit.

[0046] The island pattern (42) may not remain on the metal film (F2) after processing is completed in the case of conventional press processing. That is, it means that it cannot be physically connected to the surrounding residual part (40) and can be removed during the stamping process by press processing. According to the processing method according to one embodiment of the present invention, the island pattern (42) can also remain as a residual part (40) and form a complete electronic circuit pattern.

[0047] FIG. 3 is a drawing illustrating an electronic circuit pattern according to one embodiment of the present invention.

[0048] As described above, the island pattern (42) may refer to a residual portion (40) that is not connected to the surroundings and is surrounded by the removal portion (20). Because it is not connected to the surroundings, it may not remain as a residual portion (40) under normal punching. That is, it means that the island pattern (42) can be detached from the film (10) at the moment punching is performed on the removal portion (20) surrounding the island pattern (42). According to the method for manufacturing an electronic circuit according to one embodiment of the present invention, an electronic circuit pattern including the island pattern (42) can be formed more effectively.

[0049] FIG. 4 is a drawing illustrating a mold according to one embodiment of the present invention.

[0050] As described herein, a mold (30) according to one embodiment of the present invention may include a plurality of molds (30a to 30d). For example, this means that the mold (30) may include a first mold (30a), a second mold (30b), a third mold (30c), and a fourth mold (30d). Hereinafter, for the convenience of understanding, the case where the number of molds (30) is four will be described, but the number of molds (30) is not limited thereto. That is, it means that if there are a plurality of molds (30), it may fall within the scope of the present invention.

[0051] The first to fourth molds (30a to 30d) may include protrusions (32a to 32d). The protrusions (32a to 32d) may function as a punch (32 in FIG. 1). That is, this means that a portion of the film (10 in FIG. 1) can be removed by the protrusions (32a to 32d).

[0052] In the first to fourth molds (30a to 30d), first to fourth irregularities (32a to 32d) may be formed. Each of the first to fourth irregularities (32a to 32d) may be a group of irregularities formed with a specific irregularity.

[0053] The first to fourth protrusions (32a to 32d) formed on each of the first to fourth molds (30a to 30d) may differ from one another. For example, the first protrusion (32a) may not overlap with the second to fourth protrusions (32b to 32d). In other words, the first to fourth protrusions (32a to 32d) may not overlap with one another. For example, the first protrusion (32a) may be parallel to the second to fourth protrusions (32b to 32d). In other words, the first to fourth protrusions (32a to 32d) may be parallel to one another. In other words, the first to fourth protrusions (32a to 32d) may be formed line by line. For example, this means that a pattern of the first line is formed by the first protrusion (32a), and a pattern of the second line immediately below the pattern of the first line can be formed by the second protrusion (32b). For example, this means that one electronic circuit pattern can be divided into 54 line areas. A line can mean that protrusions (32a to 32d) of a certain height and / or width are formed parallel to each other. Therefore, it does not necessarily mean a horizontal or vertical direction, and as long as they are parallel to each other, diagonal shapes, concentric circle shapes, wave shapes, zig-zag shapes, etc. are possible.

[0054] The press process is not necessarily performed in the order from the first mold (30a) to the fourth mold (30d). For example, it means that a stamping process can be performed with the first mold (30a) to form a pattern of the first line, and then a line can be skipped to perform a stamping process with the third mold (30c) to form a pattern of the third line. In other words, it means that the press process can be performed in the order of the first mold (30a), the third mold (30c), the second mold (20b), and the fourth mold (30d). To express this differently, it can be said that multiple regions each consist of a line group that is not adjacent to one another.

[0055] The order in which punching is performed may vary depending on the shape of the electronic circuit pattern. For example, if the island pattern is separated when punching is performed with the first mold (30a) and then punching is performed with the second mold (30b), it means that punching can be performed with the third mold (30c) or the fourth mold (30d) after punching is performed with the first mold (30a).

[0056] The first to fourth irregularities (32a to 32d) can collectively form a single electronic circuit pattern. That is, this means that when punching is performed using the first to fourth molds (30a to 30d), a specific portion of the thin film corresponding to each of the first to fourth irregularities (32a to 32d) can be removed. When a portion of the thin film is removed by each, the designed electronic circuit pattern remains on the thin film as a result. According to one embodiment of the present invention, an island pattern (42 in FIG. 3) can be formed more effectively by using different first to fourth irregularities (32a to 32d) in line units, and this will be explained in more detail below.

[0057] FIG. 5 is a diagram illustrating the process of forming an electronic circuit pattern using a mold according to one embodiment of the present invention.

[0058] As described above, according to one embodiment of the present invention, an island pattern (42) can be effectively formed.

[0059] As illustrated in FIG. 5(a), island patterns (42) may exist in specific regions when observed in the xy plane, which is the plane of the film (10). At this time, the island patterns (42) may correspond to the first line (L1) to the fourth line (L4).

[0060] As illustrated in FIG. 5 (b) to (e), the first mold (30a) to the fourth mold (30d) may have first irregularities (32a) to fourth irregularities (32d) formed therein corresponding to the first line (L1) to the fourth line (L4). The first irregularities (32a) to fourth irregularities (32d) may correspond to specific areas of the target pattern. The first irregularities (32a) to fourth irregularities (32d) may correspond to parallel areas that do not overlap each other.

[0061] The first mold (30a) to the fourth mold (30d) may be operated sequentially or in any order. For example, the first mold (30a) to the fourth mold (30d) may be operated in order to perform stamping. For example, stamping may be performed alternately in the order of the first mold (30a), the third mold (30c), the second mold (30b), and the fourth mold (30d). For example, stamping may be performed in the order of the first mold (30a), the fourth mold (30d), the second mold (30b), and the third mold (30c).

[0062] Between the execution of die-cutting using the first mold (30a) to the fourth mold (30d), a step of laminating a removal film may be performed. In other words, this means that a removal film may be laminated between at least two of the multiple die-cuttings. In other words, this means that a removal film may be laminated between die-cuttings at different points in time. In other words, this means that a removal film may be laminated when at least a part of the area forming the electronic circuit is disconnected from at least another part forming the electronic circuit.

[0063] The removable film can be laminated onto the surface of the film (10) in progress. That is, it means that the removable film can be laminated on the xy plane. The laminated removable film can be removed as needed. That is, it means that the existing film and the removable film are not combined into a single film through complete adhesion, but can be laminated in a state where they can be removed by adhesion.

[0064] The removable film can prevent the island pattern (42) from falling off. To understand this, a case can be assumed where punching is performed sequentially from the first mold (30a) to the fourth mold (30c). After punching is performed sequentially from the first mold (30a) to the third mold (30c) and the removal portion (20) corresponding to the first to third lines (L1 to L3) is cut, the removable film can be laminated before punching using the fourth mold (30d). Since the removable film is laminated, even if the removal portion (20) corresponding to the fourth line (L4) is cut using the fourth mold (30d), the island pattern (42) can be maintained without falling off. This point can be clearly understood when considering that when the removal film is not laminated, the island pattern (42) may detach simultaneously with the die-cutting using the fourth mold (30d).

[0065] FIG. 6 is a drawing illustrating a press mold according to one embodiment of the present invention.

[0066] As described herein, a mold (30) according to one embodiment of the present invention may have irregularities (32a to 32d) formed corresponding to at least two of a plurality of patterns. Since irregularities (32a to 32d) corresponding to at least two patterns are formed in a specific mold (30), at least two patterns can be formed simultaneously in one region and another region of the film (10). Accordingly, the production efficiency of the electronic circuit manufacturing method according to one embodiment of the present invention can be improved.

[0067] As illustrated in FIG. 6 (a) and (b), first and second irregularities (32a, 32b) may be formed in the first mold (30a). Third and fourth irregularities (32c, 32d) may be formed in the second mold (30b). At this time, the designed electronic circuit pattern can be completed by a combination of the first to fourth irregularities (32a to 32d).

[0068] The film (10) can be supplied in one direction toward a press device that forms an electronic circuit pattern. In other words, this means that the film (10) can be supplied in the y-direction. In other words, the film (10) wound on a roll is unwound and supplied to the first mold (30a) and the second mold (30b) in the y-direction. For example, the film (10) is supplied in the y-direction, and initially, a pattern can be formed by the first protrusion (32a) of the first mold (30a). The film (10), on which a pattern has been formed by the first protrusion (32a), is moved a certain distance in the y-direction, and a pattern can be formed by the second protrusion (32b). At this time, a pattern can be simultaneously formed by the first protrusion (32a) in a subsequent area of ​​the film (10). A film (10) having a pattern formed by the second irregularity (32b) can be moved a certain distance in the y direction and positioned to correspond to the third irregularity (32c) of the second mold (30b), after which a pattern can be formed by the third irregularity (32c). At this time, a pattern formed by the first and second irregularities (32a, 32b) can be simultaneously formed in a subsequent area of ​​the film (10). A film (10) having a pattern formed by the third irregularity (32c) can be moved a certain distance in the y direction and positioned to correspond to the fourth irregularity (32d), after which a pattern can be formed by the fourth irregularity (32d). At this time, a pattern formed by the first, second, and third irregularities (32a, 32b, 32c) can be simultaneously formed in a subsequent area of ​​the film (10). Since each mold (30a, 30b) has two protrusions formed thereon, only two molds (30a, 30b) are required to form a combination of four divided parts, allowing for more effective formation of electronic circuit patterns.

[0069] FIGS. 7 to 13 are drawings illustrating the manufacturing process of an electronic circuit according to one embodiment of the present invention.

[0070] As illustrated in these drawings, according to the manufacturing process of an electronic circuit according to one embodiment of the present invention, high-precision electronic circuit patterns can be produced quickly and efficiently.

[0071] As illustrated in FIG. 7(a), a base film (F1) separated from a release film (F3) can be supplied by passing through a first roller (R1). The base film (F1) can be laminated with a metal film (F2) by passing through a second roller (R2). The laminated film (10) may be the first film.

[0072] As illustrated in FIG. 7(b), a film (10) in which a base film (F1) and a metal film (F2) are laminated can be supplied to a first mold (30a). The first mold (30a) may include a first upper mold (31a) and a first lower mold (33a). A first protrusion (32a) may be formed on the first upper mold (31a).

[0073] As illustrated in FIG. 8 (a) and (b), when the first upper mold (31a) and the second lower mold (33a) are die closed and then die separated, the first removal portion (20a) and the first remaining portion (40a) can be formed. That is, it means that a part of the film (10) can be removed by the first irregularity (32a).

[0074] As illustrated in FIG. 9, when the film (10) is observed in the xy plane after punching by the first mold (30a), n first removal portions (20a1 to 20an) may be formed parallel to each other. The n first removal portions (20a1 to 20an) may be spaced apart from each other at a certain distance. The n first removal portions (20a1 to 20an) may form a pattern corresponding to a corresponding position in an electronic circuit pattern.

[0075] As illustrated in FIG. 10 (a), a removable film (F4) can be laminated to one side of a film (10) by passing through a third roller (R3). The film (10) laminated with the removable film (F4) may be a second film.

[0076] As illustrated in FIG. 10(b), a film (10) can be supplied between the second upper mold (31b) and the second lower mold (33b) of the second mold (30b). FIG. 10(b) is a drawing illustrating the xz plane at a specific y position. The specific y position may be a position where punching has not yet occurred. In other words, the specific y position may be a different position from the first removal part (20a) by the first mold (30a in FIG. 8). Therefore, the first removal part (20a) may not be observed in the xz plane at that position.

[0077] As illustrated in FIG. 11 (a) and (b), when the second mold (30b) is joined and then separated, a second removal portion (20b) can be formed. That is, it means that the film (10) in the area corresponding to the second irregularity (32b) can be removed.

[0078] As illustrated in FIG. 12, when the film (10) is observed in the xy plane after being processed by the second mold (30b) following the first mold (30a), m second removal portions (20b1 to 20bm) may be formed. That is, it means that n first removal portions (20a1 to 20an) and m second removal portions (20a1 to 20am) may be formed on the film (10).

[0079] Since the removal film (F4) is laminated before punching by the second mold (30b), the island pattern does not detach even when the island pattern is formed by the first and second removal parts (20a, 20b).

[0080] The formation of the removal portion (20) by the mold (30) can be repeated several times. That is, in addition to the two times shown in the drawing, this means that the surface of the film (10) can be processed through punching with different molds (30) until the designed electronic circuit pattern is formed.

[0081] The removable film (F4) can be laminated between die-cutting processes as needed. For example, it can be laminated before each die-cut. For example, it can be laminated before a die-cutting process in which an island pattern is expected to be formed.

[0082] As illustrated in FIG. 13(a), removal portions (20a, 20b) may be formed on the film (10). To clearly illustrate this, FIG. 13 depicts the film (10) in the yz plane. That is, it means that removal portions (20a, 20b) are formed at specific locations in the y direction. Although only the first and second removal portions (20a, 20b) are depicted in the drawing, as previously mentioned, more removal portions (20) may be formed.

[0083] As shown in FIG. 13(b), the release film (F1) can be removed by passing through the fourth roller (R4), and the protective film (F4) can be laminated by passing through the fifth roller (R5). The protective film (F4) is made of PI material and can protect the metal film (F2) on which the electronic circuit pattern is formed.

[0084] As illustrated in FIG. 13 (c), the release film (F3) is removed as it passes through the sixth roller (F6), and the liner film (F5) can be laminated as it passes through the seventh roller (F7). The liner film (F5) can serve to protect the adhesive layer.

[0085] FIG. 14 is a drawing illustrating the shape of a mold according to one embodiment of the present invention.

[0086] As described herein, a mold (30) according to one embodiment of the present invention may include various embodiments comprising irregularities (32) that are parallel to each other.

[0087] As illustrated in FIG. 14 (a), the irregularities (32) may be in a shape that is parallel in the x-direction. For example, this means that the lines may be in the shape of multiple molds (30) that are parallel in the x-direction but do not overlap each other.

[0088] As shown in FIG. 14 (b), the irregularities (32) may be parallel in the y direction.

[0089] As illustrated in FIG. 14 (c), the protrusions (32) may be arranged in a diagonal direction. That is, it means that a completed electronic circuit pattern can be formed using a plurality of molds (30) in which the protrusions acting as punching are formed in a diagonal direction. In this regard, the protrusions (32) may be configured in the form of a plurality of concentric circles that do not overlap each other.

[0090] The foregoing detailed description should not be interpreted restrictively in all respects and should be considered exemplary. The scope of the invention shall be determined by a reasonable interpretation of the appended claims, and all modifications within the equivalent scope of the invention are included within the scope of the invention.

Claims

1. A step of forming a first film by laminating a base film and a metal film; A step of forming an electronic circuit pattern by combining multiple patterns corresponding to multiple punchings on the first film; A step of forming a second film by laminating a removable film on at least one surface; and It includes the step of laminating a protective film to form a third film, The step of forming the above electronic circuit pattern is, The step of forming a first pattern corresponding to at least one part of the plurality of patterns above, and The method includes the step of forming a second pattern corresponding to at least another part of the plurality of patterns above, The step of forming the second film above is, An electronic circuit manufacturing method performed between at least two of the above multiple stampings.

2. In Paragraph 1, The above plurality of patterns are, Method for manufacturing electronic circuits formed side by side.

3. In Paragraph 1, The above plurality of patterns are, A method for manufacturing electronic circuits formed so as not to overlap each other.

4. In Paragraph 1, Among the plurality of patterns above, the first and second patterns are, Method for manufacturing mutually spaced electronic circuits.

5. In Paragraph 1, The above electronic circuit pattern is, It includes an island pattern that is physically separated from other regions of the first film by the above punching, The above plurality of patterns are, A method for manufacturing an electronic circuit corresponding to at least one part and at least another part of the above-mentioned island pattern.

6. In Paragraph 1, The step of forming the above electronic circuit pattern is, It is performed by a press process using multiple molds, and In at least one of the plurality of molds above, A method for manufacturing an electronic circuit in which irregularities corresponding to at least two of the plurality of patterns are formed, thereby simultaneously forming the at least two patterns in one region and another region of the first film.

7. In Paragraph 1, The step of forming the above electronic circuit pattern is, A method for manufacturing an electronic circuit, wherein an area not corresponding to the electronic circuit pattern is removed from the first film by the above multiple stampings.

8. In Paragraph 1, A method for manufacturing an electronic circuit, further comprising the step of supplying the first film in one direction toward a press device that forms the electronic circuit pattern.

9. A step of supplying a laminated film including a metal film; A step of forming an electronic circuit by punching at least one area of ​​the supplied laminated film multiple times; and The method includes the step of laminating a protective film onto a laminated film having the above electronic circuit formed thereon, The step of forming the above electronic circuit is, A method for manufacturing an electronic circuit, wherein at least one of a plurality of mutually adjacent partitioned regions is stamped at a time different from at least one of the others to form the electronic circuit.

10. In Paragraph 9, A method for manufacturing an electronic circuit, further comprising the step of laminating a removable film between the die-cuts at different points in time.

11. In Paragraph 10, The step of laminating the above-mentioned removable film is, A method for manufacturing an electronic circuit performed when at least a portion of the region forming the electronic circuit is disconnected from at least another portion forming the electronic circuit by means of the above-mentioned different timing stamping.

12. In Paragraph 9, The above plurality of regions are, A method for manufacturing an electronic circuit in which, in the above electronic circuit divided line by line, each region is formed by a group of non-adjacent lines.

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