Hyper-scaled static random access memory (SRAM) based on sequential complimentary field-effective transistor (CFET) device architecture

Abstract

Aspects of the present disclosure provide a static random access memory (SRAM) including a plurality of SRAM bit-cells. Each SRAM bit-cell includes a first inverter formed using a first transistor disposed on a first wafer and a second transistor disposed on a second wafer, the first wafer being above the second wafer, a second inverter formed using a third transistor disposed on the first wafer and a fourth transistor disposed on the second wafer, and two pass-gate transistors disposed on the second wafer, wherein each of the first, second, third, fourth, and pass-gate transistors includes one or more nanosheet structures.

Description

231501W001HYPER-SCALED STATIC RANDOM ACCESS MEMORY (SRAM) BASED ON SEQUENTIAL COMPLIMENTARY FIELD -EFFECTIVE TRANSISTOR (CFET) DEVICE ARCHITECTUREFIELD OF THE INVENTION

[0001] The present disclosure relates to semiconductor processing, and, in particular, to a formation of semiconductor cladding layers for source and drain contacts and sidewall metal contacts of a semiconductor device.BACKGROUND

[0002] The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.

[0003] In the manufacture of a semiconductor device (especially on the microscopic scale), various fabrication processes are executed such as film -forming depositions, etch mask creation, patterning, material etching and removal, and dopingtreatments. These processes are performed repeatedly to form desired semiconductor device elements on a substrate. Historically, with microfabrication, transistors have been created in one plane, with wiring / metallization formed above the active device plane, and have thus been characterized as two-dimensional (2D) circuits or 2D fabrication. Scaling efforts have greatly increased the number of transistors per unit area in 2D circuits, yet scaling efforts are running into greater challenges as scaling enters single digit nanometer semiconductor device fabrication nodes. Semiconductor device fabricators have expressed a desire for three-dimensional (3D) semiconductor circuits in which transistors are stacked on top of each other.SUMMARY

[0004] Aspects of the present disclosure provide a static random access memory (SRAM) including a plurality of SRAM bit-cells. Each SRAM bit-cell includes a first inverter formed using a first transistor disposed on a first wafer and a second transistor disposed on a second wafer, the first wafer being above the second wafer, a second inverter formed using a third transistor disposed on the first wafer and a fourth transistor disposed on the second wafer, and231501W001two pass-gate transistors disposed on the second wafer, wherein each of the transistors includes one or more nanosheet structures.

[0005] Aspects of the present disclosure provide a method of forming an SRAM including a plurality of SRAM bit-cells. The method includes forming a first inverter using a first transistor disposed on a first wafer and a second transistor disposed on a second wafer, the first wafer being above the second wafer, forming a second inverter using a third transistor disposed on the first wafer and a fourth transistor disposed on the second wafer, and forming two pass-gate transistors disposed on the second wafer, wherein each of the transistors includes one or more nanosheet structures.

[0006] Note that this summary section does not specify every embodiment and / or incrementally novel aspect of the present disclosure or claimed invention. Instead, this summary only provides a preliminary discussion of different embodiments and corresponding points of novelty. For additional details and / or possible perspectives of the invention and embodiments, the reader is directed to the Detailed Description section and corresponding figures of the present disclosure as further discussed below.BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various embodiments of this disclosure that are proposed as examples will be described in detail with reference to the following figures, wherein like numerals reference like elements, and wherein:

[0008] FIG. 1 shows a schematic of a static random access memory (SRAM) bit-cell according to embodiments of the disclosure;

[0009] FIGS. 2A-2C show an NMOS device tier of a sequential complimentary fieldeffective transistor (CFET) SRAM bit-cell according to embodiments of the disclosure;

[0010] FIG. 3 shows a top view (or a layout representation) of a PMOS device tier of the sequential CFET SRAM bit-cell according to embodiments of the disclosure;

[0011] FIG. 4 shows a cross-sectional view of a formed cross-couple of the sequential CFET SRAM bit-cell according to embodiments of the disclosure;

[0012] FIGS. 5A-5D show tier-to-tier connections at the PMOS device tier of the sequential CFET SRAM bit-cell according to embodiments of the disclosure;

[0013] FIGS. 6A-6C show the M0 layer at the PMOS device tier of the sequential CFET SRAM bit-cell according to embodiments of the disclosure;231501W001

[0014] FIG. 7 shows a top view (or a layout representation) of the Ml layer at the PMOS device tier of the sequential CFET SRAM bit-cell according to embodiments of the disclosure; and

[0015] FIG. 8 is a flow chart of an exemplary process of fabricating a semiconductor device according to some embodiments of the present disclosure.DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does notin itself dictate a relationship between the various embodiments and / or configurations discussed. Further, spatially relative terms, such as “top,” “bottom,” “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0017] The order of discussion of the different steps as described herein has been presented for clarity sake. In general, these steps can be performed in any suitable order. Additionally, although each of the different features, techniques, configurations, etc. herein may be discussed in different places of this disclosure, it is intended that each of the concepts can be executed independently of each other or in combination with each other. Accordingly, the present disclosure can be embodied and viewed in many different ways.

[0018] CFET device architectures can include various integrations such as monolithic CFET integrations, hybrid CFET integrations, and sequential CFET integrations. CFET-based static random access memory (SRAM) bit-cell has been shown to be able to provide231501W001considerable improvement in read speed and significant area scaling benefits compared to logic standard cells, which have struggled to attain significant performance and power benefit over conventional gate-all-around (GAA) device architectures. In the monolithic CFET integrations, n-type metal-oxide-semiconductor (NMOS) and p-type metal-oxide-semiconductor (PMOS) devices are built from a singular superlattice composed of silicon and silicon germanium. This puts some limitations on the overall device in terms of the silicon channel being composed of the same crystal orientation whereas there are benefits to have (100) and (110) silicon orientations used for NMOS and PMOS mobilities, respectively.

[0019] Improvements of the sequential CFET integrations over the monolithic CFET integrations can include, but are not limited to, optimizing the silicon orientations for both the NMOS and PMOS mobilities, incorporating wrap-around contacts and side-wall metal contact metallization to achieve an adequate space within the SRAM bit-cell to allow for larger tier-to-tier connections to reduce the parasitic resistance penalty typically associated with the sequential CFET integrations. These concepts allow for the sequential CFET integrations to produce superior performance and power metrics over the monolithic CFET integrations.

[0020] The sequential CFET integrations can allow for design technology co -optimization (DTCO) in which improvements to the SRAM bit-cell can be made to achieve extremely small bit-cell sizes with further improvement to expected write and read margins.

[0021] This disclosure provides embodiments of SRAM bit-cells based on sequential CFET device architecture.

[0022] FIG. 1 shows a schematic of an SRAM bit-cell 100 according to embodiments of the disclosure. In FIG.l, the SRAM bit-cell 100 can include four NMOS transistors (passgate devices PG1 and PG2, and pull-down devices PD1 and PD2) and two PMOS transistors (pull-up devices PU1 and PU2). Specifically, the NMOS pull-down device PD1 and PMOS pull-up device PU1 form an inverter INV1, and the NMOS pull-down device PD2 and PMOS pull-up device PU2 form an inverter INV2. The two inverters INV1 and INV2 are latched together. That is, the output of the inverter INV1, referred as to internal node Q!, is connected to the input of the inverter INV2; and the output of the inverter INV2, referred as to internal node Q, is connected to the input of the inverter INV1. The outputs of the inverters INV1 and INV2 are connected to the pass-gate device PG1 and PG2, respectively. The pass-gate devices PG1 and PG2 can be controlled through word line WL to access bit lines BL and BL!. The power and ground rails in FIG. 1 are represented as VDD and VSS, respectively.231501W001

[0023] It is noted that the pass-gate devices PG1 and PG2 are not limited to be NMOS transistors in this disclosure. In an embodiment, the pass-gate devices PG1 and PG2 can be PMOS transistors. In an embodiment, one of the pass-gate devices PG1 and PG2 can be NMOS transistor, and the other can be PMOS transistor.

[0024] According to aspects of the disclosure, the SRAM bit-cell 100 can be implemented using a sequential CFET, and such a bit-cell can be referred to as a sequential CFET SRAM bit-cell. The sequential CFET can include a top (or upper) tier device and a bottom (or lower) tier device that is below the top tier device. The top tier and bottom tier devices can be from different wafers and processed separately. The processed devices can be bonded using a wafer-to -wafer bonding technique.

[0025] In this disclosure, the top tier and bottom tier devices of a sequential CFET SRAM bit-cell can be PMOS and NMOS transistors (or vice versa). In the below embodiments, the PMOS and NMOS transistors are used as the top tier and bottom tier devices, respectively. The top and bottom tiers of the sequential CFET SRAM bit-cell can be referred to as PMOS device tier and NMOS device tier.

[0026] It is noted that the disclosed methodscan also be applicable to embodiments where the NMOS and PMOS transistors are used as the top tier and bottom tier devices, respectively.

[0027] FIGS. 2A-2C show an NMOS device tier of a sequential CFET SRAM bit-cell (or a unit bit-cell 200) according to embodiments of the disclosure. A schematic of the unit bit-cell 200 can be referred to the SRAM bit-cell 100 in FIG. 1. Specifically, FIG. 2 A shows a top view (or a layout representation) of the NMOS device tier of the unit bit-cell 200, FIG. 2B shows a cross-sectional view of the NMOS device tier along line A of FIG. 2A, and FIG. 2C shows a cross-sectional view of the NMOS device tier along line B of FIG. 2 A. The unit bitcell 200 can be duplicated multiple times to build a sequential CFET SRAM bit-cell array.

[0028] As shown in FIG. 2 A, the unit bit-cell 200 can include NMOS channels 201-202 and gate metals 203-206. Intersections 207-210 ofthe NMOS channels 201-202 and the gate metals 203-206 can define four NMOS transistors: PD1, PD2, PG1, and PG2 of the unit bitcell 200. It is noted that each transistor can include one or multiple nanosheet structures. The unit bit-cell 200 can include VSS interconnect metals 211-212 that can connect source and drain (S / D) contacts of the pull-down transistors PD1 and PD2 to a VSS ground metal of the unit bit-cell 200 through VSS connecting vias 213-214, respectively. The unit bit-cell 200 can include bit-line interconnect metals 215-216 that can connect S / D contacts of the pass-gate transistors PG1 and PG2 to the bit lines BL! and BL of the unit bit-cell 200,231501W001respectively. The unit bit-cell 200 caninclude cross-couple interconnect metals 217-218 that can connect the internal nodes Q! and Q of the unit bit-cell 200, respectively.

[0029] In an embodiment, a minimum of a tip-to-tip separation between an interconnect metal (e.g., the VSS interconnect metal 211) and a gate metal (e.g., the gate metal 203) can be obtained through multiple patterning applications or by incorporation of advanced lithography capability within high -NA extreme ultraviolet lithography (EUV). The minimum of the tip-to-tip separation can be lOnm for example.

[0030] In an embodiment, a size of a VSS connecting via (e.g., the VSS connecting via 213) connecting a VSS interconnect metal (e.g., the VSS interconnect metal 211) to the VSS ground metal can be a nominal size, as shown in FIG. 2A.

[0031] In an embodiment, the VSS ground metal can be a metal ground plane on a back side of a wafer, and a size of a VSS connecting via (e.g., the VSS connecting via 213) connecting a VSS interconnect metal (e.g., the VSS interconnect metal 211) to the VSS ground metal can be enlarged to drive top-down self -alignment across a width of the VSS interconnect metal. For example, the size of the VSS connecting via 213 can extend in a north-south orientation of FIG. 2A as needed in order to provide superior resistivity benefit.

[0032] In an embodiment, a VSS connecting via connecting an S / D contact of a pull-down transistor (e.g., PD1) to the VSS ground metal can be formed directly underneath the S / D contact of the pull-down transistor. In an example, the VSS connecting via can be formed through a direct nano-through-silicon-via (nTSV) process. In an example, the VSS connecting via can be formed by forming a fully self-aligned contact through a replacement metal contact integration. The VSS connecting via can be made as long as the VSS interconnect metal.

[0033] FIG. 2B shows a cross-sectional view of the NMOS device tier illustrating S / D contacts of the NMOS transistors of the sequential CFET SRAM bit-cell. For example, the S / D contacts 221-222 can represent the S / D contacts of the NMOS transistors PD2 and PG1 of the unit bit-cell 200, respectively.

[0034] In an embodiment, the respective S / D contacts of the individual nanosheet structures can be merged as a single large full wrap-around S / D contact, as shown in FIG. 2B. The full wrap-around S / D contact can be formed by incorporating certain confinements to the S / D epitaxy contact formation by means of the sidewall spacer used in the initial gate spacer deposition process, or by optimizing the chemical vapor deposition (CVD) epitaxy deposition process to generate fin-like S / D contacts emanating from ends of the nanosheet structures.231501W001

[0035] It is noted that all solutions for the S / D formation can be valid in this disclosure. For example, the S / D contacts can be formed by incorporating a sidewall metal contact process. In the sidewall metal contact process, instead of the merged S / D contacts as shown in FIG. 2B, individual small and unmerged S / D contacts can be formed from each of the individual nanosheet structures. The individual small and unmerged S / D contacts can be electrically connected by the interconnect metal. As a volume of the unmerged S / D epitaxy is relatively small in the sidewall metal contact process, the growth of the S / D contacts may not be confined, which is different from the case of the merged S / D epitaxy in which the growth of the S / D contacts need to be confined.

[0036] In an embodiment, an interconnect metal can fully encompass a top portion of an S / D contact and form a full wrap-around and continuous metal interconnect structure around the S / D contact. For example, as shown in FIG. 2B, the VSS interconnect metal 212 can fully encompass the top portion of the S / D contact 221 of PD2 and form a full wrap-around and continuous metal interconnect structure around the S / D contact 221. The VSS interconnect metal 212 can also from a full wrap-around and continuous metal interconnect structure around an S / D contact adjacent to the S / D contact 221. The adjacent S / D contact can be an S / D contact of a pull-down transistor of a bit-cell adjacent to the unit bit-cell 200.

[0037] In an embodiment, while ensuring a complete wrap-around contact (e.g., the S / D contact 221) can be made, a height of an interconnect metal (e.g., the VSS interconnect metal 212) can be tailored to be as minimal as possible, in order to reduce the parasitic capacitance between the interconnect metal and gate metal (e.g., the gate metal 204). An etch selective cap can be deposited overtop the interconnect metals in order to provide some etch-selectivebased self -alignment for inter-tier connections in the inverter and cross-couple to make connections to the interconnect metals at the NMOS device tier.

[0038] In an embodiment, an S / D contact of a pull-down NMOS transistor of a bit-cell can be connected to the VSS ground metal of the bit-cell through a VSS connecting via. For example, as shown in FIG. 2B, the S / D contact 221 of PD2 can be connected to the VSS ground metal through the VSS connecting via 214. The VSS connecting via 214 can be a separate and distinct via that is used for both the unit bit-cell 200 and a bit-cell adjacent to the unit bit-cell 200.

[0039] It is noted that a shape of the VSS connecting via is not limited in this disclosure. For example, the VSS connecting via 214 can be a direct contact to the VSS ground metal and extend the full length of the VSS interconnect metal 212 to the VSS ground metal.231501W001

[0040] In an embodiment, an S / D contact of a pass-gate device, which represents an output of a bit-line, is not connected to the VSS ground metal. For example, as shown in FIG. 2B, the S / D contact 222 of the PG1 is not connected to the VSS ground metal.

[0041] It is noted that the VSS ground metal has not been formed in FIG. 2B. In an embodiment, the formation of the VSS ground metal, for example using a backside power delivery network (BSPDN) processing, can be done at a very end of an integration process of the sequential CFET SRAM.

[0042] FIG. 2C shows a cross-sectional view of the NMOS device tier illustrating the NMOS nanosheets of the sequential CFET SRAM bit-cells. For example, the NMOS nanosheets inside the dashed line boxes 231 and 232 can represent the pull-down device PD2 and the pass-gate device PG1 of the unit bit-cell 200, respectively. In FIG. 2C, each NMOS device can include four nanosheets. It is noted that a number of the nanosheets included in an NMOS or PMOS transistor is not limited in this disclosure.

[0043] In an embodiment, in order to form a transistor, an interface layer, a high-k dielectric layer, and a work function metal stack can be formed around each nanosheet structure. Then, the transistor is filled with gate metal and patterned with integrated gate-to-gate cuts etched through the gate metal. The gate-to-gate cuts can be filled with dielectric such as silicon nitride or silicon oxide. The transistor metal can be capped with an etch-selective material that can be used for the interconnect metal cap in order for the common gate tier-to-tier gate contacts to have self -aligned processing connections.

[0044] FIG. 3 shows a top view (or a layout representation) of a PMOS device tier of the unit bit-cell 200 according to embodiments of the disclosure.

[0045] As shown in FIG. 3, the uni bit-cell 200 can include PMOS channels 301-302 and gate metals 303-304. Intersections 305-306 of the PMOS channels 301-302 and the gate metals 303-304 can define two PMOS transistors: PU1 and PU2 of the unit bit-cell 200. It is noted that each transistor can include one or multiple nanosheets. The unit bit-cell 200 can include VDD interconnect metals 307-308 that can connect S / D contacts of the pull-up transistors PU1 and PU2 to a VDD power metal of the unit bit-cell 200. The unit bit-cell 200 can include cross-couple interconnect metals 309-310 that can connect S / D contacts of the transistors PU1 and PU2 to the internal nodes Q! and Q, respectively, which are further connected to the gate metals of PU2 and PU 1 , respectively. The unit bit-cell 200 can include bit-line interconnect metals (or vias) 311-312 that can connect bit-line tracks BL! and BL at a top metal layer (e.g., M0 layer at FIG. 6A) of the PMOS tier to the bit-line interconnect metals 215-216 at the NMOS device tier, respectively. The unit bit-cell 200 can include231501W001word-line interconnect metals (or vias) 313-314 that can connect word -line tracks at a top metal layer (e.g., Ml layer at FIG. 7) of the PMOS tier to the gate metals 205-206 of the pass-gate transistors PG1 and PG2 at the NMOS device tier, respectively.

[0046] In an embodiment, each PMOS transistor can include four vertically stacked nanosheets and a width of each PMOS nanosheet can be reduced down to around lOnm. The reduction in the width of the PMOS nanosheet is due to the SRAM running with a weaker PMOS device. This allows for an additional room to be available for the tier-to-tier connections which can be patterned at the PMOS device tier and dropped down to the NMOS device tier that is below the PMOS device tier.

[0047] In an embodiment, interconnect layers (e.g., the shapes with dense downward diagonals in FIG. 3) of the unit bit-cell 200 can be separated into the interconnect metals (e.g., the interconnects metals 307-310) connecting the S / D contacts of the PMOS transistors and pass-through dummy interconnect patterns (e.g., the vias 311-312). The pass-through dummy interconnect patterns can be metallized and serve as self -aligned vias to connect bit-line tracks BL and BL! at a top metal layer (e.g., M0 layer in FIG. 6A) of the PMOS device tier down to the bit-line interconnect metals (e.g., the bit-line interconnect metals 215-216 in FIG. 2 A) at the NMOS device tier. Such self-aligned via patterns in the interconnect layers can allow for the patterning and lithography processes defining the PMOS interconnects to have a fixed dielectric separation. From the fixed dielectric separation, the M0 vias (e.g., vias 605-606 in FIG. 6A) passing down from the M0 layer to the pass-through dummy interconnect patterns can be self -aligned by the same etch selective dielectric cap which is over the interconnect metals and the pass-through dummy interconnect patterns.

[0048] Additionally, the pass-through dummy interconnect patterns can allow for selfalignment for the vias (e.g., vias 505-506 in FIG. 5 A) passing from the PMOS device tier down to the interconnect structures (e.g., the bit-line interconnect metals 215-216 in FIG. 2 A) at the NMOS device tier. Without the pass-through dummy interconnect patterns, these vias may not have means of self-alignment. Given any distortion-induced overlay error between device tiers resulting from any sequential wafer-on-wafer bonding process, these vias can be at risk of being mis-aligned. For example, these vias may either not make full connections to the interconnect metals or be transferred along the side of the metal interconnect structure. The mis-alignment of these vias can induce parasitic resistance and capacitance differences, leading to a significant imbalance in the SRAM bit-cell.

[0049] In an embodiment, metal gate structures (e.g., the shapes with sparse downward diagonals in FIG. 3) of the unit bit-cell 200 can include metal pass-throughs (e.g., the vias231501W001313-314) specific for the connection of the word -line down to the NMOS pass-gates (e.g., the gate metals 205-206 in FIG. 2A) at the NMOS device tier. A metal gate can be formed through a continuous high-k metal gate (HKMG) structure which is later cut into regions so that the gates can be separated. This gate-cut-last process can allow for the placement of cuts in a closer proximity to the active channel, and thus the lateral deposition of high-k and work function metal along the sidewall of the cuts may not be needed.

[0050] According to aspects of the disclosure, a cross-couple connection of an SRAM bitcell (e.g., the SRAM bit-cell 100) is a connection that connects an output of an inverter (e.g., INV1) of the bit-cell to an input of the other inverter (e.g., INV2) of the bit-cell.

[0051] In FIG. 3, a cross-couple connection 315 of the unit bit-cell 200 can be formed by connecting the cross-couple interconnect metals 309-310 at the PMOS device tier directly to extended portions 303A-304Aof the gate metals 303-304, without passing through any metal tracks at the top metal layer (e.g., M0 layer). The gate metals 303-304 of the cross-couple connection 315 can be extended fairly a large distance away from the PMOS channels 301-302.

[0052] In an embodiment, a cross-couple formation process can include: forming interconnect trenches and transferring the interconnect trenches down through the intended patterns of the PMOS interconnect metals, silicidatingthe PMOS contacts and gap-filling the interconnect trenches with an etch-selective material which can have selectivity to the surrounding silicon oxide, patterning the extended cross-couple which can be used to open the gate spacer protecting the replacement metal gate (RMG) extension region, removing the sacrificial gap-fill material within the PMOS interconnect region, and performing metallization of the interconnect and cross-couple strap connecting to the replacement metal gate extension.

[0053] FIG. 4 shows a cross-sectional view of a formed cross-couple 400 according to embodiments of the disclosure. In FIG. 4, the PMOS RMG 401 and the PMOS interconnect metal 402 at the PMOS device tier can be merged to form the cross-couple 400. The gate spacer has been locally removed in the cross-couple region to allow for the merging of the metals. As shown in FIG. 4, the PMOS RMG 401 and PMOS interconnect metal 402 can be connected to the NMOS RMG 403 and NMOS interconnect metal 404 at the NMOS device tier through inter-tier vias 405 and 406, respectively.

[0054] FIGS. 5 A-5D show tier-to-tier connections (or inter-tier vias) at the PMOS device tier of the sequential CFET SRAM bit-cell according to embodiments of the disclosure.231501W001

[0055] FIG. 5 A shows a top view (or a layout representation) of the tier-to-tier connections of the unit bit-cell 200. The tier-to-tier connections include NMOS-to-PMOS interconnect vias 501-502, NMOS-to-PMOS gate vias 503-506, NMOS-to-PMOS bit-line connection vias 507-508, and NMOS-to-PMOS world-line connection vias 509-510. The NMOS-to-PMOS interconnect vias 501-502 can connect the cross-couple interconnect metals 217-218 at the NMOS device tierto the cross-couple interconnect metals 309-310 at the PMOS device tier, respectively. The NMOS-to-PMOS gate vias 503-506 can connect the pull-up gate metals 303-304 to the pull-down gate metals 203-204, respectively. The NMOS-to-PMOS bit-line connection vias 507-508 can connect the bit-line interconnect metals 215-216 at the NMOS device tier to the bit-line interconnect metals 311-312 at the PMOS device tier, respectively. The NMOS-to-PMOS world-line connection vias 509-510 can connect the NMOS pass gate metals 205-206 to the word-line interconnect metals 313-314 at the PMOS device tier, respectively.

[0056] A width of the PMOS nanosheet can be reduced compared to a width of the NMOS nanosheet. Accordingly, the tier-to-tier connections can be patterned at the PMOS device tier where the reduction of the width of the PMOS nanosheet can allow for the placement of the NMOS-to-PMOS interconnect vias 501-502 and the NMOS-to-PMOS gate vias 503-506. If the PMOS channel are sized the same as the NMOS channel, the available space at the PMOS device tier to accommodate the tier-to-tier connections can be inadequate. For example, for a 5-track SRAM bit-cell with the M0 pitch being less than 24nm, without either increasing the M0 pitch or the number of tracks at M0 layer, the available space at the PMOS device tier to accommodate the tier-to-tier connections can be inadequate.

[0057] FIGS. 5B-5C show cross-sectional views of the tier-to-tier connections along lines A, B, and C of FIG. 2 A and FIG. 5 A, respectively. Specifically, FIG. 5B shows the NMOS-to-PMOS bit-line connection via 507 connecting the bit-line interconnect metal 215 at the NMOS device tier to the bit-line interconnect metal 311 at the PMOS device tier. FIG. 5C shows the NMOS-to-PMOS world-line connection via 509 connecting the NMOS pass gate metal 205 to the word-line interconnect metal 313 at the PMOS device tier. FIG. 5C also shows the NMOS-to-PMOS gate vias 505-506 connecting the pull-up gate metals 304 of the pull-up device PU2 to the gate metal 204 of the pull-down device PD2. FIG. 5D shows the NMOS-to-PMOS interconnect vias 501-502 connecting the cross-couple interconnect metals 217-218 at the NMOS device tier to the cross-couple interconnect metals 309-310 at the PMOS device tier, respectively. FIG. 5D also shows the cross-couple 315 can be achieved231501W001from where the PMOS channel is cut so that the cross-couple interconnect metal 309 can be allowed to merge with the RMG 520 through the localized removal of the gate spacer.

[0058] FIGS. 6A-6C show M0 layer at the PMOS device tier of the sequential CFET SRAM bit-cell according to embodiments of the disclosure. The M0 layer can be a top metal layer used for forming the VDD power rails, the bit-line tracks, and the word-line interconnect metals.

[0059] FIG. 6A shows a top view (or a layout representation) of the M0 layer of the unit bit-cell 200. The M0 layer can include VDD power rails 601-602, bit-line tracks 603-604, and word-line interconnect metals 605-606. The VDD power rails 601-602 can be connected to the VDD interconnect metals 307-308 through the VDD connecting vias 607-608, respectively. The bit-line tracks 603-604 can be connected to the bit-line interconnect metals 311-312 through the bit-line connecting vias 609-610, respectively. The word-line interconnect metals 605-606 canbe connected to the cross-couple interconnect metals 309-310 through the word -line connecting vias 611-612, respectively. The word-line interconnect metals 605-606 can be connected to word-line tracks at Ml layer.

[0060] In an embodiment, the VDD power rails can be shared across adjacent bit-cells in the north-south orientation of FIG. 6 A, so that each bit-cell can have a shared connection to a VDD power rail disposed at the northern-most and southern-most ends of the bit-cell.

[0061] FIGS. 6B-6C show cross-section views of the M0 layer along the lines A and B of FIG. 6 A, respectively. Specifically, FIG. 6B shows the VDD power rail 602 connecting to the VDD interconnect metal 308 through the VDD connecting via 608. FIG. 6B also shows the bit-line tracks 603-604. The bit-line track 603 is connected to the bit-line interconnect metal 311 through the bit-line connecting via 609. FIG. 6C shows the word-line 605 connecting to the cross-couple interconnect metal 309 through the word -line connecting via 611.

[0062] FIG. 7 shows a top view (or a layout representation) of the Ml layer at the PMOS device tier of the sequential CFET SRAM bit-cell according to embodiments of the disclosure. The word-line track 701 can be connected to the word -line interconnect metals 605-606 through word-line connecting vias 702 and 703.

[0063] It is noted that the bit-line tracks and word-line tracks are not limited to be implemented at the M0 and Ml layers in this disclosure. A different configuration of bit-line and word-line metal layer assignments can be made in an embodiment.

[0064] In this disclosure, the SRAM device can include a back-side power distribution network (BSPDN) composed only of a large VSS ground pad, with a lower-tier device of the231501W001CFET device architecture being composed of NMOS transistors. Having the VSS ground occupy the back of the wafer allows for connections between ground and power to be isolated to the bottom tier of the CFET device architecture, and not drive any tier-to-tier connections through which the VSS ground can be connected to an upper-tier device of the CFET device architecture, which can lead to higher parasitic capacitance and resistance for the SRAM device. This also enables a much larger via to connect the NMOS device to the VSS ground through the use of a very wide via and also allows for the complete and full self -alignment of the NMOS device to the VSS ground pad.

[0065] In the embodiment, the CFET SRAM bit-cell 200 can be implemented using a 5-track layout with a size of 0.0108 urn2. For the layout, a metal pitch can be set as 24nm, contacted poly pitch can be set as 45nm, an NMOS nanosheet width can be set as 21nm, and a PMOS nanosheet width canbe set as lOnm. Each sheet canbe duplicated vertically 4 times within a unit bit-cell in order to provide an effective NMOS transistor width Weff_NMOS of 216nm and an effective PMOS transistor width Weff PMOS of 128nm. It is noted that the Weff PMOS can be reduced for the SRAM bit-cell as the SRAM device is driven by the NMOS transistor; subsequently, having a lower PMOS nanosheet width can provide for the space to drive tier-to-tier connections with the pull-up and pull-down as well as making necessary spacefor vias connecting down to bottom -device structures such as the pass gates and the bit-line connections to source / drain contacts.

[0066] FIG. 8 is a flow chart of an exemplary process 800 of fabricating a semiconductor device (e.g., the unit bit-cell 200) according to some embodiments of the present disclosure. In various embodiments, some of the steps of the process 800 shown can be performed concurrently or in a different order than shown, canbe substituted by other method steps, or can be omitted. Additional method steps can also be performed as desired.

[0067] The process 800 can start with step S810, at which the process 800 forms a first inverter using a first transistor disposed on a first wafer and a second transistor disposed on a second wafer, the first wafer being above the second wafer. Then, the process proceeds to step S820.

[0068] At step S820, the process 800 forms a second inverter using a third transistor disposed on the first wafer and a fourth transistor disposed on the second wafer. Then, the process 800 proceeds to step S830.

[0069] At step S830, the process 800 forms two pass-gate transistors disposed on the second wafer, wherein each of the first, second, third, fourth, and pass-gate transistors includes one or more nanosheet structures.231501W001

[0070] Then, the process 800 terminates.

[0071] In an embodiment, the first and third transistors are PMOS transistors, the second and fourth transistors are NMOS transistors, and the two pass-gate transistors are NMOS transistors.

[0072] In an embodiment, the first and second wafers form an upper tier and a lower tier of a sequential CFET device architecture.

[0073] In an embodiment, one of the two pass-gate transistors is connected to a word -line track through a word-line interconnect metal disposed on the first wafer. The word -line track is disposed at a first top metal layer on the first wafer.

[0074] In an embodiment, one of the two pass-gate transistors connects to a bit -line track through a bit-line interconnect metal disposed on the first wafer. The bit-line track is disposed at a second top metal layer on the first wafer.

[0075] In an embodiment, the static random access memory further includes power and ground rails disposed on the first and second wafers, respectively.

[0076] In an embodiment, the static random access memory further includes a cross-couple disposed on the first wafer. The cross-couple is formed using an RMG.

[0077] Aspects of the present disclosure provide an SRAM including a plurality of SRAM bit-cells. Each SRAM bit-cell includes a first inverter formed using a first transistor disposed on a first wafer and a second transistor disposed on a second wafer, the first wafer being above the second wafer, a second inverter formed using a third transistor disposed on the first wafer and a fourth transistor disposed on the second wafer, and two pass -gate transistors disposed on the second wafer, wherein each of the first, second, third, fourth, and pass-gate transistors includes one or more nanosheet structures.

[0078] In an embodiment, the first and third transistors are PMOS transistors, the second and fourth transistors are NMOS transistors, and the two pass-gate transistors are NMOS transistors.

[0079] In an embodiment, the first and second wafers form an upper tier and a lower tier of a sequential CFET device architecture.

[0080] In an embodiment, one of the two pass-gate transistors is connected to a word -line track through a word-line interconnect metal disposed on the first wafer. The word -line track is disposed at a first top metal layer on the first wafer.

[0081] In an embodiment, one of the two pass-gate transistors connects to a bit -line track through a bit-line interconnect metal disposed on the first wafer. The bit-line track is disposed at a second top metal layer on the first wafer.231501W001

[0082] In an embodiment, the static random access memory further includes power and ground rails disposed on the first and second wafers, respectively.

[0083] In an embodiment, the static random access memory further includes a cross-couple disposed on the first wafer. The cross-couple is formed using an RMG.

[0084] Aspects of the present disclosure provide a method of forming an SRAM including a plurality of SRAM bit-cells. The method includes forming a first inverter using a first transistor disposed on a first wafer and a second transistor disposed on a second wafer, the first wafer being above the second wafer, forming a second inverter using a third transistor disposed on the firstwafer and a fourth transistor disposed on the second wafer, and forming two pass-gate transistors disposed on the second wafer, wherein each of the first, second, third, fourth, and pass-gate transistors includes one or more nanosheet structures.

[0085] In an embodiment, the first and third transistors are PMOS transistors, the second and fourth transistors are NMOS transistors, and the two pass-gate transistors are NMOS transistors.

[0086] In an embodiment, the first and second wafers form an upper tier and a lower tier of a sequential CFET device architecture.

[0087] In an embodiment, one of the two pass-gate transistors is connected to a word -line track through a word-line interconnect metal disposed on the first wafer. The word -line track is disposed at a first top metal layer on the first wafer.

[0088] In an embodiment, one of the two pass-gate transistors connects to a bit -line track through a bit-line interconnect metal disposed on the first wafer. The bit-line track is disposed at a second top metal layer on the first wafer.

[0089] In an embodiment, the method further includes power and ground rails disposed on the first and second wafers, respectively.

[0090] In an embodiment, the method further includes a cross-couple disposed on the first wafer. The cross-couple is formed using an RMG.

[0091] In the preceding description, specific details have been set forth, such as a particular geometry of a processing system and descriptions of various components and processes used therein. It should be understood, however, that techniques herein may be practiced in other embodiments that depart from these specific details, and that such details are for purposes of explanation and not limitation. Embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for purposes of explanation, specific numbers, materials, and configurations have been set forth in order to provide a thorough understanding. Nevertheless, embodiments may be practiced without such specific details.231501W001Components having substantially the same functional constructions are denoted by like reference characters, and thus any redundant descriptions may be omitted.

[0092] Various techniques have been described as multiple discrete operations to assist in understanding the various embodiments. The order of description should not be construed as to imply that these operations are necessarily order dependent. Indeed, these operations need not be performed in the order of presentation. Operations described may be performed in a different order than the described embodiment. Various additional operations may be performed and / or described operations may be omitted in additional embodiments.

[0093] “ Substrate” or “target substrate” as used herein generically refers to an object being processed in accordance with the present disclosure. The substrate may include any material portion or structure of a device, particularly a semiconductor or other electronics device, and may, for example, be a base substrate structure, such as a semiconductor wafer, reticle, or a dielectric layer on or overlying a base substrate structure such as a thin film. Thus, substrate is not limited to any particular base structure, underlying dielectric layer or overlying dielectric layer, patterned or un-pattemed, but rather, is contemplated to include any such dielectric layer or base structure, and any combination of dielectric layers and / or base structures. The description may reference particular types of substrates, but this is for illustrative purposes only.

[0094] Those skilled in the art will also understand that there can be many variations made to the operations of the techniques explained above while still achieving the same objectives of the present disclosure. Such variations are intended to be covered by the scope of this disclosure. As such, the foregoing descriptions of embodiments of the invention are not intended to be limiting. Rather, any limitations to embodiments of the invention are presented in the following claims.

Claims

1. 231501W001WHAT IS CLAIMED IS:

1. A static random access memory (SRAM) including a plurality of SRAM bit-cells, each SRAM bit-cell comprising:a first inverter formed using a first transistor disposed on a first wafer and a second transistor disposed on a second wafer, the first wafer being above the second wafer;a second inverter formed using a third transistor disposed on the first wafer and a fourth transistor disposed on the second wafer; andtwo pass-gate transistors disposed on the second wafer,wherein each of the first, second, third, fourth, and pass-gate transistors includes one or more nanosheet structures.

2. The static random access memory of claim 1, wherein the first and third transistors are PMOS transistors, the second and fourth transistors are NMOS transistors, and the two pass-gate transistors are NMOS transistors.

3. The static random access memory of claim 1, wherein the first and second wafers form an upper tier and a lower tier of a sequential complimentary field-effective transistor (CFET) device architecture.

4. The static random access memory of claim 1, wherein one of the two pass -gate transistors is connected to a word -line track through a word -line interconnect metal disposed on the first wafer.

5. The static random access memory of claim 4, wherein the word -line track is disposed at a first top metal layer on the first wafer.

6. The static random access memory of claim 1, wherein one of the two pass -gate transistors connects to a bit -line track through a bit-line interconnect metal disposed on the first wafer.

7. The static random access memory of claim 6, wherein the bit-line track is disposed at a second top metal layer on the first wafer.231501W0018. The static random access memory of claim 1 , further comprising power and ground rails disposed on the first and second wafers, respectively.

9. The static random access memory of claim 1, further comprising a cross-couple disposed on the first wafer.

10. The static random access memory of claim 9, wherein the cross-couple is formed using a replacement metal gate (RMG).

11. A method of forming a static random access memory (SRAM) including a plurality of SRAM bit-cells, the method comprising:forming a first inverter using a first transistor disposed on a first wafer and a second transistor disposed on a second wafer, the first wafer being above the second wafer;forming a second inverter using a third transistor disposed on the first wafer and a fourth transistor disposed on the second wafer; andforming two pass-gate transistors disposed on the second wafer,wherein each of the first, second, third, fourth, and pass-gate transistors includes one or more nanosheet structures.

12. The method of claim 11, wherein the first and third transistors are PMOS transistors, the second and fourth transistors are NMOS transistors, and the two pass-gate transistors are NMOS transistors.

13. The method of claim 11, wherein the first and second wafers form an upper tier and a lower tier of a sequential complimentary field -effective transistor (CFET) device architecture.

14. The method of claim 11, wherein one of the two pass-gate transistorsis connected to a word-line track through a word-line interconnect metal disposed on the first wafer.

15. The method of claim 14, wherein the word-line track is disposed at a first top metal layer on the first wafer.231501W00116. The method of claim 11 , wherein one of the two pass-gate transistors connects to a bit-line track through a bit-line interconnect metal disposed on the first wafer.

17. The method of claim 16, wherein the bit-line track is disposed at a second top metal layer on the first wafer.

18. The method of claim 11, further comprising power and ground rails disposed on the first and second wafers, respectively.

19. The method of claim 11, further comprising a cross-couple disposed on the first wafer.

20. The method of claim 19, wherein the cross-couple is formed using a replacement metal gate (RMG).

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