Chip packaging structure, chip, and electronic device

Abstract

A chip packaging structure, a chip, and an electronic device, relating to the technical field of semiconductors. The chip packaging structure comprises: a first chip; and a redistribution structure (20) stacked with the first chip, the redistribution structure (20) comprising a first dielectric layer, a plurality of three-dimensional porous structures being embedded in the first dielectric layer, pores of each three-dimensional porous structure being filled with metal, the three-dimensional porous structures having electrical conductivity, and the coefficient of thermal expansion of the three-dimensional porous structures being less than that of the metal; wherein a lead-out terminal of the first chip is led out from a first surface (S1) of the redistribution structure (20) to a second surface (S2) of the redistribution structure (20) via at least some of the plurality of three-dimensional porous structures, the second surface (S2) is opposite to the first surface (S1), and the first surface (S1) is in contact with the first chip. The chip packaging structure provided in embodiments of the present application can mitigate the warpage problem of a redistribution layer, so as to improve the reliability of the chip.

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