Clock source and electronic device

Abstract

Embodiments of the present application relate to the technical field of integrated circuits, and disclosed are a clock source and an electronic device. The clock source comprises a plurality of inverter chain loops, wherein the plurality of inverter chain loops includes a main loop and at least two auxiliary loops, and the main loop is separately coupled to the at least two auxiliary loops to establish at least two coupling relationships.

Description

Clock source and electronic equipment

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Chinese Patent Application No. 202510050840.7, filed on January 13, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of integrated circuit technology, and more particularly to clock sources and electronic devices. Background Technology

[0004] With the increasing demands for communication speeds, traditional multi-phase clock sources face challenges in both oscillation frequency and mode stability.

[0005] To increase the oscillation frequency of the clock source, the relevant technology employs feedforward coupling to effectively reduce the single-stage delay of the inverter, thereby increasing the oscillation frequency of the clock source. However, as the number of output phases further increases, this approach leads to uncertainty in the oscillation mode of the clock source. That is, the output phase relationship and oscillation frequency change drastically under process voltage-temperature (PVT) variations, causing ambiguity in the oscillation mode and affecting the overall stability of the communication system. Summary of the Invention

[0006] The main objective of this application is to provide a clock source and an electronic device.

[0007] This application provides a clock source, including: multiple inverter chain loops, wherein the multiple inverter chain loops include a main loop and at least two sub-loops, and the main loop is coupled to at least two of the sub-loops respectively, forming at least two coupling relationships.

[0008] Furthermore, embodiments of this application also provide an electronic device, which includes a clock source as described above.

[0009] This application provides an electronic device including a clock source, which includes: multiple inverter chain loops, each inverter chain loop including a main loop and at least two sub-loops, the main loop being coupled to at least two sub-loops respectively, thus establishing at least two coupling relationships. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0011] Figure 1 is a schematic diagram of a clock source provided in an embodiment of this application;

[0012] Figure 2 is a structural schematic diagram of a specific implementation of a clock source provided in an embodiment of this application;

[0013] Figure 3 is a schematic diagram of the output phase relationships of a clock source oscillation in oscillation mode 9 provided in an embodiment of this application;

[0014] Figure 4 is a schematic diagram of the output phase relationship of a clock source oscillation in oscillation mode 11 provided in an embodiment of this application;

[0015] Figure 5 is a schematic diagram of the loop gain of various potential oscillation modes of a clock source provided in an embodiment of this application without the introduction of a second sub-loop AL2;

[0016] Figure 6 is a schematic diagram of the loop gain of various potential oscillation modes of a clock source provided in an embodiment of this application when a second sub-loop AL2 is introduced;

[0017] Figure 7 is a schematic diagram of the oscillation mode distribution of a clock source in transient Monte Carlo simulation without the introduction of the second sub-loop AL2, according to an embodiment of this application.

[0018] Figure 8 is a schematic diagram of the oscillation mode distribution of a clock source in transient Monte Carlo simulation with the introduction of a second secondary loop AL2, according to an embodiment of this application.

[0019] The implementation of the objectives, functional features, and advantages of the embodiments of this application will be explained in conjunction with the embodiments and with reference to the accompanying drawings.

[0020] Explanation of the reference numerals: 10, main loop; 20, secondary loop; ML, main loop; AL, secondary loop; AL1, first secondary loop; AL2, second secondary loop; D, main loop inverter; A1, first secondary loop inverter; A2, second secondary loop inverter. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the embodiments of this application.

[0022] In any modern communication system, the clock source is an indispensable and crucial component. Taking optical communication systems as an example, the oscillation frequency of the clock source determines the sampling rate of the sampling circuit in the optical communication system, and the number of phases of the output signal of the clock source determines the number of parallel sampling channels of the sampling circuit. Together, these two factors determine the data transmission rate of the optical communication system.

[0023] With increasingly demanding communication speeds, traditional multi-phase clock sources face challenges in both oscillation frequency and mode stability. In related clock source designs, a cascaded multi-stage inverter structure is typically used to generate multi-phase oscillation signals. However, as the number of output phases increases, the number of cascaded inverters also increases, leading to a decrease in the frequency of the oscillation signal generated by the clock source, which fails to meet communication speed requirements.

[0024] To increase the oscillation frequency of the clock source, the relevant technology employs feed-forward coupling (FFC) to effectively reduce the single-stage delay of the inverter, thereby increasing the clock source oscillation frequency. However, as the number of output phases further increases, this approach leads to uncertainty in the clock source's oscillation mode. Specifically, the output phase relationship and oscillation frequency change drastically under process voltage-temperature (PVT) variations, causing oscillation mode ambiguity and affecting the overall stability of the communication system.

[0025] Based on this, embodiments of this application provide a clock source and an electronic device. The clock source includes multiple inverter chain loops, each including a main loop and at least two sub-loops. The main loop is coupled to at least two sub-loops, establishing at least two coupling relationships. The clock source provided in this application, based on the main loop of the inverter chain loops, significantly increases the oscillation frequency of the main loop by introducing at least two sub-loops that form at least two coupling relationships with the main loop. This solves the problem in related technologies where the oscillation frequency is too low to meet communication rate requirements. Furthermore, it enables the clock source to stably complete oscillation start-up and continuous oscillation in a specified oscillation mode, overcoming the problem in related technologies where an increase in the number of output phases may cause ambiguity in the oscillation mode.

[0026] The clock source and electronic device provided in this application are specifically described through the following embodiments. First, the clock source in the embodiments of this application is described.

[0027] This application provides a clock source. Referring to Figure 1, which is a schematic diagram of the structure of a clock source provided in this application, the clock source includes: multiple inverter chain loops, each of which includes a main loop 10 and at least two sub-loops 20. The main loop 10 is coupled to at least two sub-loops 20 respectively, forming at least two coupling relationships.

[0028] The clock source provided in this embodiment can be applied to scenarios requiring multi-phase clocks, such as digital-to-analog converters / analog-to-digital converters based on time-interleaved topologies. The clock source proposed in this embodiment can be a multi-phase clock source based on an inverter chain.

[0029] In this embodiment, both the main loop 10 and the sub-loop 20 are implemented based on an inverter chain. The connection methods between the main loop 10 and different sub-loops 20 are different, thus constructing different coupling relationships.

[0030] In this embodiment, based on the clock source including a main loop (ML) of an inverter chain, at least two auxiliary loops (AL) of inverter chains are introduced to achieve the purpose of both increasing the oscillation frequency of the clock source and avoiding ambiguity in the oscillation mode.

[0031] As an example, referring to Figure 2, this embodiment introduces a first inverter chain sub-loop AL1 that forms a first type of coupling relationship with the main inverter chain ML, thereby significantly increasing the oscillation frequency of the main inverter chain ML. However, when the number of output phases is too high, there may be several potential oscillation modes, i.e., mode ambiguity exists. Therefore, based on the introduction of the first inverter chain sub-loop AL1, a second inverter chain sub-loop AL2 that forms a second type of coupling relationship with the main inverter chain ML can be introduced to increase the start-up gain of a specific oscillation mode among several potential oscillation modes. This ensures that the multi-phase clock source can stably complete the start-up and continuous oscillation under PVT variations, thus solving the mode ambiguity problem. In some embodiments, by adjusting the coupling method between AL1, AL2, and ML, and the transconductance (gm) ratio of the inverter units constituting these three loops, the oscillation mode and oscillation frequency of the multi-phase clock source can be adjusted, thereby significantly improving the flexibility of the oscillation frequency and oscillation mode of the multi-phase oscillator.

[0032] It is understood that, based on the example corresponding to Figure 2, improvements can also be made to enhance the flexibility of the oscillation mode, such as introducing a third inverter chain sub-loop AL3 that forms a third type of coupling relationship with the main loop, a fourth inverter chain sub-loop AL4 that forms a fourth type of coupling relationship with the main loop, and a third inverter chain sub-loop ALn that forms an nth type of coupling relationship with the main loop. All of these improvements should fall within the scope of protection of this embodiment, and this embodiment does not limit them.

[0033] In some feasible embodiments, the main loop 10 includes a plurality of main loop inverters, and each sub-loop 20 includes a plurality of sub-loop inverters, wherein the number of main loop inverters and the number of sub-loop inverters in each sub-loop 20 are equal.

[0034] In this embodiment, the number of inverters contained in the main loop 10 and each sub-loop 20 is the same. Although the total number of sub-loop inverters contained in different sub-loops 20 is the same, the different connection relationships between the main loop 10 and the different sub-loops 20 will result in different specific structures of the different sub-loops 20. That is, different sub-loops 20 may each include 2, 3 or more sub-loops. Therefore, the number of inverters contained in a single sub-loop in different sub-loops 20 will be different.

[0035] In some feasible embodiments, the number of main loop inverters and the number of sub-loop inverters in each sub-loop 20 are equal to the number of phases of the clock source.

[0036] In this embodiment, the number of various inverters is the same as the number of output phases of the clock source. As an example, if the clock source provided in this embodiment is a 32-phase clock source, then the number of main loop inverters is 32, and the number of secondary loop inverters in each loop 20 is also 32. Similarly, if the clock source provided in this embodiment is a 64-phase clock source, then the number of main loop inverters is 64, and the number of secondary loop inverters in each loop 20 is also 64. It should be understood that the number of phases of the clock source provided in this embodiment can be flexibly adjusted according to the actual situation, and this embodiment does not limit it.

[0037] In some feasible embodiments, multiple main loop inverters are connected end to end in sequence to form a main loop, and there is an output node between adjacent main loop inverters. Each output node is connected to at least two secondary loop inverters.

[0038] In this embodiment, taking the clock source shown in Figure 2 as an example, multiple main loop inverters D are connected end to end in sequence to form the main loop ML of the inverter chain, and there is an output node CLK between each adjacent main loop inverter D. CLK for each output node Connect at least two secondary loop inverters.

[0039] In some feasible embodiments, the sub-loop 20 includes a first sub-loop and a second sub-loop, and the sub-loop inverter includes a first sub-loop inverter for forming the first sub-loop and a second sub-loop inverter for forming the second sub-loop.

[0040] Each output node is connected to at least one first sub-loop inverter and at least one second sub-loop inverter.

[0041] In this embodiment, as shown in Figure 2, the clock source is a 32-phase clock source with three-loop coupling based on an inverter chain. It includes a main loop ML composed of 32 main loop inverters D, a first secondary loop AL1 composed of 32 first secondary loop inverters A1, and a second secondary loop AL2 composed of 32 second secondary loop inverters A2. As shown in Figure 2, with output node CLK... <0> For example, the node is connected to at least one first sub-loop inverter A1 and at least one second sub-loop inverter A2.

[0042] In some feasible embodiments, the above coupling relationship includes a first coupling relationship;

[0043] The first sub-loop consists of at least two first sub-loops, each of which is composed of multiple first sub-loop inverters. Each of the at least two first sub-loops is coupled to the main loop, thus establishing a first coupling relationship.

[0044] In this embodiment, as shown in Figure 2, the two ends of the first sub-loop inverter A1 are respectively connected to the output node CLK. and output node CLK<i+2> This is because if the two ends of the secondary loop inverter are respectively connected to the output node CLK and output node CLK<i+1> This is equivalent to each secondary loop inverter being connected in parallel with each primary loop inverter. The first secondary loop is equivalent to a parallel loop of the primary loop and cannot play a role in improving the oscillation efficiency of the primary loop. By gradually increasing i from 0 to 29, two first sub-loops consisting of 16 first secondary loop inverters A1 can be formed. The two first sub-loops are coupled to the primary loop through odd-numbered output nodes and even-numbered output nodes, respectively.

[0045] In some feasible embodiments, the first coupling relationship includes at least two main loop inverters between the two output nodes connected to the two ends of each first sub-loop inverter.

[0046] In this embodiment, the number of first sub-loops is determined by the number of main loop inverters spaced between the two ends of each first sub-loop inverter in the first coupling relationship. Taking the 32-phase clock source shown in Figure 2 as an example, the output node CLK is connected to both ends of the first sub-loop inverter A1. and output node CLK<i+2> If the two ends of the first sub-loop inverter A1 are separated by two main loop inverters D, then the number of first sub-loops is also two, and the number of first sub-loop inverters A1 forming one first sub-loop is 32 / 2 = 16; if the two ends of the first sub-loop inverter A1 are respectively connected to the output node CLK and output node CLK<i+4> When the two ends of the first sub-loop inverter A1 are spaced by 4 main loop inverters D, the number of the first sub-loop is also 4, and the number of the first sub-loop inverters A1 that make up one first sub-loop is 32 / 4 = 8. It should be understood that the number of main loop inverters spaced between the two ends of the first sub-loop inverter can be flexibly adjusted according to the actual situation, and this embodiment does not limit it.

[0047] In some feasible embodiments, the above coupling relationship includes a second coupling relationship;

[0048] The second sub-loop consists of at least three second sub-loops, each of which is composed of multiple second sub-loop inverters. Each of the at least three second sub-loops is coupled to the main loop to form a second coupling relationship.

[0049] In this embodiment, the spacing between the output nodes connected to the two ends of the second sub-loop inverter should differ from the spacing between the output nodes connected to the two ends of the first sub-loop inverter in the aforementioned embodiment. In the aforementioned embodiment, the two ends of the first sub-loop inverter A1 are respectively connected to output node CLK. In the case of the output node CLK<i+2>, in this embodiment, both ends of the second sub-loop inverter A2 are respectively connected to the output node CLK and an output node CLK<i+3>, where the output node CLK<i+3> may also be an output node CLK<i+4>, an output node CLK<i+5>, or an output node CLK<i+9> shown in FIG. 2; both ends of the second sub-loop inverter A2 are respectively connected to the output node CLK Taking the output node CLK<i+3> as an example, the second sub-loop includes three second sub-loops.

[0050] In some feasible embodiments, the second coupling relationship includes: there are at least three main-loop inverters between the two output nodes connected to both ends of each second sub-loop inverter.

[0051] In this embodiment, the number of second sub-loops is determined by the number of main-loop inverters spaced between both ends of each second sub-loop inverter in the second coupling relationship. At the same time, it is also necessary to make the second coupling relationship different from the first coupling relationship.

[0052] Taking the 32-phase clock source shown in FIG. 2 as an example, output nodes CLK are respectively connected to both ends of the second sub-loop inverter A2 When there are 9 master loop inverters D between the output node CLK<i+9>, that is, the two ends of the second sub-loop inverter A2, the number of the second sub-loops is at least 9; it should be understood that the number of master loop inverters between the two ends of the second sub-loop inverter can be flexibly adjusted according to the actual situation, and this embodiment does not limit this.

[0053] It should be understood that in the above embodiments described based on FIG. 2, the number of stages N of the main loop ML, the first sub-loop AL1, and the second sub-loop AL2 are equal, and the specific number of stages is not limited to N = 32 shown in FIG. 2. FIG. 2 is only a display of a specific embodiment, and N can be equal to any integer value greater than 2. Correspondingly, when N takes different values and different oscillation modes are required, the connection manner of AL1 and AL2 will also change correspondingly. For example, in FIG. 2, AL1 is used to connect CLK Connected to CLK<i+2> and AL2 for connecting to CLK and CLK<i+9>, where i+2 and i+9 are only an available example of AL1 and AL2 in the specific embodiment shown in FIG. 2, and do not indicate that the clock source proposed in the embodiments of the present application can only be applied to N = 32, AL1 is connected to CLK Connected to CLK<i+2> and AL2 for CLK and CLK<i + 9> as a specific implementation. Under other feasible correct connection methods, the multi-phase clock source based on multi-loop coupling proposed in this embodiment still has the effects of improving the oscillation frequency and eliminating mode ambiguity, so it should be included in the protection scope of this embodiment.

[0054] Based on the above embodiments, in this embodiment, a 32-phase clock source is used for simulation testing, and the schematic diagrams of the output phase relationships of the 32-phase clock source oscillation in different modes as shown in FIGS. 3 and 4, the schematic diagrams of the loop gains of each potential oscillation mode as shown in FIGS. 5 and 6, and the schematic diagrams of the transient Monte Carlo simulation results for eliminating mode ambiguity as shown in FIGS. 7 and 8 are obtained.

[0055] Among them, FIGS. 3 and 4 show that when the main loop ML and the first secondary loop AL1 are coupled to each other, the oscillation gains of oscillation mode 9 (mode-9) and oscillation mode 11 (mode-11) are similar, which leads to the problem of mode ambiguity. By observing FIG. 3, it can be seen that when the clock source oscillates in mode-9, if the output signal CLK<9> is coupled to CLK<0> through the second secondary loop inverter A2 to form the second secondary loop AL2, the vector amplitude of CLK<0> can be increased, that is, the oscillation gain of mode-9 is increased; at the same time, when the clock source oscillates in mode-11, if the output signal CLK<9> is coupled to CLK<0> through the second secondary loop inverter A2 to form the second secondary loop AL2, the vector amplitude of CLK<0> can be reduced, that is, the oscillation gain of mode-11 is reduced. Through the above means, the starting gain of mode-9 can be greatly increased, and the starting gain of mode-11 can be made ambiguous, so as to greatly improve the starting stability of mode-9 in the starting stage of the 32-phase clock source shown in this embodiment.

[0056] To more intuitively illustrate the technical effects that this embodiment can achieve, FIGS. 5 and 6 show the influence of the second secondary loop AL2 on each potential oscillation mode. Among them, FIG. 5 shows the loop gains of each potential oscillation mode when only the main loop ML and the first secondary loop AL1 are coupled to each other. It can be seen from FIG. 5 that no matter how the injection intensity of the first secondary loop AL1 (the abscissa in FIG. 5) changes, there are problems with similar loop gains for multiple oscillation modes. However, once the second secondary loop AL2 is introduced to be coupled with the main loop ML, the loop gain of the mdoe-9 oscillation mode can be greatly increased, so as to widen the gap with the loop gains of other oscillation modes, ensuring that mode-9 can quickly form oscillations and finally form a stable oscillation mode in the starting stage, that is, the situation shown in FIG. 6.

[0057] Figures 7 and 8 illustrate the effectiveness of the second auxiliary loop AL2 in eliminating mode ambiguity from the perspective of transient Monte Carlo simulation. Among them, Figure 7 illustrates that in the absence of the second auxiliary loop AL2, there are 4 potential states in the finally formed oscillation mode, namely mode-8, mode-9, mode-10, and mode-11, which conform to the expected results shown in Figure 5 above; in contrast, when the second auxiliary loop AL2 is added, in the 200 transient Monte Carlo simulation results, it can oscillate stably in the mode-9 mode, which conforms to the expected results shown in Figure 6 above.

[0058] In addition, the embodiment of the present application also provides an electronic device, which includes the clock source provided in the above embodiment.

[0059] The electronic device proposed in this embodiment and the clock source proposed in the above embodiment belong to the same technical concept. The technical details not described in detail in this embodiment can be referred to any of the above embodiments, and this embodiment has the same beneficial effects as each embodiment of the above clock source.

[0060] It should be noted that all directional indications (such as up, down, left, right, front, back...) in the embodiments of the present application are only used to explain the relative positional relationship and movement conditions between components in a specific posture (as shown in the drawings). If the specific posture changes, the directional indications will also change accordingly.

[0061] In addition, in the embodiments of the present application, descriptions such as "first" and "second" are only for descriptive purposes, and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the embodiments of the present application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise specifically and clearly defined. In addition, the meaning of "and / or" appearing throughout the text is to include three parallel solutions. Taking "A and / or B" as an example, it includes the A solution, or the B solution, or the solution where A and B are satisfied simultaneously.

[0062] In the embodiments of the present application, unless otherwise clearly specified and limited, terms such as "connection" and "fixation" should be understood in a broad sense. For example, "fixation" can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal connection of two components or the interaction relationship between two components, unless otherwise clearly limited. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to specific situations.

[0063] It should also be understood that the references to "one embodiment" or "some embodiments" etc. described in the specification of the embodiments of the present application mean that specific features, structures or characteristics described in connection with that embodiment are included in one or more embodiments of the embodiments of the present application. Thus, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in still some other embodiments" etc. that appear at different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized. The terms "comprise", "include", "have" and their variants all mean "including but not limited to", unless otherwise specifically emphasized.

[0064] It should be noted that the technical solutions of the various embodiments of the present application can be combined with each other, but it must be based on the fact that those skilled in the art can implement them. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the embodiments of the present application.

[0065] The above are only optional embodiments of the embodiments of the present application, and do not limit the patent scope of the embodiments of the present application. Any equivalent structural or equivalent process transformation made by using the specification and drawings of the embodiments of the present application, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the embodiments of the present application.

Claims

1. A clock source, comprising: Multiple inverter chain loops, the multiple inverter chain loops including a main loop and at least two sub-loops, the main loop being coupled to at least two of the sub-loops respectively, to establish at least two coupling relationships.

2. The clock source as described in claim 1, wherein, The main loop includes multiple main loop inverters, and each of the sub-loops includes multiple sub-loop inverters. The number of main loop inverters is equal to the number of sub-loop inverters in each sub-loop.

3. The clock source as described in claim 2, wherein, Multiple main loop inverters are connected end to end in sequence to form the main loop. There is an output node between adjacent main loop inverters, and each output node is connected to at least two secondary loop inverters.

4. The clock source as described in claim 3, wherein, The sub-loop includes a first sub-loop and a second sub-loop, and the sub-loop inverter includes a first sub-loop inverter for forming the first sub-loop and a second sub-loop inverter for forming the second sub-loop. Each of the output nodes is connected to at least one first sub-loop inverter and at least one second sub-loop inverter.

5. The clock source as described in claim 4, wherein, The coupling relationship includes a first coupling relationship; The first sub-loop is composed of at least two first sub-loops, each of which is composed of multiple first sub-loop inverters. The at least two first sub-loops are coupled to the main loop to establish the first coupling relationship.

6. The clock source as described in claim 5, wherein, The first coupling relationship includes: at least two main loop inverters are included between the two output nodes connected to the two ends of each of the first sub-loop inverters.

7. The clock source as described in claim 4, wherein, The coupling relationship includes a second coupling relationship; The second sub-loop consists of at least three second sub-loops, each of which is composed of multiple second sub-loop inverters. The at least three second sub-loops are coupled to the main loop to form the second coupling relationship.

8. The clock source as described in claim 7, wherein, The second coupling relationship includes at least three main loop inverters between the two output nodes connected to the two ends of each of the second secondary loop inverters.

9. The clock source as claimed in any one of claims 2 to 8, wherein, The number of the main loop inverters and the number of the sub-loop inverters in each sub-loop are equal to the number of phases of the clock source.

10. An electronic device comprising a clock source as claimed in any one of claims 1 to 9.

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