Hybrid passivated back-contact cell and post-texturing manufacturing method therefor

Abstract

The present disclosure belongs to the technical field of back-contact cells, and specifically relates to a hybrid passivated back-contact cell and a post-texturing manufacturing method therefor. The method comprises: S102, successively forming a first semiconductor layer and a mask layer on the back surface of a silicon substrate; S103, performing cleaning and texturing to form a textured surface on a light-receiving surface of the silicon substrate, the maximum height of pyramids on the textured surface of the light-receiving surface being T1; S104, successively forming a passivation layer and an anti-reflection layer on the light-receiving surface of the silicon substrate; S105, forming a second semiconductor opening region; S106, performing cleaning and etching to form recess structures at least in the second semiconductor opening region on the back surface of the silicon substrate; and S107, depositing a second semiconductor layer on the back surface, the second semiconductor layer comprising an amorphous passivation layer and a second doped silicon layer. The present disclosure can reduce the interfacial contact resistance of the second semiconductor opening region, prolong the minority carrier lifetime and improve the efficiency and bifaciality of cells while simplifying process steps and reducing material costs.

Description

A combined passivated back contact battery and its subsequent texturing preparation method

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 2025100260257, filed on January 8, 2025, entitled "A Combined Passivation Back Contact Battery and a Post-Texturing Preparation Method thereof", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure belongs to the field of back contact battery technology, specifically relating to a combined passivated back contact battery and its subsequent texturing preparation method. Background Technology

[0004] Currently, the combined passivated back contact battery exhibits superior battery performance compared to conventional heterojunction back contact batteries. It is fabricated using a post-texturing method with production advantages: after forming the first semiconductor layer and mask layer, a first etching is performed to form the second semiconductor opening region; then texturing and cleaning are performed; subsequently, a passivation layer and an antireflection layer are formed on the light-receiving surface of the silicon substrate; then, a single-sided etching is performed to remove the coating layer formed on the back side of the silicon substrate during the deposition of the light-receiving surface, using hydrofluoric acid or a weak alkaline solution; afterward, conventional RCA cleaning is performed to ensure that the interface cleanliness of the second semiconductor opening region on the back side of the silicon substrate meets the requirements for depositing the second semiconductor layer; finally, the second semiconductor layer is deposited on the back side.

[0005] However, the above-mentioned post-pile finishing method has the following problems:

[0006] ①After the passivation layer and antireflection layer are formed on the light-receiving surface of the silicon substrate, there is a serious back coating on the back side of the silicon substrate. It is necessary to remove the back coating before texturing or cleaning, which increases the number of process steps.

[0007] ② Laser etching of the opening on the back of the silicon substrate causes some damage, requiring a large amount of etching to completely remove it. However, the light-receiving surface of the silicon substrate does not have a damage layer. Therefore, texturing the back of the light-receiving surface at the same time increases the amount of etching on the light-receiving surface of the silicon substrate, thereby increasing the material cost.

[0008] ③ Simultaneous texturing of the back side of the silicon substrate's light-receiving surface makes it impossible to independently control the surface morphology of the light-receiving surface and the opening area on the back side of the silicon substrate, which is not conducive to improving battery efficiency.

[0009] ④ RCA cleaning is used to clean the second semiconductor opening area. RCA cleaning is relatively gentle with almost no etching. However, after texturing and cleaning, the interface of the second semiconductor opening area on the silicon substrate undergoes passivation and antireflection layer formation and single-sided etching processes. The interface of the second semiconductor opening area is severely contaminated, making it difficult for RCA to clean it thoroughly. This affects the passivation and contact performance of the interface, thereby affecting the battery efficiency.

[0010] It should be noted that this part of the disclosure only provides background technology related to this disclosure, and does not necessarily constitute prior art or publicly known technology. Summary of the Invention

[0011] The purpose of this disclosure is to overcome the shortcomings of existing methods for texturing after co-passivating back contact batteries, such as cumbersome process steps, high cost, and the need to improve battery efficiency and production yield. It provides a method for preparing a co-passivated back contact battery and its subsequent texturing, which can reduce the interface contact resistance of the second semiconductor opening region, improve minority carrier lifetime, and improve battery efficiency and bifaciality while simplifying process steps and reducing material costs.

[0012] To achieve the above objectives, in a first aspect, this disclosure provides a novel post-texturing method for preparing a combined passivated back contact battery, comprising the following steps:

[0013] S101 provides a double-sided polished silicon substrate;

[0014] S102, A first semiconductor layer and a mask layer are sequentially formed on the back side of a silicon substrate; the first semiconductor layer includes a tunneling oxide layer and a first doped polysilicon layer;

[0015] S103. Perform cleaning and texturing to form a textured surface on the light-receiving surface of the silicon substrate. The maximum height of the pyramid of the textured surface on the light-receiving surface is T1.

[0016] S104. A passivation layer and an antireflection layer are sequentially formed on the light-receiving surface of a silicon substrate;

[0017] S105. A first laser etching opening is formed on the back side obtained in S104 to form a second semiconductor opening region;

[0018] S106. Perform cleaning and etching to form a groove structure at least in the second semiconductor opening region on the back side of the silicon substrate. Control the maximum height between the bottom of the second semiconductor opening region on the back side of the silicon substrate and the top of the first doped polysilicon layer to be T2. The bottom of the groove structure of the second semiconductor opening region may or may not have a pyramid structure and the maximum height of the pyramid is T3, and satisfy T2>T1≥T3, where T3 is 0-6μm.

[0019] S107. Deposit a second semiconductor layer on the back side, the second semiconductor layer comprising an amorphous passivation layer and a second doped silicon layer.

[0020] Optionally, T1 is 0.5-10 μm.

[0021] Optionally, T2 is 2.5-15 μm.

[0022] Optionally, T3 is 0.1-6 μm.

[0023] Optionally, the ratio of T2:T1:T3 is 1.5-50:1-30:1.

[0024] Optionally, the conditions for cleaning and texturing in S103 to obtain T1 include: texturing with an alkaline solution containing texturing additives, wherein the mass concentration of alkali in the alkaline solution is 0.5wt%-5wt%, the mass content of texturing additives is 0.05wt%-2wt%, the temperature of the alkaline solution is 60-85℃, and the treatment time is 5-15min.

[0025] Optionally, the cleaning etching in S106 includes any one of texturing, polishing, texturing after polishing, or polishing after texturing.

[0026] Optionally, S106 also includes a step of removing at least a portion of the mask layer thickness after cleaning and etching.

[0027] Optionally, the groove structure in the second semiconductor opening region in S106 is a polished, semi-textured, or texturized structure. When the groove structure is a polished or semi-textured structure, T3 is 0.1-3μm, and when the groove structure is a texturized structure, T3 is 1-6μm.

[0028] Optionally, the groove structure in the second semiconductor opening region of S106 is a polished or semi-textured structure, and the corresponding conditions for cleaning and etching in S106 include: polishing with alkaline solution or forming by a combination of texturing and polishing.

[0029] Optionally, the groove structure in the second semiconductor opening region of S106 is a texturing structure, and the corresponding conditions for cleaning and etching in S106 include: texturing with alkaline solution or a combination of polishing and texturing.

[0030] Optionally, the polishing process conditions include: the mass concentration of alkali in the corresponding alkaline solution is 0.5wt%-5wt%, the alkaline solution contains polishing additives with a mass content of 0.05wt%-2wt%, the temperature of the alkaline solution is 50-85℃, and the treatment time is 0.25-5min; the texturing process conditions include: the mass concentration of alkali in the corresponding alkaline solution is 0.5wt%-5wt%, the alkaline solution contains texturing additives with a mass content of 0.05wt%-2wt%, the temperature of the alkaline solution is 60-85℃, and the treatment time is 2-12min.

[0031] Optionally, the novel post-texturing method for the combined passivated back contact battery also satisfies at least one of the following conditions:

[0032] Condition 1: The thickness of the tunneling oxide layer is 1-2 nm, the thickness of the first doped polysilicon layer is 60-200 nm, and the effective doping concentration is 5e19cm. -3 -5e20cm -3The amorphous passivation layer has a thickness of 3-10 nm, and the second doped silicon layer has a thickness of 5-40 nm and an effective doping concentration of 5e18 cm⁻¹. -3 -2e20cm -3 ;

[0033] Condition 2: The mask layer is a silicon dielectric layer, which includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0034] Condition 3: The thickness of the mask layer is 10-80 nm;

[0035] Condition 4: The passivation layer includes at least one of silicon oxide, amorphous silicon, and aluminum oxide; the antireflection layer is a silicon dielectric film, which includes at least one of silicon nitride, silicon oxynitride, and silicon oxide.

[0036] Condition 5: The thickness of the passivation layer is 2-30 nm, and the thickness of the antireflection layer is 50-180 nm.

[0037] Optionally, the novel post-texturing method for the combined passivated back contact battery further includes:

[0038] S108. A second etching opening is made on a portion of the second semiconductor layer on the back side of the silicon substrate to form a first semiconductor opening region that is spaced apart from the second semiconductor opening region.

[0039] S109. Deposit a conductive film layer on the back side obtained in S108;

[0040] S110. A third etching opening is made on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation trench.

[0041] S111, metal electrodes are formed on the outer surfaces of the corresponding conductive film layers in the regions where the first semiconductor opening region and the second semiconductor opening region are located, respectively.

[0042] Secondly, this disclosure provides a combined passivated back contact battery, which is prepared by the novel post-texturing method for the combined passivated back contact battery described in the first aspect. Beneficial effects:

[0043] This disclosure, through the above-described technical solution, and especially by employing specific steps S103 to S106, has at least the following advantages:

[0044] ①The present invention discloses that the light-receiving surface and the back surface of the silicon substrate are separately wet etched, and the surface morphology is independently controlled, which is beneficial to improving battery efficiency.

[0045] ②After the conventional silicon substrate forms a passivation layer and an antireflection layer on the light-receiving surface, there is a serious coating around the back of the silicon substrate. The method disclosed in this paper does not require the removal of the coating around the back of the substrate for texturing or cleaning, which simplifies the process steps.

[0046] ③ Since conventional methods cause some damage after the first laser etching opening on the back side of the silicon substrate, a large amount of etching is required to completely remove it. However, the light-receiving surface of the silicon substrate does not have a damaged layer. Therefore, the method disclosed in this paper can reduce the amount of etching on the silicon substrate, reduce material costs, and at the same time help reduce the interface contact resistance of the second semiconductor opening region, improve minority carrier lifetime, and improve cell efficiency and bifaciality.

[0047] ④ In this disclosure, the interface of the second semiconductor opening region of the silicon substrate is immediately followed by the deposition of the second semiconductor layer after wet cleaning and etching. The interface between the second semiconductor layer and the silicon substrate is very clean, which can avoid contamination, thereby improving the production yield and increasing the bifaciality.

[0048] This disclosure controls the textured surface structure of the light-receiving surface and the structure of the second semiconductor opening region, such that T2 > T1 ≥ T3. It can independently control the etching amount of the light-receiving surface and the corresponding opening region on the back side of the silicon substrate, improve the cleanliness of the interface of the back opening region, and thus help reduce the thickness of the silicon substrate (because the etching amount is reduced, the thickness of the silicon substrate before processing can be appropriately thinned while maintaining the consistency of the silicon substrate thickness after processing, which is expected to reduce by 5-10 μm), improve the passivation and contact effect of the silicon substrate, and thus help improve the battery efficiency, production yield, and bifaciality. Attached Figure Description

[0049] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this disclosure and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1 is a schematic diagram of the structure of the silicon substrate provided in Embodiment 1 of this disclosure;

[0051] Figure 2 is a schematic diagram of the structure of Embodiment 1 of this disclosure, in which a first semiconductor layer and a mask layer are sequentially formed on the back side;

[0052] Figure 3 is a schematic diagram of the structure of forming a textured surface on the light-receiving surface in Embodiment 1 of this disclosure;

[0053] Figure 4 is a schematic diagram of the structure of the passivation layer and the antireflection layer formed on the light-receiving surface in Embodiment 1 of this disclosure;

[0054] Figure 5 is a schematic diagram of the structure of the second semiconductor opening region formed on the back side in Embodiment 1 of this disclosure;

[0055] Figure 6 is a schematic diagram of the structure of wet cleaning and etching in Embodiment 1 of this disclosure;

[0056] Figure 7 is a schematic diagram of the structure in which a second semiconductor layer is formed on the back side in Embodiment 1 of this disclosure;

[0057] Figure 8 is a schematic diagram of the structure of the first semiconductor opening region formed on the back side in Embodiment 1 of this disclosure;

[0058] Figure 9 is a schematic diagram of the structure of the transparent conductive film layer formed on the back side in Embodiment 1 of this disclosure;

[0059] Figure 10 is a schematic diagram of the structure of the isolation groove formed on the back side in Embodiment 1 of this disclosure;

[0060] Figure 11 is a schematic diagram of the structure of forming a metal electrode on the back side in Embodiment 1 of this disclosure.

[0061] Explanation of reference numerals in the attached figures

[0062] 1. Silicon substrate, 2. Tunneling oxide layer, 3. N-type doped polycrystalline silicon layer, 4. Mask layer, 5. Passivation layer, 6. Anti-reflection layer, 7. Amorphous silicon passivation layer, 8. P-type doped amorphous silicon layer, 9. Transparent conductive film layer, 10. Metal electrode. Detailed Implementation

[0063] In this disclosure, unless otherwise stated, directional terms such as "up," "down," "left," and "right" are generally used to refer to the orientation as shown in the accompanying drawings and in practical applications.

[0064] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise expressly specified.

[0065] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0066] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges. For numerical ranges, the endpoint values ​​of the ranges, the endpoint values ​​of the ranges and individual point values, and individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein. The terms "optional" and "discretionary" mean that they may or may not be included (or may or may not be present).

[0067] In this disclosure, the area closest to the silicon substrate is defined as the inside, and the area furthest from the silicon substrate is defined as the outside.

[0068] In a first aspect, this disclosure provides a novel post-texturing method for preparing a combined passivated back contact battery, comprising the following steps:

[0069] S101 provides a double-sided polished silicon substrate;

[0070] S102, A first semiconductor layer and a mask layer are sequentially formed on the back side of a silicon substrate; the first semiconductor layer includes a tunneling oxide layer and a first doped polysilicon layer;

[0071] S103. Perform cleaning and texturing to form a textured surface on the light-receiving surface of the silicon substrate. The maximum height of the pyramid of the textured surface on the light-receiving surface is T1.

[0072] S104. A passivation layer and an antireflection layer are sequentially formed on the light-receiving surface of a silicon substrate;

[0073] S105. A first laser etching opening is formed on the back side obtained in S104 to form a second semiconductor opening region;

[0074] S106. Perform cleaning and etching to form a groove structure at least in the second semiconductor opening region on the back side of the silicon substrate. Control the maximum height between the bottom of the second semiconductor opening region on the back side of the silicon substrate and the top of the first doped polysilicon layer to be T2. The bottom of the groove structure of the second semiconductor opening region may or may not have a pyramid structure and the maximum height of the pyramid is T3, and satisfy T2>T1≥T3, where T3 is 0-6μm.

[0075] S107. Deposit a second semiconductor layer on the back side, the second semiconductor layer comprising an amorphous passivation layer and a second doped silicon layer.

[0076] In this disclosure, the groove structure can be a polished, semi-textured, or texturized structure. A semi-textured structure refers to a non-complete pyramidal textured surface, which can generally be formed by incomplete texturing or by texturing followed by polishing to remove part of the pyramidal texture. When the groove structure is a polished structure, there is a height difference in the pyramidal base after polishing, and T3 refers to the maximum height of the pyramidal base, which can be 0.

[0077] Optionally, T1 is 0.5-10 μm, more preferably 0.5-4 μm. Using a suitable textured surface for the light-receiving surface is more conducive to reducing the reflectivity of the light-receiving surface, thereby increasing the battery current.

[0078] Optionally, T2 is 2.5-15μm, preferably 5-15μm, and T3 is 0.1-6μm. Employing a second semiconductor opening region with a suitable textured surface structure is more conducive to reducing the reflectivity on the back of the battery, thereby improving the bifaciality of the battery.

[0079] Optionally, the ratio of T2:T1:T3 can be 1.5-50:1-30:1, specifically for values ​​such as 1.5:1:1, 2:1:1, 2:10:1, 20:10:1, 4:2:1, 3:2:1, 6:2:1, 9:3:1, 50:30:1, and any range between two values. The combination of a suitable textured surface on the light-receiving surface and the second semiconductor opening region further improves the battery's short-circuit current, thereby increasing battery efficiency.

[0080] Optionally, the conditions for cleaning and texturing in S103 to obtain T1 include: texturing with an alkaline solution containing texturing additives, wherein the mass concentration of alkali in the alkaline solution is 0.5wt%-5wt%, the mass content of texturing additives is 0.05wt%-2wt%, the temperature of the alkaline solution is 60-85℃, and the treatment time is 5-15min.

[0081] Optionally, the cleaning etching in S106 may include any one of texturing, polishing, texturing after polishing, or polishing after texturing.

[0082] Optionally, S106 further includes a step of removing at least a portion of the mask layer thickness after cleaning and etching, more preferably removing the entire mask layer.

[0083] Optionally, in S106, the groove structure within the second semiconductor opening region is a polished, semi-textured, or texturized structure. When the groove structure is polished or semi-textured, T3 is 0.1-3 μm; when the groove structure is texturized, T3 is 1-6 μm. Optionally, T3 when the groove structure is polished or semi-textured is smaller than T3 when the groove structure is texturized.

[0084] In some specific embodiments, the groove structure in the second semiconductor opening region in S106 is a polished, semi-textured, or texturized structure. When the groove structure is a polished or semi-textured structure, T3 is 0.1-1 μm, and when the groove structure is a texturized structure, T3 is 1.1-6 μm.

[0085] In some other specific embodiments, the groove structure in the second semiconductor opening region in S106 is a polished, semi-textured, or texturized structure. When the groove structure is a polished or semi-textured structure, T3 is 0.1-3μm, and when the groove structure is a texturized structure, T3 is 3.1-6μm.

[0086] Optionally, the groove structure within the second semiconductor opening region in S106 is a polished or semi-textured structure. The corresponding conditions for cleaning and etching in S106 include: polishing with an alkaline solution or a combination of texturing followed by polishing. A semi-textured structure in the second semiconductor opening region provides better passivation while also ensuring interface contact, thus improving battery efficiency.

[0087] Optionally, the groove structure within the second semiconductor opening region in S106 is a texturing structure. The corresponding conditions for cleaning and etching in S106 include: texturing with an alkaline solution or a combination of polishing followed by texturing. A texturing structure in the second semiconductor opening region provides better contact resistance, which is more conducive to improving the bifaciality of the battery (the power generation efficiency on the back side of the battery).

[0088] Optionally, the polishing process conditions described above each independently include: the mass concentration of alkali in the corresponding alkaline solution is 0.5wt%-5wt%, the alkaline solution contains polishing additives and the mass content of the polishing additives is 0.05wt%-2wt%, the temperature of the alkaline solution is 50-85℃, and the processing time is 0.25-5min.

[0089] Optionally, the above-mentioned process conditions for fabrication each independently include: the mass concentration of alkali in the corresponding alkaline solution is 0.5wt%-5wt%, the alkaline solution contains fabrication additives and the mass content of the fabrication additives is 0.05wt%-2wt%, the temperature of the alkaline solution is 60-85℃, and the processing time is 2-12min.

[0090] In this disclosure, the process conditions can be selected from the above-mentioned corresponding process conditions according to the required degree of polishing or texturing, as long as the desired degree of polishing or texturing is obtained.

[0091] Optionally, the thickness of the tunneling oxide layer is 1-2 nm, and the thickness of the first doped polysilicon layer is 60-200 nm with an effective doping concentration of 5e19 cm⁻¹. -3 -5e20cm -3 .

[0092] Optionally, the amorphous passivation layer has a thickness of 3-10 nm, and the second doped silicon layer has a thickness of 5-40 nm and an effective doping concentration of 5e18 cm⁻¹. -3 -2e20cm -3 .

[0093] Optionally, the mask layer is a silicon dielectric layer, which includes at least one of silicon oxide, silicon nitride, and silicon oxynitride, which is more conducive to the laser opening in step S105.

[0094] Optionally, the thickness of the mask layer is 10-80 nm.

[0095] Optionally, the passivation layer includes at least one of silicon oxide, amorphous silicon, and aluminum oxide, which is more conducive to improving the passivation effect.

[0096] Optionally, the antireflection layer is a silicon dielectric film, which includes at least one of silicon nitride, silicon oxynitride, and silicon oxide, and is more conducive to reducing the reflectivity of the light-receiving surface of the silicon substrate.

[0097] Optionally, the passivation layer thickness is 2-30nm, which is more conducive to improving the passivation effect.

[0098] Optionally, the thickness of the antireflective layer is 50-180nm, which is more conducive to reducing the reflectivity of the light-receiving surface.

[0099] In this disclosure, the second doped silicon layer can be doped amorphous silicon or microcrystalline silicon.

[0100] In this disclosure, one of the first doped polycrystalline silicon layer and the other of the second doped silicon layer is N-type and P-type, respectively.

[0101] In S102, the first semiconductor layer and the mask layer can be formed by tubular PECVD deposition followed by annealing, LPCVD deposition followed by diffusion, or other feasible existing methods. Preferably, they are formed by tubular PECVD deposition followed by annealing.

[0102] Optionally, the novel post-texturing method for the combined passivated back contact battery further includes: S108, performing a second etching opening on a portion of the second semiconductor layer on the back side of the silicon substrate to form a first semiconductor opening region spaced apart from the second semiconductor opening region.

[0103] Optionally, the novel post-texturing method for the combined passivated back contact battery further includes:

[0104] S109. Deposit a conductive film layer on the back side obtained in S108;

[0105] S110. A third etching opening is made on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation trench.

[0106] S111, metal electrodes are formed on the outer surfaces of the corresponding conductive film layers in the regions where the first semiconductor opening region and the second semiconductor opening region are located, respectively.

[0107] In this disclosure, the widths of the first semiconductor opening region, the second semiconductor opening region, and the isolation trench can be determined with reference to the range of the prior art and according to actual needs. For example, the width W1 of the second semiconductor opening region can be 300-700 μm, the width W2 of the first semiconductor opening region can be 100-400 μm, and the width W3 of the isolation trench can be, for example, 20-100 μm.

[0108] Secondly, this disclosure provides a combined passivated back contact battery, which is prepared by the novel post-texturing method for the combined passivated back contact battery described in the first aspect.

[0109] The embodiments of this disclosure described below are exemplary and are only used to explain this disclosure, and should not be construed as limiting this disclosure.

[0110] Example 1

[0111] A back-contact battery is prepared by the following method:

[0112] S101, As shown in Figure 1, a double-sided polished N-type silicon substrate 1 is provided;

[0113] S102, as shown in Figure 2, a first semiconductor layer and a mask layer 4 are sequentially formed on the back side of the silicon substrate 1. The first semiconductor layer includes a tunneling oxide layer 2 and an N-type doped polysilicon layer 3, and the mask layer 4 is a silicon dielectric layer (silicon oxide). The first semiconductor layer and mask layer are formed by tubular PECVD deposition followed by annealing. The tunneling oxide layer 2 has a thickness of 1.5 nm, and the N-type doped polysilicon layer 3 has a thickness of 130 nm and an effective doping concentration of 1e20 cm⁻¹. -3 The thickness of mask layer 4 is 60nm.

[0114] S103. As shown in Figure 3, cleaning and texturing are performed to form a textured surface on the light-receiving surface of the silicon substrate 1. The cleaning and texturing conditions are as follows: alkaline solution is used for texturing, the mass concentration of alkali in the alkaline solution is 2wt%, the content of texturing additive is 0.2%, the temperature of the alkaline solution is 75℃, and the processing time is 7min. The maximum height of the pyramid after texturing on the light-receiving surface of the silicon substrate 1 is T1, and the height of T1 is 3μm.

[0115] S104. As shown in Figure 4, a passivation layer 5 and an antireflection layer 6 are formed on the light-receiving surface of the silicon substrate 1. The passivation layer 5 is aluminum oxide with a thickness of 4 nm, and the antireflection layer 6 is silicon nitride with a thickness of 75 nm.

[0116] S105. As shown in Figure 5, a first laser etching opening is made on the back side obtained in S104 to form a second semiconductor opening region. The width W1 of the second semiconductor opening region is 500μm.

[0117] S106. As shown in Figure 6, wet cleaning and etching are performed on the second semiconductor opening area on the back side of silicon substrate 1. The cleaning and etching is formed by texturing with an alkaline solution followed by polishing. The texturing process conditions include: using an alkaline solution for texturing, with an alkaline concentration of 2 wt%, a texturing additive content of 0.2 wt%, an alkaline solution temperature of 80°C, and a processing time of 10 min. The polishing process conditions include: an alkaline concentration of 3 wt%, a polishing additive content of 0.5 wt%, an alkaline solution temperature of 75°C, and a processing time of 15 s.

[0118] The maximum height T2 between the bottom of the second semiconductor opening region on the back side of the silicon substrate 1 and the top of the N-type doped polycrystalline silicon layer 3 is 6 μm. The groove structure in the second semiconductor opening region is a semi-textured structure. The maximum height of the semi-textured structure is T3, and the height of T3 is 1.5 μm. T2 > T1 > T3. After conversion, T2:T1:T3 is 4:2:1.

[0119] S107, as shown in Figure 7, a second semiconductor layer is deposited on the back side obtained in S106. The second semiconductor layer includes an amorphous silicon passivation layer 7 with a thickness of 5 nm and a P-type doped amorphous silicon layer 8. The P-type doped amorphous silicon layer 8 has a thickness of 8 nm and an effective doping concentration of 1e19 cm⁻¹. -3 ;

[0120] S108. As shown in Figure 8, a second etching is performed on a portion of the second semiconductor layer on the back side of the silicon substrate to form a first semiconductor opening region that is spaced apart from the second semiconductor opening region. The width W2 of the first semiconductor opening region is 300 μm.

[0121] S109, As shown in Figure 9, a transparent conductive film layer 9 is deposited on the back side obtained in S108;

[0122] S110, As shown in Figure 10, a third etching is performed on the portion of the transparent conductive film layer 9 located between the first semiconductor opening region and the second semiconductor opening region to form an isolation trench, wherein the width W3 of the isolation trench is 50 μm.

[0123] S111 As shown in Figure 11, metal electrodes 10 are formed on the outer surfaces of the corresponding transparent conductive film layers 9 in the regions where the first semiconductor opening region and the second semiconductor opening region are located, respectively.

[0124] Example 2

[0125] The method is carried out in accordance with Example 1, except that T3 is adjusted to be equal to T1 and to form a flocking structure. To meet this condition, process S106 needs to be adjusted as follows:

[0126] S106. Perform wet cleaning and etching, using an alkaline polishing followed by texturing process. The polishing conditions include: an alkaline concentration of 3 wt%, a polishing additive content of 0.5 wt%, an alkaline solution temperature of 75°C, and a processing time of 50 seconds. The texturing conditions include: an alkaline concentration of 2 wt%, a texturing additive content of 0.2 wt%, an alkaline solution temperature of 75°C, and a processing time of 7 minutes. T2 remains unchanged.

[0127] Example 3

[0128] The method described in Example 1 is followed, except that T2 is adjusted to 4.5 μm. To meet this condition, the process needs to be adjusted as follows: S106, the cleaning and etching process uses an alkaline solution for texturing followed by polishing, resulting in a semi-textured groove structure. The texturing process conditions include: using an alkaline solution with an alkali concentration of 2 wt%, a texturing additive content of 0.2 wt%, an alkaline solution temperature of 80°C, and a processing time of 7 min. The polishing process conditions include: an alkali concentration of 3 wt%, a polishing additive content of 0.5 wt%, an alkaline solution temperature of 75°C, and a processing time of 15 s. The calculated ratio of T2:T1:T3 is 3:2:1.

[0129] Example 4

[0130] The method is performed according to Example 1, except that the groove structure of the second semiconductor opening region is adjusted to a polished structure. To meet this condition, the process needs to be adjusted: S106, the second semiconductor opening region on the back side of the silicon substrate 1 is cleaned and etched. The cleaning and etching conditions are alkaline polishing. The polishing process conditions include: the mass concentration of alkali in the alkaline solution is 3wt%, the content of polishing additive is 0.5wt%, the temperature of the alkaline solution is 75°C, and the processing time is 3min. The maximum height T3 of the tower base after polishing is 0.3μm, and the calculated T2:T1:T3 is 20:10:1.

[0131] Example 5

[0132] The method is performed according to Example 2, except that the groove structure of the second semiconductor opening region is adjusted to a texturing structure. To meet this condition, the process needs to be adjusted: S106, wet cleaning and etching are performed, and the etching process adopts alkaline polishing followed by texturing. The polishing process conditions include: the mass concentration of alkali in the alkaline solution is 3wt%, the content of polishing additive is 0.5wt%, the temperature of the alkaline solution is 75°C, and the processing time is 120s. The texturing process conditions include: the mass concentration of alkali in the alkaline solution is 2wt%, the content of texturing additive is 0.2wt%, the temperature of the alkaline solution is 75°C, and the processing time is 7min; T2 is 9μm, and the calculated T2:T1:T3 is 6:2:1.

[0133] Example 6

[0134] The method described in Example 1 was followed, except that the groove structure was adjusted to a semi-textured structure and the height of T2 was different. Specifically, the groove was formed by first texturing with an alkaline solution and then polishing. The texturing process conditions included: using an alkaline solution with an alkali concentration of 2 wt%, a texturing additive content of 0.2 wt%, an alkaline solution temperature of 80°C, and a processing time of 10 min. The polishing process conditions included: an alkali concentration of 3 wt%, a polishing additive content of 0.5 wt%, an alkaline solution temperature of 75°C, and a processing time of 30 s. T3 was 1 μm, and T2 was 9 μm, resulting in a T2:T1:T3 ratio of 9:3:1.

[0135] Comparative Example 1

[0136] The method is the same as in Example 1, except that steps S103 to S106 are omitted, and instead a conventional post-flocking process is used. Specifically, after S102, the following steps are performed:

[0137] A first laser etching opening is made on the back side obtained in S102 to form a second semiconductor opening region. The width of the second semiconductor opening region is the same as in Example 1.

[0138] Then, texturing and cleaning are performed to form a textured surface on both the light-receiving surface of the silicon substrate and the second semiconductor opening area. The maximum height of the pyramid on the textured surface is 3μm. After that, all mask layers outside the second semiconductor opening area on the back side of the silicon substrate are removed.

[0139] A passivation layer and an antireflection layer are formed on the light-receiving surface of a silicon substrate. The thickness and material of the passivation layer and the antireflection layer are the same as in Example 1.

[0140] Single-sided etching removes the coating layer formed on the back side of the silicon substrate during deposition on the light-receiving surface. Hydrofluoric acid is used for single-sided etching.

[0141] After routine RCA cleaning, the interface cleanliness of the second semiconductor opening area on the back side of the silicon substrate meets the requirements for depositing the second semiconductor layer. The routine RCA cleaning conditions are: sequential cleaning with alkaline hydrogen peroxide, hydrochloric acid hydrogen peroxide, and hydrofluoric acid.

[0142] Then proceed to S107 of Example 1 and its subsequent steps.

[0143] Comparative Example 2

[0144] The method is the same as in Example 1, except that T2 is adjusted to be less than T1. To meet this condition, the process needs to be adjusted as follows: S106, wet cleaning and etching are performed, and the etching process adopts a texturing process. The texturing process conditions include: the mass concentration of alkali in the alkaline solution is 2wt%, the content of texturing additive is 0.2wt%, the temperature of the alkaline solution is 75°C, and the processing time is 5min; T2 is 2μm.

[0145] Comparative Example 3

[0146] The method is the same as in Example 1, except that the structure of the first semiconductor layer is different. The passivation structure is a heterojunction. Specifically, the first semiconductor layer is an intrinsic amorphous silicon layer and an N-type doped amorphous silicon layer. The thickness of the intrinsic amorphous silicon layer is 6 nm, and the thickness of the N-type doped amorphous silicon layer is 15 nm with an effective doping concentration of 5e19 cm⁻¹. -3 .

[0147] Test case

[0148] The back contact batteries obtained in the above embodiments and comparative examples were subjected to performance tests, and the results are shown in Table 1.

[0149] The second semiconductor opening region interface contact resistance refers to the contact resistance between the silicon substrate and the second semiconductor layer within the second semiconductor opening region. It is obtained by testing the battery after depositing the second semiconductor layer and forming the metal electrode using the TLM method (Transmission Line Model). The interface contact resistances of the second semiconductor opening regions in each embodiment and comparative example are calculated using Embodiment 1 as a reference. The interface contact resistance data for the second semiconductor opening region in Embodiment 1 is a normalized reference of 1. Other examples are calculated based on Embodiment 1; for instance, the ratio of the interface contact resistance of the second semiconductor opening region in Comparative Example 1 to the interface contact resistance of the second semiconductor opening region in Embodiment 1 is 2.

[0150] Bifaciality refers to the ratio of battery efficiency when light enters from the back of the battery versus when light enters from the light-receiving side of the battery under standard test conditions.

[0151] Table 1

[0152] The results above show that, compared with the comparative example, the embodiment of this disclosure can reduce the interface contact resistance of the second semiconductor opening region, improve minority carrier lifetime, and improve battery efficiency and bifaciality while simplifying process steps and reducing material costs.

[0153] Furthermore, as can be seen from Embodiments 1 and 2-6, the preferred scheme of this disclosure is more conducive to reducing the interface contact resistance of the second semiconductor opening region, improving minority carrier lifetime, and improving battery efficiency and bifaciality.

[0154] The preferred embodiments of this disclosure have been described in detail above; however, this disclosure is not limited thereto. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, including combining the various technical features in any other suitable manner. These simple modifications and combinations should also be considered as the content disclosed in this disclosure and are all within the protection scope of this disclosure. Industrial applicability

[0155] This disclosure discloses separate wet etching of the light-receiving and back sides of a silicon substrate, allowing for independent control of surface morphology, which is beneficial for improving cell efficiency. Conventional silicon substrates, after forming passivation and antireflection layers on the light-receiving side, suffer from significant back-side coating. The method disclosed here eliminates the need to remove the back-side coating for texturing or cleaning, simplifying the process. Because conventional methods cause some damage after the first laser etching opening on the back side of the silicon substrate, requiring a large etching amount for complete removal, while the light-receiving side of the silicon substrate does not have a damaged layer, the separate etching of the light-receiving and back sides using the method disclosed here reduces the etching amount on the silicon substrate, lowers material costs, and simultaneously helps reduce the interface contact resistance of the second semiconductor opening region, improving minority carrier lifetime, cell efficiency, and bifaciality. In this disclosure, the interface of the second semiconductor opening region of the silicon substrate is immediately deposited after wet cleaning and etching. The interface between the second semiconductor layer and the silicon substrate is very clean, preventing contamination and thus improving production yield and bifaciality. This disclosure controls the textured surface structure of the light-receiving surface and the structure of the second semiconductor opening region, such that T2 > T1 ≥ T3. It can independently control the etching amount of the light-receiving surface and the corresponding opening region on the back side of the silicon substrate, improve the cleanliness of the interface of the back opening region, and thus help reduce the thickness of the silicon substrate (because the etching amount is reduced, the thickness of the silicon substrate before processing can be appropriately thinned while maintaining the consistency of the silicon substrate thickness after processing, which is expected to reduce by 5-10 μm), improve the passivation and contact effect of the silicon substrate, and thus help improve the battery efficiency, production yield, and bifaciality.

Claims

1. A novel post-texturing method for preparing a combined passivated back contact battery, characterized in that, Includes the following steps: S101 provides a double-sided polished silicon substrate; S102, A first semiconductor layer and a mask layer are sequentially formed on the back side of a silicon substrate; the first semiconductor layer includes a tunneling oxide layer and a first doped polysilicon layer; S103. Perform cleaning and texturing to form a textured surface on the light-receiving surface of the silicon substrate. The maximum height of the pyramid of the textured surface on the light-receiving surface is T1. S104. A passivation layer and an antireflection layer are sequentially formed on the light-receiving surface of a silicon substrate; S105. A first laser etching opening is formed on the back side obtained in S104 to form a second semiconductor opening region; S106. Perform cleaning and etching to form a groove structure at least in the second semiconductor opening region on the back side of the silicon substrate. Control the maximum height between the bottom of the second semiconductor opening region on the back side of the silicon substrate and the top of the first doped polysilicon layer to be T2. The bottom of the groove structure of the second semiconductor opening region may or may not have a pyramid structure and the maximum height of the pyramid is T3, and satisfy T2>T1≥T3, where T3 is 0-6μm. S107. Deposit a second semiconductor layer on the back side, the second semiconductor layer comprising an amorphous passivation layer and a second doped silicon layer.

2. The novel post-texturing preparation method for a combined passivated back contact battery according to claim 1, characterized in that, T1 is 0.5-10 μm, and / or, T2 is 2.5-15 μm, and T3 is 0.1-6 μm.

3. The novel post-texturing preparation method for a combined passivated back contact battery according to claim 1 or 2, characterized in that, The ratio of T2:T1:T3 is 1.5-50:1-30:

1.

4. The novel post-texturing preparation method for a combined passivated back contact battery according to claim 1, characterized in that, The conditions for cleaning and texturing in S103 to obtain T1 include: texturing with an alkaline solution containing texturing additives, wherein the mass concentration of alkali in the alkaline solution is 0.5wt%-5wt%, the mass content of texturing additives is 0.05wt%-2wt%, the temperature of the alkaline solution is 60-85℃, and the treatment time is 5-15min.

5. The novel post-texturing preparation method for a combined passivated back contact battery according to claim 1, characterized in that, S106 includes any one of texturing, polishing, texturing after polishing, and polishing after texturing. S106 also includes a step of removing a mask layer of at least a portion of its thickness after cleaning and etching. And / or, In S106, the groove structure in the second semiconductor opening region is a polished, semi-textured, or texturized structure. When the groove structure is a polished or semi-textured structure, T3 is 0.1-3μm, and when the groove structure is a texturized structure, T3 is 1-6μm.

6. The novel post-texturing preparation method for a combined passivated back contact battery according to claim 1, characterized in that, The groove structure in the second semiconductor opening region of S106 is a polished or semi-textured structure. The corresponding conditions for cleaning and etching in S106 include: polishing with alkaline solution or forming by combining texturing and polishing. And / or, The groove structure in the second semiconductor opening region of S106 is a texturing structure. The corresponding conditions for controlling the cleaning and etching in S106 include: texturing with alkaline solution or a combination of polishing and texturing.

7. The novel post-texturing preparation method for a combined passivated back contact battery according to claim 6, characterized in that, The polishing process conditions include: the mass concentration of alkali in the corresponding alkaline solution is 0.5wt%-5wt%, the alkaline solution contains polishing additives and the mass content of the polishing additives is 0.05wt%-2wt%, the temperature of the alkaline solution is 50-85℃, and the treatment time is 0.25-5min; The process conditions for texturing include: the mass concentration of alkali in the corresponding alkaline solution is 0.5wt%-5wt%, the alkaline solution contains texturing additives with a mass content of 0.05wt%-2wt%, the temperature of the alkaline solution is 60-85℃, and the processing time is 2-12min.

8. The novel post-texturing preparation method for a combined passivated back contact battery according to claim 1, characterized in that, The novel post-texturing method for preparing the combined passivated back contact battery also satisfies at least one of the following conditions: Condition 1: The thickness of the tunneling oxide layer is 1-2 nm, the thickness of the first doped polysilicon layer is 60-200 nm, and the effective doping concentration is 5e19cm. -3 -5e20cm -3 The amorphous passivation layer has a thickness of 3-10 nm, and the second doped silicon layer has a thickness of 5-40 nm and an effective doping concentration of 5e18 cm⁻¹. -3 -2e20cm -3 ; Condition 2: The mask layer is a silicon dielectric layer, which includes at least one of silicon oxide, silicon nitride, and silicon oxynitride. Condition 3: The thickness of the mask layer is 10-80 nm; Condition 4: The passivation layer includes at least one of silicon oxide, amorphous silicon, and aluminum oxide; the antireflection layer is a silicon dielectric film, which includes at least one of silicon nitride, silicon oxynitride, and silicon oxide. Condition 5: The thickness of the passivation layer is 2-30 nm, and the thickness of the antireflection layer is 50-180 nm.

9. The novel post-texturing preparation method for a combined passivated back contact battery according to claim 1, characterized in that, The novel post-texturing preparation method for the combined passivated back contact battery also includes: S108. A second etching opening is made on a portion of the second semiconductor layer on the back side of the silicon substrate to form a first semiconductor opening region that is spaced apart from the second semiconductor opening region. S109. Deposit a conductive film layer on the back side obtained in S108; S110. A third etching opening is made on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation trench. S111, metal electrodes are formed on the outer surfaces of the corresponding conductive film layers in the regions where the first semiconductor opening region and the second semiconductor opening region are located, respectively.

10. A combined passivated back contact battery, characterized in that, It is prepared by a novel post-texturing method for combined passivation of back contact cells as described in any one of claims 1-9.

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