Chip package structure and manufacturing method therefor, terminal device, and chip package substrate
By setting grooves and vias on the substrate and establishing electrical connections between wiring layers on both sides of the substrate, the problem of unsatisfactory electrical connection effect in chip stacking packaging structure is solved, achieving high yield, low cost and high reliability chip packaging.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- JIANGSU HUIXIAN DISPLAY TECHNOLOGY CO LTD
- Filing Date
- 2025-12-31
- Publication Date
- 2026-07-16
AI Technical Summary
In existing chip stacking packaging structures, the electrical connection between chips is not ideal, resulting in low yield, high cost and poor reliability of the packaging structure.
The design employs recesses and vias on the substrate, and wiring layers are set on both sides of the substrate. Electrical connections between chips are achieved using interconnects, avoiding the need for holes in the chips. This design also allows for the stacking of chips of different sizes and signal integration.
It improves the yield and reliability of the packaging structure, reduces costs, enhances integration and functional diversity, shortens signal transmission distance, and improves operating speed and sensitivity.
Smart Images
Figure CN2025148150_16072026_PF_FP_ABST
Abstract
Description
Chip packaging structure and its fabrication method, terminal equipment and chip packaging substrate Technical Field
[0001] This disclosure relates to the field of semiconductor technology, specifically to chip packaging structures and their fabrication methods, terminal devices, and chip packaging substrates. Background Technology
[0002] A recent trend in the semiconductor industry is towards products with high integration, thinness, lightness, speed, multifunctionality, and high efficiency, resulting in high reliability. To meet these trends, chip stacking packaging technology is considered a crucial technology in the semiconductor field, currently typically involving stacking chips within a package structure. In chip stacking packaging structures, multiple chips need to be electrically connected to each other. Currently, this is mainly achieved using through-electrodes that penetrate the chip; however, due to limitations in related technologies, the current packaging structures do not achieve ideal chip stacking performance. Summary of the Invention
[0003] In view of this, the present disclosure provides a chip packaging structure and its preparation method, a terminal device, and a chip packaging carrier.
[0004] The first aspect of this disclosure provides a chip packaging structure, including:
[0005] The substrate has a first side and a second side disposed opposite to each other in a first direction; the substrate includes at least one first groove and a plurality of through holes, the opening of the first groove is located on the first side, and the through holes penetrate the bottom wall of the first groove along the first direction;
[0006] At least one first chip is located in a first recess, with the surface of the first chip having pins facing the second side;
[0007] At least one second chip is located on the second side of the substrate, with the surface of the second chip having pins facing the first side;
[0008] The first wiring layer is located on the first side of the substrate and is electrically connected to the pins of the first chip.
[0009] The second wiring layer, located on the second side of the substrate, is electrically connected to the pins of the second chip; and
[0010] The connecting line is located in the through hole and is electrically connected to the first wiring layer and the second wiring layer.
[0011] A second aspect of this disclosure provides a chip packaging structure, including:
[0012] The substrate includes at least one first groove and a plurality of through holes, the through holes being connected to the first groove;
[0013] At least one first chip and at least one second chip, the first chip and the second chip being located on opposite sides of a substrate; at least one first chip being located in a first recess; a through-hole being located between the first chip and the second chip;
[0014] A wiring layer, located on at least one side of the substrate, is electrically connected to a first chip and a second chip; and
[0015] The connecting wire is located in the through-hole and is electrically connected to the wiring layer.
[0016] The third aspect of this disclosure provides a method for fabricating a chip packaging structure, including:
[0017] At least one first groove is formed on the first side of the base;
[0018] Multiple through holes are made on the bottom wall of the first groove, and the through holes penetrate the bottom wall of the first groove along the first direction;
[0019] Fabricate connecting wires in through holes;
[0020] A first wiring layer is prepared on a first side of the substrate, and a second wiring layer is prepared on a second side of the substrate. The first wiring layer and the second wiring layer are electrically connected by a connecting line, and the first side and the second side are arranged opposite to each other in a first direction.
[0021] At least one first chip is disposed in a first groove, and at least one second chip is disposed on a second side of the substrate. The surface of the first chip with pins faces the second side, and the surface of the second chip with pins faces the first side. A first wiring layer is electrically connected to the pins of the first chip, and a second wiring layer is electrically connected to the pins of the second chip.
[0022] The fourth aspect of this disclosure provides a method for fabricating a chip packaging structure, including:
[0023] At least one first groove is formed on the first side of the base;
[0024] Multiple through holes are made on the bottom wall of the first groove, and the through holes penetrate the bottom wall of the first groove along the first direction;
[0025] A connecting line is prepared in the through hole; optical adhesive is filled in the first groove, and optical adhesive is prepared on the second side of the substrate and the first side being disposed opposite to each other in the first direction; the optical adhesive is patterned.
[0026] The first and fourth parts are prepared on the surface of the patterned optical adhesive, and the first and fourth parts are electrically connected to the connecting wires.
[0027] At least one first chip is disposed in the first groove, and at least one second chip is disposed on the second side of the substrate; the first chip is electrically connected to the first part, and the second chip is electrically connected to the fourth part.
[0028] Fill the first groove with underfill adhesive, and drill holes in the underfill adhesive;
[0029] The second and third layers are prepared on the surface of the bottom filler after drilling, to obtain the first wiring layer.
[0030] The fifth aspect of this disclosure provides a terminal device, including the chip packaging structure described above, or including a chip packaging structure prepared by the preparation method described above.
[0031] The sixth aspect of this disclosure provides a chip packaging carrier board, comprising:
[0032] The substrate has a first side and a second side disposed opposite to each other in a first direction;
[0033] At least one first groove, the opening of the first groove being located on a first side;
[0034] Multiple through holes, which penetrate the bottom wall of the first groove along a first direction;
[0035] The connecting wire is located in the through hole;
[0036] A wiring layer, located on at least one side of the substrate, is electrically connected to the connecting wires.
[0037] According to the packaging structure provided in this disclosure, at least one first chip is disposed in a first recess of the substrate, and at least one second chip is disposed on a second side of the substrate. A first wiring layer is electrically connected to the pins of the first chip, and a second wiring layer is electrically connected to the pins of the second chip. A connecting line is electrically connected to both the first and second wiring layers. This allows for the stacking of multiple chips, avoiding the need for vias in the chips, effectively improving the yield of the packaging structure, reducing costs, and enhancing packaging reliability. Furthermore, the first and second chips can have different sizes, facilitating the stacking of chips of different sizes, improving the integration of the packaging structure, and enabling the integration of signals from different chips, thus giving the packaging structure multiple functions. Attached Figure Description
[0038] Figure 1 is a cross-sectional view of a chip packaging structure in one embodiment of this disclosure.
[0039] Figure 2 is a cross-sectional view of the chip packaging structure in another embodiment of this disclosure.
[0040] Figure 3 is a cross-sectional view of the chip packaging structure in another embodiment of this disclosure.
[0041] Figure 4 is a cross-sectional view of the chip packaging structure in another embodiment of this disclosure.
[0042] Figure 5 is a cross-sectional view of the chip packaging structure in another embodiment of this disclosure.
[0043] Figure 6 is a cross-sectional view of the chip packaging structure in another embodiment of this disclosure.
[0044] Figure 7 is a cross-sectional view of the chip packaging structure in another embodiment of this disclosure.
[0045] Figure 8 is a cross-sectional view of the chip packaging structure in another embodiment of this disclosure.
[0046] Figure 9 is a cross-sectional view of the chip packaging structure in another embodiment of this disclosure.
[0047] Figure 10 is a cross-sectional view of the chip packaging structure in another embodiment of this disclosure.
[0048] Figure 11 is a cross-sectional view of the chip packaging structure in another embodiment of this disclosure.
[0049] Figure 12 is a cross-sectional view of the chip packaging structure in another embodiment of this disclosure.
[0050] Figure 13 is a cross-sectional view of the chip packaging structure in another embodiment of this disclosure.
[0051] Figure 14 is a cross-sectional view of the chip packaging structure in another embodiment of this disclosure.
[0052] Figure 15 is a cross-sectional view of the chip packaging structure in another embodiment of this disclosure.
[0053] Figure 16 is a schematic diagram of the fabrication process of a chip packaging structure in one embodiment of this disclosure.
[0054] Figure 17 is a schematic diagram of the fabrication process of the chip packaging structure in another embodiment of this disclosure.
[0055] Figure 18 is a cross-sectional view of a chip packaging substrate in one embodiment of this disclosure.
[0056] Figure 19 is a cross-sectional view of a chip packaging substrate in another embodiment of this disclosure.
[0057] Figure 20 is a cross-sectional view of a chip packaging substrate in another embodiment of this disclosure. Detailed Implementation
[0058] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.
[0059] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods and means well-known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.
[0060] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0061] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.
[0062] This disclosure provides a chip packaging structure. Referring to the schematic diagrams of the chip packaging structure shown in Figures 1 and 2, the chip packaging structure includes: a substrate 100, the substrate 100 having a first side 110 and a second side 140 disposed opposite each other in a first direction x, the substrate 100 including at least one first recess 120 and a plurality of through holes 130; the opening of the first recess 120 is located on the first side 110, and the through holes 130 penetrate the bottom wall of the first recess 120 along the first direction x; at least one first chip 200 is located in the first recess 120, the first chip 200 having pins. The substrate 100 has a surface facing the second side 140; at least one second chip 300 located on the second side 140 of the substrate 100, the second chip 300 having a pin surface facing the first side 110; a first wiring layer 410 located on the first side 110 of the substrate 100, the first wiring layer 410 being electrically connected to the pins of the first chip 200; a second wiring layer 420 located on the second side 140 of the substrate 100, the second wiring layer 420 being electrically connected to the pins of the second chip 300; and a connecting line 430 located in a via 130 and electrically connected to the first wiring layer 410 and the second wiring layer 420.
[0063] According to the chip packaging structure provided in this disclosure, at least one first chip 200 is disposed in the first recess 120 of the substrate 100, and at least one second chip 300 is disposed on the second side 140 of the substrate 100. A first wiring layer 410 is electrically connected to the pins of the first chip 200, a second wiring layer 420 is electrically connected to the pins of the second chip 300, and a connecting line 430 is electrically connected to both the first wiring layer 410 and the second wiring layer 420. This allows for the stacking of multiple chips, avoids the need for vias in the chips, effectively improves the yield of the chip packaging structure, reduces costs, and enhances packaging reliability. Furthermore, the first chip 200 and the second chip 300 can have different sizes, facilitating the stacking of chips of different sizes, improving the integration of the chip packaging structure, and enabling the integration of signals from different chips, thus giving the chip packaging structure multiple functions.
[0064] The first wiring layer 410 can be metal wiring or metal pads, or it can include both metal wiring and metal pads. The metal pads are used for fixed connection with the first chip 200. The second wiring layer 420 can be metal wiring or metal pads, or it can include both metal wiring and metal pads. The metal pads are used for fixed connection with the second chip 300.
[0065] A first groove 120 is formed in the substrate 100. The opening of the first groove 120 is located on the first side 110. A through hole 130 penetrates the bottom wall of the first groove 120 along the first direction x. A connecting line 430 fills the through hole 130. The distance between the bottom wall of the first groove 120 and the surface of the substrate 100 located on the second side 140 is relatively short, which is beneficial to shorten the signal transmission distance between chips and can improve the operating speed and sensitivity of the chip packaging structure.
[0066] For example, when the second chip 300 is located on the second side 140 of the substrate 100, as shown in FIG1, the surface of the substrate 100 located on the second side 140 is a plane, and the second chip 300 is located on the second side 140; for example, as shown in FIG2, a second groove 150 is formed on the second side 140 of the substrate 100, and the second chip 300 is placed in the second groove 150.
[0067] Grooves are formed on the first side 110 and the second side 140 of the substrate. While ensuring the substrate has high strength, the length of the connecting line 430 is shortened, and the signal transmission distance between the first chip 200 and the second chip 300 is shortened, which can reduce the power consumption of the product.
[0068] In one embodiment, referring to FIG2, the substrate 100 further includes at least one second groove 150, the opening of the second groove 150 being located on the second side 140, and at least one second chip 300 being located in the second groove 150.
[0069] In one embodiment, the orthographic projection of the first groove 120 onto the plane of the substrate 100 at least partially overlaps with the orthographic projection of the second groove 150 onto the plane of the substrate 100. In one embodiment, the through-hole 130 penetrates the bottom walls of the first groove 120 and the second groove 150 along the first direction x. Thus, by creating grooves on opposite sides of the substrate 100, the thickness of the substrate 100 between the bottom walls of the two grooves is reduced, and the length of the connecting line 430 in the first direction x is shortened, which is more conducive to reducing the signal transmission distance between chips and further improving the operating speed and sensitivity of the chip packaging structure.
[0070] There can be multiple first grooves 120 and multiple second grooves 150. Optionally, at least one first chip 200 is located in one first groove 120, and at least one second chip 300 is located in one second groove 150.
[0071] In one embodiment, a first chip 200 is located in a first recess 120, and a second chip 300 is located in a second recess 150. This facilitates chip positioning, and the recesses provide better protection for the chips, improving the reliability of the chip packaging structure.
[0072] In one embodiment, the first chip 200 and the second chip 300 have different sizes. This facilitates the stacking of chips of different sizes, resulting in a high degree of integration in the chip package structure, which can perform the functions of multiple chips.
[0073] Regarding the dimensions of the first chip 200, its orthographic projection onto the plane of the substrate 100 is a quadrilateral, and the dimensions of the first chip 200 include the length and width of the quadrilateral. Regarding the dimensions of the second chip 300, its orthographic projection onto the plane of the substrate 100 is also a quadrilateral, and the dimensions of the second chip 300 include the length and width of the quadrilateral. The difference in dimensions between the first chip 200 and the second chip 300 refers to the following: the length of the orthographic projection of the first chip 200 onto the plane of the substrate 100 is different from the length of the orthographic projection of the second chip 300 onto the plane of the substrate 100, and / or, the width of the orthographic projection of the first chip 200 onto the plane of the substrate 100 is different from the width of the orthographic projection of the second chip 300 onto the plane of the substrate 100.
[0074] In one specific embodiment, referring to the schematic diagram of the chip packaging structure shown in FIG2, a first chip 200 is located in a first recess 120, and multiple second chips 300 are located in a second recess 150. The size of the first chip 200 is larger than the size of the second chip 300. This facilitates the stacking of chips of different sizes, enabling the chip packaging structure to have the functions of different chips, resulting in a high degree of integration.
[0075] In one embodiment, referring to the schematic diagrams of the chip packaging structure shown in Figures 3 and 4, the chip packaging structure further includes a filler layer 500. The filler layer 500 is located in the gap formed by the second chip 300 and the wall of the second recess 150, and / or in the gap formed by the first chip 200 and the wall of the first recess 120. Thus, by filling the gaps between the second chip 300 and the wall of the second recess 150, and between the first chip 200 and the wall of the first recess 120, the filler layer 500 helps to improve the packaging stability of the first chip 200 and the second chip 300, thereby improving the reliability of the chip packaging structure.
[0076] In one embodiment, the first chip 200 includes at least one logic chip located in the first recess 120; the second chip 300 includes a plurality of memory chips.
[0077] In one embodiment, at least one memory chip is located in a second recess 150. Exemplarily, the size of the memory chip is smaller than the size of the logic chip, and multiple memory chips are located in one second recess 150, resulting in a chip package structure with a larger storage space. Exemplarily, having one memory chip located in one second recess 150 facilitates memory chip positioning, and the second recess 150 provides excellent protection for the memory chip.
[0078] In one embodiment, referring to Figures 1 and 2, the first wiring layer 410 includes a first part 411, a second part 412, and a third part 413. The first part 411 is electrically connected to the connecting line 430, the second part 412 is electrically connected to the first part 411, and the third part 413 is located on the first side 110 of the substrate 100 and is electrically connected to the second part 412. Thus, electrical signals from different chips can be transmitted to the first side 110 through the third part 413. The first wiring layer 410 has a simple structure, is easy to wire, and allows for shorter signal transmission distances, resulting in stronger chip packaging performance.
[0079] Part 411 may include a multi-layer wiring structure, and Part 413 may include a multi-layer wiring structure.
[0080] In one embodiment, referring to Figures 1 and 2, the second part 412 is located on the groove wall of the first groove 120, and the groove wall of the first groove 120 is parallel to the first direction x. At this time, the second part 412 is parallel to the first direction x.
[0081] The first direction x is parallel to the direction from the second side 140 to the first side 110.
[0082] In another embodiment, referring to the schematic diagram of the chip packaging structure shown in FIG5, the second part 412 is located on the groove wall of the first groove 120, and the included angle α between the groove wall of the first groove 120 and the first direction x is 30° to 60° (for example, it can be 30°, 40°, 50° or 60°, etc.). Thus, the second part 412 also has an included angle of 30° to 60° with the first direction x, which facilitates the fabrication of the second part 412. In this embodiment, the second part 412 and the third part 413 can be fabricated by electroplating. After filling the first groove 120 with optical adhesive, the optical adhesive can be patterned to obtain patterns corresponding to the second part 412 and the third part 413, and then electroplating can be performed to obtain the second part 412 and the third part 413. Since the second part 412 is located on the groove wall of the first groove 120, that is, the second part 412 is located in the first groove 120, the first groove 120 is used to accommodate the first chip 200. The depth of the first groove 120 is relatively large relative to the thickness that the optical adhesive can fill. Therefore, when the angle α between the groove wall of the first groove 120 and the first direction x is 30° to 60°, it is convenient for the optical adhesive to climb up to the surface of the substrate 100 near the first groove 120, which facilitates the fabrication of the second part 412 and the third part 413. For example, the first chip 200 is a logic chip, the first side 110 is a signal output side, and the arrangement of the first wiring layer 410 helps to shorten the signal output distance of the logic chip, improve the operating speed of the chip packaging structure, and thus improve the performance of the chip packaging structure.
[0083] In the direction from the second side 140 to the first side 110, the groove wall of the first groove 120 gradually moves away from the first chip 200. Multiple second chips 300 are arranged along the second direction y, and the second chips 300 extend along the third direction, intersecting the third direction. Each second chip 300 corresponds to multiple first parts 411, which are spaced apart in the third direction. Among adjacent second chips 300, some first parts 411 are interconnected to expand the chip packaging structure, and some first parts 411 can also be electrically connected to the first chip 200 (see the schematic diagram of the chip packaging structure shown in Figure 6 for details), thus enabling electrical signal communication between the first chip 200 and the second chip 300.
[0084] The plane formed by the second direction y and the third direction is parallel to the plane containing the base 100. The first direction x and the second direction y are perpendicular to each other.
[0085] The second wiring layer 420 includes a plurality of fourth parts 421, which are electrically connected to the pins of the second chip 300.
[0086] In one embodiment, referring to the schematic diagram of the chip packaging structure shown in FIG7, the first chip 200 includes a first chip body 210 and a first conductive structure 220. The first conductive structure 220 is located on the surface of the first chip body 210, and the first chip body 210 is electrically connected to the first wiring layer 410 through the first conductive structure 220. The second chip 300 includes a second chip body 310 and a second conductive structure 320. The second conductive structure 320 is located on the surface of the second chip body 310, and the second chip body 310 is electrically connected to the second wiring layer 420 through the second conductive structure 320.
[0087] In one embodiment, referring to the schematic diagram of the chip packaging structure shown in FIG7, the chip packaging structure further includes: a first protective layer 600 located on a first side 110 of the substrate 100, wherein the orthographic projection of the first protective layer 600 on the plane of the substrate 100 covers the orthographic projection of the first chip 200 on the plane of the substrate 100. This helps to improve the reliability of the chip packaging structure.
[0088] In one embodiment, the first protective layer 600 covers the third part 413. Optionally, the material of the first protective layer includes at least one of polyimide (PI), aromatic benzocyclobutene film (ABF), and bismaleimide-triazine (BT) resin.
[0089] In one embodiment, referring to FIG8, the chip package structure further includes a conductive structure 700 located on the side of the third part 413 facing away from the substrate 100, and the conductive structure 700 is electrically connected to the third part 413. The conductive structure 700 can be a conductive terminal, thereby enabling the transmission of electrical signals in the chip package structure to subsequent structures.
[0090] In one embodiment, the conductive structure 700 is partially embedded in the first protective layer 600. This helps to improve the stability of the chip packaging structure.
[0091] In one embodiment, the substrate 100 is made of glass. Glass has a high load-bearing capacity, resulting in strong stability of the chip packaging structure; moreover, glass is relatively inexpensive.
[0092] In one embodiment, referring to the schematic diagram of the chip package structure shown in FIG9, the second wiring layer 420 includes a fourth part 421, a fifth part 422, and a sixth part 423 connected in sequence. The fourth part 421 is electrically connected to the connecting line 430, the fifth part 422 is electrically connected to the fourth part 421, and the sixth part 423 is located on the second side 140 of the substrate 100 and is electrically connected to the fifth part 422. Thus, electrical signals from different chips can be transmitted to the second side 140 through the sixth part 423. The second wiring layer 420 has a simple structure, is easy to wire, and has a short transmission distance for electrical signals, resulting in strong performance of the chip package structure.
[0093] Part 421 may include a multi-layer wiring structure, and Part 623 may include a multi-layer wiring structure.
[0094] In one embodiment, the fifth part 422 is located on the wall of the second groove 150, and the wall of the second groove 150 is parallel to the first direction x. In this case, the fifth part 422 is parallel to the first direction x.
[0095] In another embodiment, referring to FIG10, the fifth part 422 is located on the groove wall of the second groove 150, and the included angle β between the groove wall of the second groove 150 and the first direction x is 30° to 60° (for example, it can be 30°, 40°, 50° or 60°, etc.). Thus, the fifth part 422 also has an included angle of 30° to 60° with the first direction x, which facilitates the manufacture of the fifth part 422. In this embodiment, the fifth part 422 and the sixth part 423 can be fabricated by electroplating. After filling the second groove 150 with optical adhesive, the optical adhesive can be patterned to obtain the patterns corresponding to the fifth part 422 and the sixth part 423, and then electroplating can be performed to obtain the fifth part 422 and the sixth part 423. Since the fifth part 422 is located on the groove wall of the second groove 150, that is, the fifth part 422 is located in the second groove 150, the second groove 150 is used to accommodate the second chip 300. The depth of the second groove 150 is relatively large relative to the thickness that the optical adhesive can fill. Therefore, when the angle β between the groove wall of the second groove 150 and the first direction x is 30° to 60°, it is convenient for the optical adhesive to climb up to the surface of the substrate 100 near the second groove 150, which facilitates the fabrication of the fifth part 422 and the sixth part 423.
[0096] In the direction from the first side 110 to the second side 140, the groove wall of the second groove 150 gradually moves away from the second chip 300.
[0097] In one embodiment, referring to FIG11, the chip package structure further includes a filler layer 500, which is located in the gap formed by the second chip 300 and the second recess 150, and / or in the gap formed by the first chip 200 and the first recess 120. Thus, by using the filler layer 500 to fill the gaps between the second chip 300 and the second recess 150 and between the first chip 200 and the first recess 120, the packaging stability of the first chip 200 and the second chip 300 is improved, thereby enhancing the reliability of the chip package structure.
[0098] In one embodiment, referring to FIG12, the chip packaging structure further includes a second protective layer 800 located on the second side of the substrate 100, wherein the orthographic projection of the second protective layer 800 on the plane of the substrate 100 covers the orthographic projection of the second chip 300 on the plane of the substrate 100. This improves the reliability of the chip packaging structure.
[0099] In one embodiment, the second protective layer 800 covers the sixth part 423. Optionally, the material of the second protective layer includes at least one of polyimide (PI), aromatic benzocyclobutane film (ABF), and bismaleimide triazine (BT) resin.
[0100] In one embodiment, referring to FIG13, the chip package structure further includes a conductive structure 700 located on the side of the sixth part 423 facing away from the substrate 100, and the conductive structure 700 is electrically connected to the sixth part 423. Thus, electrical signals in the chip package structure can be transmitted to subsequent structures through the conductive structure 700.
[0101] In one embodiment, the conductive structure 700 is partially embedded in the second protective layer 800. This helps to improve the stability of the chip packaging structure.
[0102] For example, the surface of the substrate 100 located on the second side 140 is planar. In one embodiment, referring to the schematic diagram of the chip packaging structure shown in FIG14, the chip packaging structure further includes: a sealing layer 900 located on the side of the second chip 300 facing away from the substrate 100, the sealing layer 900 covering the second chip 300 and in close contact with the substrate 100. Therefore, without creating a groove on the second side 140 of the substrate 100, the second chip 300 can be directly disposed on the second side 140, and the sealing layer 900 can be used to encapsulate the second chip 300, reducing the process of creating a second groove 150 in the substrate 100 and lowering the manufacturing difficulty.
[0103] In one embodiment, referring to the schematic diagram of the chip packaging structure shown in FIG15, the second chip 300 includes a first sub-chip 301 and a second sub-chip 302, which have different functions. Therefore, chips with different functions can be integrated into the chip packaging structure, resulting in a more powerful chip packaging structure.
[0104] In one embodiment, the first wiring layer 410 includes a first part 411, a second part 412, and a third part 413, and the second wiring layer 420 includes a fourth part 421. The first part 411 and the fourth part 421 are electrically connected to the connecting line 430, the second part 412 is electrically connected to the first part 411, the third part 413 is located on the first side 110 of the substrate 100 and is electrically connected to the second part 412; the fourth part 421 is electrically connected to the first sub-chip 301 and the second sub-chip 302, and the first part 411 is electrically connected to the first chip 200.
[0105] In one embodiment, a second recess 150 includes at least one first sub-chip 301 and at least one second sub-chip 302; and / or, a second recess 150 includes at least one first sub-chip 301, and another second recess 150 includes at least one second sub-chip 302. This facilitates the integration of different types of chips, and the arrangement of the first sub-chip 301 and the second sub-chip 302 is flexible and diverse.
[0106] In one specific embodiment, the substrate 100 further includes at least one second recess 150, the opening of the second recess 150 being located on a second side 140, at least one second chip 300 being located in the second recess 150, and the chip packaging structure further includes a filling layer 500, the filling layer 500 being located in the gap formed by the second chip 300 and the groove wall of the second recess 150, and in the gap formed by the first chip 200 and the groove wall of the first recess 120; the first wiring layer 410 includes a first part 411, a second part 412, and a third part 413, the first part 411 being electrically connected to the connecting line 430, the second part 412 being electrically connected to the first part 411, and the third part 413 being located on the first side 110 of the substrate 100 and electrically connected to the second part 412. The second part 412 is located on the groove wall of the first groove 120, and the angle α between the groove wall of the first groove 120 and the first direction x is 30° to 60° (see Figure 6 for details); the chip packaging structure also includes a first protective layer 600, which is located on the first side 110 of the substrate 100. The orthographic projection of the first protective layer 600 on the plane of the substrate 100 covers the orthographic projection of the first chip 200 on the plane of the substrate 100; the first protective layer 600 covers the third part 413; the chip packaging structure also includes a conductive structure 700, which is located on the side of the third part 413 away from the substrate 100, and the conductive structure 700 is electrically connected to the third part 413; the conductive structure 700 is partially embedded in the first protective layer 600.
[0107] A second aspect of this disclosure provides a chip packaging structure. Referring to FIG1, the chip packaging structure includes: a substrate 100, the substrate 100 including at least one first recess 120 and a plurality of through holes 130, the through holes 130 communicating with the first recess 120; at least one first chip 200 and at least one second chip 300, the first chip 200 and the second chip 300 being located on opposite sides of the substrate 100; at least one first chip 200 being located in the first recess 120; the through holes 130 being located between the first chip 200 and the second chip 300; a wiring layer 400 being located on at least one side of the substrate 100, the wiring layer 400 being electrically connected to the first chip 200 and the second chip 300; and a connecting line 430 being located in the through holes 130 and electrically connected to the wiring layer 400.
[0108] The third aspect of this disclosure provides a method for fabricating a chip packaging structure. Referring to the schematic flowchart of the fabrication method shown in FIG16, the method for fabricating the chip packaging structure includes the following steps.
[0109] S110: At least one first groove is formed on the first side of the base.
[0110] The base and the first groove are the same as described above, and will not be repeated here.
[0111] For example, the method of forming at least one first groove on the first side of the substrate includes, but is not limited to, laser scribing, mechanical scribing, laser-induced wet etching, etc.
[0112] S120: Multiple through holes are opened on the bottom wall of the first groove.
[0113] The through hole penetrates the bottom wall of the first groove along the first direction.
[0114] The through-hole is the same as described above, so I will not go into details here.
[0115] For example, the methods of creating multiple through holes on the bottom wall of the first groove include, but are not limited to, laser scribing, mechanical scribing, and laser-induced wet etching.
[0116] S130: Fabricating connecting wires in through holes.
[0117] The connecting wires are as described above and will not be repeated here. Methods for preparing the connecting wires include, but are not limited to, electroplating and coating.
[0118] S140: A first wiring layer is prepared on a first side of the substrate, and a second wiring layer is prepared on a second side of the substrate.
[0119] The first and second routing layers are the same as described above, and will not be repeated here.
[0120] For example, the first wiring layer and the second wiring layer are electrically connected by a connecting line.
[0121] In one embodiment, preparing a first wiring layer on a first side of a substrate and preparing a second wiring layer on a second side of the substrate includes: filling an optical adhesive into a first groove and a second groove, and patterning the optical adhesive; preparing the first wiring layer and the second wiring layer on the surface of the patterned optical adhesive; exemplaryly, electroplating can be performed on the surface of the patterned optical adhesive to obtain the first wiring layer and the second wiring layer.
[0122] S150: At least one first chip is disposed in the first groove, and at least one second chip is disposed on the second side of the substrate.
[0123] The first chip has a pin-side surface facing the second side, and the second chip has a pin-side surface facing the first side; the first wiring layer is electrically connected to the pins of the first chip, and the second wiring layer is electrically connected to the pins of the second chip.
[0124] The first chip includes a chip body and a first conductive structure located on the surface of the chip body having pins. The first conductive structure can be connected to a first part of a first wiring layer by soldering. The second chip includes a chip body and a second conductive structure located on the surface of the chip body having pins. The second conductive structure can be connected to a fourth part of a second wiring layer by soldering.
[0125] The first and second chips are described in the same way as before, and will not be repeated here.
[0126] In one embodiment, the step of setting at least one second chip on the second side of the substrate includes: forming at least one second groove on the second side of the substrate, and setting at least one second chip in the second groove. Therefore, forming the second groove helps to further reduce the length of the connecting line and improve the signal transmission rate.
[0127] In another embodiment, the step of setting at least one first chip in the first groove and setting at least one second chip on the second side of the substrate includes: setting the second chip on the second side of the substrate, preparing a sealing layer on the side of the second chip facing away from the substrate, the sealing layer covering the second chip and being in close contact with the substrate; and setting at least one first chip in the first groove. Thus, when the substrate material is glass, it helps to reduce the risk of substrate fragmentation.
[0128] The fourth aspect of this disclosure provides a method for fabricating a chip packaging structure. Referring to the schematic flowchart of the fabrication method shown in FIG17, the method for fabricating the chip packaging structure includes the following steps.
[0129] S210: At least one first groove is formed on the first side of the base.
[0130] The first groove is the same as described above, so I will not go into detail here.
[0131] S220: Multiple through holes are opened on the bottom wall of the first groove, and the through holes penetrate the bottom wall of the first groove along the first direction.
[0132] The through-hole is the same as described above, so I will not go into details here.
[0133] S230: Fabricating connecting wires in through holes.
[0134] The connecting wires are as described above and will not be repeated here. Methods for preparing the connecting wires include, but are not limited to, electroplating and coating.
[0135] S240: Fill the first groove with optical adhesive, and prepare optical adhesive on the second side of the substrate that is disposed opposite to the first side in the first direction, and perform patterning processing on the optical adhesive.
[0136] The optical adhesive can be patterned using laser etching, and the pattern in the patterned optical adhesive corresponds to the shape of the first wiring layer.
[0137] S250: Prepare the first part and the fourth part on the surface of the patterned optical adhesive, electrically connect the first part and the fourth part to the connecting wire, and remove the first optical adhesive.
[0138] For example, electroplating can be performed on the surface of the patterned optical adhesive to obtain the first and fourth parts.
[0139] The descriptions of Parts 1, 2, 3, and 4 are consistent with those above, and will not be repeated here.
[0140] S260: At least one first chip is disposed in the first groove, and at least one second chip is disposed on the second side of the substrate; the first chip is electrically connected to the first part, and the second chip is electrically connected to the fourth part.
[0141] The first and second chips are described in the same way as before, and will not be repeated here.
[0142] S270: Fill the first groove with underfill adhesive and drill holes in the underfill adhesive.
[0143] The filler adhesive can fill the gap between the groove wall of the first groove and the first chip.
[0144] For example, holes can be drilled in the base filler using mechanical scribing, and the resulting pattern corresponds to the graphics in the fourth and fifth parts.
[0145] S280: Prepare the second and third parts on the surface of the bottom filler after drilling to obtain the first wiring layer.
[0146] The second part is electrically connected to the first part, and the third part is located on the first side of the base.
[0147] For example, electroplating can be performed on the bottom filler after drilling to obtain the second and third parts.
[0148] The fifth aspect of this disclosure provides a terminal device, including the chip packaging structure described above, or including a chip packaging structure prepared by the preparation method described above.
[0149] The aforementioned terminal devices can be desktop computers, tablet computers, high-performance calculators, etc. In addition to the chip packaging structure described above, terminal devices may also include the structures typically found in conventional terminal devices, such as display panels, touch panels, and casings, which will not be elaborated upon further here.
[0150] The sixth aspect of this disclosure provides a chip packaging carrier. Referring to the structural schematic diagram of the chip packaging carrier shown in FIG18, the chip packaging carrier includes: a substrate 100; the substrate 100 having a first side 110 and a second side 140 disposed opposite to each other in a first direction x; at least one first groove 120, the opening of the first groove 120 being located on the first side 110; a plurality of through holes 130, the through holes 130 penetrating the bottom wall of the first groove 120 along the first direction x; a connecting line 430 located in the through hole 130; and a wiring layer 400 located on at least one side of the substrate 100, the wiring layer 400 being electrically connected to the connecting line 430.
[0151] The base, first groove, through hole, first side, and first direction are consistent with the previous description and will not be repeated here.
[0152] The chip packaging substrate of this embodiment can carry chips of different sizes and functions, thereby realizing chip integration. Moreover, the distance between the bottom wall of the first groove and the surface located on the second side of the substrate is relatively short, and the length of the through hole in the first direction is relatively short, which is beneficial to shorten the signal transmission distance between chips.
[0153] In one embodiment, the wiring layer 400 includes a first wiring layer 410 and a second wiring layer 420. The first wiring layer 410 is located on a first side 110 of the substrate 100, and the second wiring layer 420 is located on a second side 140 of the substrate 100. Both the first wiring layer 410 and the second wiring layer 420 are electrically connected to the connecting line 430.
[0154] In one embodiment, the first wiring layer 410 includes a first part 411, a second part 412 and a third part 413. The first part 411 is electrically connected to the connecting line 430 and is located on the bottom wall of the first groove 120. The second part 412 is electrically connected to the first part 411. The third part 413 is located on the first side 110 of the substrate 100 and is electrically connected to the second part 412.
[0155] In one embodiment, referring to the schematic diagram of the chip packaging carrier shown in FIG19, the chip packaging carrier further includes a first pad 1100, the first pad 1100 being located on the side of the first part 411 away from the bottom wall of the first groove 120, and the first pad 1100 being electrically connected to the first part 411.
[0156] In one embodiment, the chip packaging substrate further includes a second pad 1200, which is located on the side of the second wiring layer 420 away from the substrate 100 and is electrically connected to the second wiring layer 420.
[0157] In one embodiment, referring to the schematic diagram of the chip packaging carrier shown in FIG20, the chip packaging carrier further includes: at least one second groove 150, the opening of the second groove 150 being located on the second side 140 of the substrate 100, and the first side 110 being disposed opposite to the second side 140; a through hole 130 penetrating the bottom wall of the second groove 150 along a first direction x. Thus, the distance between the bottom wall of the first groove and the bottom wall of the second groove is shorter, and the length of the through hole is further shortened in the first direction, which is beneficial for further shortening the signal transmission distance between chips.
[0158] In one embodiment, the second wiring layer 420 includes a fourth part 421, a fifth part 422, and a sixth part 423. The fourth part 421 is electrically connected to the connecting line 430 and is located on the bottom wall of the second groove 150. The fifth part 422 is electrically connected to the fourth part 421. The sixth part 423 is located on the second side 140 of the substrate 100 and is electrically connected to the fifth part 422.
[0159] In one embodiment, the chip packaging substrate further includes a second pad 1200, which is located on the side of the fourth part 421 away from the bottom wall of the second groove 150, and the second pad 1200 is electrically connected to the fourth part 421.
[0160] In one embodiment, the substrate is made of glass.
[0161] The chip packaging substrate of this embodiment can be combined with the chip packaging substrate described above in whole or in part, which will not be elaborated further here.
[0162] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.
[0163] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations therein.
Claims
1. A chip packaging structure, comprising: A substrate having a first side and a second side disposed opposite to each other in a first direction; the substrate includes at least one first groove and a plurality of through holes, the opening of the first groove being located on the first side, and the through holes penetrating the bottom wall of the first groove along the first direction; At least one first chip is located in the first recess, and the surface of the first chip having pins faces the second side; At least one second chip is located on the second side of the substrate, the surface of the second chip having pins facing the first side; A first wiring layer is located on a first side of the substrate, and the first wiring layer is electrically connected to the pins of the first chip; A second wiring layer, located on a second side of the substrate, is electrically connected to the pins of the second chip; and The connecting line is located in the through hole and is electrically connected to the first wiring layer and the second wiring layer.
2. The chip packaging structure according to claim 1, wherein, The substrate further includes at least one second groove, the opening of the second groove being located on the second side, and at least one second chip being located in the second groove; The orthographic projection of the first groove onto the plane of the substrate at least partially overlaps with the orthographic projection of the second groove onto the plane of the substrate.
3. The chip packaging structure according to claim 2, wherein, The chip packaging structure further includes: a filling layer located in the gap formed by the second chip and the groove wall of the second groove, and / or located in the gap formed by the first chip and the groove wall of the first groove; And / or, the substrate is made of glass.
4. The chip packaging structure according to claim 2 or 3, wherein, The first chip includes at least one logic chip located in the first recess; The second chip includes a plurality of memory chips, each located in one of the second recesses.
5. The chip packaging structure according to any one of claims 1 to 3, wherein, The first wiring layer includes a first part, a second part, and a third part. The first part is electrically connected to the connecting line, the second part is electrically connected to the first part, and the third part is located on a first side of the substrate and is electrically connected to the second part. The second part is located on the wall of the first groove; the angle between the wall of the first groove and the first direction is 30° to 60°, or the wall of the first groove is parallel to the first direction.
6. The chip packaging structure according to claim 5, wherein, The first side is the signal output side, and the first chip is a logic chip.
7. The chip packaging structure according to claim 5 further includes: A first protective layer is located on a first side of the substrate, and the orthographic projection of the first protective layer on the plane where the substrate is located covers the orthographic projection of the first chip on the plane where the substrate is located. The material of the first protective layer includes at least one of polyimide, aromatic benzocyclobutane film, and bismaleimide triazine resin.
8. The chip packaging structure according to claim 7, further comprising: A conductive structure is located on the side of the third part away from the substrate, and the conductive structure is electrically connected to the third part; The conductive structure is partially embedded in the first protective layer.
9. The chip packaging structure according to claim 2 or 3, wherein, The second wiring layer further includes a fourth part, a fifth part, and a sixth part, wherein the fourth part is electrically connected to the connecting line, the fifth part is electrically connected to the fourth part, and the sixth part is located on the second side of the substrate and is electrically connected to the fifth part; The fifth part is located on the wall of the second groove, and the angle between the wall of the second groove and the first direction is 30° to 60°, or the wall of the second groove is parallel to the first direction.
10. The chip packaging structure according to claim 9, further comprising: A second protective layer and a conductive structure, wherein the second protective layer is located on the second side of the substrate, and the orthographic projection of the second protective layer on the plane of the substrate covers the orthographic projection of the second chip on the plane of the substrate; the second protective layer covers the sixth part; The conductive structure is located on the side of the sixth part away from the substrate, and the conductive structure is electrically connected to the sixth part. The conductive structure is partially embedded in the second protective layer; The material of the second protective layer includes at least one of polyimide, aromatic benzocyclobutane film, and bismaleimide triazine resin.
11. The chip packaging structure according to claim 2, wherein, The second chip includes a first sub-chip and a second sub-chip, and the first sub-chip and the second sub-chip have different functions; The first wiring layer includes a first part, a second part, and a third part. The first part is electrically connected to the connecting line, the second part is electrically connected to the first part, and the third part is located on a first side of the substrate and electrically connected to the second part. The second wiring layer includes a fourth part. The fourth part is electrically connected to the first sub-chip and the second sub-chip, and the first part is electrically connected to the first chip. One of the second recesses includes at least one of the first sub-chips and at least one of the second sub-chips; and / or, one of the second recesses includes at least one of the first sub-chips, and another of the second recesses includes at least one of the second sub-chips.
12. The chip packaging structure according to claim 1, further comprising: A sealing layer is located on the side of the second chip facing away from the substrate. The sealing layer covers the second chip and is in close contact with the substrate.
13. The chip packaging structure according to claim 1, wherein, The substrate further includes at least one second groove, the opening of the second groove being located on the second side, and at least one second chip being located in the second groove; The chip packaging structure further includes: a filling layer located in the gap formed by the second chip and the groove wall of the second groove, and a filling layer located in the gap formed by the first chip and the groove wall of the first groove; The first wiring layer includes a first part, a second part, and a third part. The first part is electrically connected to the connecting line, the second part is electrically connected to the first part, and the third part is located on a first side of the substrate and is electrically connected to the second part. The second part is located on the wall of a first groove, and the angle between the wall of the first groove and the first direction is 30° to 60°. The chip packaging structure further includes a first protective layer and a conductive structure. The first protective layer is located on a first side of the substrate, and the orthographic projection of the first protective layer on the plane of the substrate covers the orthographic projection of the first chip on the plane of the substrate. The first protective layer covers the third part. The conductive structure is located on the side of the third part away from the substrate, and is partially embedded in the first protective layer. The conductive structure is electrically connected to the third part.
14. A chip packaging structure, characterized in that, include: A substrate, the substrate including at least one first groove and a plurality of through holes, the through holes being connected to the first groove; At least one first chip and at least one second chip, the first chip and the second chip being located on opposite sides of the substrate; at least one first chip being located in the first groove; The via is located between the first chip and the second chip; A wiring layer, located on at least one side of the substrate, is electrically connected to the first chip and the second chip; and The connecting line is located in the through hole and is electrically connected to the wiring layer.
15. A method for fabricating a chip packaging structure, comprising: At least one first groove is formed on the first side of the base; Multiple through holes are formed on the bottom wall of the first groove, and the through holes penetrate the bottom wall of the first groove along a first direction; A connecting wire is fabricated in the through hole; A first wiring layer is formed on the first side of the substrate, and a second wiring layer is formed on the second side of the substrate. The first wiring layer and the second wiring layer are electrically connected through the connecting line, and the first side and the second side are disposed opposite to each other in the first direction. At least one first chip is disposed in the first groove, and at least one second chip is disposed on the second side of the substrate. The surface of the first chip with pins faces the second side, and the surface of the second chip with pins faces the first side. The first wiring layer is electrically connected to the pins of the first chip, and the second wiring layer is electrically connected to the pins of the second chip.
16. The preparation method according to claim 15, wherein, The step of setting at least one second chip on the second side of the substrate includes: opening at least one second groove on the second side of the substrate, and setting at least one second chip in the second groove.
17. The preparation method according to claim 15, wherein, The step of setting at least one first chip in the first groove and setting at least one second chip on the second side of the substrate includes: The second chip is disposed on the second side of the substrate, and a sealing layer is prepared on the side of the second chip facing away from the substrate. The sealing layer covers the second chip and is in close contact with the substrate. At least one first chip is disposed in the first groove.
18. A method for fabricating a chip packaging structure, characterized in that, include: At least one first groove is formed on the first side of the base; Multiple through holes are formed on the bottom wall of the first groove, and the through holes penetrate the bottom wall of the first groove along a first direction; A connecting wire is fabricated in the through hole; Optical adhesive is filled into the first groove, and optical adhesive is prepared on the second side of the substrate that is opposite to the first side in a first direction, and the optical adhesive is patterned. A first part and a fourth part are prepared on the surface of the patterned optical adhesive, and the first part and the fourth part are electrically connected to the connecting line; At least one first chip is disposed in the first groove, and at least one second chip is disposed on the second side of the substrate; the first chip is electrically connected to the first part, and the second chip is electrically connected to the fourth part; Fill the first groove with a base filler, and drill holes in the base filler; A second and a third part are prepared on the surface of the bottom filler after drilling to obtain a first wiring layer.
19. A terminal device comprising the chip packaging structure according to any one of claims 1 to 14, or comprising the chip packaging structure prepared by the preparation method according to any one of claims 15 to 18.
20. A chip packaging carrier board, comprising: A substrate having a first side and a second side disposed opposite to each other in a first direction; At least one first groove, the opening of which is located on the first side; Multiple through holes, the through holes penetrating the bottom wall of the first groove along the first direction; The connecting wire is located in the through hole; A wiring layer is located on at least one side of the substrate, and the wiring layer is electrically connected to the connection line.
21. The chip packaging carrier board according to claim 20, wherein, The wiring layer includes a first wiring layer and a second wiring layer. The first wiring layer is located on a first side of the substrate, and the second wiring layer is located on a second side of the substrate. Both the first wiring layer and the second wiring layer are electrically connected to the connecting line. The first wiring layer includes a first part, a second part, and a third part. The first part is electrically connected to the connecting line, the second part is electrically connected to the first part, and the third part is located on a first side of the substrate and is electrically connected to the second part. The chip packaging carrier also includes a first pad located on the side of the first part away from the bottom wall of the first groove, and the first pad is electrically connected to the first part. The chip packaging substrate also includes a second pad located on the side of the second wiring layer opposite to the substrate, and the second pad is electrically connected to the second wiring layer.
22. The chip packaging carrier according to claim 20 or 21, further comprising: At least one second groove, the opening of which is located on the second side; Wherein, the through hole penetrates the bottom wall of the second groove along the first direction; The second wiring layer includes a fourth part, a fifth part, and a sixth part connected in sequence. The fourth part is electrically connected to the connecting line and is located on the bottom wall of the second groove. The fifth part is electrically connected to the fourth part. The sixth part is located on the second side of the substrate and is electrically connected to the fifth part. The chip packaging substrate further includes: a second pad located on the side of the fourth part away from the bottom wall of the second groove, and the second pad is electrically connected to the fourth part; The substrate is made of glass.