Data processing method and apparatus, and system

Abstract

Embodiments of the present application disclose a data processing method and apparatus, and a system. The method comprises: performing data processing on two acquired third data streams to obtain two fourth data streams, wherein consecutive bit blocks A0, A1, A2, A3, A4, A5, A6, and A7 in one third data stream and consecutive bit blocks B0, B1, B2, B3, B4, B5, B6, and B7 in the other third data stream constitute consecutive bit blocks A0, B0, A1, B1, A2, B2, A3, and B3 in one fourth data stream and consecutive bit blocks A4, B4, A5, B5, A6, B6, A7, and B7 in the other fourth data stream, and each bit block comprises 8 bits; and then respectively performing dual-polarization 16 QAM symbol mapping and framing processing on the two fourth data streams. FEC decoding performance can be improved, and hardware implementation is facilitated.

Description

A data processing method, apparatus and system

[0001] This application claims priority to Chinese Patent Application No. 202510039208.2, filed with the State Intellectual Property Office of China on January 9, 2025, entitled “A Data Processing Method, Apparatus and System Thereof”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communication technology, and in particular to a data processing method, apparatus and system thereof. Background Technology

[0003] Driven by 5G, cloud computing, big data, and artificial intelligence, high-speed optical transmission networks are developing towards higher capacity, packetization, and intelligence. Coherent optical communication systems utilize the amplitude, phase, polarization, or frequency of light waves to carry information. To combat optical signal distortion caused by dispersion, polarization-related impairments, noise, nonlinear effects, and other factors during transmission and to maintain long-distance transmission, coherent optical communication systems typically employ efficient forward error correction (FEC) codes and interleaving to counteract optical damage during optical transmission and maintain a sufficiently low bit error rate for long-distance transmission.

[0004] Currently, some optical transmission network architectures support transmission rates of 400Gbps and 800Gbps. Typically, 800Gbps transmission uses dual-polarization (DP) 16QAM modulation, corresponding to a baud rate of approximately 120Gbaud; 400Gbps transmission uses DP-quadrature phase shift keying (QPSK), also with a baud rate of approximately 120Gbaud. With the growth of services, next-generation metropolitan area telecom transmission and data center transmission scenarios (such as 1.6Tbps transmission using DP-16QAM and 800Gbps transmission using DP-QPSK) will require even higher baud rates (approximately 240Gbaud). Nonlinear effects such as enhanced equalization phase noise (EEPN) can lead to significant performance degradation, a problem that urgently needs to be addressed in the future. Summary of the Invention

[0005] This application provides a data processing method and apparatus for optical communication, which provides a data processing scheme suitable for high transmission rate scenarios, such as 800Gbps, 1.6Tbps, or even higher rates.

[0006] In a first aspect, a data processing method for optical communication is provided, comprising: performing forward error correction (FEC) encoding on four acquired first data streams to obtain four second data streams; interleaving the four second data streams to obtain two third data streams; and processing the two third data streams to obtain two fourth data streams, wherein consecutive bit blocks A0, A1, A2, A3, A4, A5, A6, A7 in one third data stream and consecutive bits in another third data stream are interleaved. The consecutive bit blocks B0, B1, B2, B3, B4, B5, B6, and B7 constitute consecutive bit blocks A0, B0, A1, B1, A2, B2, A3, B3 in one fourth data stream and consecutive bit blocks A4, B4, A5, B5, A6, B6, A7, B7 in another fourth data stream. Each bit block includes 8 bits. The two fourth data streams are subjected to dual-polarization 16QAM symbol mapping and framing processing respectively to obtain two dual-polarization symbol streams. Each bit block obtained through dual-polarization 16QAM symbol mapping yields one dual-polarization 16QAM symbol. In this application material, a bit block can also be referred to as a bit group or a bit set.

[0007] Secondly, a data processing method for optical communication is provided, comprising: performing forward error correction (FEC) encoding on eight acquired first data streams to obtain eight second data streams; interleaving the eight second data streams to obtain four third data streams; and processing the four third data streams to obtain two fourth data streams, wherein consecutive bit blocks A0, A1, A2, A3, A4, A5, A6, and A7 in the first third data stream, consecutive bit blocks B0, B1, B2, B3, B4, B5, B6, and B7 in the second third data stream, and consecutive bit blocks C0, C1, C2, C3, C4, and C5 in the third third data stream. C6, C7, and consecutive bit blocks D0, D1, D2, D3, D4, D5, D6, D7 in the fourth third data stream constitute consecutive bit blocks A0, B0, C0, D0, A1, B1, C1, D1, A2, B2, C2, D2, A3, B3, C3, D3 in one fourth data stream, and consecutive bit blocks A4, B4, C4, D4, A5, B5, C5, D5, A6, B6, C6, D6, A7, B7, C7, D7 in another fourth data stream. Each bit block includes 8 bits. The two fourth data streams are subjected to dual-polarization 16QAM symbol mapping and framing processing respectively to obtain two dual-polarization symbol streams. Each bit block is mapped to a dual-polarization 16QAM symbol.

[0008] The specific methods described in the first and second aspects ensure that the FEC-encoded bit data is evenly distributed across two dual-polarization symbol streams, i.e., two subcarriers. More specifically, when OFEC encoding is used, the 4096 encoded bits are represented by a 2x8 matrix, where each matrix contains 16 bits in 16 rows and 16 bits in 16 columns, totaling 256 bits. These 256 bits in each matrix are evenly distributed across the two dual-polarization symbol streams and evenly distributed along the X and Y polarization directions in each stream. This means each bit has four possible mapping positions, allowing decoding errors at the receiver to be more evenly distributed across multiple FEC decoding processes, thus improving FEC decoding performance.

[0009] Thirdly, a data processing method for optical communication is provided, comprising: performing forward error correction (FEC) encoding on four acquired first data streams to obtain four second data streams; interleaving the four second data streams to obtain two third data streams; and processing the two third data streams to obtain four fourth data streams, wherein consecutive bit blocks A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15 in one third data stream and consecutive bit blocks B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B15 in another third data stream. 2. B13, B14, and B15 constitute consecutive bit blocks A0, B0, A1, B1, A2, B2, A3, and B3 in the first fourth data stream; consecutive bit blocks A4, B4, A5, B5, A6, B6, A7, and B7 in the second fourth data stream; consecutive bit blocks A8, B8, A9, B9, A10, B10, A11, and B11 in the third fourth data stream; and consecutive bit blocks A12, B12, A13, B13, A14, B14, A15, and B15 in the fourth fourth data stream. Each bit block consists of 8 bits. The four fourth data streams are subjected to dual-polarization 16QAM symbol mapping and framing processing to obtain four dual-polarization symbol streams. Each bit block is mapped to a single dual-polarization 16QAM symbol.

[0010] Fourthly, a data processing method for optical communication is provided, comprising: performing forward error correction (FEC) coding on eight acquired first data streams to obtain eight second data streams; interleaving the eight second data streams to obtain four third data streams; and processing the four third data streams to obtain four fourth data streams, wherein consecutive bit blocks A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14 in the first third data streams... A15, consecutive bit blocks B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15 in the second third data stream, consecutive bit blocks C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15 in the third third data stream, and consecutive bit blocks D0, D1, D2, D3, D4, D5, D6, D7, D15 in the fourth third data stream. 8, D9, D10, D11, D12, D13, D14, D15 constitute consecutive bit blocks A0, B0, C0, D0, A1, B1, C1, D1, A2, B2, C2, D2, A3, B3, C3, D3 in the first fourth data stream; consecutive bit blocks A4, B4, C4, D4, A5, B5, C5, D5, A6, B6, C6, D6, A7, B7, C7, D7 in the second fourth data stream; and consecutive bit blocks A8, B8, C8 in the third fourth data stream. The four data streams are D8, A9, B9, C9, D9, A10, B10, C10, D10, A11, B11, C11, D11, and consecutive bit blocks A12, B12, C12, D12, A13, B13, C13, D13, A14, B14, C14, D14, A15, B15, C15, D15, each consisting of 8 bits. Dual-polarization 16QAM symbol mapping and framing are performed on each of the four data streams to obtain four dual-polarization symbol streams. Each bit block is mapped to a single dual-polarization 16QAM symbol.

[0011] The specific methods described in the third and fourth aspects ensure that the FEC-encoded bit data is evenly distributed across the four dual-polarization symbol streams, i.e., the four subcarriers. More specifically, when OFEC encoding is used, the 4096 encoded bits are represented by a 2x8 matrix, where each matrix contains 16 bits in each row and 16 bits in each column, totaling 256 bits. These 256 bits in each matrix are evenly distributed across the four dual-polarization symbol streams, and also evenly distributed across the X and Y polarization directions within each dual-polarization symbol stream. This means each bit has a total of eight possible mapping positions, allowing decoding errors at the receiver to be more evenly distributed across multiple FEC decoding processes, thus improving FEC decoding performance.

[0012] The framing process described above results in the dual-polarization symbol stream containing not only payload symbols (also known as pre-framing symbols) but also several added preset symbols. These preset symbols can be frame synchronization symbols, training symbols, pilot symbols, or reserved symbols, etc. Typically, frame synchronization symbols are used for frame synchronization, training symbols are used for link training, pilot symbols are used for carrier phase recovery, and reserved symbols are reserved for future use.

[0013] In light of the above, in one possible implementation, the FEC encoding employs Open FEC (OFEC) coding. Further, every 3552 bits in the first data stream are OFEC encoded to obtain 4096 encoded bits.

[0014] In conjunction with the first (or second) aspect and possible implementations described above, in one possible implementation, the second data stream comprises multiple matrices, each matrix comprising 256 bits, wherein the 256 bits of each matrix are evenly distributed along the two polarization directions of the two dual-polarization symbol streams. Further, in the multiple matrices, bits at the same position in each matrix are mapped to the same polarization direction of the same dual-polarization symbol stream.

[0015] In this embodiment, after the OFEC interleaving and data processing described above, the 256 bits in each square array can be uniformly mapped to the above four positions, and the bits at the same position in each square array are mapped to the same position. For example, if the first bit in the first square array is mapped to the X polarization direction of the first dual polarization symbol stream, then the first bit in each square array is mapped to the X polarization direction of the first dual polarization symbol stream. This simplifies the detection of bit error rate (BER) in each polarization direction of different subcarriers and facilitates hardware implementation.

[0016] In conjunction with the third (or fourth) aspect and possible implementations described above, in one possible implementation, the second data stream comprises multiple matrices, each matrix comprising 256 bits, wherein the 256 bits of each matrix are evenly distributed along the two polarization directions of the four dual-polarization symbol streams. Further, in the multiple matrices, bits at the same position in each matrix are mapped to the same polarization direction of the same dual-polarization symbol stream.

[0017] In this embodiment, after the OFEC interleaving and data processing described above, the 256 bits in each square array can be uniformly mapped to the above 8 positions, and the bits at the same position in each square array are mapped to the same position. For example, if the first bit in the first square array is mapped to the X polarization direction of the first dual polarization symbol stream, then the first bit in each square array is mapped to the X polarization direction of the first dual polarization symbol stream. This simplifies the detection of bit error rate (BER) in each polarization direction of different subcarriers and facilitates hardware implementation.

[0018] In light of the above aspects and possible implementations, in one possible implementation, the interleaving is OFEC interleaving, which includes intra-array interleaving and inter-array interleaving. Each array includes 256 bits, and the buffer for inter-array interleaving includes 672 arrays.

[0019] In light of the above aspects and possible implementations, in one possible implementation, the interleaving specifically includes:

[0020] Each pair of second data streams is interleaved within the matrix and then interleaved between the matrices to obtain a third data stream.

[0021] In conjunction with the first aspect, in one possible implementation, the data processing of the two third data streams to obtain two fourth data streams specifically includes: merging the two third data streams to obtain a merged data stream, wherein consecutive bit blocks A0, A1, A2, A3, A4, A5, A6, A7 in one third data stream and consecutive bit blocks B0, B1, B2, B3, B4, B5, B6, B7 in the other third data stream constitute consecutive bit blocks A0, B0, A1, B1, A2, B2, A3, B3, A4, B4, A5, B5, A6, B6, A7, B7 in the merged data stream; and distributing the merged data stream to obtain two fourth data streams.

[0022] Specifically, the above merging can be understood as merging the two third data streams into a single merged data stream in a round-robin fashion, with a granularity of 8 bits (i.e., 1 bit block); the above distribution can be understood as distributing the merged data stream to the two fourth data streams in a round-robin fashion, with a granularity of 64 bits (i.e., 8 bit blocks). Each of the two fourth data streams can correspond to a subcarrier or a wavelength.

[0023] Regarding the above implementation, the first aspect can be described as follows: Forward error correction (FEC) encoding is performed on the four acquired first data streams to obtain four second data streams; the four second data streams are interleaved to obtain two third data streams; the two third data streams are merged into a single merged data stream in a round-robin fashion, with a granularity of 8 bits (i.e., one bit block); the merged data stream is distributed to two fourth data streams in a round-robin fashion, with a granularity of 64 bits (i.e., eight bit blocks); and dual-polarization 16QAM symbol mapping and framing processing are performed on the two fourth data streams to obtain two dual-polarization symbol streams.

[0024] In conjunction with the second aspect, in one possible implementation, the data processing of the four third data streams to obtain two fourth data streams specifically includes: merging the four third data streams to obtain a merged data stream, wherein the consecutive bit blocks A0, A1, A2, A3, A4, A5, A6, A7 in the first third data stream, the consecutive bit blocks B0, B1, B2, B3, B4, B5, B6, B7 in the second third data stream, and the consecutive bit blocks C0, C1, C2, C3, C... 4. C5, C6, C7 and consecutive bit blocks D0, D1, D2, D3, D4, D5, D6, D7 in the fourth third data stream constitute consecutive bit blocks A0, B0, C0, D0, A1, B1, C1, D1, A2, B2, C2, D2, A3, B3, C3, D3, A4, B4, C4, D4, A5, B5, C5, D5, A6, B6, C6, D6, A7, B7, C7, D7 in the merged data stream; the merged data stream is then distributed to obtain two fourth data streams.

[0025] Specifically, the above merging can be understood as merging the four third data streams into a single merged data stream in a round-robin fashion, with a granularity of 8 bits (i.e., 1 bit block); the above distribution can be understood as distributing the merged data stream to two fourth data streams in a round-robin fashion, with a granularity of 128 bits (i.e., 16 bit blocks). Each of the two fourth data streams can correspond to a subcarrier or a wavelength.

[0026] Regarding the above implementation, the second aspect can be described as follows: Forward error correction (FEC) encoding is performed on the eight first data streams to obtain eight second data streams; the eight second data streams are interleaved to obtain four third data streams; the four third data streams are merged into a single merged data stream in a round-robin fashion at a granularity of 8 bits (i.e., one bit block); the merged data stream is distributed to two fourth data streams in a round-robin fashion at a granularity of 128 bits (i.e., 16 bit blocks); and dual-polarization 16QAM symbol mapping and framing processing are performed on the two fourth data streams to obtain two dual-polarization symbol streams.

[0027] In conjunction with the third aspect, in one possible implementation, the data processing of the two third data streams to obtain four fourth data streams specifically includes: merging the two third data streams to obtain a merged data stream, wherein consecutive bit blocks A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15 in one third data stream and consecutive bit blocks B0, B1, B2, B3, B4, B5, B... B7, B8, B9, B10, B11, B12, B13, B14, and B15 constitute consecutive bit blocks A0, B0, A1, B1, A2, B2, A3, B3, A4, B4, A5, B5, A6, B6, A7, B7, A8, B8, A9, B9, A10, B10, A11, B11, A12, B12, A13, B13, A14, B14, A15, and B15 in the merged data stream; the merged data stream is then distributed to obtain four fourth data streams.

[0028] Specifically, the above merging can be understood as merging the two third data streams into a single merged data stream in a round-robin fashion, with a granularity of 8 bits (i.e., 1 bit block); the above distribution can be understood as distributing the merged data stream to four fourth data streams in a round-robin fashion, with a granularity of 64 bits (i.e., 8 bit blocks). Each of the four fourth data streams can correspond to a subcarrier or a wavelength.

[0029] Regarding the above implementation, the third aspect can be described as follows: Forward error correction (FEC) encoding is performed on the four acquired first data streams to obtain four second data streams; the four second data streams are interleaved to obtain two third data streams; the two third data streams are merged into a single merged data stream in a round-robin fashion, with a granularity of 8 bits (i.e., one bit block); the merged data stream is distributed to four fourth data streams in a round-robin fashion, with a granularity of 64 bits (i.e., eight bit blocks); and dual-polarization 16QAM symbol mapping and framing processing are performed on the four fourth data streams to obtain four dual-polarization symbol streams.

[0030] In conjunction with the fourth aspect, in one possible implementation, the data processing of the four third data streams to obtain four fourth data streams specifically includes: merging the four third data streams to obtain a merged data stream, wherein the consecutive bit blocks A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, and A15 in the first third data stream, and the second... The consecutive bit blocks B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15 in the third data stream; the consecutive bit blocks C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15 in the third data stream; and the consecutive bit blocks D0, D... in the fourth data stream. 1. D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15 constitute consecutive bit blocks A0, B0, C0, D0, A1, B1, C1, D1, A2, B2, C2, D2, A3, B3, C3, D3, A4, B4, C4, D4, A5, B5, C5, D5, A6, B6, C6, D6, A7 in the merged data stream. B7, C7, D7, A8, B8, C8, D8, A9, B9, C9, D9, A10, B10, C10, D10, A11, B11, C11, D11, A12, B12, C12, D12, A13, B13, C13, D13, A14, B14, C14, D14, A15, B15, C15, D15; The merged data stream is then distributed to obtain four fourth data streams.

[0031] Specifically, the above merging can be understood as merging the four third data streams into a single merged data stream in a round-robin fashion, with a granularity of 8 bits (i.e., 1 bit block); the above distribution can be understood as distributing the merged data stream to the four fourth data streams in a round-robin fashion, with a granularity of 128 bits (i.e., 16 bit blocks). Each of the four fourth data streams can correspond to a subcarrier or a wavelength.

[0032] Regarding the above implementation, the fourth aspect can be described as follows: Forward error correction (FEC) encoding is performed on the eight first data streams to obtain eight second data streams; the eight second data streams are interleaved to obtain four third data streams; the four third data streams are merged into a single merged data stream in a round-robin fashion, with a granularity of 8 bits (i.e., one bit block); the merged data stream is distributed to the four fourth data streams in a round-robin fashion, with a granularity of 128 bits (i.e., 16 bit blocks); and dual-polarization 16QAM symbol mapping and framing processing are performed on the four fourth data streams to obtain four dual-polarization symbol streams.

[0033] In some existing implementations for shorter-distance transmission, a single merged data stream is directly mapped to dual polarization symbols and framed without being distributed, resulting in a single dual polarization symbol stream to be transmitted. In this case, the solutions presented in the four implementations described above are well-compatible with existing methods and can be used for longer-distance transmission scenarios, resulting in lower power consumption.

[0034] Fifthly, a data processing method for optical communication is provided, comprising: demapping two received dual-polarization symbol streams to obtain two demapped data streams; and processing the two demapped data streams to obtain two first data streams, wherein consecutive bit blocks A0, B0, A1, B1, A2, B2, A3, B3 in one demapped data stream and consecutive bit blocks A4, B4, A5, B5, A6, B6, A7, B7 in the other demapped data stream are processed to obtain consecutive bit blocks A0, A1, A2, A3, A4, A5, A6, A7 in one first data stream and consecutive bit blocks B0, B1, B2, B3, B4, B5, B6, B7 in the other first data stream, each bit block comprising 8 bits. Each bit block is obtained by demapping one dual-polarization 16QAM symbol.

[0035] Sixthly, a data processing method for optical communication is provided, comprising: demapping two received dual-polarization symbol streams to obtain two demapped data streams; and processing the two demapped data streams to obtain four first data streams, wherein consecutive bit blocks A0, B0, C0, D0, A1, B1, C1, D1, A2, B2, C2, D2, A3, B3, C3, D3 in one demapped data stream and consecutive bit blocks A4, B4, C4, D4, A5, B5, C5, D5, A6, B3, C4, D4, A5, B5, C5, D5, A6, B3, C4, D4, A5, B5, C5, D5, A6, B3, C4, D4, A5, B5, C5, D5, A5, B6, D4, C5, D5, A5, B6, D4, D5, D4, A5, B5, C5, D5, A5, B6, D4, D5, D4, A5, B5, C5, D5, A5, B6, D4, D5, D4, A5, B5, D5, A5, D5, A5, B6, D4, D5, D5, A ... D5, A5, D5, D5, A5, D5, D5, D5, A5, D5, D5, D5, D5, D5, D5, D5, D5, D5, D5, D5, D5, D5, D5, D5, D5, D5, D5, D5, D5, D5, D5, D5, D5, 6. C6, D6, A7, B7, C7, and D7 are processed to obtain consecutive bit blocks A0, A1, A2, A3, A4, A5, A6, and A7 in the first data stream; consecutive bit blocks B0, B1, B2, B3, B4, B5, B6, and B7 in the second data stream; consecutive bit blocks C0, C1, C2, C3, C4, C5, C6, and C7 in the third data stream; and consecutive bit blocks D0, D1, D2, D3, D4, D5, D6, and D7 in the fourth data stream. Each bit block consists of 8 bits. Each bit block is obtained by demapping one dual-polarization 16QAM symbol.

[0036] In a seventh aspect, a data processing method for optical communication is provided, comprising: demapping four received dual-polarization symbol streams to obtain four demapped data streams; and processing the four demapped data streams to obtain two first data streams, wherein the first demapped data stream contains consecutive bit blocks A0, B0, A1, B1, A2, B2, A3, B3; the second demapped data stream contains consecutive bit blocks A4, B4, A5, B5, A6, B6, A7, B7; and the third demapped data stream contains consecutive bit blocks A8, B8, A9, B9, A10, B10, A11, B... After data processing, consecutive bit blocks A12, B12, A13, B13, A14, B14, A15, and B15 from the 11th and 4th demapped data streams are processed to obtain consecutive bit blocks A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, and A15 from one first data stream and consecutive bit blocks B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, and B15 from another first data stream. Each bit block consists of 8 bits. Each of the above bit blocks is obtained by demapping one dual-polarization 16QAM symbol.

[0037] Eighthly, a data processing method for optical communication is provided, comprising: demapping four received dual-polarization symbol streams to obtain four demapped data streams; processing the four demapped data streams to obtain four first data streams, wherein consecutive bit blocks A0, B0, C0, D0, A1, B1, C1, D1, A2, B2, C2, D2, A3, B3, C3, D3 in the first demapped data stream, and consecutive bit blocks in the second demapped data stream... Bit blocks A4, B4, C4, D4, A5, B5, C5, D5, A6, B6, C6, D6, A7, B7, C7, D7; consecutive bit blocks A8, B8, C8, D8, A9, B9, C9, D9, A10, B10, C10, D10, A11, B11, C11, D11 in the third demapped data stream; and consecutive bit blocks A12, B12, C12, D12, A13, B13, C13 in the fourth demapped data stream. Data D13, A14, B14, C14, D14, A15, B15, C15, and D15 are processed to obtain consecutive bit blocks A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, and A15 in the first data stream, and consecutive bit blocks B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, and B11 in the second data stream. The first data stream includes B12, B13, B14, B15, consecutive bit blocks C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, and consecutive bit blocks D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, each bit block consisting of 8 bits. Each bit block is obtained by demapping one dual-polarization 16QAM symbol.

[0038] In one possible implementation, prior to the demapping, the method further includes: deleting symbols added during framing from the received multiple (e.g., 2, 4, etc.) dual-polarization data streams, such as frame synchronization symbols, training symbols, pilot symbols, or reserved symbols. Then, demapping operations are performed separately to obtain the demapped data streams.

[0039] In one possible implementation, based on the above aspects, each of the first data streams is deinterleaved to obtain two second data streams. Each of the second data streams is then forward error correction (FEC) decoded to obtain a third data stream. Further, every 4096 bits in the second data stream is subjected to OFEC decoding to obtain 3552 decoded bits.

[0040] In conjunction with the fifth (or sixth) aspect and possible implementations described above, in one possible implementation, the second data stream comprises multiple matrices, each matrix comprising 256 bits, wherein the 256 bits of each matrix are uniformly derived from the two polarization directions of the two dual-polarization symbol streams. Further, in the multiple matrices, bits at the same position in each matrix originate from the same polarization direction of the same dual-polarization symbol stream.

[0041] In conjunction with the seventh (or eighth) aspect and possible implementations described above, in one possible implementation, the second data stream comprises multiple matrices, each matrix comprising 256 bits, wherein the 256 bits of each matrix are uniformly derived from the two polarization directions of the four dual-polarization symbol streams. Further, in the multiple matrices, bits at the same position in each matrix originate from the same polarization direction of the same dual-polarization symbol stream.

[0042] In light of the above aspects and possible implementations, in one possible implementation, the deinterleaving is OFEC deinterleaving, which includes intra-matrix deinterleaving and inter-matrix deinterleaving. Each matrix includes 256 bits, and the buffer for inter-matrix deinterleaving includes 672 matrices.

[0043] In light of the above aspects and possible implementations, in one possible implementation, the deinterleaving specifically includes: performing inter-matrix deinterleaving on each of the first data streams to obtain two fourth data streams; and then performing intra-matrix deinterleaving on the two fourth data streams respectively to obtain two second data streams.

[0044] In conjunction with the fifth aspect, in one possible implementation, the two demapped data streams are processed to obtain two first data streams, specifically including: merging the two demapped data streams to obtain a merged data stream; and distributing the merged data stream to obtain two first data streams, wherein consecutive bit blocks A0, B0, A1, B1, A2, B2, A3, B3, A4, B4, A5, B5, A6, B6, A7, and B7 in the merged data stream are distributed to obtain consecutive bit blocks A0, A1, A2, A3, A4, A5, A6, and A7 in one first data stream and consecutive bit blocks B0, B1, B2, B3, B4, B5, B6, and B7 in the other first data stream.

[0045] In conjunction with the sixth aspect, in one possible implementation, the data processing of the two demapped data streams to obtain four first data streams specifically includes: merging the two demapped data streams to obtain a merged data stream; and distributing the merged data stream to obtain four first data streams, wherein consecutive bit blocks A0, B0, C0, D0, A1, B1, C1, D1, A2, B2, C2, D2, A3, B3, C3, D3, A4, B4, C4, D4, A5, B5, C 5. D5, A6, B6, C6, D6, A7, B7, C7, and D7 are distributed to obtain consecutive bit blocks A0, A1, A2, A3, A4, A5, A6, and A7 in the first data stream; consecutive bit blocks B0, B1, B2, B3, B4, B5, B6, and B7 in the second data stream; consecutive bit blocks C0, C1, C2, C3, C4, C5, C6, and C7 in the third data stream; and consecutive bit blocks D0, D1, D2, D3, D4, D5, D6, and D7 in the fourth data stream.

[0046] In conjunction with the seventh aspect, in one possible implementation, data processing is performed on the four demapped data streams to obtain two first data streams. Specifically, this includes: merging the four demapped data streams to obtain a merged data stream; and distributing the merged data stream to obtain two first data streams, wherein consecutive bit blocks A0, B0, A1, B1, A2, B2, A3, B3, A4, B4, A5, B5, A6, B6, A7, B7, A8, B8, A9, B9, A10, B... 10, A11, B11, A12, B12, A13, B13, A14, B14, A15, and B15 are distributed to obtain consecutive bit blocks A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, and A15 in the first data stream and consecutive bit blocks B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, and B15 in the second data stream.

[0047] In conjunction with the eighth aspect, in one possible implementation, the data processing of the four demapped data streams to obtain four first data streams specifically includes: merging the four demapped data streams to obtain a merged data stream; and distributing the merged data stream to obtain four first data streams, wherein consecutive bit blocks A0, B0, C0, D0, A1, B1, C1, D1, A2, B2, C... in the merged data stream... 2. D2, A3, B3, C3, D3, A4, B4, C4, D4, A5, B5, C5, D5, A6, B6, C6, D6, A7, B7, C7, D7, A8, B8, C8, D8, A 9. B9, C9, D9, A10, B10, C10, D10, A11, B11, C11, D11, A12, B12, C12, D12, A13, B13, C13, D13, A14 Bits B14, C14, D14, A15, B15, C15, and D15 are distributed to obtain consecutive bit blocks A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, and A15 in the first data stream, and consecutive bit blocks B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, and B15 in the second data stream. 1, B12, B13, B14, B15, consecutive bit blocks C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15 in the third first data stream, and consecutive bit blocks D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15 in the fourth first data stream.

[0048] A ninth aspect provides a data processing apparatus for optical communication, comprising: a processor for executing the data processing method as described in the first to eighth aspects and any possible implementation thereof.

[0049] In a tenth aspect, a chip is provided for performing the methods described in the first to eighth aspects and any possible implementation thereof.

[0050] Eleventhly, an optical module is provided, the optical module including a processor and an interface, the interface being used for transmitting and receiving signals, and the processor being used for performing the methods described in the first to eighth aspects and any possible implementation thereof.

[0051] In a twelfth aspect, a communication device is provided, the communication device comprising a host-side device and an optical module as described in the eleventh aspect; the optical module is configured to convert an electrical signal from the host-side device into an optical signal and transmit the optical signal, or the optical module is configured to convert a received optical signal into an electrical signal and transmit the electrical signal to the host-side device.

[0052] In a thirteenth aspect, a communication system is provided, comprising a plurality of communication devices, wherein at least one communication device is a communication device as described in the twelfth aspect, and the plurality of communication devices are interconnected.

[0053] In a fourteenth aspect, this application provides a computer-readable storage medium storing instructions that, when executed by a computer, enable the implementation of the methods described in the first to eighth aspects and any possible implementation thereof.

[0054] In a fifteenth aspect, this application provides a computer program product comprising program instructions that, when executed, implement the methods described in aspects one through eight and any possible implementation thereof.

[0055] In a sixteenth aspect, a data processing method for optical communication is provided, comprising: performing forward error correction (FEC) encoding on four acquired first data streams to obtain four second data streams; interleaving the four second data streams to obtain two third data streams; and processing the two third data streams to obtain two dual-polarization symbol streams, wherein consecutive bit blocks A0, A1, A2, A3, A4, A5, A6, A7 in one third data stream and consecutive bit blocks B0, B1 in the other third data stream... B2, B3, B4, B5, B6, and B7 constitute consecutive symbols T0, P0, T1, P1, T2, P2, T3, and P3 in one dual-polarization symbol stream and consecutive symbols T4, P4, T5, P5, T6, P6, T7, and P7 in another dual-polarization symbol stream. Each bit block consists of 8 bits. Ti represents the symbol formed by bit block Ai through DP-16QAM mapping, and Pi represents the symbol formed by bit block Bi through DP-16QAM mapping. i is an integer greater than or equal to 0.

[0056] In conjunction with the sixteenth aspect, in one possible implementation, the two third data streams are processed to obtain two dual-polarized symbol streams. Specifically, this includes: merging the two third data streams to obtain a merged data stream, wherein consecutive bit blocks A0, A1, A2, A3, A4, A5, A6, A7 from one third data stream and consecutive bit blocks B0, B1, B2, B3, B4, B5, B6, B7 from the other third data stream constitute consecutive bit blocks A0, B0, A1, B1, A2, B2, A3, B3, A4, B4, A5, B5, A6, B6, A7, B7 in the merged data stream; performing dual-polarized symbol mapping on the merged data stream to obtain a second dual-polarized symbol stream; and distributing the second dual-polarized symbol stream to obtain two dual-polarized symbol streams.

[0057] Specifically, the above merging can be understood as merging the two third data streams into a single merged data stream using a round-robin approach, with each stream having a granularity of 8 bits (i.e., 1 bit block). The above distribution can be understood as distributing the second dual-polarization symbol stream, with a granularity of 8 DP-16QAM symbols, to the two dual-polarization symbol streams using a round-robin approach. Each of the two dual-polarization symbol streams can correspond to a subcarrier or a wavelength.

[0058] In a seventeenth aspect, a data processing method for optical communication is provided, comprising: performing forward error correction (FEC) encoding on eight acquired first data streams to obtain eight second data streams; interleaving the eight second data streams to obtain four third data streams; and processing the four third data streams to obtain two dual-polarization symbol streams, wherein consecutive bit blocks A0, A1, A2, A3, A4, A5, A6, and A7 in the first third data stream, consecutive bit blocks B0, B1, B2, B3, B4, B5, B6, and B7 in the second third data stream, consecutive bit blocks C0, C1, C2, C3, C4, C5, C6, and C7 in the third third data stream, and consecutive bit blocks D0, D1, D2, D3, D4, and D5 in the fourth third data stream. D6 and D7 constitute consecutive symbols T0, P0, H0, K0, T1, P1, H1, K1, T2, P2, H2, K2, T3, P3, H3, K3 in one dual-polarized symbol stream and consecutive symbols T4, P4, H4, K4, T5, P5, H5, K5, T6, P6, H6, K6, T7, P7, H7, K7 in another dual-polarized symbol stream. Each bit block consists of 8 bits. Ti represents the symbol formed by bit block Ai through DP-16QAM mapping, Pi represents the symbol formed by bit block Bi through DP-16QAM mapping, Hi represents the symbol formed by bit block Ci through DP-16QAM mapping, and Ki represents the symbol formed by bit block Di through DP-16QAM mapping. i is an integer greater than or equal to 0.

[0059] In conjunction with the seventeenth aspect, in one possible implementation, the four third data streams are processed to obtain two dual-polarization symbol streams. Specifically, this includes merging the four third data streams to obtain a merged data stream, wherein the consecutive bit blocks A0, A1, A2, A3, A4, A5, A6, A7 in the first third data stream, the consecutive bit blocks B0, B1, B2, B3, B4, B5, B6, B7 in the second third data stream, the consecutive bit blocks C0, C1, C2, C3, C4, C5, C6, C7 in the third third data stream, and the fourth third data stream... The consecutive bit blocks D0, D1, D2, D3, D4, D5, D6, and D7 in the data stream constitute the consecutive bit blocks A0, B0, C0, D0, A1, B1, C1, D1, A2, B2, C2, D2, A3, B3, C3, D3, A4, B4, C4, D4, A5, B5, C5, D5, A6, B6, C6, D6, A7, B7, C7, and D7 in the merged data stream; the merged data stream is subjected to dual-polarization symbol mapping to obtain a second dual-polarization symbol stream; the second dual-polarization symbol stream is distributed to obtain two dual-polarization symbol streams.

[0060] Specifically, the above merging can be understood as merging the two third data streams into a single merged data stream using a round-robin approach, with each stream having a granularity of 8 bits (i.e., 1 bit block). The above distribution can be understood as distributing the second dual-polarization symbol stream, with a granularity of 16 DP-16QAM symbols, to the two dual-polarization symbol streams using a round-robin approach. Each of the two dual-polarization symbol streams can correspond to a subcarrier or a wavelength.

[0061] Eighteenth aspect, a data processing method for optical communication is provided, comprising: performing forward error correction (FEC) encoding on four acquired first data streams to obtain four second data streams; interleaving the four second data streams to obtain two third data streams; and processing the two third data streams to obtain four fourth data streams, wherein consecutive bit blocks A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15 in one third data stream and consecutive bit blocks B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15 in another third data stream. 15, which constitute the consecutive symbols T0, P0, T1, P1, T2, P2, T3, P3 in the first dual-polarization symbol stream, the consecutive symbols T4, P4, T5, P5, T6, P6, T7, P7 in the second dual-polarization symbol stream, the consecutive symbols T8, P8, T9, P9, T10, P10, T11, P11 in the third dual-polarization symbol stream, and the consecutive symbols T12, P12, T13, P13, T14, P14, T15, P15 in the fourth dual-polarization symbol stream; each bit block includes 8 bits, Ti represents the symbol formed by bit block Ai through DP-16QAM mapping, Pi represents the symbol formed by bit block Bi through DP-16QAM mapping, and i is an integer greater than or equal to 0.

[0062] In conjunction with the eighteenth aspect, in one possible implementation, the two third data streams are processed to obtain four dual-polarization symbol streams. Specifically, this includes merging the two third data streams to obtain a merged data stream, wherein consecutive bit blocks A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15 from one third data stream and consecutive bit blocks B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11 from the other third data stream. 1, B12, B13, B14, and B15 constitute consecutive bit blocks A0, B0, A1, B1, A2, B2, A3, B3, A4, B4, A5, B5, A6, B6, A7, B7, A8, B8, A9, B9, A10, B10, A11, B11, A12, B12, A13, B13, A14, B14, A15, and B15 in the merged data stream; the merged data stream is subjected to dual-polarization symbol mapping to obtain a second dual-polarization symbol stream; the second dual-polarization symbol stream is distributed to obtain four dual-polarization symbol streams.

[0063] Specifically, the above merging can be understood as merging the two third data streams into a single merged data stream in a round-robin manner, with each stream having a granularity of 8 bits (i.e., 1 bit block); the above distribution can be understood as distributing the second dual-polarization symbol stream, with each stream having a granularity of 8 DP-16QAM symbols, to the four dual-polarization symbol streams in a round-robin manner. Each of the four dual-polarization symbol streams can correspond to a subcarrier or a wavelength.

[0064] Nineteenthly, a data processing method for optical communication is provided, comprising: performing forward error correction (FEC) encoding on eight acquired first data streams to obtain eight second data streams; interleaving the eight second data streams to obtain four third data streams; and processing the four third data streams to obtain four fourth data streams, wherein consecutive bit blocks A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, and A15 in the first third data stream, and consecutive bits in the second third data stream... Blocks B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, consecutive bit blocks C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15 in the third data stream, and consecutive bit blocks D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15 in the fourth data stream constitute the first double polarization symbol. The consecutive symbols T0, P0, H0, K0, T1, P1, H1, K1, T2, P2, H2, K2, T3, P3, H3, K3 in the first symbol stream; the consecutive symbols T4, P4, H4, K4, T5, P5, H5, K5, T6, P6, H6, K6, T7, P7, H7, K7 in the second dual-polarized symbol stream; the consecutive symbols T8, P8, H8, K8, T9, P9, H9, K9, T10, P10, H10, K10, T11, P11, H11, K11 in the third dual-polarized symbol stream; and the consecutive symbols in the fourth dual-polarized symbol stream... The symbols are T12, P12, H12, K12, T13, P13, H13, K13, T14, P14, H14, K14, T15, P15, H15, K15; each bit block consists of 8 bits, Ti represents the symbol formed by bit block Ai through DP-16QAM mapping, Pi represents the symbol formed by bit block Bi through DP-16QAM mapping, Hi represents the symbol formed by bit block Ci through DP-16QAM mapping, Ki represents the symbol formed by bit block Di through DP-16QAM mapping, and i is an integer greater than or equal to 0.

[0065] In conjunction with the nineteenth aspect, in one possible implementation, the four third data streams are processed to obtain four dual-polarization symbol streams. Specifically, this includes merging the four third data streams to obtain a merged data stream, wherein consecutive bit blocks A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, and A15 in the first third data stream, and consecutive bit blocks A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, and A15 in the second third data stream... Bit blocks B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15; consecutive bit blocks C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15 in the third data stream; and consecutive bit blocks D0, D1, D2, D3, D4, D5, D6 in the fourth data stream. D7, D8, D9, D10, D11, D12, D13, D14, and D15 constitute consecutive bit blocks A0, B0, C0, D0, A1, B1, C1, D1, A2, B2, C2, D2, A3, B3, C3, D3, A4, B4, C4, D4, A5, B5, C5, D5, A6, B6, C6, D6, A7, B7, C7, D7, A8, B8, C8, D8, and A9 in the merged data stream. A10, B10, C10, D10, A11, B11, C11, D11, A12, B12, C12, D12, A13, B13, C13, D13, A14, B14, C14, D14, A15, B15, C15, D15; The merged data stream is then subjected to dual-polarization symbol mapping to obtain a second dual-polarization symbol stream; the second dual-polarization symbol stream is then distributed to obtain four dual-polarization symbol streams.

[0066] Specifically, the above merging can be understood as merging the two third data streams into a single merged data stream in a round-robin manner, with each stream having a granularity of 8 bits (i.e., 1 bit block); the above distribution can be understood as distributing the second dual-polarization symbol stream, with a granularity of 16 DP-16QAM symbols, to the four dual-polarization symbol streams in a round-robin manner. Each of the four dual-polarization symbol streams can correspond to a subcarrier or a wavelength.

[0067] The effects of the first to nineteenth aspects mentioned above can be referenced from each other, and will not be elaborated upon here. Attached Figure Description

[0068] Figure 1 is a schematic diagram of the optical communication system architecture applicable to this application;

[0069] Figure 2 is a schematic diagram of a data processing method provided in an embodiment of this application;

[0070] Figure 3 is a schematic diagram of the first type of encoding interleaving including PCS processing provided in the embodiments of this application;

[0071] Figure 4 is a schematic diagram of the first type of merged distribution provided in an embodiment of this application;

[0072] Figure 5(a) is a schematic diagram of the second data processing method provided in the embodiment of this application;

[0073] Figure 5(b) is a schematic diagram of the second type of merged distribution provided in the embodiments of this application;

[0074] Figure 6 is a schematic diagram of an OFEC interleaving process provided in an embodiment of this application;

[0075] Figure 7 is a schematic diagram of interlacing within a square matrix provided in an embodiment of this application;

[0076] Figure 8 is a schematic diagram of inter-array interleaving provided in an embodiment of this application;

[0077] Figure 9(a) is a schematic diagram of the third data processing method provided in the embodiments of this application;

[0078] Figure 9(b) is a schematic diagram of the third type of merged distribution provided in the embodiments of this application;

[0079] Figure 10(a) is a schematic diagram of the fourth data processing method provided in the embodiments of this application;

[0080] Figure 10(b) is a schematic diagram of the fourth type of merged distribution provided in the embodiments of this application;

[0081] Figure 11(a) is a schematic diagram of the fifth data processing method provided in the embodiments of this application;

[0082] Figure 11(b) is a schematic diagram of the fifth type of merged distribution provided in the embodiments of this application;

[0083] Figure 12 is a schematic diagram of the sixth data processing method provided in the embodiments of this application;

[0084] Figure 13 is a schematic diagram of the sixth type of merged distribution provided in the embodiments of this application;

[0085] Figure 14 is a schematic diagram of the seventh type of merged distribution provided in the embodiments of this application;

[0086] Figure 15 is a schematic diagram of the eighth type of merged distribution provided in the embodiments of this application;

[0087] Figure 16 is a schematic diagram of the ninth type of merged distribution provided in the embodiments of this application;

[0088] Figure 17 is a schematic diagram of a data processing device provided in an embodiment of this application;

[0089] Figure 18 is a schematic diagram of an optical module provided in an embodiment of this application;

[0090] Figure 19 is a schematic diagram of a communication device provided in an embodiment of this application. Detailed Implementation

[0091] This application provides a data processing method, apparatus, and system to offer a data processing solution suitable for next-generation metropolitan area telecommunications transmission and data center transmission scenarios.

[0092] It should be noted that the terms "first," "second," etc., in this application specification, claims, and the accompanying drawings are used to distinguish similar objects, not to limit a specific order or sequence. It should be understood that the above terms can be interchanged where appropriate so that the embodiments described in this application can be implemented in an order other than that described in this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices. In the description of this application, unless otherwise stated, "a plurality of" means two or more. Additionally, " / " indicates that the related objects are in an "or" relationship; for example, A / B can represent A or B. "And / or" in this application is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone, where A and B can be singular or plural.

[0093] Before providing a detailed explanation of the embodiments of this application, the application scenarios of these embodiments will be described first. This application can be applied to data center transmission scenarios, such as data communication networks (DCN) and data center interconnects (DCI). This application can also be applied to metropolitan area telecommunications transmission scenarios.

[0094] Referring to Figure 1, which is a schematic diagram of the communication system structure applicable to the embodiments of this application, the communication system includes a transmitting end device and a receiving end device. Exemplarily, the transmitting end device may include a signal source, an encoder, and a transmitting end signal processor. The receiving end device may include a receiving end signal processor, a decoder, and a signal sink.

[0095] At the transmitting device, the source provides a stream of bit data to be transmitted. The encoder receives this bit data stream, encodes it, adds check bits, and sends the encoded bits to the transmitting signal processor for symbol mapping and framing, among other digital signal processing. The data is then transmitted through the channel to the receiving device. This framing process ensures that the dual-polarization symbol stream contains not only payload symbols (also called pre-framing symbols) but also several pre-set symbols. These pre-set symbols can be frame synchronization symbols, training symbols, pilot symbols, or reserved symbols. Typically, frame synchronization symbols are used for frame synchronization, training symbols for link training, pilot symbols for carrier phase recovery, and reserved symbols are reserved for future use. At the receiving device, after receiving distorted signals caused by noise or other impairments in the channel, the data is sent to the receiving signal processor for dispersion compensation, synchronization, phase recovery, removal of symbols added during framing, and demapping. The data is then decoded by a decoder to recover the original data and sent to the destination.

[0096] It should be noted that the channel can also be called the channel transmission medium, such as optical fiber. The encoder and the transmitting signal processor can be deployed in a module (or chip or chip system), which can be an optical module, an electrical module, or other modules that process data during data transmission. For example, the optical module can be a coherent optical module. The decoder and the receiving signal processor can also be deployed in a module, which can be an optical module, an electrical module, or other modules that process data during data transmission. The signal source can also be deployed in the same module as the encoder and the transmitting signal processor; this application does not impose specific constraints.

[0097] As business grows, the requirements for transmission rates in metropolitan area telecom transmission, DCN, and DCI scenarios are increasing, leading to higher baud rates. For example, a 1.6Tbps transmission using DP-16QAM and an 800Gbps transmission using DP-QPSK correspond to a baud rate of approximately 240Gbaud. At this point, nonlinear effects such as Enhanced Equalization Phase Noise (EEPN) can cause significant performance degradation. Furthermore, metropolitan area telecom transmission and data center transmission scenarios often require low power consumption. Therefore, current data processing solutions are unsuitable for next-generation metropolitan area telecom transmission, DCN, and DCI scenarios.

[0098] Here, baud refers to the modulation rate. Baud rate represents the number of symbolic units transmitted per unit time. It is a measure of the symbol transmission rate, expressed as the number of times the carrier modulation state changes per unit time. In short, baud rate refers to the number of symbols transmitted per unit time.

[0099] Based on this, embodiments of this application provide a data processing method, apparatus and system for optical communication, which are applicable to next-generation metropolitan area telecommunications, data centers and other transmission scenarios.

[0100] The following is a detailed description of the solutions provided in the embodiments of this application. First, the solutions provided in the embodiments of this application will be described from the perspective of the sending device.

[0101] Figure 2 is a schematic diagram of a data processing method for optical communication provided in an embodiment of this application. This method can be applied to a transmitting device, such as being executed by the transmitting device itself or by a module within the transmitting device. The module within the transmitting device can be a chip or a chip system.

[0102] 201. Perform FEC encoding on each of the 2M first data streams to obtain 2M second data streams; interleave every 2 second data streams in the 2M second data streams to obtain M third data streams, where M is an integer greater than 1.

[0103] For example, the client device in the sending device generates a first data stream to be sent. The bit data stream to be sent can be processed by FEC in a polling and parallel manner. As shown in Figure 2, each of the M FEC processes (0, 1, ..., or M-1) includes 2 FEC encodings and 1 FEC interleaving, resulting in a total of 2M FEC encodings and M FEC interleavings, namely FEC encodings 0 to 2M-1 and FEC interleavings 0 to M-1. FEC interleaving can also be simply referred to as interleaving. Every 2 first data streams in the 2M first data streams are fed into the above FEC processes (0, 1, ..., or M-1) for FEC encoding to obtain 2 second data streams, resulting in a total of 2M second data streams; the 2 second data streams are then FEC interleaved to obtain 1 third data stream, resulting in a total of M third data streams.

[0104] In some specific applications, each FEC code encodes every 3552 bits in the first data stream to obtain 4096 encoded bits. An FEC interleaving separates the output bits of two FEC codes into groups, shuffling their order to improve burst resistance. The block size of the FEC interleaving is 172032 bits. Typically, the above FEC encoding uses open FEC codes, or OFEC codes for short. The 4096 encoded bits are represented by a 2x8 square block, where each square block contains 16 bits in each row and 16 bits in each column, totaling 256 bits. The above FEC interleaving uses an OFEC interleaver, which includes intra-block interleaving and inter-block interleaving.

[0105] In some specific applications, the FEC encoding (0, 1, ..., or M-1) also includes probabilistic constellation shaping (PCS) processing. PCS technology changes the probability of constellation points appearing while keeping their positions unchanged, making them non-uniformly distributed, thereby improving system transmission performance. For example, the information data stream to be transmitted first undergoes PCS processing and PCS interleaving to obtain a first data stream, and then FEC encoding and FEC interleaving are performed. As shown in Figure 3, taking FEC encoding 0 as an example, each k in information data stream 0 (or information data stream 1)... cs k in +1504 bits cs Each bit is processed by PCS 0 (or PCS 1) to obtain 2048 processed bits. The probability of 0 and 1 bits appearing is not equal, where 0... <k cs <2048; k cs The remaining 1504 bits from the +1504 bits have equal probabilities of 0 and 1. These, combined with the bits processed by 2048 PCS, result in a total of 3552 bits. These are then interleaved using PCS 0 (or PCS interleaving 1) to obtain 3552 bits in the first data stream 0 (or first data stream 1). These 3552 bits in the first data stream 0 (or first data stream 1) are then encoded using FEC 0 (FEC encoding 1) to obtain 4096 encoded bits. 2048 bits out of every 3552 bits in the first data stream 0 represent the k bits in the information data stream 0. cs Each bit is obtained through the PCS process, and the probability of its 0 and 1 bits appearing is not equal; 1504 bits out of every 3552 bits in the first data stream 0 are from the information data stream 0, and the probability of their 0 and 1 bits appearing is equal.

[0106] It should be noted that the PCS processing described above can also be called distribution matching (DM) processing. In some specific applications, PCS processing is implemented using a lookup table (LUT), in which case PCS processing is also called LUT processing. The PCS interleaving described above can also be called PCS mapping or block mapping.

[0107] 202. Perform first data processing on M third data streams to obtain W fourth data streams. Perform dual polarization symbol mapping and framing on the W fourth data streams to obtain W first dual polarization symbol streams, where W is an integer greater than 1.

[0108] Each of the M third data streams contains q bits, totaling q×M bits. After the first data processing, these q bits become a single, consecutive q×M bits in one of the W fourth data streams, where q is an integer greater than 1. Furthermore, each of the M third data streams contains q×a bits, totaling q×M×a bits. After the first data processing, this also becomes a single, consecutive q×M×a bits in one of the W fourth data streams, where a is a positive integer and a multiple of 4. In some specific applications, a equals 4.

[0109] In the aforementioned fourth data stream, consecutive q×M×a bits are mapped by double polarization symbols to obtain consecutive M×a double polarization symbols in a double polarization symbol stream, wherein each q bits of the q×M×a bits are mapped by double polarization symbols to obtain one double polarization symbol.

[0110] A dual-polarization (DP) symbol comprises two symbols in two polarization directions. The symbols referred to here are those obtained through symbol mapping processing, also known as modulation symbols. In the embodiments of this application, the two polarization directions are orthogonal, which can be represented as the X-polarization direction and the Y-polarization direction. A dual-polarization symbol includes a symbol in the X-polarization direction and a symbol in the Y-polarization direction. In some descriptions, X-polarization can also be represented by H-polarization, and Y-polarization by V-polarization. In the subsequent descriptions of this application, X-polarization and Y-polarization will be used as examples.

[0111] For DP-QPSK modulation, each q = 4 bits maps to one dual-polarization modulation symbol. For DP-8QAM modulation, each q = 6 bits maps to one dual-polarization modulation symbol. For DP-16QAM modulation, each q = 8 bits maps to one dual-polarization modulation symbol. For DP-32QAM modulation, each q = 10 bits maps to one dual-polarization modulation symbol. For DP-64QAM modulation, each q = 12 bits maps to one dual-polarization modulation symbol.

[0112] This application material considers DP-16QAM mapping, which will use 8 bits (c 8i ,c 8i+1 ,c 8i+2 ,c 8i+3 ,c 8i+4 ,c 8i+5 ,c 8i+6 ,c 8i+7 ) is mapped to one DP-16QAM symbol. For example, (c) in the above 8 bits 8i ,c 8i+2The mapping is to the DP-16QAM symbol in the I-direction distribution (in-phase component) on the X-polarization direction, (c 8i+4 ,c 8i+6 The mapping is the quadrature-phase component of the DP-16QAM symbol in the Q direction of X polarization. 8i+1 ,c 8i+3 The mapping is to the DP-16QAM symbol in the I-direction of Y polarization (in-phase component), (c 8i+5 ,c 8i+7 The quadrature-phase component is mapped to the Q-direction of the DP-16QAM symbol in Y polarization.

[0113] In some possible implementations, PCS technology is also employed to change the probability of constellation points appearing while keeping their positions constant, resulting in a non-uniform distribution and thus improving system transmission performance. In this case, QAM modulation can also be called PCS-QAM modulation; for example, 16QAM is also called PCS-16QAM.

[0114] The dual-polarization symbol stream in this application embodiment can also be called a symbol data stream, a dual-polarization symbol stream, or a dual-polarization stream. Of course, other names can also be used, and this application embodiment does not specifically limit them.

[0115] The framing described above can be performed before dual-polarization symbol mapping. In this case, the framing process inserts a preset bit sequence into each of the W fourth data streams, and then performs dual-polarization symbol mapping to obtain W first dual-polarization symbol streams. Alternatively, framing can be performed after dual-polarization symbol mapping. In this case, the W fourth data streams undergo dual-polarization symbol mapping, and then a preset symbol sequence is inserted to obtain W first dual-polarization symbol streams. This framing operation is beneficial for the receiver to perform synchronization, phase recovery, and other processing, thereby improving the quality of the received signal. Framing can also be called DSP framing.

[0116] In some specific applications, the aforementioned W first dual-polarization symbol streams are each carried on W subcarriers and digitally multiplexed to obtain a single signal for transmission. In this case, the baud rate corresponding to each subcarrier is 1 / W of the transmitted signal baud rate. This allows the receiver to employ a less complex signal processing method to reduce dispersion costs and enhanced equalization phase noise (EEPN) costs, thereby resulting in lower power consumption in the hardware implementation.

[0117] It should be understood that other implementation methods can be used when sending W first dual-polarization symbol streams. For example, the W first dual-polarization symbol streams can be carried on W optical signals for transmission. In this case, the signal baud rate is lower, eliminating the need for devices with higher baud rates and resulting in lower power consumption. In some specific applications, the wavelengths of the aforementioned W optical signals are all different and are transmitted through a single optical fiber. In other specific applications, the aforementioned W optical signals are transmitted through W optical fibers.

[0118] It should be noted that, using the data processing method provided by this invention, the FEC-encoded bits are distributed more evenly across the W dual-polarization symbol streams, so that the decoding errors at the receiving end are more evenly distributed across multiple FEC decoding processes, thereby improving the encoding and decoding performance.

[0119] It should be noted that the first data processing described above can be implemented in two steps. For example, first, M third data streams are merged to obtain one merged data stream, and then this merged data stream is distributed to obtain W fourth data streams. In some specific applications, the M third data streams are merged in a round-robin manner at a granularity of q bits to obtain one merged data stream; the merged data stream is then distributed in a round-robin manner at a granularity of q×M×a bits to obtain W fourth data streams. This application material considers DP-16QAM mapping, where q = 8, that is, the M third data streams are merged in a round-robin manner at a granularity of 8 bits to obtain one merged data stream.

[0120] The aforementioned merging can also be called bit block merging, block merging, etc., and other names are not specifically limited in this application. The aforementioned distribution can also be called other names, such as data stream partitioning, wavelength distribution, splitting, demultiplexing, allocation, interleaving, etc., and no specific limitation is made here. The following description in this application will use distribution as an example.

[0121] As shown in Figure 4, consider a = 4. Each of the M third data streams has 4 × q bits. Using q bits as the granularity, a round-robin method is used to merge the data to obtain a single merged data stream containing 4×q×M consecutive bits. in represents q bits (also referred to as a bit block, or a bit group, or a bit set), where 0 ≤ i < M and 0 ≤ j < 4. The above 4×q×M bits are distributed in one of the W fourth data streams, for example, the consecutive 4×q×M bits in the fourth data stream 0 in Figure 4. The above consecutive 4×q×M bits are subjected to dual-polarization symbol mapping to obtain consecutive 4×M dual-polarization symbols. In this application material, DP-16QAM mapping is considered, with q = 8. That is, the above 1 merged data stream is distributed in a polling manner in units of 32×M bits to obtain W fourth data streams. For example, considering M = 4, the above distribution is in units of 128 bits, and the bits in the above 1 merged data stream are distributed to W fourth data streams in a polling manner. Another example, considering M = 2, the above distribution is in units of 64 bits, and the bits in the above 1 merged data stream are distributed to W fourth data streams in a polling manner.

[0122] Taking DP-16QAM (i.e., q = 8) and a = 4 as an example, several specific embodiments are given in combination with the values of M and W. Here, sji also represents q bits, which are 8 bits here and are called a bit set or a bit block.

[0123] Embodiment 1: Consider the case where M = 4 and W = 4

[0124] As shown in Figure 5(a), 8 first data streams are respectively subjected to FEC encoding to obtain 8 second data streams, where the FEC encoding uses OFEC encoding. The 8 second data streams are subjected to FEC interleaving to obtain 4 third data streams. Among them, 2 of the 8 second data streams are subjected to FEC interleaving to obtain 1 third data stream, and the FEC interleaving uses OFEC interleaving. Here, an implementation manner of OFEC interleaving is given in this embodiment. The OFEC interleaving in other embodiments can also refer to the implementation manner given in this embodiment and will not be elaborated later.

[0125] Specifically, each OFEC interleaver receives the bits output by 2 OFEC encoders (from 2 second data streams), and performs "intra-block interleaving" and "inter-block interleaving" to obtain 1 third data stream. Figure 6 introduces OFEC interleaving 0 as an example. Among them, the second data stream 0 and the second data stream 1 respectively perform intra-block interleaving, and then perform inter-block interleaving to obtain the third data stream 0.

[0126] Figure 7 is a schematic diagram of intra-block interleaving in an embodiment of this application. As shown in Figure 7, the OFEC interleaver first performs intra-block interleaving on each received matrix, that is, each 16x16 input matrix is ​​interleaved and shuffled according to the interleaving rules shown in Figure 14 to obtain a 16x16 output matrix. In Figure 7, the element in the i1th row and j1st column (0≤i1<16 and 0≤j1<16) is (a,b), which indicates that the bit in the i1th row and j1st column of the output matrix after intra-block interleaving comes from the bit in the ath row and bth column of the input matrix. For example, if the element in the 1st row and 0th column of Figure 7 is (14,15), then the bit in the 1st row and 0th column of the output matrix after intra-block interleaving comes from the bit in the 14th row and 15th column of the input matrix.

[0127] Bits that have undergone intra-block interleaving are then inter-block interleaving to improve overall burst resistance. The inter-block interleaving operation is described below.

[0128] Figure 8 is a schematic diagram of inter-matrix interleaving in an embodiment of this application. As shown in Figure 8, the inter-matrix interleaving includes an 84-row, 8-column interleaving buffer M, with each row containing 8 matrices, and each matrice containing 16 rows and 16 columns, totaling 256 bits. The size of the interleaving buffer for inter-matrix interleaving is 84 × 8 × 256 = 172032 bits, corresponding to 172032 / 4096 = 42 output packets interleaved within the matrices. Among these, 21 output packets come from the output packets interleaved within one of the matrices and are located in even-numbered rows of the interleaving buffer M, while the other 21 output packets come from the output packets interleaved within the other matrices and are located in odd-numbered rows of the interleaving buffer M. Here, each output packet is a 2-row, 8-column matrice set totaling 4096 bits, which is the 2-row, 8-column matrice set obtained by interleaving the 4096 bits output by the OFEC encoder within the matrices. The interleaving buffer M, which is interleaved between square matrices, can be divided into 4 sets, as shown in Figure 8. Set 0 contains a total of 21 × 16 × 128 = 43008 bits of square matrices in rows 0, 2, 4, ..., 40 of interleaving buffer M. Set 1 contains a total of 43008 bits of square matrices in rows 1, 3, 5, ..., 41 of interleaving buffer M. Set 2 contains a total of 43008 bits of square matrices in rows 42, 44, 46, ..., 82 of interleaving buffer M. Set 3 contains a total of 43008 bits of square matrices in rows 43, 45, 47, ..., 83 of interleaving buffer M.

[0129] Bits in each column are read from the interleaved buffer M in 8-bit granularities, polling each set in turn. After reading all bits in each column, the next column is read. First, the first group of 8 bits is read from set 0 from top to bottom. Then, the first 8 bits are read from sets 1, 2, and 3 respectively from top to bottom, for a total of 32 bits per cycle. Next, the next cycle reads the next group of 8 bits from sets 0, 1, 2, and 3 respectively from top to bottom, for a total of 32 bits. After a total of 42 cycles, the current column of 1344 bits is read. The specific operation for reading bits from each column from each set is as follows:

[0130] First, read 8 bits sequentially from top to bottom from the 0th row of the interleaved buffer M (the 0th to 7th bit row of the matrix).

[0131] Read 8 bits sequentially from top to bottom from the first row of the interleaved buffer M (the 0th to 7th bit row of the matrix).

[0132] Read 8 bits sequentially from top to bottom from the 42nd row of the interleaved buffer M (the 0th to 7th bit row of the matrix).

[0133] Read 8 bits sequentially from top to bottom from the 43rd row of the interleaved buffer M (the 0th to 7th bit row of the matrix).

[0134] Then, read 8 bits sequentially from top to bottom from the 0th row of the interleaved buffer M (the 8th to 15th bit row of the matrix).

[0135] Read 8 bits sequentially from top to bottom from the first row of the interleaved buffer M (row 8-15 of the matrix).

[0136] Read 8 bits sequentially from top to bottom from the 42nd row of the interleaved buffer M (row 8-15 in the matrix).

[0137] Read 8 bits sequentially from top to bottom from the 43rd row of the interleaved buffer M (row 8-15 in the matrix).

[0138] Then, read 8 bits sequentially from top to bottom from the second row of the interleaved buffer M (the 0th to 7th bit row of the matrix).

[0139] …, until all 1344 bits in the current bit column of the interleaved buffer M have been read out.

[0140] After OFEC interleaving, a third data stream is obtained, resulting in a total of four third data streams. More specifically, as shown in Figure 5(a), in third data stream 0... A total of 4 × q = 32 bits, in the third data stream 1 A total of 4 × q = 32 bits, in the third data stream 2 A total of 4 × q = 32 bits, in the third data stream 3 A total of 4 × q = 32 bits, or 128 bits in total, are processed by the first data stream to obtain 16 × q = 128 consecutive bits in the fourth data stream 0. Of the 128 bits, 4 × q = 32 consecutive bits come from four third data streams, for example, in the fourth data stream 0. These are 8 bits from third data stream 0, 8 bits from third data stream 1, 8 bits from third data stream 2, and 8 bits from third data stream 3, respectively. Here, It represents 8 bits (also called a bit block, bit group, or bit set).

[0141] In the third data stream 0 A total of 4 × q = 32 bits, in the third data stream 1 A total of 4 × q = 32 bits, in the third data stream 2 A total of 4 × q = 32 bits, in the third data stream 3 A total of 4 × q = 32 bits, or 128 bits in total, are processed by the first data stream to obtain 16 × q = 128 consecutive bits in the fourth data stream 1. Of the 128 bits, 4 × q = 32 consecutive bits come from four third data streams, for example, in the fourth data stream 1. These are 8 bits from the third data stream 0, 8 bits from the third data stream 1, 8 bits from the third data stream 2, and 8 bits from the third data stream 3.

[0142] In the third data stream 0 A total of 4 × q = 32 bits, in the third data stream 1 A total of 4 × q = 32 bits, in the third data stream 2 A total of 4 × q = 32 bits, in the third data stream 3 A total of 4 × q = 32 bits, or 128 bits in total, are processed by the first data stream to obtain 16 × q = 128 consecutive bits in the fourth data stream 2. Of the 128 bits, 4 × q = 32 consecutive bits come from four third data streams, such as the fourth data stream 2. These are 8 bits from the third data stream 0, 8 bits from the third data stream 1, 8 bits from the third data stream 2, and 8 bits from the third data stream 3.

[0143] In the third data stream 0 A total of 4 × q = 32 bits, in the third data stream 1 A total of 4 × q = 32 bits, in the third data stream 2 A total of 4 × q = 32 bits, in the third data stream 3 A total of 4 × q = 32 bits, or 128 bits in total, are processed by the first data stream to obtain 16 × q = 128 consecutive bits in the fourth data stream 3. Of the 128 bits, 4 × q = 32 consecutive bits come from four third data streams, such as the fourth data stream 3. These are 8 bits from the third data stream 0, 8 bits from the third data stream 1, 8 bits from the third data stream 2, and 8 bits from the third data stream 3.

[0144] The four fourth data streams mentioned above are respectively subjected to DP-16QAM dual-polarization symbol mapping and framing to obtain four first dual-polarization symbol streams. The above bit blocks contain 8 bits each. One DP-16QAM dual-polarization symbol is obtained by mapping the dual-polarization 16QAM symbol.

[0145] It should be understood that the bit blocks mentioned above can also be represented in another way. For example, let A, B, C, and D represent four third data streams, where the bit blocks in third data stream 0 are represented by A, the bit blocks in third data stream 1 by B, the bit blocks in third data stream 2 by C, and the bit blocks in third data stream 3 by D. In this case, They can be represented by A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14 and A15 respectively; They can be represented by B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14 and B15 respectively; They can be represented by C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14 and C15 respectively; These can be represented by D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, and D15, respectively. Subsequent embodiments also satisfy the above conditions, and will not be described in detail hereafter.

[0146] The aforementioned four first dual-polarization symbol streams are each carried on four subcarriers and digitally multiplexed to obtain a single signal for transmission. In this case, the baud rate corresponding to each subcarrier is 1 / 4 of the transmitted signal baud rate. This allows the receiver to employ a lower-complexity implementation for signal processing, reducing dispersion and EEPN costs, thereby resulting in lower power consumption in the hardware implementation.

[0147] The specific method described in this embodiment ensures that the OFEC-encoded bit data is evenly distributed across the four dual-polarization symbol streams, i.e., the four subcarriers. More specifically, the 4096 encoded bits after OFEC encoding are represented by a 2x8 matrix, where each matrix contains 16 bits in each row and 16 bits in each column, totaling 256 bits. These 256 bits in each matrix are evenly distributed across the four dual-polarization symbol streams, and also evenly distributed across the X and Y polarization directions within each dual-polarization symbol stream. This means that each bit has a total of eight possible mapping positions, allowing decoding errors at the receiver to be more evenly distributed across multiple FEC decoding processes, thus improving FEC decoding performance. Furthermore, after the OFEC interleaving and the first data processing described above, these 256 bits can be uniformly mapped to the above 8 positions, and the bits at the same position in each matrix are mapped to the same position. For example, if the first bit in the first matrix is ​​mapped to the X polarization direction of the first dual polarization symbol stream, then the first bit in each matrix is ​​mapped to the X polarization direction of the first dual polarization symbol stream. This simplifies the detection of bit error rate (BER) in each polarization direction of different subcarriers and facilitates hardware implementation.

[0148] Example 2:

[0149] Based on Example 1, a specific implementation of the first data processing is given. As shown in Figure 5(b), four third data streams are merged in a round-robin fashion with a granularity of q = 8 bits to obtain one merged data stream. More specifically, in third data stream 0... A total of 16 × q = 128 bits, in the third data stream 1 A total of 16 × q = 128 bits, in the third data stream 2 A total of 16 × q = 128 bits, in the third data stream 3 A total of 16 × q = 128 bits, or 512 bits in total, are merged to obtain 512 consecutive bits in the merged data stream.

[0150] The aforementioned merged data stream, with a granularity of q×M×a = 128 bits, is distributed using a round-robin method to obtain four fourth data streams. More specifically, the 512 consecutive bits from the merged data stream are distributed into the four fourth data streams, of which 128 bits... Distributed to the fourth data stream 0, 128 bits Distributed to the fourth data stream 1, 128 bits Distributed to the fourth data stream 2, 128 bits Distribute to the fourth data stream 3.

[0151] In some existing implementations for short-distance transmission, a merged data stream is directly mapped to dual polarization symbols and framed without being distributed, resulting in a single dual polarization symbol stream to be transmitted. In this case, the solution presented in this embodiment is more compatible with existing methods and can be used for longer-distance transmission scenarios, resulting in lower power consumption.

[0152] Example 3: Consider the case where M=4 and W=2

[0153] As shown in Figure 9(a), the eight first data streams are each FEC encoded to obtain eight second data streams, where the FEC encoding uses OFEC encoding. The eight second data streams are then FEC interleaved to obtain four third data streams. Two of the eight second data streams are then FEC interleaved to obtain one third data stream, where the FEC interleaving uses OFEC interleaving.

[0154] In the third data stream 0 A total of 4 × q = 32 bits, in the third data stream 1 A total of 4 × q = 32 bits, in the third data stream 2 A total of 4 × q = 32 bits, in the third data stream 3 A total of 4 × q = 32 bits, or 128 bits in total, are processed by the first data stream to obtain 16 × q = 128 consecutive bits in the fourth data stream 0. Of the 128 bits, 4 × q = 32 consecutive bits come from four third data streams, for example, in the fourth data stream 0. These are 8 bits from the third data stream 0, 8 bits from the third data stream 1, 8 bits from the third data stream 2, and 8 bits from the third data stream 3.

[0155] In the third data stream 0 A total of 4 × q = 32 bits, in the third data stream 1 A total of 4 × q = 32 bits, in the third data stream 2 A total of 4 × q = 32 bits, in the third data stream 3 A total of 4 × q = 32 bits, or 128 bits in total, are processed by the first data stream to obtain 16 × q = 128 consecutive bits in the fourth data stream 1. Of the 128 bits, 4 × q = 32 consecutive bits come from four third data streams, for example, in the fourth data stream 1. These are 8 bits from the third data stream 0, 8 bits from the third data stream 1, 8 bits from the third data stream 2, and 8 bits from the third data stream 3.

[0156] The two fourth data streams mentioned above are respectively subjected to DP-16QAM dual-polarization symbol mapping and framing to obtain two first dual-polarization symbol streams. The aforementioned bit blocks contain 8 bits. One DP-16QAM dual-polarization symbol is obtained by mapping the dual-polarization 16QAM symbol.

[0157] The two first dual-polarization symbol streams mentioned above are each carried on two subcarriers and digitally multiplexed to obtain a single signal for transmission. In this case, the baud rate corresponding to each subcarrier is half the baud rate of the transmitted signal. This allows the receiver to use a less complex implementation method for signal processing, reducing dispersion and EEPN costs, thereby resulting in lower power consumption in the hardware implementation.

[0158] The specific method described in this embodiment ensures that the OFEC-encoded bit data is evenly distributed across two dual-polarization symbol streams, i.e., two subcarriers. More specifically, the 4096 encoded bits after OFEC encoding are represented by a 2x8 matrix, where each matrix contains 16 bits in each row and 16 bits in each column, totaling 256 bits. These 256 bits in each matrix are evenly distributed across the two dual-polarization symbol streams and along the X and Y polarization directions within each stream. This means each bit has four possible mapping positions, allowing for a more even distribution of decoding errors across multiple FEC decoding processes at the receiver, thus improving FEC decoding performance. Furthermore, after the OFEC interleaving and the first data processing, these 256 bits can be evenly mapped to the four positions, and bits at the same position in each matrix are mapped to the same location. This simplifies bit error rate (BER) detection across each polarization direction of different subcarriers and facilitates hardware implementation.

[0159] Example 4:

[0160] Based on Example 3, a specific implementation of the first data processing is given. As shown in Figure 9(b), four third data streams are merged in a round-robin fashion with a granularity of q = 8 bits to obtain one merged data stream. More specifically, in third data stream 0... A total of 8 × q = 64 bits, in the third data stream 1 A total of 8 × q = 64 bits, in the third data stream 2 A total of 8 × q = 64 bits, in the third data stream 3 A total of 8 × q = 64 bits, or 256 bits in total, are merged to obtain 256 consecutive bits in the merged data stream.

[0161] The merged data stream, with a granularity of q×M×a = 128 bits, is distributed using a round-robin method to obtain two fourth data streams. More specifically, the aforementioned 256 consecutive bits from the merged data stream are distributed into the two fourth data streams, of which 128 bits... Distributed to the fourth data stream 0, 128 bits Distribute to the fourth data stream 1.

[0162] In some existing implementations for short-distance transmission, a merged data stream is directly mapped to dual polarization symbols and framed without being distributed, resulting in a single dual polarization symbol stream to be transmitted. In this case, the solution presented in this embodiment is more compatible with existing methods and can be used for longer-distance transmission scenarios, resulting in lower power consumption.

[0163] Example 5: Consider the case where M=2 and W=4

[0164] As shown in Figure 10(a), the four first data streams are respectively FEC encoded to obtain four second data streams, where the FEC encoding uses OFEC encoding. The four second data streams are FEC interleaved to obtain two third data streams, where two of the four second data streams are FEC interleaved to obtain one third data stream, and the FEC interleaving uses OFEC interleaving.

[0165] In the third data stream 0 A total of 4 × q = 32 bits, in the third data stream 1 A total of 4 × q = 32 bits, or 64 bits in total, are processed by the first data stream to obtain 8 × q = 64 consecutive bits in the fourth data stream 0. Of the 64 bits, 2 × q = 16 consecutive bits come from two third data streams, for example, from fourth data stream 0. These are 8 bits from the third data stream 0 and 8 bits from the third data stream 1, respectively.

[0166] In the third data stream 0 A total of 4 × q = 32 bits, in the third data stream 1 A total of 4 × q = 32 bits, or 64 bits in total, are processed by the first data stream to obtain 8 × q = 64 consecutive bits in the fourth data stream 1. Of the 64 bits, 2 × q = 16 consecutive bits come from two third data streams, for example, in fourth data stream 1. These are 8 bits from the third data stream 0 and 8 bits from the third data stream 1, respectively.

[0167] In the third data stream 0 A total of 4 × q = 32 bits, in the third data stream 1 A total of 4 × q = 32 bits, or 64 bits in total, are processed by the first data stream to obtain 8 × q = 64 consecutive bits in the fourth data stream 2. Of the 64 bits, 2 × q = 16 consecutive bits come from two third data streams, for example, in fourth data stream 2. These are 8 bits from the third data stream 0 and 8 bits from the third data stream 1, respectively.

[0168] In the third data stream 0 A total of 4 × q = 32 bits, in the third data stream 1 A total of 4 × q = 32 bits, or 64 bits in total, are processed by the first data stream to obtain 8 × q = 64 consecutive bits in the fourth data stream 3. Of the 64 bits, 2 × q = 16 consecutive bits come from two third data streams, for example, from the fourth data stream 3. These are 8 bits from the third data stream 0 and 8 bits from the third data stream 1, respectively.

[0169] The four fourth data streams mentioned above are respectively subjected to DP-16QAM dual-polarization symbol mapping and framing to obtain four first dual-polarization symbol streams. The above bit blocks contain 8 bits each. One DP-16QAM dual-polarization symbol is obtained by mapping the dual-polarization 16QAM symbol.

[0170] The aforementioned four first dual-polarization symbol streams are each carried on four subcarriers and digitally multiplexed to obtain a single signal for transmission. In this case, the baud rate corresponding to each subcarrier is 1 / 4 of the transmitted signal baud rate. This allows the receiver to employ a lower-complexity implementation for signal processing, reducing dispersion and EEPN costs, thereby resulting in lower power consumption in the hardware implementation.

[0171] The specific method described in this embodiment ensures that the OFEC-encoded bit data is evenly distributed across the four dual-polarization symbol streams, i.e., the four subcarriers. More specifically, the 4096 encoded bits after OFEC encoding are represented by a 2x8 matrix, where each matrix contains 16 bits in each row and 16 bits in each column, totaling 256 bits. These 256 bits in each matrix are evenly distributed across the four dual-polarization symbol streams and evenly distributed along the X and Y polarization directions within each stream. This means each bit has eight possible mapping positions, allowing for a more even distribution of decoding errors across multiple FEC decoding processes at the receiver, thus improving FEC decoding performance. Furthermore, after the OFEC interleaving and the first data processing, these 256 bits can be evenly mapped to the eight positions, and bits at the same position in each matrix are mapped to the same location. This simplifies bit error rate (BER) detection across each polarization direction of different subcarriers and facilitates hardware implementation.

[0172] Example 6:

[0173] Based on Example 5, a specific implementation of the first data processing is given. As shown in Figure 10(b), two third data streams are merged in a round-robin fashion with a granularity of q = 8 bits to obtain one merged data stream. More specifically, in third data stream 0... A total of 16 × q = 128 bits, in the third data stream 1 A total of 16 × q = 128 bits, or 256 bits in total, are merged to obtain 256 consecutive bits in the merged data stream.

[0174] The merged data stream, with a granularity of q×M×a = 64 bits, is distributed in a round-robin fashion to obtain four fourth data streams. More specifically, the aforementioned 256 consecutive bits from the merged data stream are distributed into the four fourth data streams, of which 64 bits... Distributed to the fourth data stream 0, 64 bits Distributed to the fourth data stream 1, 64 bits Distributed to the fourth data stream 2, 64 bits Distribute to the fourth data stream 3.

[0175] In some existing implementations for short-distance transmission, a merged data stream is directly mapped to dual polarization symbols and framed without being distributed, resulting in a single dual polarization symbol stream to be transmitted. In this case, the solution presented in this embodiment is more compatible with existing methods and can be used for longer-distance transmission scenarios, resulting in lower power consumption.

[0176] Example 7: Consider the case where M=2 and W=2

[0177] As shown in Figure 11(a), the four first data streams are respectively FEC encoded to obtain four second data streams, where the FEC encoding uses OFEC encoding. The four second data streams are FEC interleaved to obtain two third data streams, where two of the four second data streams are FEC interleaved to obtain one third data stream, and the FEC interleaving uses OFEC interleaving.

[0178] In the third data stream 0 A total of 4 × q = 32 bits, in the third data stream 1 A total of 4 × q = 32 bits, or 64 bits in total, are processed by the first data stream to obtain 8 × q = 64 consecutive bits in the fourth data stream 0. Of the 64 bits, 2 × q = 16 consecutive bits come from two third data streams, for example, from fourth data stream 0. These are 8 bits from the third data stream 0 and 8 bits from the third data stream 1, respectively.

[0179] In the third data stream 0 A total of 4 × q = 32 bits, in the third data stream 1 A total of 4 × q = 32 bits, or 64 bits in total, are processed by the first data stream to obtain 8 × q = 64 consecutive bits in the fourth data stream 1. Of the 64 bits, 2 × q = 16 consecutive bits come from two third data streams, for example, in fourth data stream 1. These are 8 bits from the third data stream 0 and 8 bits from the third data stream 1, respectively.

[0180] The two fourth data streams mentioned above are respectively subjected to DP-16QAM dual-polarization symbol mapping and framing to obtain two first dual-polarization symbol streams. The aforementioned bit blocks contain 8 bits. One DP-16QAM dual-polarization symbol is obtained by mapping the dual-polarization 16QAM symbol.

[0181] The two first dual-polarization symbol streams mentioned above are each carried on two subcarriers and digitally multiplexed to obtain a single signal for transmission. In this case, the baud rate corresponding to each subcarrier is half the baud rate of the transmitted signal. This allows the receiver to use a less complex implementation method for signal processing, reducing dispersion and EEPN costs, thereby resulting in lower power consumption in the hardware implementation.

[0182] The specific method described in this embodiment ensures that the OFEC-encoded bit data is evenly distributed across two dual-polarization symbol streams, i.e., two subcarriers. More specifically, the 4096 encoded bits after OFEC encoding are represented by a 2x8 matrix, where each matrix contains 16 bits in each row and 16 bits in each column, totaling 256 bits. These 256 bits in each matrix are evenly distributed across the two dual-polarization symbol streams and along the X and Y polarization directions within each stream. This means each bit has four possible mapping positions, allowing for a more even distribution of decoding errors across multiple FEC decoding processes at the receiver, thus improving FEC decoding performance. Furthermore, after the OFEC interleaving and the first data processing, these 256 bits can be evenly mapped to the four positions, and bits at the same position in each matrix are mapped to the same location. This simplifies bit error rate (BER) detection across each polarization direction of different subcarriers and facilitates hardware implementation.

[0183] Example 8:

[0184] Based on Example 7, a specific implementation of the first data processing is given. As shown in Figure 11(b), two third data streams are merged in a round-robin fashion with a granularity of q = 8 bits to obtain one merged data stream. More specifically, in the third data stream 0... A total of 8 × q = 64 bits, in the third data stream 1 A total of 8 × q = 64 bits, or 128 bits in total, are merged to obtain 128 consecutive bits in the merged data stream.

[0185] The merged data stream, with a granularity of q×M×a = 64 bits, is distributed using a round-robin method to obtain two fourth data streams. More specifically, the aforementioned 128 consecutive bits from the merged data stream are distributed into the two fourth data streams, of which 64 bits... Distributed to the fourth data stream 0, 64 bits Distribute to the fourth data stream 1.

[0186] In some existing implementations for short-distance transmission, a merged data stream is directly mapped to dual polarization symbols and framed without being distributed, resulting in a single dual polarization symbol stream to be transmitted. In this case, the solution presented in this embodiment is more compatible with existing methods and can be used for longer-distance transmission scenarios, resulting in lower power consumption.

[0187] It should be noted that in the first aspect mentioned above, "firstly, the M third data streams are merged to obtain one merged data stream, and then the merged data stream is distributed to obtain W fourth data streams; the W fourth data streams are subjected to dual-polarization symbol mapping and framing to obtain W first dual-polarization symbol streams," the distribution operation is performed before the dual-polarization symbol mapping, that is, the distribution is performed on the bit stream, which can also be called bit distribution. In the second aspect of this application, the distribution operation is considered to be performed after the dual-polarization symbol mapping, that is, the distribution is performed on the dual-polarization symbol stream, which can also be called dual-polarization symbol distribution. The specific operation will be described in detail below with reference to Figure 12.

[0188] 301. Perform FEC encoding on each of the 2M first data streams to obtain 2M second data streams, and interleave every 2 second data streams in the 2M second data streams to obtain M third data streams, where M is an integer greater than 1.

[0189] Please refer to the specific description of operation 201 above; it will not be repeated here.

[0190] 302. Merge M third data streams to obtain 1 merged data stream, perform dual-polarization symbol mapping to obtain 1 second dual-polarization symbol stream, and perform dual-polarization symbol distribution on the 1 second dual-polarization symbol stream to obtain W third dual-polarization symbol streams.

[0191] In some specific applications, M third data streams are merged in a round-robin fashion, with a granularity of q bits, to obtain a single merged data stream.

[0192] Each q bits in the merged data stream described above is mapped to a single polarized symbol to obtain a second polarized symbol stream. When considering DP-16QAM symbol mapping, the positive integer q is 8.

[0193] The aforementioned second dual-polarization symbol stream is grouped into M×a dual-polarization symbols and distributed using a round-robin method to obtain W third dual-polarization symbol streams. These W third dual-polarization symbol streams are then framed to obtain W first dual-polarization symbol streams. Here, a is a positive integer and a multiple of 4. In some specific applications, a equals 4.

[0194] The q×a bits in each of the M third data streams, totaling q×M×a bits, are merged, mapped to dual polarization symbols, and distributed to dual polarization symbols as described above, resulting in M×a consecutive dual polarization symbols in one of the W third dual polarization symbol streams.

[0195] In some specific applications, considering a = 4, the aforementioned second dual-polarization symbol stream is divided into groups of 4M dual-polarization symbols, and distributed using a polling method to obtain W third dual-polarization symbol streams. Each of the M third data streams contains 32 bits, totaling 32 × M bits. After the aforementioned merging, dual-polarization symbol mapping, and dual-polarization symbol distribution, a single third dual-polarization symbol stream containing 4 × M consecutive dual-polarization symbols is obtained from the aforementioned W third dual-polarization symbol streams.

[0196] 303, W third dual-polarization symbol streams are framed to obtain W first dual-polarization symbol streams.

[0197] The framing operation inserts W third-polarized symbol streams into a preset symbol sequence to obtain W first-polarized symbol streams. This framing operation facilitates synchronization and phase recovery at the receiver, thereby improving the quality of the received signal. Framing can also be called DSP framing.

[0198] In some specific applications, the aforementioned W first dual-polarization symbol streams are each carried on W subcarriers and digitally multiplexed to obtain a single signal for transmission. In this case, the baud rate corresponding to each subcarrier is 1 / W of the transmitted signal baud rate. This allows the receiver to employ a less complex signal processing method to reduce dispersion costs and enhanced equalization phase noise (EEPN) costs, thereby resulting in lower power consumption in the hardware implementation.

[0199] It should be understood that other implementation methods can be used when sending W first dual-polarization symbol streams. For example, the W first dual-polarization symbol streams can be carried on W optical signals for transmission. In this case, the signal baud rate is lower, eliminating the need for devices with higher baud rates and resulting in lower power consumption. In some specific applications, the wavelengths of the aforementioned W optical signals are all different and are transmitted through a single optical fiber. In other specific applications, the aforementioned W optical signals are transmitted through W optical fibers.

[0200] It should be noted that, using the data processing method provided by this invention, the FEC-encoded bits are distributed more evenly in the aforementioned W first dual-polarization symbol streams, so that the decoding errors at the receiving end are more evenly distributed across multiple FEC decoding processes, thereby improving the encoding and decoding performance.

[0201] The following uses DP-16QAM (i.e., q=8) and a=4 as an example, and combines the values ​​of M and W to give several specific embodiments for the second aspect of this application.

[0202] Example 9: Consider the case where M=4 and W=4

[0203] Referring to Figure 12, 2M = 8 first data streams are each FEC encoded to obtain 8 second data streams, where OFEC encoding is used. The 8 second data streams are FEC interleaved to obtain 4 third data streams, where 2 of the 8 second data streams are FEC interleaved to obtain 1 third data stream, where OFEC interleaving is used.

[0204] As shown in Figure 13, in the third data stream 0 A total of 16 × q = 128 bits, in the third data stream 1 A total of 16 × q = 128 bits, in the third data stream 2 A total of 16 × q = 128 bits, in the third data stream 3 A total of 16 × q = 128 bits are used, and a total of 512 bits are merged to obtain 512 consecutive bits in the merged data stream. The aforementioned 512 bits are mapped using DP-16QAM dual-polarization symbol mapping to obtain 64 dual-polarization symbols in the second dual-polarization symbol data stream.

[0205] The aforementioned 64 dual-polarization symbols are grouped into sets of M×a = 16 dual-polarization symbols. A polling method is used to distribute the dual-polarization symbols, resulting in four third dual-polarization symbol streams. The 16 consecutive dual-polarization symbols... Located in the third double-polarized symbol stream 0, 16 consecutive double-polarized symbols Located in the third dual-polarization symbol stream 1, 16 consecutive dual-polarization symbols Located in the third dual-polarization symbol stream 2, 16 consecutive dual-polarization symbols Located in the third dual-polarization symbol stream 3.

[0206] The above four third dual-polarization symbol streams are framed to obtain four first dual-polarization symbol streams.

[0207] It should be understood that the above-mentioned double polarization symbols can also be expressed in another way. For example, T, P, H, and K can be used to represent four third double polarization symbol streams, where the symbols in third double polarization symbol stream 0 are represented by T, the symbols in third double polarization symbol stream 1 by P, the symbols in third double polarization symbol stream 2 by H, and the symbols in third double polarization symbol stream 3 by K. In this case, They can be represented by T0, T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14 and T15 respectively; They can be represented by P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14 and P15 respectively; They can be represented by H0, H1, H2, H3, H4, H5, H6, H7, H8, H9, H10, H11, H12, H13, H14 and H15 respectively; These can be represented by K0, K1, K2, K3, K4, K5, K6, K7, K8, K9, K10, K11, K12, K13, K14, and K15, respectively. Subsequent embodiments also satisfy the above conditions, and will not be described in detail hereafter.

[0208] The aforementioned four first dual-polarization symbol streams are each carried on four subcarriers and digitally multiplexed to obtain a single signal for transmission. In this case, the baud rate corresponding to each subcarrier is 1 / 4 of the transmitted signal baud rate. This allows the receiver to employ a lower-complexity implementation for signal processing, reducing dispersion and EEPN costs, thereby resulting in lower power consumption in the hardware implementation.

[0209] The specific method described in this embodiment ensures that the OFEC-encoded bit data is evenly distributed across the four dual-polarization symbol streams, i.e., the four subcarriers. More specifically, the 4096 encoded bits after OFEC encoding are represented by a 2x8 matrix, where each matrix contains 16 bits in each row and 16 bits in each column, totaling 256 bits. These 256 bits in each matrix are evenly distributed across the four dual-polarization symbol streams and evenly distributed along the X and Y polarization directions within each stream. This means each bit has eight possible mapping positions, allowing for a more even distribution of decoding errors across multiple FEC decoding processes at the receiver, thus improving FEC decoding performance. Furthermore, after the OFEC interleaving and the first data processing, these 256 bits can be evenly mapped to the eight positions, and bits at the same position in each matrix are mapped to the same location. This simplifies bit error rate (BER) detection across each polarization direction of different subcarriers and facilitates hardware implementation.

[0210] In some existing implementations for short-distance transmission, a merged data stream is first mapped to dual polarization symbols, and then directly framed without distribution to obtain a single dual polarization symbol stream to be transmitted. In this case, the solution presented in this embodiment is more compatible with existing methods and can be used for scenarios with longer transmission distances, resulting in lower power consumption.

[0211] Example 10: Consider the case where M=4 and W=2

[0212] Referring to Figure 12, 2M = 8 first data streams are each FEC encoded to obtain 8 second data streams, where OFEC encoding is used. The 8 second data streams are FEC interleaved to obtain 4 third data streams, where 2 of the 8 second data streams are FEC interleaved to obtain 1 third data stream, where OFEC interleaving is used.

[0213] As shown in Figure 14, in the third data stream 0 A total of 8 × q = 64 bits, in the third data stream 1 A total of 8 × q = 64 bits, in the third data stream 2 A total of 8 × q = 64 bits, in the third data stream 3 A total of 8 × q = 64 bits, or 256 bits in total, are merged to obtain 256 consecutive bits in the merged data stream. The aforementioned 256 bits are mapped using DP-16QAM dual-polarization symbols to obtain 32 dual-polarization symbols in the second dual-polarization symbol data stream.

[0214] The aforementioned 32 dual-polarization symbols are grouped into sets of M×a = 16 dual-polarization symbols. A polling method is used to distribute the dual-polarization symbols, resulting in two third dual-polarization symbol streams. The 16 consecutive dual-polarization symbols... Located in the third double-polarized symbol stream 0, 16 consecutive double-polarized symbols

[0215] The two third dual-polarization symbol streams mentioned above are framed to obtain two first dual-polarization symbol streams.

[0216] The two first dual-polarization symbol streams mentioned above are each carried on two subcarriers and digitally multiplexed to obtain a single signal for transmission. In this case, the baud rate corresponding to each subcarrier is half the baud rate of the transmitted signal. This allows the receiver to use a less complex implementation method for signal processing, reducing dispersion and EEPN costs, thereby resulting in lower power consumption in the hardware implementation.

[0217] The specific method described in this embodiment ensures that the OFEC-encoded bit data is evenly distributed across two dual-polarization symbol streams, i.e., four subcarriers. More specifically, the 4096 encoded bits after OFEC encoding are represented by a 2x8 matrix, where each matrix contains 16 bits in each row and 16 bits in each column, totaling 256 bits. These 256 bits in each matrix are evenly distributed across the two dual-polarization symbol streams and along the X and Y polarization directions within each stream. This means each bit has four possible mapping positions, allowing for a more even distribution of decoding errors across multiple FEC decoding processes at the receiver, thus improving FEC decoding performance. Furthermore, after the OFEC interleaving and the first data processing, these 256 bits can be evenly mapped to the four positions, and bits at the same position in each matrix are mapped to the same location. This simplifies bit error rate (BER) detection across each polarization direction of different subcarriers and facilitates hardware implementation.

[0218] In some existing implementations for short-distance transmission, a merged data stream is first mapped to dual polarization symbols, and then directly framed without distribution to obtain a single dual polarization symbol stream to be transmitted. In this case, the solution presented in this embodiment is more compatible with existing methods and can be used for scenarios with longer transmission distances, resulting in lower power consumption.

[0219] Example 11: Consider the case where M=2 and W=4

[0220] Referring to Figure 12, the 2M = 4 first data streams are each FEC encoded to obtain 4 second data streams, where OFEC encoding is used. The 4 second data streams are FEC interleaved to obtain 2 third data streams, where 2 of the 4 second data streams are FEC interleaved to obtain 1 third data stream, where OFEC interleaving is used.

[0221] As shown in Figure 15, in the third data stream 0 A total of 16 × q = 128 bits, in the third data stream 1 A total of 16 × q = 128 bits are used, and a total of 256 bits are merged to obtain 256 consecutive bits in the merged data stream. The aforementioned 256 bits are mapped using DP-16QAM dual-polarization symbols to obtain 32 dual-polarization symbols in the second dual-polarization symbol data stream.

[0222] The aforementioned 32 dual-polarization symbols are grouped into sets of M×a = 8 dual-polarization symbols, and distributed using a round-robin method to obtain 4 third dual-polarization symbol streams. 8 consecutive dual-polarization symbols... Located in the third double-polarized symbol stream 0, 8 consecutive double-polarized symbols Located in the third double-polarized symbol stream 1, 8 consecutive double-polarized symbols Located in the third double-polarized symbol stream 2, 8 consecutive double-polarized symbols Located in the third dual-polarization symbol stream 3.

[0223] The above four third dual-polarization symbol streams are framed to obtain four first dual-polarization symbol streams.

[0224] The aforementioned four first dual-polarization symbol streams are each carried on four subcarriers and digitally multiplexed to obtain a single signal for transmission. In this case, the baud rate corresponding to each subcarrier is 1 / 4 of the transmitted signal baud rate. This allows the receiver to employ a lower-complexity implementation for signal processing, reducing dispersion and EEPN costs, thereby resulting in lower power consumption in the hardware implementation.

[0225] The specific method described in this embodiment ensures that the OFEC-encoded bit data is evenly distributed across the four dual-polarization symbol streams, i.e., the four subcarriers. More specifically, the 4096 encoded bits after OFEC encoding are represented by a 2x8 matrix, where each matrix contains 16 bits in each row and 16 bits in each column, totaling 256 bits. These 256 bits in each matrix are evenly distributed across the four dual-polarization symbol streams and evenly distributed along the X and Y polarization directions within each stream. This means each bit has eight possible mapping positions, allowing for a more even distribution of decoding errors across multiple FEC decoding processes at the receiver, thus improving FEC decoding performance. Furthermore, after the OFEC interleaving and the first data processing, these 256 bits can be evenly mapped to the eight positions, and bits at the same position in each matrix are mapped to the same location. This simplifies bit error rate (BER) detection across each polarization direction of different subcarriers and facilitates hardware implementation.

[0226] In some existing implementations for short-distance transmission, a merged data stream is first mapped to dual polarization symbols, and then directly framed without distribution to obtain a single dual polarization symbol stream to be transmitted. In this case, the solution presented in this embodiment is more compatible with existing methods and can be used for scenarios with longer transmission distances, resulting in lower power consumption.

[0227] Example 12: Consider the case where M=2 and W=2

[0228] Referring to Figure 12, the 2M = 4 first data streams are each FEC encoded to obtain 4 second data streams, where OFEC encoding is used. The 4 second data streams are FEC interleaved to obtain 2 third data streams, where 2 of the 4 second data streams are FEC interleaved to obtain 1 third data stream, where OFEC interleaving is used.

[0229] As shown in Figure 16, in the third data stream 0 A total of 8 × q = 64 bits, in the third data stream 1 A total of 8 × q = 64 bits, or 128 bits in total, are merged to obtain 128 consecutive bits in the merged data stream. The aforementioned 128 bits are mapped using DP-16QAM dual-polarization symbol mapping to obtain 16 dual-polarization symbols in the second dual-polarization symbol data stream.

[0230] The aforementioned 16 dual-polarization symbols are grouped into sets of M×a = 8 dual-polarization symbols. A polling method is used to distribute the dual-polarization symbols, resulting in two third dual-polarization symbol streams. The eight consecutive dual-polarization symbols... Located in the third double-polarized symbol stream 0, 16 consecutive double-polarized symbols

[0231] The two third dual-polarization symbol streams mentioned above are framed to obtain two first dual-polarization symbol streams.

[0232] The two first dual-polarization symbol streams mentioned above are each carried on two subcarriers and digitally multiplexed to obtain a single signal for transmission. In this case, the baud rate corresponding to each subcarrier is half the baud rate of the transmitted signal. This allows the receiver to use a less complex implementation method for signal processing, reducing dispersion and EEPN costs, thereby resulting in lower power consumption in the hardware implementation.

[0233] The specific method described in this embodiment ensures that the OFEC-encoded bit data is evenly distributed across two dual-polarization symbol streams, i.e., four subcarriers. More specifically, the 4096 encoded bits after OFEC encoding are represented by a 2x8 matrix, where each matrix contains 16 bits in each row and 16 bits in each column, totaling 256 bits. These 256 bits in each matrix are evenly distributed across the two dual-polarization symbol streams and along the X and Y polarization directions within each stream. This means each bit has four possible mapping positions, allowing for a more even distribution of decoding errors across multiple FEC decoding processes at the receiver, thus improving FEC decoding performance. Furthermore, after the OFEC interleaving and the first data processing, these 256 bits can be evenly mapped to the four positions, and bits at the same position in each matrix are mapped to the same location. This simplifies bit error rate (BER) detection across each polarization direction of different subcarriers and facilitates hardware implementation.

[0234] In some existing implementations for short-distance transmission, a merged data stream is first mapped to dual polarization symbols, and then directly framed without distribution to obtain a single dual polarization symbol stream to be transmitted. In this case, the solution presented in this embodiment is more compatible with existing methods and can be used for scenarios with longer transmission distances, resulting in lower power consumption.

[0235] Figure 17 is a schematic diagram of a data processing device according to an embodiment of this application. This data processing device is applied at the transmitting end. As shown in Figure 17, the data processing device includes a first processing unit 1701 and a second processing unit 1702. The first processing unit 1701 is used to perform processing steps such as FEC encoding and interleaving. The second processing unit 1702 is used to perform data processing on the interleaved data stream, for example, the first data processing mentioned in the above embodiments, and in Figures 5(a), 9(a), 10(a), and 11(a), as well as steps such as dual-polarization symbol mapping and framing, to obtain the dual-polarization data stream in the above embodiments. Specific implementation methods have been described in previous embodiments and will not be repeated here.

[0236] It should be understood that the structure of the data processing device at the receiving end can also be as shown in Figure 17. In this case, the first processing unit is used to perform demapping and other processing on the received dual-polarization data stream, and then the second processing unit further processes the demapped data stream to restore the original data. This can be understood as the reverse process of the sending end. The processing process of the sending end has been described in previous embodiments and will not be repeated here.

[0237] It should be understood that the data processing device shown in Figure 17 can also be implemented in other ways. For example, the unit division in the above device is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system. In addition, the functional units in the various embodiments of this application may be integrated into one processing unit, or they may be independent physical units, or two or more functional units may be integrated into one processing unit. The integrated unit described above can be implemented in hardware or in the form of software functional units.

[0238] Figure 18 is a schematic diagram of an optical module structure according to an embodiment of this application. As shown in Figure 18, the optical module includes a processor 1801 and an interface 1802. The interface 1802 can be a transceiver or an input / output interface, and is used to receive signals from other devices and transmit them to the processor 1801 or to send signals from the processor 1801 to other devices. Optionally, the optical module may also include a memory 1803, wherein the memory 1803 is used to store program instructions and data.

[0239] In one possible scenario, the optical module is used at the transmitting end, and the processor 1801 is used to perform processing steps such as FEC encoding and interleaving; it is also used to perform data processing on the interleaved data stream, such as the first data processing mentioned in the above embodiments and in Figures 5(a), 9(a), 10(a), and 11(a), as well as steps such as dual-polarization symbol mapping and framing, to obtain the dual-polarization data stream in the above embodiments; the specific implementation methods have been described in previous embodiments and will not be repeated here. For example, the processor 1801 includes the first processing unit and the second processing unit shown in Figure 17. As an example, after the processor 1801 performs the operations in the above embodiments to obtain the dual-polarization symbol stream, it sends the dual-polarization symbol stream through interface 1802. In this example, interface 1802 can specifically refer to an electrical interface. As another example, the processor 1801 performs the operations in the above embodiments to obtain a dual-polarization symbol stream, and the modulator in the optical module performs signal processing such as electro-optic conversion on the dual-polarization symbol stream to obtain an optical signal, and then sends the optical signal through interface 1802. In this example, interface 1802 can specifically refer to an optical interface.

[0240] In another possible scenario, the optical module is used at the receiving end, and the processor 1801 is used to perform the receiving-side functions described in the above embodiments. For example, it performs demapping and other processing on the received dual-polarization data stream, and further processes the demapping data stream to restore the original data. This can be understood as the reverse process of the transmitting end. The processing process at the transmitting end has been described in previous embodiments and will not be repeated here. As an example, the interface receives the optical signal transmitted through the channel, and the demodulator in the optical module performs photoelectric conversion and other signal processing on the optical signal to obtain a dual-polarization data stream. The processor 1801 performs the receiving-side operations described in the above embodiments on the dual-polarization data stream. In this example, the interface 1802 can specifically refer to the optical interface. As another example, the demodulator in the optical module performs photoelectric conversion and other signal processing on the received optical signal to obtain a dual-polarization data stream, and transmits the dual-polarization data stream to the processor 1801 through the interface 1802. The processor 1801 performs the receiving-side operations described in the above embodiments on the dual-polarization data stream. In this example, the interface 1802 can specifically refer to the electrical interface.

[0241] Typically, an optical module consists of optoelectronic devices, a processor, and an interface. The optoelectronic devices include transmitting and receiving devices. The transmitting end of the optical module converts electrical signals into optical signals and transmits them through optical fibers. The receiving end of the optical module receives the optical signals and converts them back into electrical signals.

[0242] It should be noted that the types of optical modules in this application embodiment include, but are not limited to, normal optical modules, near package optics (NPO) modules, and co-packaged optics (CPO) modules. Normal optical modules can perform functions including, but not limited to, digital signal processing (DSP) and clock data recovery (CDR). For example, a normal optical module converts analog signals to digital signals, performs DSP on the digital signals, and then converts them back to analog signals before sending them to the host device. Because DSP requires retiming, a normal optical module can also be called a retimed module. Normal optical modules are connected to the host device via an attachment unit interface (AUI). NPO and CPO modules do not have pluggable physical packaging and are closer to the host device. NPO and CPO modules can also be called optical engines. NPO or CPO technology is a technology that "packages" the host device (or host chip) and the optical engine. When NPO technology is used to encapsulate the host-side device and the optical engine, the optical engine can be called an NPO module. When CPO technology is used to encapsulate the host-side device and the optical engine, the optical engine can be called a CPO module.

[0243] Figure 19 is a schematic diagram of a communication device according to an embodiment of this application. As shown in Figure 19, the communication device includes a host-side device 1901 and an optical module 1902. The host-side device 1901 is used to send electrical signals to the optical module 1902, and the optical module 1902 converts the electrical signals into optical signals and transmits the optical signals through a channel. For example, the host-side device 1901 may specifically be a switch, router, or server. This communication device can be a communication device including the host-side device 1901 and the optical module 1902.

[0244] This application also provides an Optical Transport Network (OTN) device, which includes line-side equipment and client-side equipment. The client-side equipment may also be referred to as a tributary-side equipment in some scenarios. The line-side equipment includes a processor and an interface. In one possible scenario, the OTN device is used at the transmitting end, and the processor is used to execute the operation of step 101 in the above embodiment. In another possible scenario, the OTN device is used at the receiving end, and the processor is used to execute the operation of step 103 in the above embodiment. The interface can be a transceiver or an input / output interface, used to receive signals from other devices besides the line-side equipment and transmit them to the processor, or to send signals from the processor to other devices besides the line-side equipment.

[0245] This application also provides a chip. This chip integrates circuitry for implementing the functions of the processor 1801 described above, and one or more interfaces. As an example, the chip integrates a memory. As another example, when the chip does not integrate a memory, it can be connected to an external memory via the interface. This chip can perform the method steps of any one or more of the foregoing embodiments. Alternatively, the chip can implement the actions performed by the processing and transmission device in the foregoing embodiments based on program code stored in the memory.

[0246] As an example, the chip in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, any conventional processor, or a processing circuit that implements a specific function.

[0247] This application also provides a computer-readable storage medium including a program or instructions that, when run on a computer, cause the method performed as described in the above method embodiments to be implemented.

[0248] It should be understood that the processor mentioned in the embodiments of this application can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc. When implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. The memory can exist independently and be connected to the processor, or the memory can be integrated with the processor.

[0249] As an example, the processor in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, any conventional processor, or a processing circuit that implements a specific function.

[0250] In embodiments of this application, the memory may be random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium may also be a component of the processor. The processor and storage medium may reside in an ASIC. Additionally, the ASIC may reside in a network device or a terminal device. Alternatively, the processor and storage medium may exist as discrete components in the network device or terminal device.

[0251] In the above embodiments, it can be implemented entirely or partially by software, hardware, firmware, or any combination thereof.

[0252] When implemented in hardware, the data transmission method provided in this application embodiment may be implemented without reading software code or instructions. For example, it may be implemented by CPU, DSP, ASIC, FPGA, other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0253] When implemented using software, it can be implemented entirely or partially in the form of a computer program product. A computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, all or part of the processes or functions of the embodiments of this application are performed. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a network device, a terminal device, or other programmable device. The computer program or instructions can be stored in or transmitted through a computer-readable storage medium. The computer-readable storage medium can be any available medium that a computer can access, or a data storage device such as a server that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a Digital Versatile Disc (DVD); or it can be a semiconductor medium, such as a solid-state disk (SSD).

[0254] Finally, it should be noted that the above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A data processing method for optical communication, characterized in that, include: The eight first data streams were each subjected to forward error correction (FEC) encoding to obtain eight second data streams. The eight second data streams are interleaved to obtain four third data streams; The four third data streams are merged into a single merged data stream using an 8-bit granularity and a round-robin approach. The merged data stream is distributed to two fourth data streams in a round-robin fashion, with each stream having a granularity of 128 bits. The two fourth data streams are subjected to dual-polarization 16QAM symbol mapping and framing processing respectively to obtain two dual-polarization symbol streams.

2. A data processing method for optical communication, characterized in that, include: The eight first data streams were each subjected to forward error correction (FEC) encoding to obtain eight second data streams. The eight second data streams are interleaved to obtain four third data streams; Data processing is performed on the four third data streams to obtain two fourth data streams. The fourth data streams consist of consecutive bit blocks A0, A1, A2, A3, A4, A5, A6, and A7 in the first third data stream; consecutive bit blocks B0, B1, B2, B3, B4, B5, B6, and B7 in the second third data stream; consecutive bit blocks C0, C1, C2, C3, C4, C5, C6, and C7 in the third third data stream; and consecutive bit blocks in the fourth third data stream. D0, D1, D2, D3, D4, D5, D6, and D7 constitute consecutive bit blocks A0, B0, C0, D0, A1, B1, C1, D1, A2, B2, C2, D2, A3, B3, C3, and D3 in one fourth data stream, and consecutive bit blocks A4, B4, C4, D4, A5, B5, C5, D5, A6, B6, C6, D6, A7, B7, C7, and D7 in another fourth data stream. Each bit block consists of 8 bits. The two fourth data streams are subjected to dual-polarization 16QAM symbol mapping and framing processing respectively to obtain two dual-polarization symbol streams.

3. The method as described in claim 1 or 2, characterized in that, The FEC encoding uses the Open FEC (OFEC) code.

4. The method as described in claim 3, characterized in that, In the first data stream, every 3552 bits are OFEC encoded to obtain 4096 encoded bits.

5. The method according to any one of claims 1-4, characterized in that, The second data stream comprises multiple square matrices, each containing 256 bits, with the 256 bits of each square matrice evenly distributed along the two polarization directions of the two dual-polarization symbol streams.

6. The method as described in claim 5, characterized in that, In the plurality of matrices, bits at the same position in each matrix are mapped to the same polarization direction of the same dual-polarization symbol stream.

7. The method according to any one of claims 1-6, characterized in that, The interleaving is OFEC interleaving, which includes intra-array interleaving and inter-array interleaving. Each array includes 256 bits, and the buffer for inter-array interleaving includes 672 arrays.

8. The method as described in claim 7, characterized in that, The interweaving specifically includes: Each pair of second data streams is interleaved within the matrix and then interleaved between the matrices to obtain a third data stream.

9. The method according to any one of claims 1-8, characterized in that, The two dual-polarization symbol streams are respectively carried on two subcarriers, and the method further includes: The two subcarriers are multiplexed to obtain a single output signal.

10. The method as described in claim 2, characterized in that, The process of processing the four third data streams to obtain two fourth data streams specifically includes: The four third data streams are merged to obtain a merged data stream, wherein the consecutive bit blocks A0, A1, A2, A3, A4, A5, A6, A7 in the first third data stream, the consecutive bit blocks B0, B1, B2, B3, B4, B5, B6, B7 in the second third data stream, the consecutive bit blocks C0, C1, C2, C3, C4, C5, C6, C7 in the third third data stream, and the fourth... The consecutive bit blocks D0, D1, D2, D3, D4, D5, D6, and D7 in the third data stream constitute the consecutive bit blocks A0, B0, C0, D0, A1, B1, C1, D1, A2, B2, C2, D2, A3, B3, C3, D3, A4, B4, C4, D4, A5, B5, C5, D5, A6, B6, C6, D6, A7, B7, C7, and D7 in the merged data stream. The merged data stream is then distributed to obtain two fourth data streams.

11. A data processing method for optical communication, characterized in that, include: The two received dual-polarization symbol streams are demapped to obtain two demapped data streams; The two demapped data streams are merged into a single merged data stream in a round-robin fashion, with each stream having a granularity of 128 bits. The merged data stream is distributed to the four first data streams in a round-robin fashion, with each stream having an 8-bit granularity.

12. A data processing method for optical communication, characterized in that, include: The two received dual-polarization symbol streams are demapped to obtain two demapped data streams; The two demapped data streams are processed to obtain four first data streams. Specifically, consecutive bit blocks A0, B0, C0, D0, A1, B1, C1, D1, A2, B2, C2, D2, A3, B3, C3, D3 from one demapped data stream and consecutive bit blocks A4, B4, C4, D4, A5, B5, C5, D5, A6, B6, C6, D6, A7, B7, C7, D7 from the other demapped data stream are processed to obtain... The first data stream contains consecutive bit blocks A0, A1, A2, A3, A4, A5, A6, A7; the second data stream contains consecutive bit blocks B0, B1, B2, B3, B4, B5, B6, B7; the third data stream contains consecutive bit blocks C0, C1, C2, C3, C4, C5, C6, C7; and the fourth data stream contains consecutive bit blocks D0, D1, D2, D3, D4, D5, D6, D7. Each bit block consists of 8 bits.

13. The method as described in claim 11 or 12, characterized in that, Each of the first data streams is deinterleaved to obtain two second data streams. Each of the second data streams is then forward error correction (FEC) decoded to obtain a third data stream.

14. The method as described in claim 13, characterized in that, In the second data stream, OFEC decoding is performed on every 4096 bits to obtain 3552 bits.

15. The method according to any one of claims 11-14, characterized in that, The second data stream comprises multiple square matrices, each containing 256 bits, wherein the 256 bits of each square matrice are uniformly derived from the two polarization directions of the two dual-polarization symbol streams.

16. The method as described in claim 15, characterized in that, In the plurality of matrices, bits at the same position in each matrix come from the same polarization direction of the same dual-polarization symbol stream.

17. The method according to any one of claims 11-16, characterized in that, The deinterleaving is OFEC deinterleaving, which includes intra-array deinterleaving and inter-array deinterleaving. Each array includes 256 bits, and the buffer for inter-array deinterleaving includes 672 arrays.

18. The method as described in claim 17, characterized in that, The deinterleaving specifically includes: Each of the first data streams is deinterleaved between the matrices to obtain two fourth data streams; then, the two fourth data streams are deinterleaved within the matrices to obtain two second data streams.

19. The method according to any one of claims 11-18, characterized in that, Before demapping the two received dual-polarization symbol streams respectively, the method further includes: The received input signal stream is demultiplexed by subcarrier to obtain two dual-polarization symbol streams carried on two subcarriers respectively.

20. The method as described in claim 12, characterized in that, The data processing of the two demapped data streams to obtain four first data streams specifically includes: The two demapped data streams are merged to obtain a merged data stream; The merged data stream is distributed to obtain four first data streams. The consecutive bit blocks A0, B0, C0, D0, A1, B1, C1, D1, A2, B2, C2, D2, A3, B3, C3, D3, A4, B4, C4, D4, A5, B5, C5, D5, A6, B6, C6, D6, A7, B7, C7, and D7 in the merged data stream are distributed to obtain the first first data stream. The consecutive bit blocks A0, A1, A2, A3, A4, A5, A6, A7 in the first data stream; the consecutive bit blocks B0, B1, B2, B3, B4, B5, B6, B7 in the second first data stream; the consecutive bit blocks C0, C1, C2, C3, C4, C5, C6, C7 in the third first data stream; and the consecutive bit blocks D0, D1, D2, D3, D4, D5, D6, D7 in the fourth first data stream.

21. A data processing device for optical communication, characterized in that, include: First processor and second processor, The first processor is configured to perform forward error correction (FEC) encoding on the acquired eight first data streams to obtain eight second data streams; The eight second data streams are interleaved to obtain four third data streams; The second processor is configured to merge the four third data streams into a single merged data stream in a round-robin fashion, with each stream having an 8-bit granularity; distribute the merged data stream to two fourth data streams in a round-robin fashion, with each stream having a 128-bit granularity; and perform dual-polarization 16QAM symbol mapping and framing processing on the two fourth data streams respectively to obtain two dual-polarization symbol streams.

22. A data processing device for optical communication, characterized in that, include: First processor and second processor, The first processor is configured to perform forward error correction (FEC) encoding on the acquired eight first data streams to obtain eight second data streams; and to interleave the eight second data streams to obtain four third data streams. The second processor is used to process the four third data streams to obtain two fourth data streams, wherein the fourth data stream consists of consecutive bit blocks A0, A1, A2, A3, A4, A5, A6, A7 in the first third data stream, consecutive bit blocks B0, B1, B2, B3, B4, B5, B6, B7 in the second third data stream, consecutive bit blocks C0, C1, C2, C3, C4, C5, C6, C7 in the third third data stream, and consecutive bit blocks D0, D1, D2, D3, D4, D5 in the fourth third data stream. D6 and D7 constitute consecutive bit blocks A0, B0, C0, D0, A1, B1, C1, D1, A2, B2, C2, D2, A3, B3, C3, D3 in one fourth data stream and consecutive bit blocks A4, B4, C4, D4, A5, B5, C5, D5, A6, B6, C6, D6, A7, B7, C7, D7 in another fourth data stream. Each bit block includes 8 bits. They are also used to perform dual-polarization 16QAM symbol mapping and framing processing on the two fourth data streams respectively to obtain two dual-polarization symbol streams.

23. The apparatus as claimed in claim 21 or 22, characterized in that, The FEC encoding uses the Open FEC (OFEC) code.

24. The apparatus as claimed in claim 23, characterized in that, The first processor is specifically used to perform OFEC encoding on every 3552 bits in the first data stream to obtain 4096 encoded bits.

25. The apparatus as claimed in any one of claims 21-24, characterized in that, The second data stream comprises multiple square matrices, each containing 256 bits, with the 256 bits of each square matrice evenly distributed along the two polarization directions of the two dual-polarization symbol streams.

26. The apparatus as claimed in claim 25, characterized in that, In the plurality of matrices, bits at the same position in each matrix are mapped to the same polarization direction of the same dual-polarization symbol stream.

27. The apparatus as claimed in any one of claims 21-26, characterized in that, The interleaving is OFEC interleaving, which includes intra-array interleaving and inter-array interleaving. Each array includes 256 bits, and the buffer for inter-array interleaving includes 672 arrays.

28. The apparatus as claimed in claim 27, characterized in that, The interweaving specifically includes: Each pair of second data streams is interleaved within the matrix and then interleaved between the matrices to obtain a third data stream.

29. The apparatus as claimed in any one of claims 21-28, characterized in that, The two dual-polarization symbol streams are respectively carried on two subcarriers, and the second processor is further used for: The two subcarriers are multiplexed to obtain a single output signal.

30. The apparatus as claimed in claim 22, characterized in that, The second processor is specifically used for: The four third data streams are merged to obtain a merged data stream, wherein the consecutive bit blocks A0, A1, A2, A3, A4, A5, A6, A7 in the first third data stream, the consecutive bit blocks B0, B1, B2, B3, B4, B5, B6, B7 in the second third data stream, the consecutive bit blocks C0, C1, C2, C3, C4, C5, C6, C7 in the third third data stream, and the fourth... The consecutive bit blocks D0, D1, D2, D3, D4, D5, D6, and D7 in the third data stream constitute the consecutive bit blocks A0, B0, C0, D0, A1, B1, C1, D1, A2, B2, C2, D2, A3, B3, C3, D3, A4, B4, C4, D4, A5, B5, C5, D5, A6, B6, C6, D6, A7, B7, C7, and D7 in the merged data stream. The merged data stream is then distributed to obtain two fourth data streams.

31. A data processing device for optical communication, characterized in that, include: First processor and second processor, The first processor is configured to demap the two received dual-polarization symbol streams respectively to obtain two demapped data streams; The second processor is used to merge the two demapped data streams into a single merged data stream in a round-robin manner, with each stream having a granularity of 128 bits. The merged data stream is distributed to the four first data streams in a round-robin fashion, with each stream having an 8-bit granularity.

32. A data processing device for optical communication, characterized in that, include: First processor and second processor, The first processor is configured to demap the two received dual-polarization symbol streams respectively to obtain two demapped data streams; The second processor is used to process the two demapped data streams to obtain four first data streams. The first data streams consist of consecutive bit blocks A0, B0, C0, D0, A1, B1, C1, D1, A2, B2, C2, D2, A3, B3, C3, D3 from one demapped data stream and consecutive bit blocks A4, B4, C4, D4, A5, B5, C5, D5, A6, B6, C6, D6, A7, B7, C7, D7 from the other demapped data stream, after data processing... The algorithm is used to obtain consecutive bit blocks A0, A1, A2, A3, A4, A5, A6, A7 in the first data stream, consecutive bit blocks B0, B1, B2, B3, B4, B5, B6, B7 in the second data stream, consecutive bit blocks C0, C1, C2, C3, C4, C5, C6, C7 in the third data stream, and consecutive bit blocks D0, D1, D2, D3, D4, D5, D6, D7 in the fourth data stream. Each bit block consists of 8 bits.

33. The apparatus as claimed in claim 31 or 32, characterized in that, The second processor is also used for: Each of the first data streams is deinterleaved to obtain two second data streams. Each of the second data streams is then forward error correction (FEC) decoded to obtain a third data stream.

34. The apparatus as claimed in claim 33, characterized in that, The second processor is specifically used to perform OFEC decoding on every 4096 bits in the second data stream to obtain 3552 bits.

35. The apparatus as claimed in any one of claims 31-34, characterized in that, The second data stream comprises multiple square matrices, each containing 256 bits, wherein the 256 bits of each square matrice are uniformly derived from the two polarization directions of the two dual-polarization symbol streams.

36. The apparatus as claimed in claim 35, characterized in that, In the plurality of matrices, bits at the same position in each matrix come from the same polarization direction of the same dual-polarization symbol stream.

37. The apparatus according to any one of claims 31-36, characterized in that, The deinterleaving is OFEC deinterleaving, which includes intra-array deinterleaving and inter-array deinterleaving. Each array includes 256 bits, and the buffer for inter-array deinterleaving includes 672 arrays.

38. The apparatus as claimed in claim 37, characterized in that, The deinterleaving specifically includes: Each of the first data streams is deinterleaved between the matrices to obtain two fourth data streams; then, the two fourth data streams are deinterleaved within the matrices to obtain two second data streams.

39. The apparatus as claimed in any one of claims 31-38, characterized in that, The first processor is also used for: The received input signal stream is demultiplexed by subcarrier to obtain two dual-polarization symbol streams carried on two subcarriers respectively.

40. The apparatus as claimed in claim 32, characterized in that, The second processor is specifically used for: The two demapped data streams are merged to obtain a merged data stream; The merged data stream is distributed to obtain four first data streams. The consecutive bit blocks A0, B0, C0, D0, A1, B1, C1, D1, A2, B2, C2, D2, A3, B3, C3, D3, A4, B4, C4, D4, A5, B5, C5, D5, A6, B6, C6, D6, A7, B7, C7, and D7 in the merged data stream are distributed to obtain the first first data stream. The consecutive bit blocks A0, A1, A2, A3, A4, A5, A6, A7 in the first data stream; the consecutive bit blocks B0, B1, B2, B3, B4, B5, B6, B7 in the second first data stream; the consecutive bit blocks C0, C1, C2, C3, C4, C5, C6, C7 in the third first data stream; and the consecutive bit blocks D0, D1, D2, D3, D4, D5, D6, D7 in the fourth first data stream.

41. A chip, characterized in that, The chip is used to perform the method as described in any one of claims 1 to 20.

42. An optical module, characterized in that, The optical module includes a processor and an interface, the interface being used for transmitting and receiving signals, and the processor being used for performing the method as described in any one of claims 1 to 20.

43. A communication device, characterized in that, The communication device includes a host-side device and an optical module as described in claim 42; the optical module is used to convert electrical signals from the host-side device into optical signals and transmit the optical signals, or the optical module is used to convert received optical signals into electrical signals and transmit the electrical signals to the host-side device.

44. A communication system, characterized in that, It includes multiple communication devices, wherein at least one communication device is the communication device as described in claim 43, and the multiple communication devices are interconnected.

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