Semiconductor device and manufacturing method therefor, and memory system

Abstract

The present disclosure provides a semiconductor device and a manufacturing method therefor, and a memory system. The semiconductor device comprises: a plurality of transistors, wherein each transistor comprises a semiconductor body extending in a first direction and a gate structure located on at least one side of the semiconductor body in a direction perpendicular to the first direction, the gate structures of the transistors arranged in a second direction among the plurality of transistors are connected to each other, and the first direction intersects the second direction; a plurality of first row word lines, wherein the plurality of first row word lines are stacked in a third direction, the first row word lines extend in the first direction and are connected to the gate structures of the transistors, and the third direction is perpendicular to both the first direction and the second direction; and a plurality of bit lines, wherein the bit lines extend in the third direction, the transistors arranged in the third direction among the plurality of transistors are connected to a same bit line, two transistors adjacent in the first direction are connected to different bit lines, and each bit line is located on one of two opposite sides of the corresponding first row word line in the second direction.

Description

Semiconductor devices and their fabrication methods, memory systems

[0001] Cross-references to related applications

[0002] This disclosure is based on and claims priority to Chinese Patent Application No. 202510053543.8, filed on January 13, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of semiconductor technology, such as a semiconductor device and its fabrication method, and a memory system. Background Technology

[0004] With the continuous development of science and technology, semiconductor devices are widely used in various electronic devices and products. For example, Dynamic Random Access Memory (DRAM), as a volatile memory, is a commonly used semiconductor memory device in computers. Summary of the Invention

[0005] According to a first aspect of the present disclosure, a semiconductor device is provided, the semiconductor device comprising: a plurality of transistors; each transistor including a semiconductor body extending along a first direction and a gate structure located on at least one side of the semiconductor body perpendicular to the first direction; the gate structures of transistors arranged along a second direction among the plurality of transistors being interconnected; the first direction intersecting the second direction; a plurality of first row word lines; the plurality of first row word lines stacked along a third direction, the first row word lines extending along the first direction and connected to the gate structures of the transistors; the third direction being perpendicular to both the first direction and the second direction; a plurality of bit lines; the bit lines extending along the third direction, transistors arranged along the third direction among the plurality of transistors being connected to the same bit line, and two adjacent transistors along the first direction being connected to different bit lines; the bit lines being located on one side of the first row word lines opposite each other along the second direction.

[0006] According to a second aspect of the present disclosure, a memory system is provided, comprising: a semiconductor device as described in any of the above embodiments; and a memory controller; the memory controller being coupled to the semiconductor device and configured to control the semiconductor device.

[0007] According to a third aspect of the present disclosure, a method for fabricating a semiconductor device is provided, the method comprising: forming a plurality of transistors; each transistor including a semiconductor body extending along a first direction and a gate structure located on at least one side of the semiconductor body perpendicular to the first direction; the gate structures of transistors arranged along a second direction among the plurality of transistors being interconnected; the first direction intersecting the second direction; forming a plurality of first row word lines; the plurality of first row word lines stacked along a third direction, the first row word lines extending along the first direction and connected to the gate structures of the transistors; the third direction being perpendicular to both the first direction and the second direction; forming a plurality of bit lines; the bit lines extending along the third direction, transistors arranged along the third direction among the plurality of transistors being connected to the same bit line, and two adjacent transistors along the first direction being connected to different bit lines; the bit lines being located on one side of the first row word lines opposite each other along the second direction. Attached Figure Description

[0008] Figure 1 is a schematic diagram of an electronic device provided in an embodiment of this disclosure;

[0009] Figure 2 is a schematic diagram of the DRAM provided in an embodiment of this disclosure;

[0010] Figure 3a is a top view of a semiconductor device provided in an embodiment of this disclosure;

[0011] Figure 3b is a schematic cross-sectional view of a semiconductor device along the XY plane according to an embodiment of the present disclosure;

[0012] Figure 3c is a magnified schematic diagram of the transistor shown in Figures 3b and 3j;

[0013] Figure 3d is an enlarged schematic diagram of the capacitor shown in Figures 3b and 3j;

[0014] Figure 3e is a top view of a semiconductor device provided in another embodiment of this disclosure;

[0015] Figure 3f is a schematic cross-sectional view of the semiconductor device provided in another embodiment of this disclosure along the XY plane;

[0016] Figure 3g is a three-dimensional structural schematic diagram of a semiconductor device provided in another embodiment of this disclosure;

[0017] Figure 3h is a partial three-dimensional structural schematic diagram of a semiconductor device provided in another embodiment of this disclosure;

[0018] Figure 3i is a top view of a semiconductor device provided in another embodiment of the present disclosure;

[0019] Figure 3j is a schematic cross-sectional view of a semiconductor device along the XY plane according to another embodiment of the present disclosure;

[0020] Figure 3k is a three-dimensional structural schematic diagram of the semiconductor device provided in another embodiment of the present disclosure;

[0021] Figure 31 is a partial three-dimensional structural schematic diagram of a semiconductor device provided in another embodiment of the present disclosure;

[0022] Figure 4a is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of the present disclosure;

[0023] Figure 4b is a schematic flowchart of a method for fabricating a semiconductor device according to another embodiment of this disclosure;

[0024] Figures 5 to 63 are schematic diagrams illustrating the fabrication process of a semiconductor device according to an embodiment of this disclosure;

[0025] Figures 64 to 97 are schematic diagrams illustrating the fabrication process of a semiconductor device according to another embodiment of this disclosure. Detailed Implementation

[0026] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0027] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0028] In the accompanying drawings, the same reference numerals denote the same elements throughout.

[0029] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0031] Figure 1 is a schematic diagram of an electronic device provided in an embodiment of this disclosure. The electronic device 1 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory therein.

[0032] As shown in Figure 1, the electronic device 1 may include a memory system 10 and a host 20. The memory system 10 may include a memory controller 110 and a memory 120. The host 20 may include a processor of the electronic device 1, such as a central processing unit (CPU) or a system-on-chip (SoC) (e.g., an application processor (AP)). The memory controller 110 is coupled to both the host 20 and the memory 120, and the memory controller 110 may be configured to communicate with the host 20 and control the memory 120.

[0033] In some embodiments, the memory controller 110 may be configured to control operations of the memory 120, such as read operations, erase operations, write operations, refresh operations, etc. In some embodiments, the memory controller 110 is also configured to process error correction codes (ECCs) regarding data read from or written to the memory 120. In other embodiments, the memory controller 110 may also be configured to perform any other suitable operation, such as formatting the memory 120.

[0034] In some embodiments, the memory controller 110 can receive data, commands, and addresses from the host 20, and can send data, commands, and addresses to the memory 120. Specifically, the memory controller 110 may include a command generator 111, an address generator 112, a device interface 113, and a host interface 114. The memory controller 110 can receive data, commands, and addresses from the host 20 through the host interface 114, decode the commands received from the host 20 through the command generator 111 to generate an access command CMD, and provide the access command CMD to the memory 120 through the device interface 113. The memory controller 110 can decode the addresses received from the host interface 114 through the address generator 112 to generate an address ADDR to be accessed in the memory array 121, and provide the address ADDR to be accessed to the memory 120 through the device interface 113. The access command may be a signal instructing the memory 120 to write or read data by accessing one or more memory cells in the memory array 121 corresponding to the address ADDR. In addition, the memory controller 110 can also send a refresh command to the memory 120. The refresh command can be a signal instructing the memory 120 to read and rewrite data by accessing one or more memory cells of the memory array 121 corresponding to the address ADDR.

[0035] In some specific examples, memory 120 can be random access memory (RAM), such as dynamic random access memory, synchronous dynamic random access memory (SDRAM), static random access memory (SRAM), double data rate SDRAM (DDR SDRAM), phase-change random access memory (PRAM), resistive random access memory (ReRAM), magnetic random access memory (MRAM), etc. The following explanation will use DRAM as an example.

[0036] In some embodiments, FIG2 is a schematic diagram of a DRAM according to an embodiment of the present disclosure. Referring to FIG1 and FIG2, the DRAM includes a memory array 121 and peripheral circuitry 122 coupled to the memory array 121. The peripheral circuitry 122 may include a sense amplifier circuit, a row decoder, a column decoder, a data input / output buffer, etc. The memory array 121 includes a plurality of memory cells arranged in an array. A plurality of memory cells located in the same row are coupled to a word line WL, and a plurality of memory cells located in the same column are coupled to a bit line BL. Each memory cell includes a transistor T and a capacitor C. The word line WL is connected to the gate of the transistor T, the bit line BL is connected to one of the source and drain of the transistor T, the other of the source and drain of the transistor T is connected to one electrode of the capacitor C, and the other electrode of the capacitor C is connected to a fixed voltage. The memory cell is configured to store 1 or 0 by utilizing the amount of charge stored in the capacitor C. By specifying row and column addresses, individual memory cells in a DRAM chip can be accessed independently, and data stored in them can be read, written, or refreshed.

[0037] With increasingly higher requirements for memory integration, how to improve memory integration has become an urgent problem to be solved. In response, this disclosure proposes the following implementation methods.

[0038] This disclosure provides a semiconductor device, as shown in Figures 3a to 3h. The semiconductor device 200 includes: a plurality of transistors 201; each transistor 201 includes a semiconductor body 202 extending along a first direction and a gate structure 203 located on at least one side of the semiconductor body 202 perpendicular to the first direction; the gate structures 203 of the transistors 201 arranged along a second direction are connected to each other; the first direction intersects the second direction; a plurality of first row word lines 204; the plurality of first row word lines 204 are stacked along a third direction, the first row word lines 204 extend along the first direction and are connected to the gate structures 203 of the transistors 201; the third direction is perpendicular to both the first and second directions; a plurality of bit lines 205; the bit lines 205 extend along a third direction, the transistors 201 arranged along the third direction are connected to the same bit line 205, and two adjacent transistors 201 along the first direction are connected to different bit lines 205; the bit line 205 is located on one side of the first row word line 204 opposite to each other along the second direction.

[0039] In this embodiment, the first direction and the second direction intersect. The following description uses the example of the first direction and the second direction being perpendicular. In this embodiment, the first direction can be understood as the X-axis direction in the accompanying drawings, the second direction can be understood as the Y-axis direction in the accompanying drawings, and the third direction can be understood as the Z-axis direction in the accompanying drawings.

[0040] Figure 3a is a top view of a semiconductor device provided in one embodiment of the present disclosure; Figure 3b is a cross-sectional view of a semiconductor device provided in one embodiment of the present disclosure along the XY plane; Figure 3c is an enlarged view of the transistor shown in Figure 3b; Figure 3d is an enlarged view of the capacitor shown in Figure 3b; Figure 3e is a top view of a semiconductor device provided in another embodiment of the present disclosure; Figure 3f is a cross-sectional view of the semiconductor device provided in the other embodiment of the present disclosure along the XY plane; Figure 3g is a three-dimensional view of the semiconductor device provided in the other embodiment of the present disclosure; Figure 3h is a partial three-dimensional view of the semiconductor device provided in the other embodiment of the present disclosure.

[0041] In the solution provided by the embodiments of this disclosure, firstly, the semiconductor device 200 includes a plurality of transistors 201, which are arranged along a first direction, a second direction, and a third direction. Each transistor 201 includes a semiconductor body 202 extending along the first direction. That is, the transistors 201 in this embodiment are vertical transistors 201, and the plurality of transistors are stacked in three dimensions. This results in a high transistor density, reduces the area occupied by the semiconductor device 200, and facilitates the miniaturization of the semiconductor device 200. Secondly, the gate structures 203 of the transistors 201 arranged along the second direction are interconnected. The semiconductor device 200 includes a plurality of first word lines 204 stacked along a third direction, which extend along the first direction and are connected to the gate structures 203 of the transistors 201. Since there is no need to set a step structure, the transistor density is high, reducing the area occupied by the semiconductor device 201 and facilitating its miniaturization. By setting corresponding word line contacts on the first row of word lines 204 extending along the first direction, the gate structures 203 can be brought out, thereby further reducing the area occupied by the semiconductor device 200. Thirdly, the gate structure 203 of the transistor 201 is brought out through the first row of word lines 204 extending along the first direction, resulting in low word line resistance and low resistance-capacitance delay. Fourthly, the first row of word lines 204 is connected to the gate structure 203 of the transistor 201. Among the multiple transistors 201, the transistors 201 arranged along the third direction are connected to the same bit line 205, and two adjacent transistors 201 along the first direction are connected to different bit lines 205. This ensures that only one transistor 201 is connected to both a first row of word lines 204 and a bit line 205. The bit line 205 extends along the third direction and can be brought out vertically, thereby reducing the coupling capacitance between the bit lines 205 and increasing the sensing margin.

[0042] The semiconductor device 200 in this embodiment can be understood as the memory 120 shown in FIG1, or as the memory array 121 in the memory shown in FIG1.

[0043] In the semiconductor device 200 provided in this embodiment, a plurality of first row word lines 204 are stacked along a third direction, and each first row word line 204 extends along a first direction. For any first row word line 204, the first row word line 204 is connected to the gate structure 203 of the transistor 201 closest to the first row word line 204 among the plurality of transistors 201 arranged along the second direction. The gate structure 203 of each transistor 201 among the plurality of transistors 201 arranged along the third direction is connected to a different first row word line 204. It can be understood that the semiconductor device 200 includes a plurality of transistor layers stacked along a third direction. Each transistor layer includes a plurality of transistors 201 arranged in an array along the first direction and the second direction. The transistor 201 closest to the first row word line 204 among the plurality of transistors 201 arranged along the second direction in each transistor layer is connected to the first row word line 204. All transistors in the same transistor layer can share a first row word line 204, and transistors in different transistor layers are connected to different first row word lines 204.

[0044] In some specific examples, the material of the first line word line 204 is a conductive material, which includes, but is not limited to, at least one of doped semiconductor materials (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metallic materials (e.g., aluminum, copper, tungsten, titanium, tantalum, etc.) and metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0045] In this embodiment of the disclosure, bit line 205 extends along a third direction, and a plurality of transistors 201 arranged along the third direction are connected to the same bit line 205. In addition, each of the plurality of transistors 201 arranged along the second direction is connected to a different bit line 205, and each of the plurality of transistors 201 arranged along the first direction is connected to a different bit line 205.

[0046] In some specific examples, the material of bit line 205 is a conductive material, which includes, but is not limited to, at least one of doped semiconductor materials (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metallic materials (e.g., aluminum, copper, tungsten, titanium, tantalum, etc.) and metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0047] In this embodiment of the present disclosure, as shown in FIG3h, the semiconductor device 200 further includes a first insulating layer 223, through which the first row word line 204 adjacent in the third direction and the transistor 201 adjacent in the third direction are isolated. The material of the first insulating layer 223 here includes, but is not limited to, silicon oxide.

[0048] In some embodiments, as shown in FIG3a and FIG3b, the semiconductor device 200 further includes a plurality of first line word line contacts 207; the first line word line contacts 207 extend along a third direction, each of the plurality of first line word line contacts 207 is connected to a different first line word line 204, and the plurality of first line word line contacts 207 are arranged along a first direction.

[0049] In this embodiment of the present disclosure, based on the provision of a plurality of first line character lines 204 extending along a first direction, first line character line contacts 207 are provided on the first line character lines 204, so that different first line character lines 204 are led out through different first line character line contacts 207. Since the first line character lines 204 extend along the first direction, the plurality of first line character line contacts 207 are arranged along the first direction, thereby reducing the area occupied by the character line contacts.

[0050] In this embodiment of the disclosure, a first line character line contact 207 is connected to a first line character line 204. The first line character line contact 207 connected to a certain first line character line 204 will pass through other first line character lines above the first line character line. A corresponding first dielectric layer is provided between the first line character line contact 207 and the other first line character lines above the first line character line, so that the first line character line contact 207 is separated from the other first line character lines above the first line character line.

[0051] In some embodiments, the number of first line word line contacts 207 is the same as the number of first line word lines 204 stacked along a third direction.

[0052] Understandably, a first line word line 204 is led out through a first line word line contact 207, so that the number of first line word line contacts 207 is the same as the number of first line word lines 204 stacked along a third direction.

[0053] In some embodiments, the number of first line word lines 204 penetrated by different first line word line contacts 207 among a plurality of first line word line contacts 207 is different.

[0054] In this embodiment, the number of first line character lines 204 traversed by each first line character line contact 207 is different. The multiple first line character lines 204 stacked along a third direction are numbered sequentially from top to bottom as 1, 2, 3…N, where N is the total number of first line character lines 204 stacked along the third direction. The number of first line character line contacts 207 traversed by the first line character line contact 207 connected to the m-th first line character line 204 is (m-1), where m is an integer greater than or equal to 1 and less than or equal to N. For example, the number of first line character line contacts 207 traversed by the first line character line contact 207 connected to the 1st first line character line 204 is 0, the number of first line character line contacts 207 traversed by the second first line character line 204 is 1, and so on for the other first line character lines.

[0055] In some embodiments, the dimensions of each of the plurality of first line word line contacts 207 arranged along the first direction are different along the third direction.

[0056] In some embodiments, as shown in Figures 3f to 3h, the semiconductor device 200 further includes a plurality of second word lines 206; the plurality of second word lines 206 are stacked along a third direction, the second word lines 206 extend along a first direction and are connected to the gate structure 203 of the transistor 201; the second word lines 206 and the first word lines 204 are arranged along a second direction.

[0057] In some embodiments, the second line word line 206 is located on one side of the two opposite sides of the bit line 205 along the second direction. Multiple second word lines 206 are stacked along a third direction, and each second word line 206 extends along a first direction. For any second word line 206, the second word line 206 is connected to the gate structure 203 of the transistor 201 closest to the second word line 206 among the multiple transistors 201 arranged along the second direction. The gate structure 203 of each transistor 201 arranged along the third direction is connected to a different second word line 206. It can be understood that the semiconductor device 200 includes multiple transistor layers stacked along a third direction. Each transistor layer includes multiple transistors 201 arranged in an array along the first and second directions. Among the multiple transistors 201 arranged along the second direction in each transistor layer, the transistor 201 closest to the second word line 206 is connected to the second word line 206. All transistors 201 in the same transistor layer can share a second word line 206. Transistors 201 in different transistor layers are connected to different second word lines 206.

[0058] It is understandable that, in addition to the first row of word lines 204, the semiconductor device 200 may also include a second row of word lines 206. Among the multiple transistors 201 arranged along the second direction in the same transistor layer, the transistors 201 closer to the first row of word lines 204 are connected to the first row of word lines 204, and the transistors 201 closer to the second row of word lines 206 are connected to the second row of word lines 206. The same transistor layer can either lead out the gate structure 203 by setting corresponding word line contacts on the first row of word lines 204, or it can lead out the gate structure 203 by setting corresponding word line contacts on the second row of word lines 206. This makes the setting of word line contacts more flexible and allows the word line contacts to be set more dispersed, thus avoiding short circuit problems and high process difficulty caused by too dense word line contacts.

[0059] In some embodiments, as shown in Figures 3f to 3h, a plurality of transistors 201 are located between the first row word line 204 and the second row word line 206.

[0060] In some embodiments, as shown in Figures 3f to 3h, the first row word line 204 and the second row word line 206 are respectively located on opposite sides of a plurality of transistors 201 arranged along the second direction. Furthermore, the first row word line 204 and the second row word line 206 are respectively located on opposite sides of a plurality of bit lines 205 arranged along the second direction.

[0061] In some examples, the material of the first line of text 204 is the same as the material of the second line of text 206.

[0062] In some embodiments, as shown in Figures 3e to 3h, the semiconductor device 200 further includes: a plurality of second row word line contacts 208; the second row word line contacts 208 extend along a third direction, each of the plurality of second row word line contacts 208 is connected to a different first row word line 204, and the plurality of second row word line contacts 208 are arranged along a first direction; a plurality of third row word line contacts 209; the third row word line contacts 209 extend along a third direction, each of the plurality of third row word line contacts 209 is connected to a different second row word line 206, and the plurality of third row word line contacts 209 are arranged along a first direction.

[0063] Understandably, based on the first row of word lines 204 and the second row of word lines 206, a portion of the gate structure 203 of the transistor layer can be led out through the second row of word line contacts 208, and another portion of the gate structure 203 of the transistor layer can be led out through the third row of word line contacts 209. This makes the setting of word line contacts more flexible, allows the word line contacts to be set more dispersed, and avoids short circuit problems and high process difficulty caused by too dense word line contacts.

[0064] In some embodiments, the number of second line word line contacts 208 is less than the number of first line word lines 204 stacked along a third direction, and the number of third line word line contacts 209 is less than the number of second line word lines 206 stacked along a third direction.

[0065] In this embodiment, transistors 201 within the same transistor layer are led out through second row word line contacts 208 or third row word line contacts 209. That is, not every first row word line 204 needs to be connected to a second row word line contact 208, nor does every second row word line 206 need to be connected to a third row word line contact 209. Since the number of transistor layers is equal to the number of first row word lines 204, and the number of first row word lines 204 is equal to the number of second row word lines 206, the number of second row word line contacts 208 can be less than the number of first row word lines 204 stacked along a third direction, and the number of third row word line contacts 209 can be less than the number of second row word lines 206 stacked along a third direction. The sum of the number of second row word line contacts 208 and the number of third row word line contacts 209 can be equal to the number of transistor layers.

[0066] In some examples, the number of second-line character line contacts 208 can be equal to the number of third-line character line contacts 209, or the number of second-line character line contacts 208 can differ from the number of third-line character line contacts 209 by one, thus making the distribution of character line contacts more uniform.

[0067] In some embodiments, the number of first line characters 204 penetrated by different second line character line contacts 208 among a plurality of second line character line contacts 208 is different, the number of second line characters 206 penetrated by different third line character line contacts 209 among a plurality of third line character line contacts 209 is different, and the number of first line characters 204 penetrated by second line character line contacts 208 is different from the number of second line characters 206 penetrated by third line character line contacts 209.

[0068] In some embodiments, the dimensions of each of the plurality of second line word line contacts 208 arranged along the first direction are different along the third direction, and the dimensions of each of the plurality of third line word line contacts 209 arranged along the first direction are different along the third direction, and the dimensions of the second line word line contacts 208 and the third line word line contacts 209 are different along the third direction.

[0069] In some embodiments, the different first line word lines 204 stacked along a third direction have equal lengths in a first direction, and the different first line word lines 204 stacked along a third direction have equal lengths in a second direction.

[0070] It is understood that in this embodiment of the present disclosure, by setting corresponding word line contacts on a plurality of first row word lines 204 stacked along a third direction to bring out the gate structure 203 of transistor 201, without setting a step structure to bring out the gate structure 203 of transistor 201 of different transistor layers, the area of ​​semiconductor device 200 can be reduced.

[0071] In some embodiments, the dimension of the first line character line 204 along the second direction may be equal to the dimension of the corresponding character line contact connected to the first line character line 204 along the second direction; or, the dimension of the first line character line 204 along the second direction may be slightly larger than the dimension of the corresponding character line contact connected to the first line character line 204 along the second direction; or, the dimension of the first line character line 204 along the second direction may be smaller than the dimension of the corresponding character line contact connected to the first line character line 204 along the second direction.

[0072] In some embodiments, the different second line characters 206 stacked along a third direction have equal lengths in a first direction, and the different second line characters 206 stacked along a third direction have equal lengths in a second direction.

[0073] In some embodiments, the dimension of the second line character line 206 along the second direction may be equal to the dimension of the corresponding character line contact connected to the second line character line 206 along the second direction; or, the dimension of the second line character line 206 along the second direction may be slightly larger than the dimension of the corresponding character line contact connected to the second line character line 206 along the second direction; or, the dimension of the second line character line 206 along the second direction may be smaller than the dimension of the corresponding character line contact connected to the second line character line 206 along the second direction.

[0074] In some embodiments, the dimension of the first line character line 204 along the first direction is equal to the dimension of the second line character line 206 along the first direction.

[0075] In some embodiments, the material of the semiconductor body 202 includes a metal oxide semiconductor.

[0076] In some examples, the metal oxide semiconductor includes at least one element selected from indium, gallium, zinc, tin, and tungsten. Exemplarily, the metal oxide semiconductor in this disclosure is indium gallium zinc oxide (IGZO).

[0077] In this embodiment of the present disclosure, the material of the semiconductor body 202 includes metal oxide semiconductor, which allows the stacked structure to be constructed using mature processes such as silicon nitride-silicon oxide (NO) stacking during the formation of the semiconductor device 200, and is not limited by the number of stacked layers.

[0078] In some embodiments, as shown in FIG3c, the semiconductor body includes a first semiconductor portion 277, a second semiconductor portion 278, and a third semiconductor portion 279 arranged along a first direction; the second semiconductor portion 278 is located between the first semiconductor portion 277 and the third semiconductor portion 279; the dimension of the second semiconductor portion 278 along the second direction is greater than the dimension of the first semiconductor portion 277 along the second direction, and the dimension of the second semiconductor portion 278 along the second direction is greater than the dimension of the third semiconductor portion 279 along the second direction.

[0079] In this embodiment of the present disclosure, the size of the second semiconductor portion 278 gradually increases and then gradually decreases along the second direction, in the first direction. The second semiconductor portion 278 has protruding portions on both sides opposite to the first semiconductor portion 277 and the third semiconductor portion 279 along the second direction, and the outer contour shape of these protruding portions is similar to a cone. The sidewalls of these protruding portions are covered by the gate structure 203.

[0080] In this embodiment of the present disclosure, as shown in FIG3c, the semiconductor body 202 extends along a first direction. The semiconductor body 202 includes a first electrode, a channel region, and a second electrode arranged sequentially along the first direction. Here, the first electrode can be one of the source and drain of a transistor, and the second electrode can be the other of the source and drain of a transistor.

[0081] In some embodiments, as shown in FIG3c and FIG3h, the gate structure 203 of transistor 201 is located on two opposite sides of semiconductor body 202 of transistor 201 along a second direction and on two opposite sides of semiconductor body 202 along a third direction.

[0082] In this embodiment, the gate structure 203 surrounds the channel region of the semiconductor body 202, forming a full-to-the-loop gate transistor. It is understood that the gate structure 203 surrounding the channel region of the semiconductor body 202 enhances the gate structure 203's control over the channel region, thereby reducing leakage current.

[0083] It should be noted that the arrangement of the gate structure 203 in Figures 3c and 3h is only an example. In other embodiments, the gate structure 203 may be located on one side, two sides, or three sides of the channel region. This disclosure does not impose any specific limitations on this.

[0084] In some examples, as shown in FIG3c, the gate structure 203 includes a gate dielectric layer 255 and a gate 276. The gate dielectric layer 255 is located between the gate 276 and the channel region. The material of the gate dielectric layer 255 may include at least one of a high dielectric constant material, silicon oxide, silicon nitride, and silicon oxynitride, wherein the high dielectric constant material may include at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The material of the gate 276 includes at least one of conductive materials, such as doped semiconductor materials (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metallic materials (e.g., aluminum, copper, tungsten, titanium, tantalum, etc.), and metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0085] In some examples, as shown in Figures 3c and 3h, the channel region of the semiconductor body 202 is surrounded by a gate dielectric layer 255. The gate 276 includes a first gate layer 253 and a second gate layer 254. The first gate layer 253 surrounds the gate dielectric layer 255, and the second gate layer 254 surrounds the first gate layer 253. The material of the first gate layer 253 includes titanium nitride, and the material of the second gate layer 254 includes tungsten. In some examples, as shown in Figure 3h, the first gate layer 253 also surrounds the second gate layer 254, and the gate dielectric layer 255 also surrounds the first gate layer 253.

[0086] In some embodiments, as shown in FIG3h, the semiconductor device 200 further includes a first isolation structure 227, a second isolation structure 236, and a third isolation structure 242; the first isolation structure 227, the second isolation structure 236, and the third isolation structure 242 are all located between the semiconductor bodies 202 of two adjacent transistors 201 along the second direction, the first isolation structure 227 and the third isolation structure 242 are respectively located on opposite sides of the gate structure 203 along the first direction, and the second isolation structure 236 is located between the semiconductor body 202 and the third isolation structure 242; the width of the bit line 205 in the second direction is a first width, and the width of the gate structure 203 between the first isolation structure 227 and the third isolation structure 242 in the first direction is a second width; the first width is greater than the second width.

[0087] In some examples, the materials of the first isolation structure 227, the second isolation structure 236, and the third isolation structure 242 include, but are not limited to, silicon oxide.

[0088] In some embodiments, as shown in FIG3b, FIG3d, FIG3f and FIG3h, the semiconductor device 200 further includes a plurality of capacitors 213; the capacitors 213 include a first electrode 214, a second electrode 215 and a dielectric layer 216 located between the first electrode 214 and the second electrode 215; one end of the semiconductor body 202 opposite to each other along a first direction is connected to the first electrode 214 of the capacitor 213, and the other end of the semiconductor body 202 opposite to each other along the first direction is connected to the bit line 205.

[0089] In some examples, the first electrode 214 can be used as the inner electrode of the capacitor 213, and the second electrode 215 can be used as the outer electrode of the capacitor 213. The dielectric layer 216 is made of a high-dielectric-constant (High-K) material; exemplaryly, the material of the dielectric layer 216 may include, but is not limited to, alumina (Al2O3), zirconium oxide (ZrO), hafnium oxide (HfO2), etc. The material of the first electrode 214 may include a conductive material; exemplaryly, it may be tungsten. The material of the second electrode 215 may include a conductive material; exemplaryly, it may be tungsten.

[0090] In some embodiments, as shown in Figures 3b and 3f, a plurality of transistors 201 arranged along a first direction include a first transistor 218 and a second transistor 219 arranged alternately along the first direction; adjacent first transistors 218 and second transistors 219 along the first direction constitute a transistor group 217; one end of the semiconductor body 202 of the first transistor 218, located away from the second transistor 219 in the same transistor group 217, is connected to a bit line 205; one end of the semiconductor body 202 of the second transistor 219, located away from the first transistor 218 in the same transistor group 217, is connected to a bit line 205; one end of the semiconductor body 202 of the first transistor 218, located near the second transistor 219 in the same transistor group 217, is connected to a capacitor 213; one end of the semiconductor body 202 of the second transistor 219, located near the first transistor 218 in the same transistor group 217, is connected to a capacitor 213.

[0091] In this embodiment of the present disclosure, as shown in Figures 3b and 3f, the bit lines 205 connected to the two transistors 201 in the same transistor group 217 are located on opposite sides of the transistor group 217 along the first direction; two bit lines 205 are provided between adjacent transistor groups 217 along the first direction, and the two bit lines 205 are respectively connected to their respective nearest transistors 201; the capacitors 213 connected to the first transistor 218 and the second transistor 219 in the same transistor group 217 are located between the first transistor 218 and the second transistor 219 in the transistor group 217.

[0092] In some embodiments, as shown in Figures 3b, 3f, and 3h, the second plate 215 of the capacitor 213 to which the first transistor 218 is connected is connected to the second plate 215 of the capacitor 213 to which the second transistor 219 in the same transistor group 217 is connected. The second plates 215 of the capacitors 213 to which the plurality of first transistors 218 arranged along the second direction are connected. The second plates 215 of the capacitors 213 to which the plurality of second transistors 219 arranged along the second direction are connected. The second plates 215 of the capacitors 213 to which the plurality of first transistors 218 arranged along the third direction are connected. The second plates 215 of the capacitors 213 to which the plurality of second transistors 219 arranged along the third direction are connected.

[0093] In this embodiment of the disclosure, the second plates 215 of the plurality of capacitors 213 are connected, which reduces the number of contacts leading out from the second plates 215, thereby further saving the area of ​​the semiconductor device 200.

[0094] In this embodiment of the present disclosure, as shown in Figures 3b, 3f, and 3h, the dielectric layers 216 of capacitors 213 to which the first transistor 218 and the second transistor 219 in the same transistor group 217 are respectively connected, the dielectric layers 216 of capacitors 213 to which a plurality of first transistors 218 arranged along the second direction are connected, the dielectric layers 216 of capacitors 213 to which a plurality of second transistors 219 arranged along the second direction are connected, and the dielectric layers 216 of capacitors 213 to which a plurality of first transistors 218 arranged along the third direction are connected, and the first dielectric layer 216 of capacitors 213 to which a plurality of second transistors 219 arranged along the third direction are connected.

[0095] This disclosure provides another semiconductor device, as shown in Figures 3i to 3l. The semiconductor device 200 includes: a plurality of transistors 201; each transistor 201 includes a semiconductor body 202 extending along a first direction and a gate structure 203 located on at least one side of the semiconductor body 202 perpendicular to the first direction; the gate structures 203 of the plurality of transistors 201 arranged along a second direction are connected to each other; the first direction intersects the second direction; a plurality of first word lines 204 and second word lines 206 extending along the first direction; the plurality of first word lines 204 are stacked along a third direction, and the plurality of second word lines 206 are stacked along a third direction; the third direction is perpendicular to both the first and second directions; two adjacent transistors 201 along the first direction are connected to the same bit line 205, and two adjacent transistors 201 connected to the same bit line 205 along the first direction are respectively connected to the first word line 204 and the second word line 206.

[0096] Figure 3i is a top view of a semiconductor device provided in an embodiment of the present disclosure; Figure 3j is a cross-sectional view of a semiconductor device provided in an embodiment of the present disclosure along the XY plane; Figure 3c is an enlarged view of the transistor shown in Figure 3j; Figure 3d is an enlarged view of the capacitor shown in Figure 3j; Figure 3k is a three-dimensional view of a semiconductor device provided in an embodiment of the present disclosure; and Figure 3l is a partial three-dimensional view of a semiconductor device provided in an embodiment of the present disclosure.

[0097] In the solution provided by the embodiments of this disclosure, firstly, the semiconductor device 200 includes a plurality of transistors 201, which are arranged along a first direction, a second direction, and a third direction. Each transistor 201 includes a semiconductor body 202 extending along the first direction. That is, the transistors 201 in this embodiment are vertical transistors 201, and the plurality of transistors are stacked in three dimensions. This results in a high transistor density, reduces the area occupied by the semiconductor device 200, and facilitates the miniaturization of the semiconductor device 200. Secondly, the gate structures 203 of the transistors 201 arranged along the second direction are interconnected. The semiconductor device 200 includes a plurality of first word lines 204 stacked along a third direction, which extend along the first direction and are connected to the gate structures 203 of the transistors 201. The semiconductor device 200 includes a plurality of second word lines 206 stacked along a third direction, which extend along the first direction and are connected to the gate structures 203 of the transistors 201. Since no step structure is required, the transistors can achieve higher density and smaller area. By setting corresponding word line contacts on multiple first row word lines 204 extending along the first direction and on multiple second row word lines 206 extending along the first direction, the gate structure 203 can be brought out, thereby further reducing the area occupied by the semiconductor device 200. Thirdly, the gate structure 203 of the transistor 201 is brought out through the first row word lines 204 and the second row word lines 206 extending along the first direction, resulting in low word line resistance and low resistance-capacitance delay. Fourthly, the first row word lines 204 and the second row word lines 206 are respectively connected to the gate structure 203 of the transistor 201. Among the multiple transistors 201, the transistors 201 arranged along the third direction are connected to the same bit line 205, and two adjacent transistors 201 along the first direction are connected to the same bit line 205. Thus, there is at least a pair of transistors and a pair of capacitors between two adjacent bit lines 205 along the first direction (X direction). Based on this, the bit line spacing is greatly increased, the coupling between bit lines is reduced, the bit line capacitance is effectively reduced, and the process complexity is reduced.

[0098] The semiconductor device 200 in this embodiment can be understood as the memory 120 shown in FIG1, or as the memory array 121 in the memory shown in FIG1.

[0099] In the semiconductor device 200 provided in this embodiment, the gate structure 203 of each of the plurality of transistors 201 arranged along a third direction is connected to different first row word lines 204, or the gate structure 203 of each of the plurality of transistors 201 arranged along a third direction is connected to different second row word lines 206. It can be understood that the semiconductor device 200 includes a plurality of transistor layers stacked along a third direction, each transistor layer including a plurality of transistors 201 arranged in an array along a first direction and a second direction. The plurality of transistors 201 in each transistor layer are arranged in rows along the first direction and columns along the second direction. For example, transistors arranged along the first direction (X direction) and located in the same transistor layer are called a transistor row or a row of transistors, and transistors arranged along the second direction (Y direction) and located in the same transistor layer are called a transistor column or a column of transistors. The gate structures of odd-numbered transistor columns arranged along the first direction are connected to the first row word line 204, and the gate structures of even-numbered transistor columns arranged along the first direction are connected to the second row word line 206. Half of all transistors in the same transistor layer may share a first row word line 204, and the other half may share a second row word line 206. Transistors in different transistor layers are connected to different first row word lines 204 or second row word lines 206.

[0100] In some specific examples, the first line word line 204 and the second line word line 206 are made of conductive materials. The conductive materials include, but are not limited to, at least one of the following: doped semiconductor materials (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metallic materials (e.g., aluminum, copper, tungsten, titanium, tantalum, etc.), and metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0101] In this embodiment of the disclosure, bit line 205 extends along a third direction, and a plurality of transistors 201 arranged along the third direction are connected to the same bit line 205, and two adjacent transistors 201 along the first direction are connected to the same bit line 205.

[0102] In some specific examples, the material of bit line 205 is a conductive material, which includes, but is not limited to, at least one of doped semiconductor materials (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metallic materials (e.g., aluminum, copper, tungsten, titanium, tantalum, etc.) and metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0103] In this embodiment of the present disclosure, as shown in FIG3h, the semiconductor device 200 further includes a first insulating layer 223, through which the first row word line 204, the second row word line 206, and the transistor 201 adjacent in the third direction are all isolated. The material of the first insulating layer 223 here includes, but is not limited to, silicon oxide.

[0104] In some embodiments, as shown in FIG3i and FIG3j, the semiconductor device 200 further includes a plurality of first row word line contacts 207; the first row word line contacts 207 extend along a third direction, each of the plurality of first row word line contacts 207 is connected to a different first row word line 204, and the plurality of first row word line contacts 207 are arranged in a row along a first direction.

[0105] In this embodiment of the disclosure, based on the provision of a plurality of first line character lines 204 extending along a first direction, first line character line contacts 207 are provided on the first line character lines 204, such that different first line character lines 204 are led out through different first line character line contacts 207. Since the first line character lines 204 extend along the first direction, the plurality of first line character line contacts 207 are arranged in a row along the first direction, thereby reducing the area occupied by the character line contacts. In other words, the area occupied by the plurality of first line character line contacts 207 is close to the area occupied by one first line character line 204, or in other words, the orthographic projection of the plurality of first line character line contacts 207 overlaps with the orthographic projection of one first line character line 204.

[0106] In this embodiment of the disclosure, a first line character line contact 207 is connected to a first line character line 204. The first line character line contact 207 connected to a certain first line character line 204 will pass through other first line character lines above the first line character line. A corresponding first dielectric layer is provided between the first line character line contact 207 and the other first line character lines above the first line character line, so that the first line character line contact 207 is separated from the other first line character lines above the first line character line.

[0107] In some embodiments, the number of first line word line contacts 207 is the same as the number of first line word lines 204 stacked along a third direction.

[0108] Understandably, a first line word line 204 is led out through a first line word line contact 207, so that the number of first line word line contacts 207 is the same as the number of first line word lines 204 stacked along a third direction.

[0109] In some embodiments, the number of first line word lines 204 penetrated by different first line word line contacts 207 among a plurality of first line word line contacts 207 is different.

[0110] In some embodiments, the number of first line word lines 204 that two adjacent first line word line contacts 207 pass through are different.

[0111] In some embodiments, the dimensions of each of the plurality of first line word line contacts 207 arranged along the first direction are different along the third direction.

[0112] In some embodiments, as shown in Figures 3i to 3l, a plurality of transistors 201 are located between the first row word line 204 and the second row word line 206.

[0113] In some embodiments, as shown in Figures 3i to 3l, the first row word line 204 and the second row word line 206 are respectively located on opposite sides of a plurality of transistors 201 arranged along the second direction. Furthermore, the first row word line 204 and the second row word line 206 are respectively located on opposite sides of a plurality of bit lines 205 arranged along the second direction.

[0114] In some examples, the material of the first line of text 204 is the same as the material of the second line of text 206.

[0115] In some embodiments, the semiconductor device 200 further includes: a plurality of second line word line contacts 208; the second line word line contacts 208 extend along a third direction, each of the plurality of second line word line contacts 208 is connected to a different second line word line 206, and the plurality of second line word line contacts 208 are arranged in a row along a first direction. In other words, the area occupied by the plurality of second line word line contacts 208 is close to the area occupied by a second line word line 206, or in other words, the orthographic projection of the plurality of second line word line contacts 208 overlaps with the orthographic projection of a second line word line 206.

[0116] Understandably, based on the first row of word lines 204 and the second row of word lines 206, a portion of the gate structure 203 of the transistor layer can be led out through the first row of word line contacts 207, and another portion of the gate structure 203 of the transistor layer can be led out through the second row of word line contacts 208. This makes the setting of word line contacts more flexible, allows the word line contacts to be set more dispersed, and avoids short circuit problems and high process difficulty caused by too dense word line contacts.

[0117] In some embodiments, the number of second line word line contacts 208 is the same as the number of second line word lines 206 stacked along a third direction.

[0118] In this embodiment of the disclosure, transistors 201 within the same transistor layer are led out through first row word line contacts 207 and second row word line contacts 208. That is, each first row word line 204 needs to be connected to a first row word line contact 207, and each second row word line 206 needs to be connected to a second row word line contact 208. The number of transistor layers is equal to the number of first row word lines 204, and the number of first row word lines 204 is the same as the number of second row word lines 206. Therefore, the number of first row word line contacts 207 is the same as the number of second row word line contacts 208, and the number of first row word line contacts 207 and the number of second row word line contacts 208 can both be equal to the number of transistor layers.

[0119] In some embodiments, the number of second line characters 206 penetrated by different second line character contact points 208 among a plurality of second line character contact points 208 is different.

[0120] In some embodiments, the number of second line characters 206 that two adjacent second line character contact points 208 pass through are different.

[0121] In some embodiments, the dimensions of each of the plurality of second line word line contacts 208 arranged along the first direction are different along the third direction.

[0122] In some embodiments, the different first line word lines 204 stacked along a third direction have equal lengths in a first direction, and the different first line word lines 204 stacked along a third direction have equal lengths in a second direction.

[0123] It is understood that in this embodiment of the present disclosure, by setting corresponding word line contacts on a plurality of first row word lines 204 and second row word lines 206 stacked along a third direction to bring out the gate structure 203 of transistor 201, without setting a step structure to bring out the gate structure 203 of transistor 201 of different transistor layers, the area of ​​semiconductor device 200 can be reduced.

[0124] In some embodiments, the dimension of the first line character line 204 along the second direction may be equal to the dimension of the first line character line contact 207 along the second direction, or the dimension of the first line character line 204 along the second direction may be slightly larger than the dimension of the first line character line contact 207 along the second direction, or the dimension of the first line character line 204 along the second direction may be smaller than the dimension of the first line character line contact 207 along the second direction.

[0125] In some embodiments, the different second line characters 206 stacked along a third direction have equal lengths in a first direction, and the different second line characters 206 stacked along a third direction have equal lengths in a second direction.

[0126] In some embodiments, the dimension of the second line character line 206 along the second direction may be equal to the dimension of the second line character line contact 208 along the second direction, or the dimension of the second line character line 206 along the second direction may be slightly larger than the dimension of the second line character line contact 208 along the second direction, or the dimension of the second line character line 206 along the second direction may be smaller than the dimension of the second line character line contact 208 along the second direction.

[0127] In some embodiments, the dimension of the first line character line 204 along the first direction is equal to the dimension of the second line character line 206 along the first direction.

[0128] In some embodiments, the material of the semiconductor body 202 includes a metal oxide semiconductor.

[0129] In some examples, the metal oxide semiconductor includes at least one element selected from indium, gallium, zinc, tin, and tungsten. Exemplarily, the metal oxide semiconductor in this disclosure is indium gallium zinc oxide (IGZO).

[0130] In this embodiment of the present disclosure, the material of the semiconductor body 202 includes metal oxide semiconductor, which allows the stacked structure to be constructed using mature processes such as silicon nitride-silicon oxide (NO) stacking during the formation of the semiconductor device 200, and is not limited by the number of stacked layers.

[0131] In this embodiment of the present disclosure, as shown in FIG3c, the semiconductor body 202 extends along a first direction. The semiconductor body 202 includes a first electrode, a channel region, and a second electrode arranged sequentially along the first direction. Here, the first electrode can be one of the source and drain of a transistor, and the second electrode can be the other of the source and drain of a transistor.

[0132] In this embodiment of the disclosure, the extension direction of the first word line 204 and the second word line 206 is the same as the extension direction of the semiconductor body 202.

[0133] In some embodiments, as shown in FIG3c and FIG3l, the gate structure 203 of transistor 201 is located on two opposite sides of semiconductor body 202 of transistor 201 along a second direction and on two opposite sides of semiconductor body 202 along a third direction.

[0134] In this embodiment, the gate structure 203 surrounds the channel region of the semiconductor body 202, forming a full-to-the-loop gate transistor. It is understood that the gate structure 203 surrounding the channel region of the semiconductor body 202 enhances the gate structure 203's control over the channel region, thereby reducing leakage current.

[0135] It should be noted that the arrangement of the gate structure 203 in Figures 3c and 3l is only an example. In other embodiments, the gate structure 203 may be located on one side, two sides, or three sides of the channel region. This disclosure does not impose any specific limitations on this.

[0136] In some examples, as shown in FIG3c, the gate structure 203 includes a gate dielectric layer 255 and a gate 276. The gate dielectric layer 255 is located between the gate 276 and the channel region. The material of the gate dielectric layer 255 may include at least one of a high dielectric constant material, silicon oxide, silicon nitride, and silicon oxynitride, wherein the high dielectric constant material may include at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The material of the gate 276 includes at least one of conductive materials, such as doped semiconductor materials (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metallic materials (e.g., aluminum, copper, tungsten, titanium, tantalum, etc.), and metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0137] In some examples, as shown in Figures 3c and 3l, the channel region of the semiconductor body 202 is surrounded by a gate dielectric layer 255. The gate 276 includes a first gate layer 253 and a second gate layer 254. The first gate layer 253 surrounds the gate dielectric layer 255, and the second gate layer 254 surrounds the first gate layer 253. The material of the first gate layer 253 includes titanium nitride, and the material of the second gate layer 254 includes tungsten. In some examples, as shown in Figure 3h, the first gate layer 253 also surrounds the second gate layer 254, and the gate dielectric layer 255 also surrounds the first gate layer 253.

[0138] In some embodiments, as shown in FIG31, the semiconductor device 200 further includes a first isolation structure 227, a second isolation structure 236, and a third isolation structure 242; the first isolation structure 227, the second isolation structure 236, and the third isolation structure 242 are all located between the semiconductor bodies 202 of two adjacent transistors 201 along the second direction, the first isolation structure 227 and the third isolation structure 242 are respectively located on opposite sides of the gate structure 203 along the first direction, and the second isolation structure 236 is located between the semiconductor body 202 and the third isolation structure 242; the width of the bit line 205 in the second direction is a first width, and the width of the gate structure 203 between the first isolation structure 227 and the third isolation structure 242 in the first direction is a second width; the first width is greater than the second width.

[0139] In some examples, the materials of the first isolation structure 227, the second isolation structure 236, and the third isolation structure 242 include, but are not limited to, silicon oxide.

[0140] In some embodiments, as shown in FIG3j, FIG3d, FIG3k and FIG3l, the semiconductor device 200 further includes a plurality of capacitors 213; the capacitors 213 include a first electrode 214, a second electrode 215 and a dielectric layer 216 located between the first electrode 214 and the second electrode 215; one end of the semiconductor body 202 opposite to each other along a first direction is connected to the first electrode 214 of the capacitor 213, and the other end of the semiconductor body 202 opposite to each other along the first direction is connected to the bit line 205.

[0141] In some examples, the first electrode 214 can be used as the inner electrode of the capacitor 213, and the second electrode 215 can be used as the outer electrode of the capacitor 213. The dielectric layer 216 is made of a high-dielectric-constant (High-K) material; exemplaryly, the material of the dielectric layer 216 may include, but is not limited to, alumina (Al2O3), zirconium oxide (ZrO), hafnium oxide (HfO2), etc. The material of the first electrode 214 may include a conductive material; exemplaryly, it may be tungsten. The material of the second electrode 215 may include a conductive material; exemplaryly, it may be tungsten.

[0142] In some embodiments, as shown in FIG3j, a plurality of transistors 201 arranged along a first direction, wherein a first transistor 218 and a second transistor 219 are alternately arranged along the first direction; adjacent first transistors 218 and second transistors 219 along the first direction constitute a transistor group 217; in the same transistor group 217, the end of the semiconductor body 202 of the first transistor 218 that is far from the second transistor 219 along the first direction is connected to a bit line 205, and the end that is close to the second transistor 219 is connected to a capacitor 213; the end of the semiconductor body 202 of the second transistor 219 that is far from the first transistor 218 along the first direction is connected to a bit line 205, and the end that is close to the first transistor 218 is connected to a capacitor 213.

[0143] In some embodiments, the gate structure of the first transistor 218 is connected to the first row word line 204, and the gate structure of the second transistor 219 is connected to the second row word line 206; the gate structures of a plurality of first transistors 218 arranged along the second direction are connected to the same first row word line 204, and the gate structures of a plurality of second transistors arranged along the second direction are connected to the same second row word line 206. Here, the plurality of first transistors 218 arranged along the second direction constitute an odd-numbered transistor column, and the plurality of second transistors arranged along the second direction constitute an even-numbered transistor column.

[0144] In some embodiments, transistor 201 and capacitor 213 constitute a memory cell. In each memory cell, transistor 201 and capacitor 213 are arranged along a first direction. In other words, the memory cell extends along the first direction. In embodiments of this disclosure, the extending directions of the first word line 204 and the second word line 206 are the same as the extending directions of the memory cell.

[0145] In this embodiment of the present disclosure, as shown in FIG3j, the bit lines 205 connected to the two transistors 201 in the same transistor group 217 are located on opposite sides of the transistor group 217 along the first direction; two bit lines 205 are provided between adjacent transistor groups 217 along the first direction, and the two bit lines 205 are respectively connected to their respective adjacent transistors 201; the capacitors 213 connected to the first transistor 218 and the second transistor 219 in the same transistor group 217 are located between the first transistor 218 and the second transistor 219 in the transistor group 217.

[0146] In some embodiments, as shown in FIG3j and FIG3l, the second plate 215 of the capacitor 213 to which the first transistor 218 is connected is connected to the second plate 215 of the capacitor 213 to which the second transistor 219 in the same transistor group 217 is connected; the second plates 215 of the capacitors 213 to which the plurality of first transistors 218 arranged along the second direction are connected; the second plates 215 of the capacitors 213 to which the plurality of second transistors 219 arranged along the second direction are connected; and the second plates 215 of the capacitors 213 to which the plurality of first transistors 218 arranged along the third direction are connected; and the second plates 215 of the capacitors 213 to which the plurality of second transistors 219 arranged along the third direction are connected.

[0147] In this embodiment of the disclosure, the second plates 215 of the plurality of capacitors 213 are connected, which reduces the number of contacts leading out from the second plates 215, thereby further saving the area of ​​the semiconductor device 200.

[0148] In this embodiment of the present disclosure, as shown in Figures 3j and 3l, the dielectric layers 216 of capacitors 213 to which the first transistor 218 and the second transistor 219 in the same transistor group 217 are respectively connected, the dielectric layers 216 of capacitors 213 to which a plurality of first transistors 218 arranged along the second direction are connected, the dielectric layers 216 of capacitors 213 to which a plurality of second transistors 219 arranged along the second direction are connected, and the dielectric layers 216 of capacitors 213 to which a plurality of first transistors 218 arranged along the third direction are connected, and the first dielectric layer 216 of capacitors 213 to which a plurality of second transistors 219 arranged along the third direction are connected.

[0149] Based on the semiconductor device 200 described above, this disclosure also provides a memory system, including: a semiconductor device 200 as described in any of the above embodiments; and a memory controller; the memory controller is coupled to the semiconductor device 200 and configured to control the semiconductor device 200.

[0150] The memory system in this embodiment can be understood as the memory system 10 shown in FIG1. ​​Other details about the memory system have been described in detail above, and will not be repeated here for the sake of brevity.

[0151] Based on the above-described semiconductor device, this disclosure also provides a method for fabricating a semiconductor device. Figure 4a is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this disclosure. As shown in Figure 4a, the method for fabricating a semiconductor device includes the following steps: Step S1001: Forming a plurality of transistors; each transistor includes a semiconductor body extending along a first direction and a gate structure located on at least one side of the semiconductor body perpendicular to the first direction; the gate structures of the transistors arranged along a second direction among the plurality of transistors are connected to each other; the first direction intersects the second direction; Step S1002: Forming a plurality of first row word lines; the plurality of first row word lines are stacked along a third direction, the first row word lines extend along the first direction and are connected to the gate structures of the transistors; the third direction is perpendicular to both the first and second directions; Step S1003: Forming a plurality of bit lines; the bit lines extend along a third direction, the transistors arranged along the third direction among the plurality of transistors are connected to the same bit line, and two adjacent transistors along the first direction are connected to different bit lines; the bit lines are located on one side of the two opposite sides of the first row word lines along the second direction.

[0152] It should be understood that the steps shown in Figure 4a are not exclusive, and other steps may be performed before, after, or between any of the steps shown in the operation; the order of the steps shown in Figure 4a can be adjusted according to actual needs.

[0153] Figures 5 to 63 are schematic diagrams of the fabrication process of a semiconductor device provided in an embodiment of the present disclosure. The fabrication method of the semiconductor device provided in the embodiment of the present disclosure will be described below with reference to Figures 4a and 5 to 63.

[0154] In some embodiments, a plurality of transistors are formed, including: as shown in FIG5 and FIG6, a substrate 220 is provided, the substrate 220 includes a semiconductor layer 221 and a stacked structure 222 formed on the semiconductor layer 221, the stacked structure 222 includes a first insulating layer 223 and a first sacrificial layer 224 alternately disposed along a third direction; the stacked structure 222 includes a first sub-stacked structure 225 and a second sub-stacked structure 226 alternately arranged along a first direction.

[0155] It should be noted that, in order to more clearly illustrate the semiconductor device formation process, Figure 6 shows a three-dimensional structural diagram after removing some structures from Figure 5.

[0156] In some examples, the semiconductor layer 221 includes, but is not limited to, a substrate, the material of which includes, but is not limited to, a single semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, a composite semiconductor material substrate (e.g., a germanium-silicon (SiGe) substrate), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.

[0157] In some examples, the first insulating layer 223 and the first sacrificial layer 224 may have the same thickness or different thicknesses. The material of the first insulating layer 223 includes, but is not limited to, one or more of silicon oxide layers and silicon carbide layers; the material of the first sacrificial layer 224 includes, but is not limited to, one or more of silicon nitride layers and silicon oxide nitride layers. In some specific examples, the material of the first insulating layer 223 is silicon oxide (SiO2), and the material of the first sacrificial layer 224 is silicon nitride (SiN), thereby forming a stacked structure 222 that is a nitride-oxide (NO) stack.

[0158] In this embodiment of the disclosure, NO stacking can be used, which is a mature process and the number of stacked layers is not limited.

[0159] In some examples, a stacked structure 222 can be formed on the semiconductor layer 221 by a deposition process.

[0160] In this disclosure, the deposition process includes, but is not limited to, chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0161] In this embodiment of the present disclosure, the stacking structure 222 includes a first sub-stacking structure 225 and a second sub-stacking structure 226 arranged alternately along a first direction, wherein a first insulating layer 223 extends from the first sub-stacking structure 225 to the second sub-stacking structure 226, and a first sacrificial layer 224 extends from the first sub-stacking structure 225 to the second sub-stacking structure 226.

[0162] It should be noted that the number of the first sub-stack structure 225 and the second sub-stack structure 226 in Figure 5 is only an example, and this disclosure does not impose specific limitations on the number of the first sub-stack structure 225 and the second sub-stack structure 226.

[0163] In some embodiments, a plurality of transistors are formed, including: as shown in FIG7 to FIG9, a plurality of first isolation structures 227 extending through a first sub-stack structure 225 along a third direction and a plurality of first isolation structures 227 extending through a second sub-stack structure 226 along a third direction; the plurality of first isolation structures 227 in the first sub-stack structure 225 and the plurality of first isolation structures 227 in the second sub-stack structure 226 are both arranged along a second direction, and the first isolation structures 227 extend along a first direction.

[0164] It should be noted that, in order to more clearly illustrate the semiconductor device formation process, Figure 8 shows a three-dimensional structural diagram after removing some structures from Figure 7.

[0165] Specifically, as shown in Figures 7 and 8, forming the first isolation structure 227 includes: etching the stacked structure 222 to form a plurality of eighth trenches 256 penetrating the first sub-stacked structure 225 along a third direction and a plurality of eighth trenches 256 penetrating the second sub-stacked structure 226 along a third direction. The plurality of eighth trenches 256 in the first sub-stacked structure 225 are arranged along a second direction, and the plurality of eighth trenches 256 in the second sub-stacked structure 226 are arranged along a second direction. The eighth trenches 256 expose the semiconductor layer 221. As shown in Figure 9, the first isolation structure 227 is formed in the eighth trenches 256.

[0166] The etching processes described here include, but are not limited to, plasma etching (PE), sputtering etching (SE), ion beam etching (IBE), and reactive ion etching (RIE). The material of the first isolation structure 227 includes, but is not limited to, silicon oxide, and the first isolation structure 227 can be formed by a deposition process.

[0167] In some embodiments, as shown in FIG9, the distance between the first isolation structures 227 adjacent in the first direction in the first sub-stack structure 225 and the second sub-stack structure 226 is a first distance C1, and the distance between the first isolation structures 227 adjacent in the second direction is a second distance C2; ​​the second distance C2 is greater than the first distance C1.

[0168] It is understood that in this embodiment, the second distance is greater than the first distance, so that when the second sacrificial layer and the initial semiconductor body are subsequently formed in the first filling region, only the second sacrificial layer can be formed between the first isolation structures adjacent in the first direction without forming the initial semiconductor body. This separates the semiconductor bodies of the two transistors adjacent in the second direction in the final semiconductor device, and also connects the gate structures 203 of the two transistors adjacent in the second direction in the final semiconductor device.

[0169] In some embodiments, a plurality of transistors are formed, including: as shown in FIG10 and FIG11, forming a first trench 228 in the second sub-stack structure 226 that penetrates the second sub-stack structure 226 and the first isolation structure 227 along a third direction; the first trench 228 is arranged along a first direction and extends along a second direction, and is located between two first isolation structures 227 arranged along the second direction.

[0170] 256 In some examples, as shown in Figures 10 and 11, the first trench 228 retains a complete first isolation structure 227 on each of its opposite sides along the second direction, and the first trench 228 exposes a portion of the sidewall of the complete first isolation structure 227; in addition, a portion of the first isolation structure 227 penetrated by the first trench 228 is retained on each of its opposite sides along the first direction. The first trench 228 exposes the semiconductor layer 221. The first trench exposes a portion of the first sacrificial layer 224.

[0171] It should be noted that, in order to more clearly illustrate the semiconductor device formation process, Figure 11 shows a three-dimensional structural diagram after removing some structures from Figure 10.

[0172] In some embodiments, forming a plurality of transistors further includes: as shown in FIG11 and FIG12, removing a portion of the first sacrificial layer 224 through the first trench 228 to form a first filling region 229.

[0173] As shown in Figure 12, the size W1 of the portion of the first filling region 229 located between adjacent first isolation structures 227 along the first direction is smaller than the size W2 of the portion of the first filling region 229 located between adjacent first isolation structures 227 along the second direction.

[0174] In some embodiments, forming a plurality of transistors further includes: forming a second sacrificial layer 230 on the inner wall of a first filling region 229, as shown in FIG12 to 16; forming an initial semiconductor body 231 in the first filling region 229 in which the second sacrificial layer 230 is formed; the initial semiconductor body 231 includes a first portion 232, a second portion 233, and a third portion 234 arranged along a first direction.

[0175] Specifically, as shown in Figures 12 and 13, a second sacrificial material layer 257 is filled in the first filling region 229 and the first trench 228; as shown in Figure 14, an initial semiconductor material layer 258 is filled in the first filling region 229 and the first trench 228 filled with the second sacrificial material layer 257, and a second sacrificial material layer 257 and an initial semiconductor material layer 258 are also formed on the top of the stacked structure 222; as shown in Figure 15, the second sacrificial material layer 257 and the initial semiconductor material layer 258 on the top of the stacked structure 222 are removed; as shown in Figure 16, the second sacrificial material layer 257 and the initial semiconductor material layer 258 in the first trench 228 are removed, and the remaining second sacrificial material layer 257 in the first filling region 229 constitutes the second sacrificial layer 230, and the remaining initial semiconductor material layer 258 in the first filling region 229 constitutes the initial semiconductor body 231.

[0176] In some embodiments, forming a plurality of transistors further includes: as shown in FIG16 and FIG17, removing a portion of the second sacrificial layer 230 through the first trench 228 to form a second filling region 235; the second filling region 235 exposing a first portion 232; and as shown in FIG18 and FIG19, forming a second isolation structure 236 in the second filling region 235 and the first trench 228.

[0177] As shown in Figure 17, the second sacrificial layer 230 surrounding the first portion 232 of the initial semiconductor body 231 can be removed to form the second filled region 235. As shown in Figure 18, a second isolation material layer 259 is formed in the second filled region 235 and the first trench 228, and also on top of the stacked structure 222; as shown in Figure 19, the second isolation material layer 259 on top of the stacked structure 222 is removed to form the second isolation structure 236. In some examples, the material of the second isolation structure 236 includes, but is not limited to, silicon oxide.

[0178] In some embodiments, the method further includes: as shown in FIG20 and FIG21, forming a second trench 237 in the first sub-stack structure 225 that penetrates the first sub-stack structure 225 and the first isolation structure 227 along a third direction; the second trench 237 extends along a second direction and is located between two first isolation structures 227 arranged along the second direction.

[0179] It should be noted that, in order to more clearly illustrate the semiconductor device formation process, Figure 21 shows a three-dimensional structural diagram after removing some structures from Figure 20.

[0180] In some examples, as shown in Figures 20 and 21, the second trench 237 retains a complete first isolation structure 227 on each of its opposite sides along the second direction, and the second trench 237 exposes a portion of the sidewall of the complete first isolation structure 227; in addition, a portion of the first isolation structure 227 through which the second trench 237 penetrates is retained on each of its opposite sides along the first direction. The second trench 237 also exposes the semiconductor layer 221.

[0181] In some embodiments, the method further includes: as shown in Figures 21 to 23, removing a portion of the first sacrificial layer 224 and a portion of the second sacrificial layer 230 through the second trench 237 to form a third filling region 238; the third filling region 238 exposes a third portion 234.

[0182] As shown in Figures 21 and 22, a portion of the first sacrificial layer 224 is removed through the second trench 237, and the removed portion of the first sacrificial layer 224 surrounds the third portion 234 of the initial semiconductor body 231.

[0183] In some embodiments, the method further includes: before forming capacitors in the third filling region 238 and the second trench 237, as shown in FIG24, forming a first isolation layer 239 on the inner wall of the third filling region 238 and the inner wall of the second trench 237; as shown in FIG25, removing a portion of the first isolation layer 239 on the inner wall of the second trench 237 and the inner wall of the third filling region 238 to expose a third portion 234 of the initial semiconductor body; the remaining first isolation layer 239 in the third filling region 238 is located at least between the subsequently formed capacitor and the second sacrificial layer 230.

[0184] As shown in Figure 25, the remaining first isolation layer 239 covers the second sacrificial layer 230, so that the first plate of the subsequently formed capacitor is separated from the subsequently formed gate structure 203.

[0185] In some embodiments, the method further includes forming a capacitor 213 in a third filling region 238 and a second trench 237, as shown in Figures 25 to 29.

[0186] Specifically, as shown in Figures 25 and 26, a first electrode material layer 260 is formed on the inner wall of the second trench 237, the inner wall of the third filling region 238, and the top of the stacked structure 222; as shown in Figure 27, the first electrode material layer 260 in the second trench 237 is removed, and the remaining first electrode material layer 260 in the third filling region 238 constitutes the first electrode 214; as shown in Figure 28, the third filling region 238, the second trench 237, and the stacked structure 222 where the first electrode 214 is formed are... A dielectric material layer 261 is formed on the top of 2. A second electrode material layer 262 is formed on the top of the third filling region 238, the second trench 237, and the stacked structure 222 where the first electrode 214 and the dielectric material layer 261 are formed. As shown in FIG29, the first electrode material layer 260, the dielectric material layer 261, and the second electrode material layer 262 on the top of the stacked structure 222 are removed. The remaining dielectric material layer 261 constitutes the dielectric layer 216, and the remaining second electrode material layer 262 constitutes the second electrode 215.

[0187] In some embodiments, forming a plurality of transistors further includes: as shown in Figures 30 to 32, removing the first isolation structure 227 and a portion of the second isolation structure 236 in the second sub-stack structure 226 to form a plurality of third trenches 240 penetrating the second sub-stack structure 226 along a third direction; the plurality of third trenches 240 are arranged along a second direction and all extend along a first direction.

[0188] It should be noted that, in order to more clearly demonstrate the formation process of the semiconductor device 200, Figure 32 shows a three-dimensional structural schematic diagram after removing some structures from Figure 31.

[0189] Specifically, as shown in Figure 30, a first mask layer 263 is formed on top of the stacked structure 222. The material of the first mask layer 263 includes, but is not limited to, silicon oxide. As shown in Figures 30, 31, and 32, the first isolation structure 227 and part of the second isolation structure 236 in the second sub-stacked structure 226 are removed to form a plurality of third trenches 240, which expose the second sacrificial layer 230.

[0190] In some embodiments, forming a plurality of transistors further includes: as shown in Figures 32 and 33, removing the remaining second sacrificial layer 230 through a third trench 240 to form a fourth fill region 241. As shown in Figure 33, the fourth fill region 241 exposes a second portion 233 of the initial semiconductor body 231.

[0191] In some embodiments, forming a plurality of transistors further includes forming a gate structure 203 in a fourth filling region 241, as shown in Figures 33 to 38.

[0192] Specifically, as shown in Figures 33 and 34, a gate dielectric material layer 264 is formed on the inner wall of the third trench 240, the inner wall of the fourth filling region 241, and the first mask layer 263; as shown in Figure 35, a first gate material layer 265 covering the gate dielectric material layer 264 is formed on the inner wall of the third trench 240, the inner wall of the fourth filling region 241, and the first mask layer 263; as shown in Figure 36, a second gate material layer 266 covering the first gate material layer 265 is formed on the inner wall of the third trench 240, the inner wall of the fourth filling region 241, and the first mask layer 263; as shown in Figure 37, the gate dielectric material layer 264 is removed. The gate dielectric material layer 264, the first gate material layer 265, and the second gate material layer 266 on top of the first mask layer 263; as shown in FIG38, the gate dielectric material layer 264, the first gate material layer 265, and the second gate material layer 266 in the third trench 240 are removed, and the remaining gate dielectric material layer 264, the first gate material layer 265, and the second gate material layer 266 located in the fourth filling region 241 respectively constitute the gate dielectric layer 255, the first gate layer 253, and the second gate layer 254; the gate dielectric layer 255, the first gate layer 253, and the second gate layer 254 constitute the gate structure 203.

[0193] In some embodiments, a plurality of transistors and a plurality of bit lines are formed, including: as shown in FIG38 and FIG39, forming a third isolation structure 242 in a third trench 240; as shown in FIG40 and FIG41, removing a portion of the second isolation structure 236 and a portion of the third isolation structure 242 to form a fourth trench 243 penetrating the second sub-stack structure 226 along a third direction, and removing the third isolation structure 242 and the first mask layer 263 on top of the stack structure 222; the fourth trench 243 exposes the initial semiconductor body 231, and the fourth trench 243 is located between two third isolation structures 242 arranged along a second direction.

[0194] It should be noted that, in order to more clearly illustrate the formation process of the semiconductor device 200, Figure 41 shows a three-dimensional structural schematic diagram after removing some structures from Figure 40.

[0195] In some examples, the material of the third isolation structure 242 includes, but is not limited to, silicon oxide.

[0196] In some embodiments, forming a plurality of transistors and a plurality of bit lines further includes: as shown in Figures 41 and 42, removing a portion of the second isolation structure 236 through the fourth trench 243 to form a fifth filling region 244; as shown in Figure 43, removing the initial semiconductor body 231 to form a sixth filling region 245; as shown in Figure 44, filling the fifth filling region 244 and the sixth filling region 245 with a metal oxide semiconductor material layer 246; as shown in Figure 45, removing a portion of the metal oxide semiconductor material layer 246 to form a plurality of fifth trenches 247 extending along a third direction, the remaining metal oxide semiconductor material layer 246 constituting a semiconductor body 202 extending along a first direction.

[0197] As shown in Figure 44, a metal oxide semiconductor material layer 246 is also formed on top of the stacked structure 222.

[0198] In some embodiments, forming a plurality of bit lines further includes forming bit line 205 in a fifth trench 247, as shown in Figures 45 to 49.

[0199] Specifically, as shown in Figures 45 and 46, a bit line material layer 267 is formed in the fifth trench 247, the fourth trench 243, and the top of the stacked structure 222; as shown in Figure 47, the bit line material layer 267 in the fourth trench 243 is removed; as shown in Figure 48, a bit line isolation structure material layer 269 is formed in the fourth trench 243 and the top of the stacked structure 222; as shown in Figure 49, the bit line isolation structure material layer 269, the metal oxide semiconductor material layer 246, and the bit line material layer 267 at the top of the stacked structure 222 are removed, the remaining bit line material layer 267 constitutes a plurality of bit lines 205, and the remaining bit line isolation structure material layer 269 constitutes a bit line isolation structure 268.

[0200] In this embodiment of the disclosure, the use of metal oxide semiconductor materials and NO stacks reduces the difficulty of vertical stacking and increases the number and density of transistors in the vertical direction.

[0201] In some embodiments, the method further includes, as shown in Figures 50 to 56, forming a plurality of first row word lines 204; the plurality of first row word lines 204 are stacked along a third direction, the first row word lines 204 extend along a first direction and are connected to the gate structure 203 of the transistor; the third direction is perpendicular to both the first direction and the second direction.

[0202] In some embodiments, the method further includes: forming a plurality of second row word lines 206 as shown in Figures 50 to 56; stacking the plurality of second row word lines 206 along a third direction; the second row word lines 206 extending along a first direction and connected to the gate structure 203 of the transistor; and arranging the second row word lines 206 and the first row word lines 204 along a second direction.

[0203] In this embodiment of the disclosure, only the first line of text 204 may be formed, or the first line of text 204 and the second line of text 206 may be formed. This embodiment of the disclosure will be illustrated by taking the formation of the first line of text 204 and the second line of text 206 as an example.

[0204] In some embodiments, forming a first row word line 204 and a second row word line 206 includes: as shown in FIG50 and 51, forming a sixth trench 248 and a seventh trench 249 that penetrate the stacked structure 222 along a third direction; the sixth trench 248 and the seventh trench 249 both extend from the first sub-stacked structure 225 to the second sub-stacked structure 226; the sixth trench 248 and the seventh trench 249 are respectively located on opposite sides of a plurality of transistors arranged along a second direction.

[0205] It should be noted that, in order to more clearly illustrate the semiconductor device formation process, Figure 51 shows a three-dimensional structural diagram after removing some structures from Figure 50.

[0206] In this embodiment of the present disclosure, as shown in Figures 50 and 51, a portion of a first sacrificial layer 224 exists between the sixth trench 248 and the third isolation structure 242 closest to the sixth trench 248, and a portion of the first sacrificial layer 224 also exists between the seventh trench 249 and the third isolation structure 242 closest to the seventh trench 249. The sixth trench 248 and the seventh trench 249 are respectively located in the regions of two opposite edges of the stacked structure 222 along the second direction. Both the sixth trench 248 and the seventh trench 249 expose the semiconductor layer 221.

[0207] In some embodiments, forming the first row word line 204 and the second row word line 206 further includes: as shown in FIG52 and 53, removing the remaining first sacrificial layer 224 through the sixth trench 248 and the seventh trench 249 to form a seventh filling region 250 and an eighth filling region 251; both the seventh filling region 250 and the eighth filling region 251 expose the gate structure 203; both the seventh filling region 250 and the eighth filling region 251 extend along a first direction; and the seventh filling region 250 and the eighth filling region 251 are respectively located on opposite sides of a plurality of transistors arranged along a second direction.

[0208] It should be noted that, in order to more clearly illustrate the semiconductor device formation process, Figure 53 shows a three-dimensional structural diagram after removing some structures from Figure 52.

[0209] In some examples, as shown in Figure 53, the method further includes removing the exposed first gate layer and the exposed gate dielectric layer to expose the second gate layer.

[0210] In some embodiments, forming the first line character line 204 and the second line character line 206 further includes: forming the first line character line 204 in the seventh filling region 250 and forming the second line character line 206 in the eighth filling region 251, as shown in Figures 54 to 56.

[0211] In some embodiments, the method further includes forming a word line isolation structure 252 in the sixth trench 248 and the seventh trench 249, as shown in Figures 55 and 56.

[0212] Specifically, as shown in Figure 54, word line material layers 270 are formed in the sixth groove 248, the seventh groove 249, the seventh filling region 250, the eighth filling region 251, and the top of the stacked structure 222. As shown in Figure 55, the word line material layers 270 in the sixth groove 248 and the seventh groove 249 are removed, and word line isolation structure material layers 271 are formed in the sixth groove 248, the seventh groove 249, and the top of the stacked structure 222. As shown in Figure 56, the word line isolation structure material layer 271 at the top of the stacked structure 222 is removed, and the remaining word line isolation structure material layers 271 in the sixth groove 248 and the seventh groove 249 constitute the word line isolation structure 252. The word line material layer 270 at the top of the stacked structure 222 is also removed, and the remaining word line material layer 270 in the seventh filling region 250 constitutes the first row of word lines 204, and the remaining word line material layer 270 in the eighth filling region 251 constitutes the second row of word lines 206.

[0213] In some embodiments, the method further includes: as shown in Figures 57 to 63, forming a plurality of second line character line contacts 208 and a plurality of third line character line contacts 209; the second line character line contacts 208 extend along a third direction, each of the plurality of second line character line contacts 208 is connected to different first line character lines 204 stacked along the third direction, and the plurality of second line character line contacts 208 are arranged along a first direction; the third line character line contacts 209 extend along a third direction, each of the plurality of third line character line contacts 209 is connected to different second line character lines 206 stacked along the third direction, and the plurality of third line character line contacts 209 are arranged along the first direction.

[0214] It should be noted that, in order to more clearly illustrate the semiconductor device formation process, Figure 58 shows a three-dimensional structural diagram after removing some structures from Figure 57, and Figure 63 shows a three-dimensional structural diagram after removing some structures from Figure 62.

[0215] Specifically, as shown in Figures 57 and 58, a plurality of first contact holes 272 and a plurality of second contact holes 273 are formed; as shown in Figure 59, a first dielectric layer 275 is formed on the sidewalls and bottom walls of the first contact holes 272, the sidewalls and bottom walls of the second contact holes 273, and the top of the stacked structure 222; as shown in Figure 60, the first dielectric layer 275 on the top of the stacked structure 222, the first dielectric layer 275 on the bottom wall of the first contact holes 272, and the first dielectric layer 275 on the bottom wall of the second contact holes 273 are removed to expose the first contact holes 272. The bottom wall has a first line of text 204 and a second line of text 206 that exposes the bottom wall of the second contact hole 273; as shown in FIG61, a contact point material layer 274 is formed in the first contact hole 272, the second contact hole 273 and the top of the stacked structure 222; as shown in FIG62 and 63, the contact point material layer 274 at the top of the stacked structure 222 is removed, the contact point material layer 274 in the first contact hole 272 constitutes the second line of text contact 208, and the contact point material layer 274 in the second contact hole 273 constitutes the third line of text contact 209.

[0216] In this embodiment of the disclosure, the number of processes such as hole drilling, etching, and filling is reduced during the formation of the complex three-dimensional DRAM, resulting in a lower process difficulty.

[0217] Based on the above-described semiconductor device, this disclosure also provides another method for fabricating a semiconductor device. Figure 4b is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this disclosure. As shown in Figure 4b, the method for fabricating a semiconductor device includes the following steps: Step S2001: Forming a plurality of transistors; each transistor includes a semiconductor body extending along a first direction and a gate structure located on at least one side of the semiconductor body perpendicular to the first direction; the gate structures of the transistors arranged along a second direction are connected to each other; the first direction intersects the second direction; Step S2002: Forming a plurality of bit lines; each bit line extends along a third direction; the third direction is perpendicular to both the first and second directions; Step S2003: Forming a plurality of first row word lines and second row word lines; the first row word lines and second row word lines extend along the first direction; two adjacent transistors along the first direction are connected to the same bit line, and two adjacent transistors along the first direction connected to the same bit line are respectively connected to the first row word line and the second row word line.

[0218] It should be understood that the steps shown in Figure 4b are not exclusive, and other steps may be performed before, after, or between any of the steps shown in the operation; the order of the steps shown in Figure 4b can be adjusted according to actual needs.

[0219] Figures 64 to 97 are schematic diagrams of the fabrication process of a semiconductor device provided in an embodiment of the present disclosure. The fabrication method of the semiconductor device provided in the embodiment of the present disclosure will be described below with reference to Figures 4b and 64 to 97.

[0220] In some embodiments, forming a plurality of transistors includes: as shown in FIG64 and FIG65, providing a substrate 220, the substrate 220 including a semiconductor layer 221 and a stacked structure 222 formed on the semiconductor layer 221, the stacked structure 222 including a first insulating layer 223 and a first sacrificial layer 224 alternately disposed along a third direction; the stacked structure 222 includes a first sub-stacked structure 225 and a second sub-stacked structure 226 alternately arranged along a first direction.

[0221] It should be noted that, in order to more clearly illustrate the semiconductor device formation process, Figure 65 shows a three-dimensional structural diagram after removing some structures from Figure 64.

[0222] In some examples, the semiconductor layer 221 includes, but is not limited to, a substrate, the material of which includes, but is not limited to, a single semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, a composite semiconductor material substrate (e.g., a germanium-silicon (SiGe) substrate), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.

[0223] In some examples, the first insulating layer 223 and the first sacrificial layer 224 may have the same thickness or different thicknesses. The material of the first insulating layer 223 includes, but is not limited to, one or more of silicon oxide layers and silicon carbide layers; the material of the first sacrificial layer 224 includes, but is not limited to, one or more of silicon nitride layers and silicon oxide nitride layers. In some specific examples, the material of the first insulating layer 223 is silicon oxide (SiO2), and the material of the first sacrificial layer 224 is silicon nitride (SiN), thereby forming a stacked structure 222 that is a nitride-oxide (NO) stack.

[0224] In this embodiment of the disclosure, NO stacking can be used, which is a mature process and the number of stacked layers is not limited.

[0225] In some examples, a stacked structure 222 can be formed on the semiconductor layer 221 by a deposition process.

[0226] In this disclosure, the deposition process includes, but is not limited to, chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0227] In this embodiment of the present disclosure, the stacking structure 222 includes a first sub-stacking structure 225 and a second sub-stacking structure 226 arranged alternately along a first direction, wherein a first insulating layer 223 extends from the first sub-stacking structure 225 to the second sub-stacking structure 226, and a first sacrificial layer 224 extends from the first sub-stacking structure 225 to the second sub-stacking structure 226.

[0228] It should be noted that the number of the first sub-stack structure 225 and the second sub-stack structure 226 in Figure 64 is only an example, and this disclosure does not impose any specific restrictions on the number of the first sub-stack structure 225 and the second sub-stack structure 226.

[0229] In some embodiments, forming a plurality of transistors includes: as shown in FIGS. 66 to 68, forming a first isolation structure 227 in a stacked structure 222. The first isolation structure 227 defines a bit line region and a capacitor region. The bit line region is used to form a bit line, and the capacitor region is used to form a capacitor. Specifically, forming the first isolation structure 227 in the stacked structure 222 includes: forming a plurality of first isolation structures 227 penetrating a first sub-stacked structure 225 along a third direction and a plurality of first isolation structures 227 penetrating a second sub-stacked structure 226 along a third direction; the plurality of first isolation structures 227 in the first sub-stacked structure 225 and the plurality of first isolation structures 227 in the second sub-stacked structure 226 are both arranged along a second direction, and the first isolation structures 227 extend along a first direction. Here, the capacitor region is located in the first sub-stacked structure 225, and the bit line region is located in the second sub-stacked structure 226. The first sub-stacked structure 225 and the second sub-stacked structure 226 are arranged alternately along the first direction, thereby the capacitor region and the bit line region are also arranged alternately along the first direction.

[0230] It should be noted that, in order to more clearly illustrate the semiconductor device formation process, Figure 67 shows a three-dimensional structural diagram after removing some structures from Figure 66.

[0231] Specifically, as shown in Figures 66 and 67, forming the first isolation structure 227 includes: etching the stacked structure 222 to form a plurality of first trenches 256 penetrating the first sub-stacked structure 225 along a third direction and a plurality of first trenches 280 penetrating the second sub-stacked structure 226 along a third direction. The plurality of first trenches 280 in the first sub-stacked structure 225 are arranged along a second direction, and the plurality of first trenches 280 in the second sub-stacked structure 226 are arranged along a second direction. The first trenches 280 expose the semiconductor layer 221. As shown in Figure 68, the first isolation structure 227 is formed in the first trenches 280.

[0232] The etching processes described here include, but are not limited to, plasma etching (PE), sputtering etching (SE), ion beam etching (IBE), and reactive ion etching (RIE). The material of the first isolation structure 227 includes, but is not limited to, silicon oxide, and the first isolation structure 227 can be formed by a deposition process.

[0233] In some embodiments, as shown in FIG68, the distance between the first isolation structures 227 adjacent in the first direction in the first sub-stack structure 225 and the second sub-stack structure 226 is a first distance C1, and the distance between the first isolation structures 227 adjacent in the second direction is a second distance C2; ​​the second distance C2 is greater than the first distance C1.

[0234] It is understood that in this embodiment, the second distance is greater than the first distance, so that when the second sacrificial layer and the initial semiconductor body are subsequently formed in the first filling region, only the second sacrificial layer can be formed between the first isolation structures adjacent in the first direction without forming the initial semiconductor body. This separates the semiconductor bodies of the two transistors adjacent in the second direction in the final semiconductor device, and also connects the gate structures 203 of the two transistors adjacent in the second direction in the final semiconductor device.

[0235] In some embodiments, forming a plurality of transistors includes: as shown in Figures 69 and 70, forming a plurality of first holes 281 penetrating the stacked structure 222 and located in the bit line region, and removing a portion of the first sacrificial layer 224 through the first holes 281 to form a first filling region 229. Specifically, a first hole 281 penetrating the second sub-stacked structure 226 along a third direction is formed in the second sub-stacked structure 226; the first holes 281 are arranged along a first direction in the bit line region.

[0236] In some examples, as shown in Figure 69, the etching of the first hole 281 avoids the first isolation structure 227, and the first hole 281 exposes part of the sidewall of the first isolation structure 227.

[0237] As shown in Figure 70, the size W1 of the portion of the first filling region 229 located between adjacent first isolation structures 227 along the first direction is smaller than the size W2 of the portion of the first filling region 229 located between adjacent first isolation structures 227 along the second direction.

[0238] In some embodiments, forming a plurality of transistors further includes: forming a second sacrificial layer 230 on the inner wall of the first filling region 229 as shown in FIG71; and forming a semiconductor pillar 282 in the first filling region 229 on which the second sacrificial layer 230 is formed.

[0239] Specifically, forming a second sacrificial layer 230 on the inner wall of the first filling region 229; forming a semiconductor pillar 282 in the first filling region 229 where the second sacrificial layer 230 is formed specifically includes: filling a second sacrificial material layer in the first filling region and the first trench; filling an initial semiconductor material layer in the first filling region and the first trench where the second sacrificial material layer is filled, and also forming a second sacrificial material layer and an initial semiconductor material layer on top of the stacked structure; removing the second sacrificial material layer and the initial semiconductor material layer on top of the stacked structure; removing the second sacrificial material layer and the initial semiconductor material layer in the first trench, the remaining second sacrificial material layer in the first filling region constitutes the second sacrificial layer, and the remaining initial semiconductor material layer in the first filling region constitutes the semiconductor pillar.

[0240] In some embodiments, forming a plurality of transistors further includes: as shown in FIG72, forming a plurality of first longitudinal grooves 283 penetrating the stacked structure, the first longitudinal grooves 283 dividing each semiconductor pillar 282 into an initial semiconductor body 284. Specifically, a first longitudinal groove 283 is formed in the second sub-stacked structure 226 penetrating the second sub-stacked structure 226 and the first isolation structure 227 along a third direction; the first longitudinal grooves 283 are arranged along a first direction and extend along a second direction.

[0241] The initial semiconductor body 284 includes a first portion 284-1, a second portion 284-2, and a third portion 284-3 arranged along a first direction. The third portion 284-3 of the initial semiconductor body 284 is close to the capacitor region, and the first portion 284-1 of the initial semiconductor body 284 is close to the bit line region.

[0242] It should be noted that the capacitor region is located in the first sub-stacking structure 225, and the bit line region is located in the second sub-stacking structure 226. Between the capacitor region and the bit line region lies the transistor region, which is used to form transistors; that is, the transistor region is partially located in the first sub-stacking structure 225 and partially in the second sub-stacking structure 226. The capacitor region and the bit line region are arranged alternately along the first direction, thus, there are two transistor regions and one bit line region between two adjacent capacitor regions. The capacitors formed by the capacitor regions and the transistors formed by the transistor regions are subsequently arranged along the first direction.

[0243] As shown in Figure 73, a second filling region 235 is formed by etching back the second sacrificial layer 230 through the first longitudinal groove 283; the second filling region 235 exposes the first portion 284-1; as shown in Figure 74, insulating material is filled into the second filling region 235 and the first longitudinal groove 283 to form a second isolation structure 236. The remaining second sacrificial layer 230 is a word line sacrificial layer.

[0244] In some embodiments, as shown in FIG73, the back etching of the second sacrificial layer 230 through the first longitudinal groove 283 can specifically be to remove the second sacrificial layer 230 surrounding the first portion 284-1 of the initial semiconductor body 284, thereby forming the second filling region 235.

[0245] In some embodiments, as shown in FIG74, forming a second isolation structure 236 within the second filling region 235 and the first longitudinal groove 283 may specifically include: filling the second filling region 235 and the first longitudinal groove 283 with insulating material, and also having insulating material on top of the stacked structure 222; removing the insulating material located on top of the stacked structure 222 to form the second isolation structure 236. In some examples, the insulating material includes, but is not limited to, silicon oxide.

[0246] In some embodiments, the method further includes forming a plurality of second trenches penetrating the stacked structure, as shown in FIG75. Specifically, a second trench 237 is formed in the first sub-stacked structure 225 penetrating the first sub-stacked structure 225 and the first isolation structure 227 along a third direction; the second trench 237 extends along a second direction.

[0247] In some examples, as shown in FIG75, the second trench 237 retains a complete first isolation structure 227 on each of its opposite sides along the second direction, and the second trench 237 exposes a portion of the sidewall of the complete first isolation structure 227; in addition, a portion of the first isolation structure 227 through which the second trench 237 penetrates is retained on each of its opposite sides along the first direction. The second trench 237 also exposes the semiconductor layer 221.

[0248] In some embodiments, the method further includes: as shown in FIG76, removing a portion of the first sacrificial layer 224 through the second trench 237 to form a third fill region 238; the third fill region 238 exposes the word line sacrificial layer (second sacrificial layer 230).

[0249] As shown in Figure 77, the word line sacrificial layer (second sacrificial layer 230) exposed in the third filling region 238 is etched to expose the third portion 284-3 of the initial semiconductor body 231. That is, the word line sacrificial layer (second sacrificial layer 230) surrounding the third portion 284-3 of the initial semiconductor body 231 is removed.

[0250] In some embodiments, the method further includes: before forming capacitors in the third filling region 238 and the second trench 237, as shown in FIG78, forming a first isolation layer 239 on the inner wall of the third filling region 238 and the inner wall of the second trench 237; as shown in FIG79, partially etching the first isolation layer 239 in the third filling region 238 and the second trench 237 to expose the third portion 284-3 of the initial semiconductor body 231; the remaining first isolation layer 239 at least covers one exposed end of the word line sacrificial layer (second sacrificial layer 230), that is, the remaining first isolation layer 239 in the third filling region 238 is at least located between the subsequently formed capacitor and the second sacrificial layer 230.

[0251] As shown in Figure 79, the remaining first isolation layer 239 covers one end of the word line sacrificial layer (second sacrificial layer 230) that is exposed, so that the first plate of the subsequently formed capacitor is electrically isolated from the subsequently formed gate structure 203.

[0252] In some embodiments, the method further includes: as shown in Figures 79 to 82, forming a first electrode 214, a dielectric layer 216, and a second electrode 215 sequentially in the third filling region 238 and the second trench 237 to form a capacitor 213.

[0253] Specifically, as shown in Figures 79 and 80, a first electrode material layer 260 is formed on the inner wall of the second trench 237, the inner wall of the third filling region 238, and the top of the stacked structure 222; as shown in Figure 81, the first electrode material layer 260 in the second trench 237 is removed, and the remaining first electrode material layer 260 in the third filling region 238 constitutes the first electrode 214; as shown in Figure 82, the third filling region 238 where the first electrode 214 is formed, the second trench 237, and the stacked structure 222 are all connected. A dielectric material layer 261 is formed on the top of the structure 222. A second electrode material layer 262 is formed on the top of the third filling region 238 where the first electrode 214 and the dielectric material layer 261 are formed, the second trench 237 and the stacked structure 222. The first electrode material layer 260, the dielectric material layer 261 and the second electrode material layer 262 on the top of the stacked structure 222 are removed. The remaining dielectric material layer 261 constitutes the dielectric layer 216 and the remaining second electrode material layer 262 constitutes the second electrode 215.

[0254] In some embodiments, the first plates 214 of capacitors 213 of different layers are arranged at intervals in the third direction (Z direction); the second plates 215 of the plurality of capacitors 213 arranged in the third direction (Z direction) are an integral structure. The second plates 215 fill the cavity formed by the dielectric layer 216. The second plates 215 can be a cavity structure or a solid structure.

[0255] In some embodiments, forming a plurality of transistors further includes: as shown in FIGS. 83 to 86, etching the first isolation structure 227 to form a third trench 240, the third trench 240 exposing a word line sacrificial layer (second sacrificial layer 230); and replacing the word line sacrificial layer (second sacrificial layer 230) with a gate structure 203 through the third trench 240. Etching the first isolation structure 227 to form the third trench 240 specifically includes: removing the first isolation structure 227 and a portion of the second isolation structure 236 in the second sub-stack structure 226 to form a plurality of third trenches 240 penetrating the second sub-stack structure 226 along a third direction; the third trenches 240 extend along a first direction, and the plurality of third trenches 240 are arranged along a second direction.

[0256] Specifically, a first mask layer is formed on top of the stacked structure 222. The material of the first mask layer includes, but is not limited to, silicon oxide. The first mask layer is patterned, and the first isolation structure 227 and part of the second isolation structure 236 are etched using the patterned first mask layer as a mask to form a plurality of third trenches 240, which expose word line sacrificial layers (second sacrificial layers 230).

[0257] In some embodiments, replacing the word line sacrificial layer (second sacrificial layer 230) with the gate structure 203 via the third trench 240 includes: as shown in FIG84, removing the remaining second sacrificial layer 230 (word line sacrificial layer) via the third trench 240 to form a fourth fill region 241. The fourth fill region 241 exposes a second portion 284-2 of the initial semiconductor body 284.

[0258] In some embodiments, replacing the word line sacrificial layer (second sacrificial layer 230) with the gate structure 203 via the third trench 240 further includes: as shown in FIG85, forming a gate dielectric material layer 264 on the inner wall of the third trench 240 and the inner wall of the fourth filling region 241; forming a first gate material layer 265 covering the gate dielectric material layer 264 on the inner wall of the third trench 240 and the inner wall of the fourth filling region 241; and forming a second gate material layer 266 covering the first gate material layer 265 on the inner wall of the third trench 240 and the inner wall of the fourth filling region 241.

[0259] In some embodiments, replacing the word line sacrificial layer (second sacrificial layer 230) with the gate structure 203 via the third trench 240 further includes: as shown in FIG86, removing the gate dielectric material layer 264, the first gate material layer 265, and the second gate material layer 266 at the top of the stacked structure 222; removing the gate dielectric material layer 264, the first gate material layer 265, and the second gate material layer 266 in the third trench 240, and the remaining gate dielectric material layer 264, the first gate material layer 265, and the second gate material layer 266 located in the fourth filling region 241 respectively constitute the gate dielectric layer 255, the first gate layer 253, and the second gate layer 254; the gate dielectric layer 255, the first gate layer 253, and the second gate layer 254 constitute the gate structure 203.

[0260] In some embodiments, forming a plurality of transistors includes, as shown in FIG87, filling an isolation material in a third trench 240 to form a third isolation structure 242.

[0261] In some examples, the material of the third isolation structure 242 includes, but is not limited to, silicon oxide.

[0262] In some embodiments, forming a plurality of transistors includes: as shown in FIG88 and FIG90, forming a plurality of second holes 285 through the stacked structure 222 and located in the bit line region, the second holes 285 exposing the initial semiconductor body 333 (specifically exposing the first portion 284-1 of the initial semiconductor body 333); and replacing the initial semiconductor body 333 with the semiconductor body 202 through the second holes 285.

[0263] As shown in Figure 88, the second isolation structure 236 is etched to form a second hole 285 that penetrates the second sub-stack structure 226 in a third direction; the second hole 285 exposes the first portion 284-1 of the initial semiconductor body 333.

[0264] As shown in Figure 89, the initial semiconductor body 284 is removed through the second hole 285 and the metal oxide semiconductor material layer 246 is filled through the second hole 285. As shown in Figure 89, the metal oxide semiconductor material layer 246 is also formed on top of the stacked structure 222.

[0265] In some embodiments, forming a plurality of bit lines includes: as shown in FIGS. 90 and 91, removing the metal oxide semiconductor material layer 246 within the second hole 285, the remaining metal oxide semiconductor material layer 246 constituting a semiconductor body 202 extending along a first direction; and filling the second hole 285 with a conductive material to form bit lines 205.

[0266] Specifically, filling the second hole 285 with conductive material to form bit lines 205 includes: forming a bit line material layer 267 in the second hole 285 and on top of the stacked structure 222; removing the bit line material layer 267 and the metal oxide semiconductor material layer 246 on top of the stacked structure 222, with the remaining bit line material layer 267 constituting a plurality of bit lines 205. The material of the bit line material layer 267 includes conductive material.

[0267] In this embodiment of the disclosure, the width of the bit line 205 in the second direction is the first width, and the width of the gate structure 203 between the first isolation structure 227 and the third isolation structure 242 in the first direction is the second width; the first width is greater than the second width.

[0268] In this embodiment of the disclosure, the use of metal oxide semiconductor materials and NO stacks reduces the difficulty of vertical stacking and increases the number and density of transistors in the vertical direction.

[0269] In some embodiments, forming a plurality of first word lines and second word lines includes: as shown in Figures 91 to 93, forming a plurality of first word line transverse slots and second word line transverse slots penetrating the stacked structure 222; etching a first sacrificial layer through the first word line transverse slots to form a first transverse groove, the first transverse groove exposing the gate structure; etching the first sacrificial layer through the second word line transverse slots to form a second transverse groove, the second transverse groove exposing the gate structure 203; forming a first word line 204 in the first transverse groove, and forming a second word line 206 in the second transverse groove. The plurality of first word lines 204 are stacked along a third direction, and the plurality of second word lines 206 are stacked along a third direction. The first word lines 204 extend along a first direction and are connected to the gate structure 203 of the transistor, and the second word lines 206 extend along the first direction and are connected to the gate structure 203 of the transistor; the third direction is perpendicular to both the first and second directions. The second word lines 206 are arranged along a second direction with the first word lines 204.

[0270] In some embodiments, forming a first row word line 204 and a second row word line 206 includes: as shown in FIG91, forming a first word line horizontal slot 286 and a second word line horizontal slot 287 that penetrate the stacked structure 222 along a third direction; the first word line horizontal slot 286 and the second word line horizontal slot 287 both extend from the first sub-stacked structure 225 to the second sub-stacked structure 226; the first word line horizontal slot 286 and the second word line horizontal slot 287 are respectively located on opposite sides of a plurality of transistors arranged along a second direction.

[0271] In this embodiment of the present disclosure, as shown in FIG91, a portion of a first sacrificial layer 224 exists between the first word line slot 286 and the third isolation structure 242 closest to the first word line slot 286, and a portion of a first sacrificial layer 224 also exists between the second word line slot 287 and the third isolation structure 242 closest to the second word line slot 287. The first word line slot 286 and the second word line slot 287 are respectively located in the regions of two opposite edges of the stacked structure 222 along the second direction. Both the first word line slot 286 and the second word line slot 287 expose the semiconductor layer 221.

[0272] In some embodiments, forming the first word line 204 and the second word line 206 further includes: as shown in FIG92, etching the first sacrificial layer 224 through the first word line horizontal slot 286 and the second word line horizontal slot 287 to form a first lateral groove 288 and a second lateral groove 289; both the first lateral groove 288 and the second lateral groove 289 expose the gate structure 203; both the first lateral groove 288 and the second lateral groove 289 extend along a first direction; and the first lateral groove 288 and the second lateral groove 289 are respectively located on opposite sides of a plurality of transistors arranged along a second direction.

[0273] In some examples, as shown in Figure 92, the method further includes removing the exposed first gate layer and the exposed gate dielectric layer to expose the second gate layer.

[0274] In some embodiments, forming the first line of text 204 and the second line of text 206 further includes: as shown in FIG93, forming the first line of text 204 in the first horizontal groove 288 and forming the second line of text 206 in the second horizontal groove 289.

[0275] In some embodiments, the method further includes filling the first character line groove 286 and the second character line groove 287 with an insulating material to form a character line isolation structure 252, as shown in FIG94.

[0276] Specifically, as shown in Figure 93, character line material layers 270 are formed in the first character line horizontal groove 286, the second character line horizontal groove 287, the first horizontal groove 288, the second horizontal groove 289, and the top of the stacked structure 222. After removing the character line material layers 270 in the first character line horizontal groove 286 and the second character line horizontal groove 287, the remaining character line material layers 270 in the first horizontal groove 288 constitute the first row of character lines 204, and the remaining character line material layers 270 in the second horizontal groove 289 constitute the second row of character lines 206. As shown in Figure 94, a character line isolation structure material layer 271 is formed in the first character line slot 286 and the second character line slot 287, as well as on top of the stacked structure 222. As shown in Figure 95, the character line isolation structure material layer 271 and the character line material layer 270 on top of the stacked structure 222 are removed, and the remaining character line isolation structure material layer 271 located in the first character line slot 286 and the second character line slot 287 constitutes the character line isolation structure 252. The material of the character line isolation structure material layer 271 includes an isolation material.

[0277] In some embodiments, the method further includes: as shown in Figures 95 and 96, forming a first line character line contact 207 coupled to a first line character line 204 and a second line character line contact 208 coupled to a second line character line 206; the first line character line contact 207 extends along a third direction, each of the plurality of first line character line contacts 207 is connected to different first line character lines 204 stacked along the third direction, and the plurality of first line character line contacts 207 are arranged in a row along a first direction; the second line character line contact 208 extends along a third direction, each of the plurality of second line character line contacts 208 is connected to different second line character lines 206 stacked along the third direction, and the plurality of second line character line contacts 208 are arranged in a row along the first direction.

[0278] It should be noted that, in order to more clearly illustrate the semiconductor device formation process, Figure 96 shows a three-dimensional structural diagram after removing some structures from Figure 97. In order to illustrate the second row word line contact 208 in Figure 97, part of the word line isolation structure 252 has been removed from Figure 97.

[0279] Specifically, as shown in Figures 96 and 97, forming a first line word line contact 207 coupled to the first line word line 204 and a second line word line contact 208 coupled to the second line word line 206 includes: forming a plurality of first contact holes 272 and a plurality of second contact holes 273; forming a first dielectric layer on the sidewalls and bottom walls of the first contact holes 272, the sidewalls and bottom walls of the second contact holes 273, and the top of the stacked structure 222; removing the first dielectric layer on the top of the stacked structure 222 and the first dielectric layer 275 on the bottom wall of the first contact holes 272. The first dielectric layer on the bottom wall of the second contact hole 273 exposes the first line of text 204 on the bottom wall of the first contact hole 272 and the second line of text 206 on the bottom wall of the second contact hole 273; a contact point material layer is formed in the first contact hole 272, the second contact hole 273 and the top of the stacked structure 222; the contact point material layer on the top of the stacked structure 222 is removed, the contact point material layer in the first contact hole 272 constitutes the second line of text contact 208, and the contact point material layer in the second contact hole 273 constitutes the third line of text contact 209.

[0280] As shown in Figures 96 and 97, the first row of character line contacts 207 are coupled to first row of character lines 204 of different layers, and the second row of character line contacts 208 are coupled to second row of character lines 206 of different layers. The number of first row of character line contacts 207 penetrated by different first row of character lines 204 varies. Similarly, the number of second row of character line contacts 208 penetrated by different second row of character lines 206 varies.

[0281] In this embodiment of the disclosure, the number of processes such as hole drilling, etching, and filling is reduced during the formation of the complex three-dimensional DRAM, resulting in a lower process difficulty.

[0282] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0283] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0284] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor device, the semiconductor device comprising: Multiple transistors; The transistor includes a semiconductor body extending along a first direction and a gate structure located on at least one side of the semiconductor body perpendicular to the first direction. The gate structures of the transistors arranged along the second direction in the plurality of transistors are interconnected; The first direction intersects with the second direction; Multiple first-line character lines; Multiple first row word lines are stacked along a third direction, the first row word lines extend along the first direction and are connected to the gate structure of the transistor; the third direction is perpendicular to both the first direction and the second direction; Multiple bit lines; The bit line extends along the third direction, and transistors arranged along the third direction among the plurality of transistors are connected to the same bit line, and two adjacent transistors along the first direction are connected to different bit lines; the bit line is located on one side of the first row word line on opposite sides along the second direction.

2. The semiconductor device according to claim 1, wherein, The semiconductor device also includes a plurality of second row word lines; Multiple second row word lines are stacked along the third direction, the second row word lines extend along the first direction and are connected to the gate structure of the transistor; the second row word lines and the first row word lines are arranged along the second direction.

3. The semiconductor device according to claim 2, wherein, The plurality of transistors are located between the first row word line and the second row word line.

4. The semiconductor device according to claim 1, wherein, The semiconductor device also includes a plurality of first row word line contacts; The first line contact extends along the third direction, and each of the plurality of first line contacts is connected to a different first line contact, and the plurality of first line contacts are arranged along the first direction.

5. The semiconductor device according to claim 4, wherein, The number of the first line contact is the same as the number of the first line stacked along the third direction.

6. The semiconductor device according to claim 4, wherein, The number of first line characters that different first line character contact points penetrate is different.

7. The semiconductor device according to claim 2, wherein, The semiconductor device further includes: Multiple second-line character line contacts; the second-line character line contacts extend along the third direction, each of the multiple second-line character line contacts is connected to a different first-line character line, and the multiple second-line character line contacts are arranged along the first direction; Multiple third-line character line contacts; the third-line character line contacts extend along the third direction, each of the multiple third-line character line contacts is connected to a different second-line character line, and the multiple third-line character line contacts are arranged along the first direction.

8. The semiconductor device according to claim 7, wherein, The number of contacts in the second line is less than the number of contacts in the first line stacked along the third direction, and the number of contacts in the third line is less than the number of contacts in the second line stacked along the third direction.

9. The semiconductor device according to claim 7, wherein, The number of first line characters penetrated by different second line character line contacts among the multiple second line character line contacts is different, the number of second line character lines penetrated by different third line character line contacts among the multiple third line character line contacts is different, and the number of first line character lines penetrated by the second line character line contacts is different from the number of second line character lines penetrated by the third line character line contacts.

10. The semiconductor device according to any one of claims 1 to 9, wherein, The different first line characters stacked along the third direction have equal lengths in the first direction, and the different first line characters stacked along the third direction have equal lengths in the second direction.

11. The semiconductor device according to claim 1, wherein, The semiconductor device further includes a first isolation structure, a second isolation structure, and a third isolation structure; the first isolation structure, the second isolation structure, and the third isolation structure are all located between the semiconductor bodies of two adjacent transistors along the second direction, the first isolation structure and the third isolation structure are respectively located on opposite sides of the gate structure along the first direction, and the second isolation structure is located between the semiconductor body and the third isolation structure; The width of the bit line in the second direction is a first width, and the width of the gate structure between the first isolation structure and the third isolation structure in the first direction is a second width; the first width is greater than the second width.

12. The semiconductor device according to claim 1, wherein, The semiconductor device further includes a plurality of capacitors; the capacitors include a first plate, a second plate, and a dielectric layer located between the first plate and the second plate. One end of the semiconductor body at opposite ends along the first direction is connected to the first plate of the capacitor, and the other end of the semiconductor body at opposite ends along the first direction is connected to the bit line.

13. The semiconductor device according to claim 12, wherein, In a plurality of transistors arranged along the first direction, the first transistor and the second transistor are arranged alternately along the first direction; adjacent first transistors and second transistors along the first direction constitute a transistor group. One end of the semiconductor body of the first transistor, located away from the second transistor in the same transistor group, is connected to a bit line at one of its two opposite ends along the first direction; the other end of the semiconductor body of the second transistor, located away from the first transistor in the same transistor group, is connected to a bit line at one of its two opposite ends along the first direction; the other end of the semiconductor body of the first transistor, located closer to the second transistor in the same transistor group, is connected to a capacitor at one of its two opposite ends along the first direction; and the other end of the semiconductor body of the second transistor, located closer to the first transistor in the same transistor group, is connected to a capacitor at one of its two opposite ends along the first direction.

14. The semiconductor device according to claim 13, wherein, The second plate of the capacitor to which the first transistor is connected is connected to the second plate of the capacitor to which the second transistor is connected within the same transistor group. The second plates of the capacitors to which multiple first transistors are arranged along the second direction are connected. The second plates of the capacitors to which multiple second transistors are arranged along the second direction are connected. The second plates of the capacitors to which multiple first transistors are arranged along the third direction are connected. The second plates of the capacitors to which multiple second transistors are arranged along the third direction are connected.

15. The semiconductor device according to claim 1, wherein, The gate structure of the transistor is located on two opposite sides of the semiconductor body of the transistor along the second direction and on two opposite sides of the semiconductor body along the third direction.

16. The semiconductor device according to claim 1, wherein, The semiconductor body is made of metal oxide semiconductor.

17. The semiconductor device according to claim 1, wherein, The semiconductor body includes a first semiconductor portion, a second semiconductor portion, and a third semiconductor portion arranged along the first direction; the second semiconductor portion is located between the first semiconductor portion and the third semiconductor portion; the dimension of the second semiconductor portion along the second direction is greater than the dimension of the first semiconductor portion along the second direction, and the dimension of the second semiconductor portion along the second direction is greater than the dimension of the third semiconductor portion along the second direction.

18. A memory system comprising: The semiconductor device as described in any one of claims 1 to 17; as well as Memory controller; The memory controller is coupled to the semiconductor device and configured to control the semiconductor device.

19. A method for fabricating a semiconductor device, the method comprising: Multiple transistors are formed; The transistor includes a semiconductor body extending along a first direction and a gate structure located on at least one side of the semiconductor body perpendicular to the first direction. The gate structures of the transistors arranged along the second direction in the plurality of transistors are interconnected; the first direction intersects the second direction; Multiple first-line character lines are formed; Multiple first row word lines are stacked along a third direction, the first row word lines extend along the first direction and are connected to the gate structure of the transistor; the third direction is perpendicular to both the first direction and the second direction; Multiple bit lines are formed; The bit line extends along the third direction, and transistors arranged along the third direction among the plurality of transistors are connected to the same bit line, and two adjacent transistors along the first direction are connected to different bit lines; the bit line is located on one side of the first row word line on opposite sides along the second direction.

20. The manufacturing method according to claim 19, wherein, The manufacturing method further includes: Multiple second row word lines are formed; the multiple second row word lines are stacked along the third direction, the second row word lines extend along the first direction and are connected to the gate structure of the transistor; the second row word lines and the first row word lines are arranged along the second direction.

21. The manufacturing method according to claim 20, wherein, The formation of multiple transistors includes: A substrate is provided, the substrate including a semiconductor layer and a stacked structure formed on the semiconductor layer, the stacked structure including a first insulating layer and a first sacrificial layer alternately disposed along the third direction; the stacked structure includes a first sub-stacked structure and a second sub-stacked structure alternately arranged along the first direction; A plurality of first isolation structures are formed that penetrate the first sub-stack structure along the third direction and a plurality of first isolation structures that penetrate the second sub-stack structure along the third direction; the plurality of first isolation structures in the first sub-stack structure and the plurality of first isolation structures in the second sub-stack structure are arranged along the second direction, and the first isolation structures extend along the first direction.

22. The manufacturing method according to claim 21, wherein, The distance between the first sub-stack structure and the first isolation structure in the second sub-stack structure that are adjacent along the first direction is the first distance, and the distance between the first isolation structures that are adjacent along the second direction is the second distance; the second distance is greater than the first distance.

23. The manufacturing method according to claim 21, wherein, The formation of multiple transistors includes: A first trench is formed in the second sub-stack structure, penetrating the second sub-stack structure and the first isolation structure along the third direction; the first trench is arranged along the first direction and extends along the second direction, and is located between two first isolation structures arranged along the second direction; A portion of the first sacrificial layer is removed through the first trench to form a first filling region; A second sacrificial layer is formed on the inner wall of the first filling region; An initial semiconductor body is formed in the first filling region where the second sacrificial layer is formed; the initial semiconductor body includes a first portion, a second portion, and a third portion arranged along the first direction; A portion of the second sacrificial layer is removed through the first trench to form a second filling region; the second filling region exposes the first portion. A second isolation structure is formed in the second filling area and the first trench.

24. The manufacturing method according to claim 23, wherein, The method further includes: A second trench is formed in the first sub-stack structure, extending along the third direction through the first sub-stack structure and the first isolation structure; the second trench extends along the second direction and is located between two first isolation structures arranged along the second direction; A third filling region is formed by removing a portion of the first sacrificial layer and a portion of the second sacrificial layer through the second trench; the third filling region exposes the third portion. Capacitors are formed in the third filled region and in the second trench.

25. The manufacturing method according to claim 24, wherein, The method further includes: Before forming capacitors in the third filling region and the second trench, a first insulating layer is formed on the inner wall of the third filling region and the inner wall of the second trench; The first isolation layer on the inner wall of the second trench and a portion of the first isolation layer on the inner wall of the third filling region are removed to expose the initial semiconductor body; the remaining first isolation layer in the third filling region is located at least between the capacitor and the second sacrificial layer.

26. The manufacturing method according to claim 24, wherein, The process of forming multiple transistors also includes: Remove the first isolation structure and part of the second isolation structure from the second sub-stack structure to form a plurality of third trenches that penetrate the second sub-stack structure along the third direction; the plurality of third trenches are arranged along the second direction and all extend along the first direction. The remaining second sacrificial layer is removed through the third trench to form a fourth filling region; The gate structure is formed in the fourth filling region.

27. The manufacturing method according to claim 26, wherein, The formation of multiple transistors and multiple bit lines includes: A third isolation structure is formed in the third trench; A portion of the second isolation structure and a portion of the third isolation structure are removed to form a fourth trench penetrating the second sub-stack structure along the third direction; the fourth trench exposes the initial semiconductor body and is located between two of the third isolation structures arranged along the second direction; A portion of the second isolation structure is removed through the fourth trench to form a fifth filling region; The initial semiconductor body is removed to form a sixth filling region; A metal oxide semiconductor material layer is filled in the fifth filling region and the sixth filling region; A portion of the metal oxide semiconductor material layer is removed to form a plurality of fifth trenches extending along the third direction, and the remaining metal oxide semiconductor material layer constitutes a semiconductor body extending along the first direction. The bit line is formed in the fifth trench.

28. The manufacturing method according to claim 27, wherein, The formation of the first line of text and the second line of text includes: A sixth trench and a seventh trench are formed along the third direction through the stacked structure; the sixth trench and the seventh trench both extend from the first sub-stacked structure into the second sub-stacked structure; the sixth trench and the seventh trench are respectively located on opposite sides of a plurality of transistors arranged along the second direction; The remaining first sacrificial layer is removed through the sixth trench and the seventh trench to form a seventh filling region and an eighth filling region; both the seventh filling region and the eighth filling region expose the gate structure; both the seventh filling region and the eighth filling region extend along the first direction; and the seventh filling region and the eighth filling region are respectively located on opposite sides of a plurality of transistors arranged along the second direction. The first line of text is formed in the seventh filling region, and the second line of text is formed in the eighth filling region.

29. The manufacturing method according to claim 28, wherein, The method further includes: Word line isolation structures are formed in the sixth and seventh trenches.

30. The manufacturing method according to claim 28, wherein, The method further includes: Multiple second-row character line contacts are formed; the second-row character line contacts extend along the third direction, each of the multiple second-row character line contacts is connected to different first-row character lines stacked along the third direction, and the multiple second-row character line contacts are arranged along the first direction; Multiple third-line character line contacts are formed; the third-line character line contacts extend along the third direction, each of the multiple third-line character line contacts is connected to different second-line character lines stacked along the third direction, and the multiple third-line character line contacts are arranged along the first direction.

Images