Logical function computation device, logical function conversion device, and logical function computation method

Abstract

The present invention realizes a logical function representation that achieves both a high compression ratio and high computational power. Let ASC be a logical function expressed by: labeling each leaf node in a rooted directed acyclic graph with one of 1, 0, xi, and ￢xi; labeling each non-leaf node with + or ∧; setting the number of children for each ∧ node to 2; setting the number of children for each + node to an arbitrary number; and assigning the sign –1 or 1 to the edge between each + node and each child node for the + node. Define a logical function fv corresponding to a node v of ASC recursively, and when the logical function for an arbitrary node of ASC is Boolean, let st-DASC be an ASC logical function expressed by decomposition according to an arbitrary binary tree. A logical function computation device according to the present disclosure includes an input unit that receives input of a logical expression, and a computation unit that performs an operation on st-DASC when the received logical expression is st-DASC.

Description

Logical function arithmetic unit, logical function conversion unit, and logical function arithmetic method

[0001] This disclosure relates to logical functions and their arithmetic techniques.

[0002] Logical functions and their operations are applied to real-world problems such as network reliability. Since the number of input types for a logical function increases exponentially with the number of input variables, naively maintaining input-output relationships results in an enormous size, and consequently, the calculations require a great deal of time.

[0003] SDD (Sentential Decision Diagram) is a well-known technique for representing logical functions in a compressed form and performing calculations on them while they remain compressed (see, for example, Non-Patent Document 1). SDD is a data structure that represents logical functions using a Directed Acyclic Graph (DAG), and supports various logical operations, including model counting. Due to its high compression ratio and computational power, SDD has been applied to a variety of real-world problems.

[0004] Another known technique is structured d-DNNF (structured decomposable Deterministic Negation Normal Form) (see, for example, Non-Patent Document 2). Structured d-DNNF offers superior compression ratios compared to SDD, but it supports fewer operations.

[0005] Darwiche, Adnan. "SDD: A new canonical representation of propositional knowledge bases." Twenty-Second International Joint Conference on Artificial Intelligence. 2011. Pipatsrisawat, Knot, and Adnan Darwiche. "New Compilation Languages ​​Based on Structured Decomposability." AAAI. Vol. 8. 2008.

[0006] The representation of logical functions inherently involves a trade-off between its compression ratio and the number of operations it supports. That is, while there are techniques to compress logical functions and perform operations within that compressed state, traditional representations of logical functions cannot simultaneously achieve high compression ratios and high computational power (supporting a large number of operations). This has resulted in the inability to flexibly solve large-scale real-world problems.

[0007] This disclosure aims to provide a technology that realizes logical function representation that achieves both high compression ratio and computational power.

[0008] One aspect of this disclosure is a logical function arithmetic unit in which i is an arbitrary integer and x is an arbitrary variable, and each leaf node in a rooted directed acyclic graph is assigned 1, 0, x ｉ ,￢x ｉ Let ASC be a logical function expressed by assigning one of the following labels to each node, assigning either + or ∧ to each non-leaf node, setting the number of children of ∧ nodes to 2, the number of children of + nodes to be arbitrary, and assigning either -1 or 1 to the edges between each + node and its child nodes. Then, let f be the logical function corresponding to node v of ASC. v The logical function of ASC is defined recursively, and when the logical function for any node of ASC is Boolean, the logical function of ASC expressed according to an arbitrary binary tree is defined as st-DASC. The logical function arithmetic unit has an input unit that accepts logical expressions as input, and an arithmetic unit that performs operations on st-DASC when the accepted logical expression is st-DASC.

[0009] The technology disclosed herein enables the realization of logical function representations that achieve both high compression ratio and computational power.

[0010] Figure 1 is a diagram illustrating directed acyclic graphs of ASC and st-DASC. Figure 2 is a diagram illustrating vtree. Figure 3 is a diagram illustrating a non-structured decomposable ASC. Figure 4 is a diagram illustrating an example of the functional configuration of the logic function arithmetic unit according to this embodiment. Figure 5 is a diagram illustrating an example of the processing flow of the logic function arithmetic unit according to this embodiment. Figure 6 is a diagram illustrating an example of the functional configuration of the arithmetic unit according to this embodiment. Figure 7 is a diagram illustrating an example of the processing flow of logical AND according to this embodiment. Figure 8 is a diagram illustrating an example of the logical AND algorithm according to this embodiment. Figure 9 is a diagram illustrating logical negation. Figure 10 is a diagram showing operations supported in polynomial time. Figure 11 is a diagram illustrating an example of the functional configuration of the logic function arithmetic unit according to a modified example of this embodiment. Figure 12 is a diagram illustrating an example of the processing flow of the logic function arithmetic unit according to a modified example of this embodiment. Figure 13 is a diagram illustrating an example of the functional configuration of the logic function converter. Figure 14 is a diagram illustrating an example of the functional configuration of a computer.

[0011] The embodiments of this disclosure will be described in detail below. Components having the same function will be numbered the same, and redundant explanations will be omitted.

[0012] <ASC, st-DASC> The logic function arithmetic unit 1 of this disclosure uses ASC (And-Sum Circuit) and st-DASC (structured Decomposable And-Sum Circuit). Therefore, ASC and st-DASC will be described below.

[0013] (ASC: And-Sum Circuit) ASC is a fundamental concept for st-DASC, a logical function representation. An ASC is a rooted directed acyclic graph represented by (R1) to (R5) below.

[0014] (R1): Let i be any integer and x be any variable. (R2): Each leaf node has 1, 0, x ｉ ,￢x ｉAttach any one of the labels. (R3): Attach either a + or ∧ label to each non-leaf node. (R4): Set the number of children of an ∧ node to 2 and the number of children of a + node to be arbitrary. (R5): Attach either a -1 or 1 sign to the edge between each + node and its child nodes.

[0015] The logical function represented by ASC is defined by the following (R6) to (R11).

[0016] (R6): The function f corresponding to the node v of ASC v is recursively defined as shown in the following (R7) to (R9).

[0017] (R7): When v is a leaf node, f v is equal to its label.

[0018] (R8): When v is an ∧ node with children {c1, c2}, f v is a function that satisfies the following equation for any input a.

[0019] (R9): When v has children {c1,..., c k} and its signs are {w1,..., w k}, f v is a function that satisfies the following equation for any input a.

[0020] (R10): The function corresponding to ASC is taken as the function corresponding to its root.

[0021] (R11): Assume that ASC is Boolean.

[0022] Here, an explanation about Boolean is given. When all components of a are 0 or 1 and f v (a) is also 0 or 1, "f vIt is said that "it is Boolean." "ASC is Boolean" means the case where the function corresponding to any node is Boolean. Hereinafter, unless otherwise specified, ASC is assumed to be Boolean. FIG. 1 is a diagram for explaining the directed acyclic graph of ASC and st-DASC. FIG. 1 is an ASC representing the function x ∧ y ∧ z + ¬x ∧ ¬y ∧ ¬z. Each node shows the corresponding function. Since all of these functions are Boolean, this ASC is Boolean.

[0023] (st-DASC: structured Decomposable And-Sum Circuit) st-DASC is an ASC to which the following requirement (R12) is added in addition to the above (R1) to (R11).

[0024] (R12): Assume that ASC is structured decomposable.

[0025] That is, assume that the decomposition of ASC follows a predetermined binary tree. FIG. 2 is a diagram for explaining the vtree. "vtree" means a binary tree as shown in FIG. 2, and each leaf node corresponds to a variable. For the node v of st-DASC, its scope Var(v) is defined as the set of variables that appear in the subgraph rooted at v. The scope Var(s) is similarly defined for the node s of the vtree. "ASC is decomposable" means that the left and right children c L , c R of any ∧ node v do not share variables, that is, the following equation holds. "A decomposable st-DASC is structured decomposable" means that there exists a vtree, and for any ∧ node v on the st-DASC and its child nodes c L , c R and for a certain node s on the vtree and its child nodes γ L , γ R exist and satisfy both of the following two equations. In this case, s is called the decomposition node of v and is expressed by the following equation.

[0026] Figure 3 is a diagram for explaining an ASC that is not structured decomposable. For example, since the left and right subtrees in FIG. 1 both follow the variable order according to the binary tree (vtree) in FIG. 2, this ASC is structured decomposable. On the other hand, in FIG. 3, the variable order is not unified in the left and right subtrees, so it is not structured decomposable. In the present disclosure, a structured decomposable ASC is denoted as st-DASC.

[0027] Summarizing the above (R1)-(R12), st-DASC has both of the following (1) and (2). (1) Let i be an arbitrary integer and x be an arbitrary variable. Each leaf node in the rooted directed acyclic graph is labeled with one of 1, 0, x ｉ , ¬x ｉ , and each non-leaf node is labeled with either + or ∧. The number of children of the ∧ node is 2, and the number of children of the + node is arbitrary. The logical function expressed by attaching either -1 or 1 to the edge between each + node and the child node of the + node is defined as ASC. (2) The logical function f v corresponding to the node v of the ASC is defined recursively. When the logical function for any node of the ASC is Boolean, the logical function of the ASC expressed according to an arbitrary binary tree is defined as st-DASC.

[0028] <First Embodiment> Figure 4 is a diagram showing an example of the functional configuration of the logic function arithmetic unit according to this embodiment. Figure 5 is a diagram showing an example of the processing flow of the logic function arithmetic unit according to this embodiment. The logic function arithmetic unit 1 of this embodiment has an input unit 10, an arithmetic unit 30, and an output unit 40, as shown in Figure 4. The logic function arithmetic unit 1 receives graph definition information from the definition database X. The definition database X has the definition condition information of (1) and (2) described above. The logic function arithmetic unit 1 receives the definition condition of (1) and (2) described above from the definition database X and performs calculations according to the definition of (1) and (2) described above. In this example, the definition database X is provided outside the logic function arithmetic unit 1, but the definition database X may also be provided inside the logic function arithmetic unit 1. The logic function arithmetic unit 1 follows the graph creation rules of st-DASC described above of (1) and (2) received from the definition database X. In this example, the logic function arithmetic unit 1 receives input of a logic function expressed in st-DASC from the user, performs calculations on st-DASC, and outputs the result.

[0029] A logical expression consisting only of logical AND operations is called a "term," and a logical expression consisting only of logical OR operations is called a "clause." The logic function arithmetic unit 1 can efficiently perform the following operations in st-DASC f,g, term t, and clause γ.

[0030] In other words, the efficiently possible operations are CO (whether f has a model), VA (whether f is 1 for all inputs), CE (whether the model set of f contains the model set of γ), EQ (whether f and g are equal), SE (whether the model set of f contains the model set of g), IM (whether the model set of t contains the model set of f), CT (model count of f), ME (enumeration of models of f), ∧BC (logical AND of f and g), ∨BC (logical OR of f and g), ¬C (logical negation of f), CD (conditioning of t for f), and SFO (forgetting of x for f).

[0031] The logic function arithmetic unit 1 performs the logic function arithmetic method of this embodiment by implementing the processing flow illustrated in Figure 5. Hereinafter, with reference to Figure 5, an example of the processing flow of the logic function arithmetic method in the logic function arithmetic unit 1 will be described in order of procedure.

[0032] (Input Unit 10) The input unit 10 receives a logical expression from the user (step S10). The received logical expression is sent to the calculation unit 30.

[0033] (Calculation Unit 30) If the received logical expression is st-DASC, the calculation unit 30 performs calculations on st-DASC (step S30). The calculation result is sent to the output unit 40. If the received logical expression is not st-DASC, the logic function calculation device 1 may be configured to terminate processing.

[0034] (Output Unit 40) The output unit 40 outputs the received calculation result as the output result (calculation result) for the input to the logical function arithmetic unit 1 (step S40).

[0035] (Calculations performed by the calculation unit 30) Figure 6 is a diagram showing an example of the functional configuration of the calculation unit according to this embodiment. The calculation unit 30 includes a ∧BC calculation unit 301, a CT calculation unit 302, a ¬C calculation unit 303, a CD calculation unit 304, a CO calculation unit 305, a VA calculation unit 306, a SE calculation unit 307, an EQ calculation unit 308, a CE calculation unit 309, an IM calculation unit 310, a ME calculation unit 311, a ∨BC calculation unit 312, and an SFO calculation unit 313. As will be described later, many calculations can be performed by combinations of ∧BC, CT, ¬C, and CD. Therefore, it is also possible to configure the calculation unit 30 itself to control the ∧BC calculation unit 301 to the CD calculation unit 304, thereby effectively performing the functions of the CO calculation unit 305 to the SFO calculation unit 313, without providing the CO calculation unit 305 to the SFO calculation unit 313.

[0036] [∧BC Calculation Unit 301] The ∧BC calculation unit 301 calculates ∧BC. ∧BC is an operation that calculates the logical AND of two input logical functions. ∧BC can be implemented on st-DASC by the processing flow shown in Figure 7, for example. CON(u,v) shown in Figure 8 is f u ∧f vThis shows an example of a recursive algorithm that outputs the corresponding st-DASC. The processing details of the ∧BC calculation unit 301 will be explained below with reference to Figures 7 and 8.

[0037] The ∧BC calculation unit 301 determines whether at least one of the following conditions (i) or (ii) is met (step S301a): (i) d(u) = d(v), and u is a + node, and v is an ∧ node. (ii) d(v) is a higher-level node than d(u) (d(v) is an ancestor of d(u)).

[0038] If at least one of the above conditions (i) or (ii) is met (step S301a, Yes), the ∧BC arithmetic unit 301 performs the process in step S301c after swapping u and v (step S301b).

[0039] If the output result for u and v is stored in the cache (not shown) of the logical function arithmetic unit 1 (step S301c, Yes), the ∧BC arithmetic unit 301 outputs the value of the stored content (step S301d, lines 1-2 of Figure 8), and the processing of the ∧BC arithmetic unit 301 ends.

[0040] The ∧BC calculation unit 301 outputs one of the trivial values, 0, u, or v (step S301f, lines 3-8 in Figure 8) if the output results for u and v are not stored in the cache of the logical function calculation unit 1 (step S301c, No), and one of u or v is a 01 node (step S301e, Yes). Then the processing of the ∧BC calculation unit 301 ends. That is, if u or v is a 0 node, 0 is output. If u is a 1 node, v is output. If v is a 1 node, u is output.

[0041] The ∧BC calculation unit 301 calculates the decomposition nodes s and t for u and v respectively, and the minimum common ancestor anc of s and t, when one of u and v is not a 01 node, i.e., when neither u nor v is a 01 node (step S301e, No). (step S301g, lines 10-12 of Figure 8).

[0042] The ∧BC calculation unit 301, if anc is neither s nor t (step S301h, Yes), connects u and v with an ∧ node and returns them because u and v do not share a variable (step S301i, lines 13-14 in Figure 8). After that, it performs the processing in step S301p, which will be described later.

[0043] The ∧BC calculation unit 301, when anc is either s or t (step S301h, No), and both u and v are leaf nodes (step S301j, Yes), returns the value of the label if the labels of u and v are the same, or 0 if they are different (step S301k, lines 15-19 in Figure 8). After that, it performs the processing in step S301p, which will be described later.

[0044] The ∧BC calculation unit 301, when one of u and v is a leaf node, or both are non-leaf nodes (step S301j, No), and one of u and v is a + node (step S301l, Yes), decomposes the function into the sum of its child nodes and returns it connected by + nodes (step S301m, lines 20-21 of Figure 8). After that, it performs the processing in step S301p, which will be described later.

[0045] The ∧BC calculation unit 301, when neither u nor v is a + node (step S301l, No), and both u and v are ∧ nodes (step S301n, Yes), decomposes them into logical AND operations of their left and right child nodes and connects them back together with ∧ nodes (step S301o, lines 22-23 in Figure 8). After that, it performs the processing in step S301p, which will be described later.

[0046] The ∧BC calculation unit 301, when either u or v is an ∧ node, or when both u and v are non-∧ nodes (step S301n, No), returns anc to be the decomposition node of the return value, saves the return value to the cache of the logical function calculation unit 1, outputs the calculation result (return value) as the logical function calculation unit 1 (step S301p, lines 24-26 in Figure 8), and terminates the processing of the ∧BC calculation unit 301.

[0047] [CT Calculation Unit 302] The CT calculation unit 302 calculates the CT. CT is an operation that counts the number of models of the input logical function, and on st-DASC, it can be implemented, for example, as in the following steps S302a to 302g.

[0048] Let CT(f) represent the number of models of the logical function f. For any node v in st-DASC, CT(f v We consider recursively calculating (step S302a).

[0049] If v is a 0 node, CT(f v ) = 0 (step S302b).

[0050] If v is a literal node, CT(f v ) = 2^(n-1) (step S302c).

[0051] If v is a single node, CT(f v ) = 2^n. In this case, f v It is always treated as a function of n variables. (Step S302d).

[0052] If v is a + node, its child nodes are c1, ..., c k , weights w1, ..., w k The following equation holds (step S302e).

[0053] If v is an inverted node, then its child nodes are c L ,c R , the sign is w L ,w R The following equation holds (step S302f).

[0054] By calculating the values ​​in steps S302a to S302f in a bottom-up manner, the value CT(f) corresponding to the root r is obtained. r Calculate the value CT(f r This is the desired output.

[0055] [¬C Calculation Unit 303] The ¬C calculation unit 303 calculates ¬C. ¬C is an operation that outputs the logical negation of a logical function f. The function ¬C can be implemented on st-DASC, for example, in the following steps S303a to 303b. Figure 9 is a diagram to illustrate logical negation. An example of the processing of the ¬C calculation unit 303 will be described below with reference to Figure 9.

[0056] The ¬C calculation unit 303 prepares a + node (step S303a).

[0057] The ¬C operation unit 303 makes one of the children into one node and one signed edge (step S303b).

[0058] The ¬C operation unit 303 sets the other child to the input logic function f and a -1 signed edge (step S303c).

[0059] The graph created by steps S303a to S303c above is st-DASC, which represents ¬f.

[0060] [CD Calculation Unit 304] The CD calculation unit 304 calculates CD. CD is a conditional operation. For a logical function f and a term t, the condition f|t of f is a function obtained by substituting x=1 into f if x is included in t, and x=0 into f if ¬x is included in t. CD can be implemented on st-DASC by replacing leaf nodes, for example, as shown in the following steps S304a to 304b.

[0061] The CD calculation unit 304 replaces leaf nodes labeled x with 1 node and leaf nodes labeled ¬x with 0 nodes if x is included in t (step S304a).

[0062] Similarly, if ¬x is included in t, replace the leaf node labeled x with node 0 and the leaf node labeled ¬x with node 1 (step S304b).

[0063] The st-DASC obtained in steps S304a to S304b described above is the desired output.

[0064] [CO Calculation Unit 305] The CO calculation unit 305 calculates CO. CO is an operation that determines whether the input logical function f has a model. The CO calculation unit 305 calculates CO by having the CT calculation unit 302 determine whether CT(f) >= 1.

[0065] [VA Calculation Unit 306] The VA calculation unit 306 calculates VA. VA is an operation that determines whether the input logical function f is a tautology. The VA calculation unit 306 calculates VA by having the CT calculation unit 302 determine whether CT(f) = 2^n.

[0066] [SE Calculation Unit 307] For logical functions f and g, the fact that the model set of f encompasses the model set of g is expressed as follows: The SE calculation unit 307 calculates SE. SE is an operation that determines whether the input logical functions f and g satisfy the above equation (9). The SE calculation unit 307 calculates SE by having the ∧BC calculation unit 301 and the CT calculation unit 302 determine whether CT(f∧g) = CT(g) holds true.

[0067] [EQ Calculation Unit 308] The EQ calculation unit 308 calculates EQ. EQ is an operation that determines whether the input logical functions f and g are equal. The EQ calculation unit 308 calculates EQ by having the ∧BC calculation unit 301 and the CT calculation unit 302 determine whether CT(f∧g)=CT(f)=CT(g).

[0068] [CE Calculation Unit 309] The CE calculation unit 309 calculates CE. CE is an operation that determines whether the set of models of f encompasses the set of models of γ, given an input logical function f and clause γ. CE is the same operation as SE except that the input form is different. Therefore, the CE calculation unit 309 calculates CE by performing a combined operation of ∧BC by the ∧BC calculation unit 301 and CT by the CT calculation unit 302.

[0069] [IM Calculation Unit 310] The IM calculation unit 310 calculates the IM. The IM is an operation that determines whether the model set of t encompasses the model set of f, given an input logical function f and term t. The IM is the same operation as SE except that the input form is different. As previously described, term and clause can be expressed by st-DASC. Therefore, the IM calculation unit 310 calculates the IM by performing a combined operation of ∧BC by the ∧BC calculation unit 301 and CT by the CT calculation unit 302.

[0070] [ME Calculation Unit 311] The ME calculation unit 311 calculates ME. ME is an operation that enumerates the models of the input logical function f. The ME calculation unit 311 can calculate ME by using CD and CO on st-DASC to create a trie corresponding to the set of models, for example, as in the following steps S311a to 311d.

[0071] The ME calculation unit 311 causes the CO calculation unit 305 to perform CO, creating the root r of the trie if a model exists, and outputting an empty set if no model exists (step S311a).

[0072] The ME calculation unit 311 causes the CO calculation unit 305 to perform CO on the function obtained by conditional x1 from f, and if a model exists, it creates node x1 on the trie and connects it to r (step S311b).

[0073] The ME calculation unit 311 similarly causes the CO calculation unit 305 to perform CO on the function obtained by conditional ¬x1 from f, and if a model exists, it creates a node ¬x1 on the trie and connects it to r (step S311c).

[0074] Perform the same operations as in steps S311a to S311c x2, ..., x n This is also done recursively (step S311d). The trie tree finally obtained as a result of steps S311a to S311d corresponds to the desired set of models.

[0075] [∨BC Calculation Unit 312] The ∨BC calculation unit 312 calculates ∨BC. ∨BC is an operation that takes the logical OR of the input logical functions f and g. Since f∨g = ¬(f∧g), the ∨BC calculation unit 312 calculates ∨BC by performing a combined operation of ¬C by the ¬C calculation unit 303 and ∧BC by the ∧BC calculation unit 301.

[0076] [SFO calculation unit 313] The SFO calculation unit 313 calculates SFO. SFO is an operation that performs forgetting of the input logical function f with respect to the variable x. For a logical function f and a set of variables X, the forgetting of f with respect to X ∃Xf means that for any x, the following equation is satisfied.

[0077] Furthermore, for any logical function g that does not contain the variable X, it is a logical function that satisfies the following equation.

[0078] Here, since ∃Xf=(A|x)∨(A|¬x), the SFO calculation unit 313 calculates SFO by combining the ¬C calculated by the ¬C calculation unit 303, the CD calculated by the CD calculation unit 304, and the ∨BC calculated by the ∨BC calculation unit 312.

[0079] The configuration and processing of the logical function arithmetic unit 1 have been explained above. In terms of compression ratio, st-DASC surpasses both SDD and structured d-DNNF. Specifically, any logical function that can be represented with size S in SDD or structured d-DNNF can always be represented with size S or less in st-DASC. On the other hand, there exists a logical function f that can be represented with size S in st-DASC, but whose size cannot be expressed as a polynomial in S when represented in SDD or structured d-DNNF.

[0080] Figure 10 shows the operations supported in polynomial time. As shown in Figure 10, in terms of the types of operations supported, st-DASC is comparable to SDD, which has high computational power. Structured d-DNNF does not support logical negation (¬C), but st-DASC can implement logical negation. Therefore, it supports more operations than structured d-DNNF in that it supports logical negation and other operations that can be reduced to logical negation (∨BC, SFO, etc.). In addition, when logical negation is taken in structured d-DNNF, there are functions whose representation size increases by more than a polynomial factor. On the other hand, since st-DASC supports logical negation, such functions can be represented in polynomial size. In other words, logical negation plays an important role in both computational power and compression ratio. Therefore, the logic function arithmetic device 1 of this disclosure can realize a logic function representation that achieves both high compression ratio and computational power.

[0081] <Modification> The logic function arithmetic unit 1 described above may be configured as the logic function arithmetic unit 1B shown below. Figure 11 is a diagram showing an example of the functional configuration of the logic function arithmetic unit according to a modification of this embodiment. In the logic function arithmetic unit 1B, the input unit 10 of the logic function arithmetic unit 1 is replaced with the input unit 10B. The logic function arithmetic unit 1B has a function calculation unit 20 added to the logic function arithmetic unit 1. The logic function arithmetic unit 1B performs the logic function arithmetic method of this embodiment by implementing the processing flow illustrated in Figure 12. The processing of the input unit 10B and the function calculation unit 20 will be described below with reference to Figure 12.

[0082] (Input Unit 10B) The input unit 10B of the logic function arithmetic unit 1B accepts a logical expression input from the user (step S10B-1).

[0083] The input unit 10B determines whether the received logical expression is a logical expression in st-DASC representation (step S10-2). If the received logical expression is a logical expression in st-DASC representation (step S10-2, Yes), it is sent to the calculation unit 30. If the received logical expression is not a logical expression in st-DASC representation (step S10-2, No), it is sent to the conversion unit 20.

[0084] (Conversion Unit 20) The conversion unit 20 converts the non-st-DASC logical expression received by the input unit 10B into st-DASC (step S20). The converted st-DASC logical expression is sent to the arithmetic unit 30.

[0085] As previously mentioned, st-DASC supports ∧BC (logical AND), ∨BC (logical OR), and ¬C (logical negation). Therefore, if the input is a more general logical expression (an expression expressed as a combination of ∧ (AND), ∨ (OR), ¬ (NOT) and a variable), st-DASC representing the input logical expression can be constructed by repeatedly applying ∧BC (logical AND), ∨BC (logical OR), and ¬C (logical negation). In particular, if the input is a Conjunctive Normal Form (CNF) in which several conditional units are ultimately joined by AND, it can be constructed more simply as follows: (1) A Term is a single variable or its negation connected by ∧, a Clause is a single variable or its negation connected by ∨, and a CNF is several clauses connected by ∧. (2) A Term can be converted to st-DASC as described below. Furthermore, the clause can be constructed as described below.

[0086] That is, for any vtree and term t, the st-DASC corresponding to t can be constructed as follows. First, for any leaf node x of the vtree, replace x with an x ​​node if x is included in t, with a ¬x node if ¬x is included in t, and with a 1 node otherwise. Next, replace any non-leaf nodes of the vtree with ∧ nodes. Finally, reduce any redundant edges. That is, remove any ∧ nodes where one child is a 1 node, and directly connect the other child to the parent. Also, since any classuse is the negation of a term, the st-DASC corresponding to classuse γ can be constructed in a similar manner using ¬C. (3) The st-DASC of CNF can be constructed by repeatedly applying ∧BC after constructing the classuse. Also, if it is known that the input is structured d-DNNF or SDD, it can be transformed as described below.

[0087] In other words, structured d-DNNF is a representation that decomposes a logical function into ∧ and ∨. Structured d-DNNF guarantees that for any input, at most one of the inputs of the ∨ node will be 1 (determinism). On the other hand, the st-DASC disclosed here decomposes a logical function into ∧, +, and edge signs. st-DASC is a generalization of structured d-DNNF. This is because the structure other than the + node is common to both, and under determinism, the + node can be considered a generalization of the ∨ node. That is, since 0+0=0∨0, and 0+1=0∨1, and 1+0=1∨0, the same function can be easily represented in st-DASC by replacing the ∨ node in structured d-DNNF with the + node.

[0088] The embodiments relating to this disclosure have been described above. The various processes in the embodiments described above may be executed not only in chronological order as described, but also in parallel or individually as needed, depending on the processing capacity of the device performing the processes. Needless to say, further modifications can be made as appropriate without departing from the spirit of this disclosure.

[0089] This disclosure may further include a device (terminal) for using the device or method of this disclosure via a network (telecommunication line). The "device (terminal) for use" may be equipped with functions necessary to obtain the effects of implementing the device or method of this disclosure (e.g., control functions, decoding functions, restoration functions, input / output functions, etc.).

[0090] <Modification> The logic function conversion device 1B described above may be configured as a logic function conversion device 2 that does not have the functions of the calculation unit 30 or the output unit 40. Figure 13 is a diagram showing an example of the functional configuration of the logic function conversion device. The logic function conversion device 2 shown in Figure 13 has the input unit 10 and the conversion unit 20 described above. In this example, the logic function conversion device 2 is a device that converts the logic expression received by the input unit to st-DASC when the logic expression is not st-DASC and outputs the conversion result. By having the outputted st-DASC calculated by an arithmetic unit capable of st-DASC calculation processing, the calculation result of st-DASC can be obtained.

[0091] [Processors, Programs, Recording Media] The functions realized by the components described herein may be implemented in a circuitry or processing circuitry, including general-purpose processors, application-specific processors, integrated circuits, ASICs (Application Specific Integrated Circuits), CPUs (a Central Processing Unit), conventional circuits, and / or combinations thereof, programmed to realize the functions described herein. A processor includes transistors and other circuits and is considered a circuitry or processing circuitry. A processor may be a programmed processor that executes a program stored in memory.

[0092] In this specification, circuitry, unit, and means are hardware programmed to perform or execute the functions described herein. Such hardware may be any hardware disclosed herein, or any hardware known to be programmed to perform or execute the functions described herein.

[0093] If the hardware is a processor that is considered to be a type of circuitry, then the circuitry, means, or unit is a combination of hardware and software used to constitute the hardware and / or processor.

[0094] The various processes described above can be carried out by loading a program that executes each step of the above method into the recording unit 2020 of the computer 2000 shown in Figure 14, and then causing the control unit 2010, input unit 2030, output unit 2040, display unit 2050, etc. to operate.

[0095] The program describing this process can be recorded on a computer-readable recording medium. Any computer-readable recording medium can be used, such as a magnetic recording device, optical disc, magneto-optical recording medium, or semiconductor memory.

[0096] Furthermore, this program may be distributed, for example, by selling, transferring, or lending portable recording media such as DVDs or CD-ROMs on which the program is recorded. Alternatively, the program may be stored in the storage device of a server computer and distributed by transferring the program from the server computer to other computers via a network.

[0097] A computer executing such a program may, for example, first store the program recorded on a portable storage medium or a program transferred from a server computer in its own storage device. Then, when processing is to be executed, the computer reads the program stored on its own storage medium and executes the processing according to the read program. Alternatively, the computer may directly read the program from the portable storage medium and execute the processing according to that program, or it may sequentially execute the processing according to the received program each time a program is transferred to it from a server computer. Furthermore, the processing may be executed using a so-called ASP (Application Service Provider) type service, where the processing function is realized only by issuing execution instructions and obtaining results, without transferring the program from the server computer to this computer.In addition, the processing may be executed using a so-called SaaS (Software as a Service) type service, where a part of the server computer is made available to the user along with the program. Furthermore, the term "program" in this form includes information used for processing by an electronic computer that is equivalent to a program (data, etc., that is not a direct instruction to the computer but has the property of defining the processing of the computer).

[0098] Furthermore, in this configuration, the device is configured by executing a predetermined program on a computer, but at least a part of these processes may be implemented in hardware.

Claims

1. Let i be any integer and x be any variable, and assign 1, 0, x to each leaf node in a rooted directed acyclic graph. ｉ ,￢x ｉ ASC is a logical function expressed by assigning one of the following labels to each node, assigning either the label + or ∧ to each non-leaf node, setting the number of children of ∧ nodes to 2, the number of children of + nodes to be arbitrary, and assigning either the sign -1 or 1 to the edges between each + node and its child nodes. The logical function f corresponds to node v of the ASC. v A logic function arithmetic device that recursively defines a logical function such that when the logical function for any node of the ASC is a Boolean, the logical function of the ASC expressed according to an arbitrary binary tree is defined as st-DASC, the logic function arithmetic device comprising: an input unit that accepts a logical expression as input; and an arithmetic unit that performs operations on the st-DASC when the accepted logical expression is the st-DASC.

2. The logic function arithmetic device according to claim 1, further comprising a conversion unit that converts the received logic expression to the st-DASC when the logic expression received by the input unit is not the st-DASC.

3. The logic function arithmetic device according to claim 2, wherein the arithmetic unit comprises: a ∧BC arithmetic unit for calculating the logical AND of two logic functions; a CT arithmetic unit for calculating the number of models of a logic function; a ¬C arithmetic unit for calculating the logical negation of a logic function; and a CD arithmetic unit for calculating the condition of a logic function.

4. Let i be any integer and x be any variable, and assign 1, 0, x to each leaf node in a rooted directed acyclic graph. ｉ ,￢x ｉ ASC is a logical function expressed by assigning one of the following labels to each node, assigning either the label + or ∧ to each non-leaf node, setting the number of children of ∧ nodes to 2, the number of children of + nodes to be arbitrary, and assigning either the sign -1 or 1 to the edges between each + node and its child nodes. The logical function f corresponds to node v of the ASC. v A logic function conversion device that recursively defines a logic function, and when the logic function for any node of the ASC is Boolean, the logic function of the ASC expressed according to an arbitrary binary tree is defined as st-DASC, the logic function conversion device comprising: an input unit that accepts a logic expression as input; and a conversion unit that converts the logic expression received by the input unit to st-DASC if the logic expression received is not st-DASC.

5. Let \(i\) be an arbitrary integer, \(x\) be an arbitrary variable, and label each leaf node in a rooted directed acyclic graph with one of \(1, 0, x\) ｉ , \(\neg x\) ｉ and label each non - leaf node with either \(+\) or \(\land\). Let the number of children of an \(\land\) node be 2, the number of children of a \(+\) node be arbitrary, and assign either \(-1\) or \(1\) to the edge between each \(+\) node and its child nodes. Denote the logical function expressed in this way as \(ASC\). For the logical function \(f\) v corresponding to the node \(v\) of the said \(ASC\), define it recursively. When the logical function for any node of the said \(ASC\) is Boolean, the logical function of the said \(ASC\) expressed according to an arbitrary binary tree is defined as \(st - DASC\). A logical function operation method, wherein the input part of a logical function operation device receives an input of a logical formula, and when the received logical formula is the said \(st - DASC\), the operation part of the said logical function operation device performs an operation on the said \(st - DASC\).

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