Display device, electronic apparatus, and semiconductor device

Abstract

[Problem] To make it possible to reduce latency when performing XR video display. [Solution] This display device comprises: a display unit that has a plurality of light-emitting element groups arranged in a first direction and a second direction intersecting each other; a trimming unit that cuts out a portion of input image data to generate trimmed image data; and an image processing unit that performs time warp processing for, on the basis of the position and / or the posture of a user viewing the display unit, transforming the trimmed image data to generate image data to be displayed on the display unit.

Description

Display device, electronic device, and semiconductor device

[0001] The present disclosure relates to a display device, an electronic device, and a semiconductor device.

[0002] A head-mounted display (HMD) that allows a user to experience a worldview of XR (Extended Reality) such as VR (Virtual Reality), AR (Augmented Reality), or MR (Mixed Reality) has attracted attention.

[0003] In XR video display processing, in order to minimize the latency from when a user's body movement called Motion to Photon is detected until it is reflected in the video display, image reprojection called time warp processing is performed based on the position / pose information of the user detected by a motion sensor.

[0004] If reprojection is performed by a GPU (Graphics Processing Unit) connected to the HMD, the computational load on the GPU increases, and processing delay and increased power consumption on the GPU can become problems. In addition, there may be transmission delay and display delay until the image generated by reprojection is transmitted to and displayed on the HMD.

[0005] To solve such problems, a technique for performing reprojection inside the HMD has been proposed (see Patent Document 1).

[0006] Japanese Unexamined Patent Application Publication No. 2023-014116

[0007] However, in Patent Document 1, it is premised that XR video display is performed over the entire display area of the HMD. XR video display reconstructs and displays a 3D shape based on depth information and UV texture, so the display process takes time. The larger the display area, the more difficult it is to reduce latency, and there is a risk that the displayed image will not follow the change in the posture of the user wearing the HMD, resulting in a display that feels uncomfortable.

[0008] Therefore, the present disclosure provides a display device, an electronic device, and a semiconductor device capable of reducing latency when performing XR video display.

[0009] To solve the above problems, the present disclosure provides a display device comprising: a display unit having a plurality of light-emitting groups arranged in a first direction and a second direction that intersect each other; a trimming unit that extracts a portion of input image data and generates trimmed image data; and an image processing unit that performs time warp processing to deform the trimmed image data based on at least one of the position or orientation of a user viewing the display unit and generates image data to be displayed on the display unit.

[0010] The input image data may have a wider field of view than the image data displayed on the display unit.

[0011] The input image data may be data with the same resolution as the image data displayed on the display unit.

[0012] The input image data may be data with a lower resolution than the image data displayed on the display unit, or data with a lower frame rate than the image data displayed on the display unit.

[0013] The image processing unit may, in addition to the time warp processing, perform processing to increase the resolution of low-resolution image data or processing to increase the frame rate.

[0014] The input image data may include data with the same resolution as the image data displayed on the display unit and data with a lower resolution than the image data displayed on the display unit.

[0015] The data with the same resolution as the image data displayed on the display unit may include data in the direction of the user's center of posture.

[0016] The system includes a tracking unit that tracks at least one of the user's position or posture, a trimming unit that generates trimmed image data based on at least one of the user's position or posture tracked by the tracking unit, and an image processing unit that performs the time warp processing based on at least one of the user's position or posture tracked by the tracking unit.

[0017] The tracking unit may track changes in the user's posture in multiple axial directions based on detection information from multiple sensors that detect changes in the user's posture.

[0018] The system includes a storage unit for storing the input image data, and the trimming unit may generate the trimmed image data by cutting out a portion of the input image data stored in the storage unit based on at least one of the user's position or posture tracked by the tracking unit.

[0019] The storage unit stores a plurality of input image data, each with a different orientation of the user's posture center, and the trimming unit may generate the trimmed image data by selecting any of the input image data stored in the storage unit based on at least one of the user's position or posture tracked by the tracking unit.

[0020] According to this disclosure, an electronic device is provided, comprising: a display device; a display control device that performs rendering processing to generate input image data to be input to the display device, wherein the display device comprises: a display unit having a plurality of light-emitting groups arranged in a first direction and a second direction that intersect each other, respectively; a trimming unit that cuts out a portion of the input image data to generate trimmed image data; and an image processing unit that performs time warp processing to deform the trimmed image data based on at least one of the position or orientation of a user viewing the display unit to generate image data to be displayed on the display unit.

[0021] The display device has a tracking unit that tracks at least one of the user's position or posture, and the information of at least one of the user's position or posture tracked by the tracking unit may be sent to the trimming unit and the image processing unit instead of the display control device.

[0022] The display device has a storage unit for storing the input image data, and the trimming unit may generate the trimmed image data by cutting out a portion of the input image data stored in the storage unit based on at least one of the user's position or posture tracked by the tracking unit.

[0023] The display control device transmits to the display device differential data, which includes the input image data already transmitted to the display device, to the display device; the storage unit updates the input image data based on the differential data; and the trimming unit generates the trimmed image data by cutting out a portion of the updated input image data stored in the storage unit.

[0024] The display control device transmits input image data to the display device having a lower resolution or a lower frame rate than the image data displayed on the display unit, and the image processing unit may perform the time warp processing and super-resolution processing on the input image data to generate image data with a higher resolution than the input image data, or increase the frame rate of the input image data after performing the time warp processing and upscaling processing on the input image data.

[0025] The display device has a tracking unit that tracks at least one of the user's position or posture, and the information of at least one of the user's position or posture tracked by the tracking unit may be sent to the display control device, the trimming unit, and the image processing unit.

[0026] The display control device may include a rendering unit that generates input image data by performing rendering processing on the original image data based on at least one of the user's position or orientation tracked by the tracking unit.

[0027] The display control device may stop transmitting new input image data to the display device if the trimming range of the trimming unit, which is set based on at least one of the user's position or posture tracked by the tracking unit, is included in the input image data transmitted to the display device.

[0028] According to this disclosure, a semiconductor device to be implemented in a display device is provided, comprising: a trimming unit that extracts a portion of input image data to generate trimmed image data; an image processing unit that performs time warp processing to transform the trimmed image data based on at least one of the position or orientation of a user viewing the display device to generate image data to be displayed on the display device; and an interface unit that sends the image data generated by the time warp processing to a control unit that performs at least one of the writing timing or light emission timing for the display device.

[0029] A diagram illustrating an example of the appearance of the electronic device of this disclosure. A diagram illustrating a modified example of the appearance of the electronic device of this disclosure. A perspective view of the electronic device of this disclosure. A block diagram showing the schematic configuration of the electronic device according to the first embodiment. A diagram illustrating the trimming process. A diagram illustrating the trimming process. A diagram showing an example of input image data (IMG) transmitted from the GPU to the HMD. A diagram showing image data written to the display panel and illuminated (displayed) based on the input image data of Figure 5. A diagram comparing the time required to write to the display panel in one embodiment and a second comparative example. A diagram showing the configuration of the display panel according to one embodiment. A block diagram showing the internal configuration of a vertical scanning control circuit that generates a plurality of write enable signals and a plurality of light emission enable signals. A diagram illustrating a power consumption reduction technique when driving the display panel according to one embodiment. A block diagram showing the schematic configuration of the electronic device 1 according to the second embodiment. A block diagram showing the schematic configuration of the electronic device 1 according to the third embodiment. A block diagram showing the schematic configuration of the electronic device 1 according to the fourth embodiment. A block diagram showing the schematic configuration of the electronic device 1 according to the fifth embodiment. A block diagram showing the schematic configuration of the electronic device 1 according to the sixth embodiment. A block diagram showing the schematic configuration of the electronic device 1 according to the seventh embodiment. External view of an HMD relating to the first application example. External view of an HMD relating to the second application example. Front view showing an example of the appearance of a digital still camera. Rear view showing an example of the appearance of a digital still camera. Circuit diagram of the first pixel configuration example. Circuit diagram of the second pixel configuration example. Circuit diagram of the third pixel configuration example. Circuit diagram of the fourth pixel configuration example. Circuit diagram of the fifth pixel configuration example. Circuit diagram of the sixth pixel configuration example. Circuit diagram of the seventh pixel configuration example. Circuit diagram of the eighth pixel configuration example. Circuit diagram of the ninth pixel configuration example.

[0030] Embodiments of the display device and electronic device will be described below with reference to the drawings. While the main components of the display device and electronic device will be described below, there may be components and functions not shown or described. The following description does not exclude any components or functions not shown or described.

[0031] Figure 1A is a diagram illustrating an example of the appearance of the electronic device 1 of the present disclosure, Figure 1B is a diagram illustrating a modified example of the appearance of the electronic device 1 of the present disclosure, and Figure 2 is a perspective view of the electronic device 1 of the present disclosure. As shown in Figure 2, the electronic device 1 according to this embodiment comprises a display device 2 and a display control device 3. The display device 2 is, for example, a head-mounted display (HMD).

[0032] As shown in Figure 2, the display device 2 having an HMD and the display control device 3 having a GPU communicate, for example, via wireless communication. Alternatively, wired communication via a USB (Universal Serial Bus) interface may be used instead of wireless communication. Various sensors are connected to the HMD. Typical sensors connected to the HMD include, for example, a camera with a built-in CIS (CMOS Image Sensor) and an IMU (Inertial Measurement Unit). The camera captures images of the area around the HMD and generates image data. The IMU tracks the position and orientation of the user wearing the HMD and outputs position / orientation information. In this specification, the tracking information of the position and orientation of the user wearing the HMD detected by the IMU is referred to as position / orientation information.

[0033] Image data and position / orientation information detected by the HMD's sensors are transmitted to the GPU. The GPU then performs rendering processing on the image data transmitted from the HMD based on the user's position / orientation information transmitted from the HMD.

[0034] The HMD 1001 shown in Figure 1A has an output mechanism 1011 and a mounting mechanism 1012. The mounting mechanism 1012 includes a mounting band 1013 that wraps around the user's head to secure the HMD. Note that the structure for securing the HMD to the user's head is not limited to that shown in Figure 1A.

[0035] The output mechanism 1011 includes a housing 1014 shaped to cover the left and right eyes when the HMD 1001 is worn by the user, and has a display panel inside the housing 1014 positioned to face the user's eyes when worn. The housing 1014 may also include an optical system positioned between the display panel and the user's eyes when the HMD 1001 is worn, which expands the user's field of view. Stereo images corresponding to the parallax between the two eyes may be displayed in each region that divides the display panel into left and right sections, and stereoscopic vision can be achieved by such a display.

[0036] The HMD 1001 may also be equipped with speakers and earphones to match the position of the user's ears when worn. In Figure 1A, the HMD 1001 has a camera 1015 on the front of the housing 1014, and the surrounding real space is captured as a video in a field of view corresponding to the user's line of sight. In this specification, the camera 1015 may be referred to as the imaging unit 60.

[0037] The camera 1015 (imaging unit 60) may incorporate a CIS as described above, or it may incorporate a CCD (Charge Coupled Device) sensor. In addition, the camera 1015 includes an optical system such as an imaging lens. For example, the camera 1015 in Figure 1A is a stereo camera that images the space in front from left and right viewpoints corresponding to the user's left and right eyes. The camera 1015 is not limited to a stereo camera, but may be a monocular camera or a multi-lens camera with three or more lenses. Furthermore, it may be a combination of multiple types of sensors. In hand tracking applications, the camera 1015 may image the space below the electronic device. In eye tracking and face tracking applications, the camera 1015 may image the user's eyes or face.

[0038] As described above, an IMU is connected to the HMD1001. The IMU includes at least one of various sensors for determining the movement, attitude, and position of the HMD1001, such as an accelerometer, gyroscope, angular velocity sensor, and geomagnetic sensor.

[0039] The HMD 1001 may have a function to run online applications such as games that can be participated in by multiple users via a wireless or wired network. In this case, the HMD 1001 performs predetermined processing on the image captured by the camera 1015, and generates and displays a display image by superimposing various content images as needed onto the image captured within the field of view of the camera 1015.

[0040] Here, the specific content of the displayed image is not particularly limited and varies depending on the functions the user requests from the system and the content of the application launched.

[0041] For example, the HMD 1001 may perform some processing on the image captured by the camera 1015, or superimpose and draw virtual objects that interact with the image of a real object. Alternatively, the HMD 1001 may draw a virtual world in the user's field of view based on the captured image or the measured values ​​from the motion sensors included in the sensor group of the HMD 1001.

[0042] Typical examples of these embodiments include XR images such as virtual reality (VR), augmented reality (AR), and mixed reality (MR). Alternatively, by using the image captured by the camera (imaging unit 60) 1015 as the display image, a see-through form (VST: Video See Through) in which the real world can be seen through the screen of the HMD 1001 may be realized.

[0043] The electronic device 1101 according to this embodiment, shown in Figure 1B, is a glasses-type HMD.

[0044] The HMD main body 1111 of the glass-type HMD in FIG. 1B is worn on the user's head for use. The HMD main body 1111 includes a front portion 1112, a right temple portion 1113 provided on the right side of the front portion 1112, a left temple portion 1114 provided on the left side of the front portion 1112, and a glass portion 1115 attached to the lower side of the front portion 1112. In FIG. 1B, although the glasses are integrated, they may have two glasses separated for each eye, or may be configured to cover only one eye.

[0045] The display unit 1103 is a see-through type display unit and is provided on the surface of the glass portion 1115. The display unit 1103 performs AR display of virtual objects according to the control of the processing circuit (control unit) 2001. Note that the display unit 1103 may be a non-see-through type display unit. In this case, AR display is performed by displaying an image in which a virtual object is superimposed on the image currently captured by the camera 1104 on the display unit 1103.

[0046] The camera 1104 is, for example, the imaging unit 60 and has an image sensor such as a CCD sensor or a CIS, or a distance measuring sensor or the like. In addition, the camera 1104 includes an optical system such as an imaging lens. The camera 1104 is provided outwardly on the outer surface of the front portion 1112, captures an object in the real space, and outputs the image information obtained by the capture to the processing circuit (control unit) 2001. In FIG. 1B, for example, two cameras 1104 are provided at a predetermined interval in the horizontal direction in the front portion 1112. Note that the camera (imaging unit 60) 1104 is not limited to this, and may be a monocular camera or a multi-eye camera of three or more. Furthermore, a combination of multiple types of sensors may be used. In the application of hand tracking, the camera 1104 may be provided to capture the space below the electronic device. In the application of eye tracking or face tracking, the camera 1104 may be provided to capture the user's eyes or face.

[0047] A glass-type HMD 1101 is connected to an IMU. The IMU may include at least any of various sensors for deriving the movement, posture, position, etc. of the HMD 1001, such as an acceleration sensor, a gyro sensor, an angular velocity sensor, and a geomagnetic sensor.

[0048] Further, the glass-type HMD 1101 may have a communication interface (communication IF). It communicates with a smartphone or an external device other than a smartphone (for example, a PC (Personal Computer), or a server device on a network, etc.) by wire or wirelessly.

[0049] As shown in FIG. 2, the display device 2 having the HMD 4 according to this embodiment performs (1) tracking processing of the position and posture of the user, (3) trimming processing of the rendered image data transmitted from the GPU 11, (4) time warp processing on the trimmed image data, and (5) processing of writing the time warped image data to the display unit 9. Further, the display control device 3 having the GPU 11 according to this embodiment performs (2) rendering processing of the image data captured by a camera or the like based on the tracking information transmitted from the HMD 4.

[0050] (Hardware Configuration Example of Display Device 2 and Electronic Device) FIG. 3 is a block diagram showing a schematic configuration of an electronic device 1 according to the first embodiment. As shown in FIG. 3, the electronic device 1 according to the first embodiment includes a display device 2 and a display control device 3. Hereinafter, an example in which the display device 2 has an HMD 4 similar to FIG. 1A or FIG. 1B will be described.

[0051] The HMD 4 has a receiving unit (RX) 5, a tracking unit (tracker) 6, a trimming unit 7, an image processing unit 8, and a display unit 9. An IMU 10 is connected to the HMD 4. As described above, the IMU 10 is a detection unit that detects at least one of the position or posture of the user wearing the HMD 4.

[0052] The receiving unit 5 receives the input image data transmitted from the display control device 3. As will be described later, the display control device 3 transmits the input image data after the rendering process to the display device 2.

[0053] The tracker 6 tracks at least one of the user's position or posture wearing the HMD 4 based on the detection information from the IMU 10. The tracker 6 transmits information about at least one of the tracked user's position or posture to the trimming unit 7 and the image processing unit 8. Hereinafter, the information output by the tracker 6 will be referred to as position / posture information. The position / posture information includes information about at least one of the user's position or posture.

[0054] The tracking process performed by the tracker 6 is executed, for example, by the CPU (Central Processing Unit) of the HMD 4. Alternatively, the tracker 6 may be located inside the display control device 3 instead of inside the HMD 4.

[0055] The trimming unit 7 generates trimmed image data by cutting out a portion of the input image data based on position / orientation information. For example, the trimming unit 7 cuts out the input image data in line with the user's center of posture.

[0056] The image processing unit 8 has a warp driver 10 that performs time warp processing on the image data after trimming (trimmed image data). Time warp processing refers to the process of transforming the input image data based on position / orientation information from the tracker 6. The image processing unit 8 may also perform various other image processing operations besides time warp processing.

[0057] The trimming unit 7 and image processing unit 8 described above can be implemented in a semiconductor device mounted on the display unit 9. This semiconductor device includes a trimming unit that cuts out a portion of the input image data to generate trimmed image data, an image processing unit that performs time-warp processing to transform the trimmed image data based on at least one of the position or orientation of the user viewing the display unit 9 to generate image data to be displayed on the display unit 9, and an interface unit that sends the image data generated by the time-warp processing to a control unit that performs at least one of the writing timing or light emission timing for the display unit 9.

[0058] The display unit 9 has a plurality of light-emitting element groups arranged in a first direction and a second direction that intersect each other. In this specification, the first direction may be referred to as the row direction and the second direction as the column direction. The light-emitting element groups are self-light-emitting elements such as OLEDs (Organic Light Emitting Diodes) or liquid crystal display elements arranged in a two-dimensional plane. An optical system (not shown) may be placed between the display panel and the eyes of the user wearing the HMD 4. The optical system may be, for example, eyepieces for the left eye and the right eye.

[0059] The display control device 3 includes a GPU 11 and a transmission unit (TX) 12. The GPU 11 receives the original image data as input. The display control device 3 may also have an image storage unit 20 for storing the original image data, or it may receive the original image data from a cloud server or the like (not shown).

[0060] The GPU 11 has a rendering unit (renderer) 13 that performs rendering processing. Rendering processing refers to the process of combining still images, moving images, background images, and text information. In the first embodiment, the GPU 11 performs rendering processing independently of the position / orientation information output by the tracker 6. The GPU 11 generates input image data by performing rendering processing on raw image data with a wider field of view than the display area of ​​the display unit 9, assuming that the trimming unit 7 of the display unit 9 performs trimming processing. The rendered input image data generated by the GPU 11 in the first embodiment is data with the same resolution as the display image of the display unit 9. In addition, the rendered input image data has a wider field of view than the display area of ​​the display unit 9.

[0061] Figures 4A and 4B illustrate the cropping process. If the user's center of orientation may be facing any direction within the 360-degree sphere 14, it is necessary to send the image data of the 360-degree sphere 14 from the GPU 11 to the HMD 4. In this case, the GPU 11 may compress the image data of the 360-degree sphere 14 by downsampling or other means, and then send the compressed image data of the 360-degree sphere 14 to the HMD 4.

[0062] Alternatively, the GPU 11 may estimate the range of changes in the user's 30 posture, extract an image of a portion of the 360-degree sphere 14, and transmit it to the HMD 4. Figure 4A shows an example in which the GPU 11 extracts an image of a portion 14a of the 360-degree sphere 14 and transmits it to the HMD 4. The portion 14a extracted by the GPU 11 is wider than the display area of ​​the display unit 9.

[0063] Figure 4B shows an example of cropping and transforming an image of a portion of the range 14a transmitted from the GPU 11 based on the position / orientation information of the user 30. As shown in Figure 4B, the warp 10 of the user 30 HMD 4 transforms the image data cropped from the portion of the range 14a (hereinafter referred to as trimmed image data) based on the position / orientation information of the user 30. The display unit 9 displays the image data 14b transformed by the warp 10.

[0064] (Writing and Light-Emitting Processing of Display Unit 9) The HMD 4 according to one embodiment is characterized by efficiently performing writing and light-emitting processing to the display unit 9. Figure 5 is a diagram showing an example of input image data IMG1 transmitted from the GPU 11 to the HMD 4. The input image data IMG1 is transmitted from the GPU 11 to the HMD 4, for example, in line units. Figure 5 shows an example in which the input image data IMG1 is scanned line by line from the top row to the bottom row, and the image data is transmitted line by line. Specifically, Figure 5 shows an example in which the image data is transmitted in the order of (1) top row, (2) middle row, and (3) bottom row.

[0065] Figure 6 shows image data IMG2 that is written to the display unit 9 and illuminated (displayed) based on the input image data IMG1 of Figure 5. Figure 6 shows an example in which the image data IMG2, which has been deformed into a trapezoid shape by time warp processing, is written to the display unit 9 and illuminated (displayed). In the example of Figure 6, the image data IMG2 is not displayed in a part of the upper area of ​​the display unit 9 (hereinafter referred to as the non-writing area) 31. Therefore, in this embodiment, the writing process of the image data IMG2 and the illumination process are not performed in the non-writing area 31. Figure 6 shows an example in which the writing process of the image data IMG2 is performed in the order of (1) the top row, (2) the middle row, and (3) the bottom row.

[0066] As shown in Figure 6, the top row of the image data IMG2 is displayed immediately before the non-write area 31 located above the display area of ​​the display unit 9. The writing process of the image data IMG2 to the display unit 9 is performed row by row by scanning from the top row to the bottom row of the display area of ​​the display unit 9. However, since the writing process is omitted for the non-write area 31, the time required to write the image data IMG2 to the entire display area can be reduced.

[0067] Figure 7 is a diagram comparing the time required to write to the display unit 9 in one embodiment and a second comparative example. In the second comparative example, as shown by the dashed line L10, image data is written to all lines of the display area of ​​the display unit 9. In one embodiment, as shown by the thick solid line L11 in Figures 6 and 7, image data is written to the display area of ​​the display unit 9, excluding the non-writing area 31. The thick solid line L11 representing one embodiment can write one frame's worth of image data in a shorter time than the dashed line L10 representing the second comparative example, thus reducing latency.

[0068] (Write Control and Light Emission Control) Figure 8 shows the configuration of a display unit 9 according to one embodiment. As shown in Figure 8, the display unit 9 has a plurality of pixel circuits PX arranged in a first direction (e.g., row direction) X and a second direction (e.g., column direction) Y, and a plurality of write control lines L1 and a plurality of light emission control lines L2, each extending in the first direction (e.g., row direction) X and arranged in the second direction (e.g., column direction) Y. These write control lines L1 and light emission control lines L2 are driven by a vertical scanning control circuit 15.

[0069] Multiple write control lines L1 transmit multiple write enable signals WS_EN0 to WS_EN2, etc. Multiple light emission control lines L2 transmit multiple light emission enable signals DS_EN0 to DS_EN2, etc.

[0070] Each of the multiple pixel circuits PX has a light-emitting element. The light-emitting element is, for example, an OLED. A group of pixel circuits (group of light-emitting elements) that includes two or more pixel circuits PX located in the same row is connected to a corresponding write control line L1 and a corresponding light emission control line L2. That is, each pixel circuit PX in the group of light-emitting elements in the same row is supplied with a corresponding write enable signal and a corresponding light emission enable signal.

[0071] The display unit 9 has a plurality of signal lines L3 that extend in a second direction (e.g., column direction) and are arranged in a first direction (e.g., row direction). These signal lines L3 are driven by a signal line driving circuit 16. A group of pixel circuits (group of light-emitting elements) that includes two or more pixel circuits PX located in the same column is connected to a corresponding signal line L3. Each signal line L3 transmits a brightness signal. The OLED of each pixel circuit PX emits light with a brightness corresponding to the brightness signal on the corresponding signal line L3.

[0072] Figure 9 is a block diagram showing the internal configuration of a vertical scanning control circuit 15 that generates multiple write enable signals WS_EN0 to WS_EN2 and multiple light emission enable signals DS_EN0 to DS_EN2. As shown in Figure 9, the vertical scanning control circuit 15 includes a write scanning control circuit 21 and a light emission control circuit 22.

[0073] The write scan control circuit 21 includes a first address decoder 23 and a plurality of first latch circuits 24. The first address decoder 23 generates a signal to select one of a plurality of write control lines L1 by decoding the input write address signal. The plurality of write control lines L1 are connected to the plurality of first latch circuits 24. The plurality of first latch circuits 24 generate a plurality of write enable signals by holding the output signal of the first address decoder 23, for example, on the rising edge of the write clock signal, and output them to the plurality of write control lines L1.

[0074] The light emission control circuit 22 includes a second address decoder 25, a plurality of second latch circuits 26, and a plurality of AND circuits 27. The second address decoder 25 generates a signal to select one of a plurality of light emission control lines L2 by decoding the input light emission address signal. A plurality of AND circuits 27 are connected to the plurality of second latch circuits 26. The plurality of second latch circuits 26 hold the output signal of the second address decoder 25, for example, on the rising edge of the light emission clock signal. Each of the plurality of AND circuits 27 generates a corresponding light emission enable signal by performing a logical AND operation between the output signal of the corresponding second latch circuit 26 and the corresponding write enable signal, and outputs it to the corresponding light emission control line L2.

[0075] In this manner, the vertical scanning control circuit 15 provides a different write enable signal and a light emission enable signal for each group of light-emitting elements arranged in the column direction. If the enable states of the write enable signal and the light emission enable signal for the same group of light-emitting elements conflict, the light emission enable signal is disabled while the write enable signal is enabled, and after the write enable signal transitions from the enabled state to the disabled state, the light emission enable signal transitions from the disabled state to the enabled state.

[0076] The write scan control circuit and the light emission control circuit within the vertical scan control circuit individually control each write control line and each read control line, so that, as shown in Figure 6, the drive of the write control lines and read control lines in the non-write area can be stopped in a portion of the display area.

[0077] (Reduced Power Consumption) Figure 10 illustrates a power consumption reduction technique when driving a display unit 9 according to one embodiment. When the original input image is rotated by time warp processing, non-write areas 31a, 31b may occur at least one of the upper, lower, right, or left ends of the display area of ​​the display unit 9. The vertical scanning control circuit 15 stops the writing process of image data and also stops the light emission process for the non-write areas 31a at the upper and lower ends of the display area. Specifically, the vertical scanning control circuit 15 does not drive the write control line L1 and the light emission control line L2 at the upper and lower ends of the display area. This reduces the power consumption of the vertical scanning control circuit 15.

[0078] Furthermore, the vertical scanning control circuit 15 and the signal line driving circuit 16 set the group of light-emitting elements located in the non-writing area (second background area) 31b on one or both sides in the row direction of the image displayed in the display area of ​​the display unit 9 to a predetermined brightness level (for example, a black level), and also fix the signal level of the signal lines for the group of light-emitting elements located in the non-emitting area (first background area) 31a on one or both sides in the column direction of the image displayed in the display unit 9. This reduces the power consumption of the signal line driving circuit 16.

[0079] Thus, in the first embodiment, the trimming unit 7 in the HMD 4 extracts a portion of the input image data from the GPU 11 based on position / orientation information, and then the warp unit 10 performs time warp processing based on the position / orientation information to generate display image data. This reduces the processing load on the GPU 11 and allows for rapid updating of the display image data in response to changes in the posture of the user 30 wearing the HMD 4.

[0080] (Second Embodiment) Figure 11 is a block diagram illustrating the schematic configuration of the electronic device 1 according to the second embodiment. As shown in Figure 11, the electronic device 1 according to the second embodiment comprises a display device 2 and a display control device 3. The display device 2 in Figure 11 differs from the display device 2 in Figure 3 in that a camera 32 is connected to it. The camera 32 is used to estimate the posture of the user 30 wearing the HMD 4. The direction of the user 30's posture center can be estimated from the image captured by the camera 32. The display device 2 in Figure 11 has the same internal configuration as the display device 2 in Figure 3, except that the camera 32 is connected to it. The display control device 3 in Figure 11 also has the same internal configuration as the display control device 3 in Figure 3.

[0081] The tracker 6 in the display device 2 tracks at least one of the user 30's position or orientation based on the detection information from the IMU 10 and the image captured by the camera 32, and outputs position / orientation information. Because the tracker 6 takes into account not only the detection information from the IMU 10 but also the image captured by the camera 32 when outputting position / orientation information, more multidimensional position / orientation information of the user 30 can be obtained compared to when the image captured by the camera 32 is not taken into consideration. The position / orientation information includes, for example, 6DoF (Degree of Freedom) position / orientation information. The number of DoF is arbitrary. By connecting various sensors other than the camera 32 to the HMD 4, the tracker 6 may output position / orientation information with more dimensions than 6DoF. In some cases, the tracker 6 may also output position / orientation information with fewer dimensions than 6DoF (for example, 3DoF).

[0082] In the second embodiment, the trimming unit 7 trims the input image data based on more multidimensional position / orientation information than in the first embodiment, so it can set the optimal trimming range and perform trimming processing in accordance with changes in the user's 30 posture. Furthermore, since the warp 10 deforms the trimmed image data based on more multidimensional position / orientation information than in the first embodiment, it can deform the trimmed image data in accordance with the user's 30 posture center direction.

[0083] (Third Embodiment) Figure 12 is a block diagram showing the schematic configuration of the electronic device 1 according to the third embodiment. The electronic device 1 according to the third embodiment comprises a display device 2 and a display control device 3. The display device 2 in Figure 12 has a data storage unit 33 in addition to the configuration of the display device 2 in Figure 3. The data storage unit 33 stores data transmitted from the display control device 3.

[0084] The data transmitted by the display control device 3 to the display device 2 is not necessarily limited to input image data. In addition to input image data, the display control device 3 may also transmit metadata, such as depth information, to the display device 2. The data storage unit 33 stores the input image data and various other data transmitted from the display control device 3. Since the data storage unit 33 mainly stores the input image data transmitted from the display control device 3 frame by frame, it is sometimes referred to as a frame memory in this specification.

[0085] The display control device 3 in Figure 12, like the display control device 3 in Figure 3, has a GPU 11 and a transmission unit 12. The GPU 11 generates data that is different from data already transmitted (difference data) among the data to be transmitted to the display device 2. The display control device 3 transmits the difference data generated by the GPU 11 to the display device 2. For example, the GPU 11 transmits only the difference data from the input image data for each frame. The display device 2 stores the difference data transmitted from the display control device 3 in the data storage unit 33. For example, if the display control device 3 transmits difference data that includes only a part of the input image data, the input image data stored in the data storage unit 33 is updated based on the transmitted difference data. The trimming unit 7 of the display device 2 reads the input image data for each frame stored in the data storage unit 33 and performs trimming processing based on position / orientation information to generate trimmed image data. The image processing unit 8 performs time warp processing on the trimmed image data based on position / orientation information and displays the deformed trimmed image data.

[0086] Thus, in the third embodiment, since the display device 2 is provided with a data storage unit 33, only the data that has been changed from the data already transmitted needs to be sent from the GPU 11 to the display device 2. Therefore, the amount of data transmitted from the display control device 3 to the display device 2 can be reduced, and data transmission can be accelerated. As a result, the image data displayed on the display unit 9 can be updated quickly.

[0087] (Fourth Embodiment) Figure 13 is a block diagram showing the schematic configuration of the electronic device 1 according to the fourth embodiment. The electronic device 1 according to the fourth embodiment comprises a display device 2 and a display control device 3. The HMD 4 in the display device 2 of Figure 13 has the same internal configuration as the HMD 4 in Figure 3. The display control device 3 in Figure 13 has the same internal configuration as the display control device 3 in Figure 3, but the GPU 11 in the display control device 3 generates input image data by rendering image data at a resolution lower than the display resolution. The display control device 3 transmits the input image data rendered at a resolution lower than the display resolution to the display device 2. Alternatively, if the input image data is moving image data, the display control device 3 transmits input image data with a reduced number of frames. This reduces the amount of data of the input image data transmitted from the display control device 3 to the display device 2, thereby lowering transmission costs.

[0088] The trimming unit 7 within the display device 2 performs trimming processing on the input image data transmitted from the display control device 3. The trimming processing is performed either at the resolution of the input image data or at the number of frames of the input image data.

[0089] The image processing unit 8 in the display device 2 performs time warp processing, as well as super-resolution processing to increase the resolution of the input image data transmitted from the display control device 3 to the display resolution, or upscaling processing to increase the number of frames, and displays the image data after super-resolution processing or upscaling processing on the display unit 9.

[0090] Thus, in the fourth embodiment, the amount of data transmitted between the display control device 3 and the display device 2 can be reduced, allowing for rapid display updates.

[0091] (Fifth Embodiment) Figure 14 is a block diagram showing the schematic configuration of the electronic device 1 according to the fifth embodiment. The electronic device 1 according to the fifth embodiment comprises a display device 2 and a display control device 3. The display device 2 in Figure 14 has the same internal configuration as the display device 2 in Figure 3, but the position / orientation information output from the tracker 6 is transmitted not only to the trimming unit 7 and the image processing unit 8, but also to the CPU in the display control device 3.

[0092] The display control device 3 in Figure 14 has the same internal configuration as the display device 2 in Figure 3, but the renderer 13 in the GPU 11 performs rendering based on position / orientation information. Specifically, the renderer 13 in Figure 14 generates input image data with a high resolution in the direction of the user 30's orientation center and a low resolution in directions away from the orientation center, based on the position / orientation information. Because the input image data generated by the GPU 11 has a low resolution in directions other than the orientation center, the amount of data is reduced. The display control device 3 can reduce the amount of data transmitted by sending the input image data generated by the renderer 13 to the display device 2. Thus, the input image data transmitted from the display control device 3 to the display device 2 includes data with the same resolution as the image data displayed on the display unit 9 and data with a lower resolution than the image data displayed on the display unit 9.

[0093] The display device 2 performs trimming and time warp processing on the input image data transmitted from the display control device 3 based on position / orientation information, and then displays it on the display unit 9.

[0094] Thus, in the fifth embodiment, by transmitting position / orientation information from the display device 2 to the display control device 3, the GPU 11 in the display control device 3 can generate input image data with high resolution in the direction of the orientation center and low resolution in directions away from the line of sight based on the position / orientation information, thereby reducing the amount of data transmitted between the display control device 3 and the display device 2.

[0095] (Sixth Embodiment) Figure 15 is a block diagram showing the schematic configuration of the electronic device 1 according to the sixth embodiment. The electronic device 1 according to the sixth embodiment comprises a display device 2 and a display control device 3. The electronic device 1 in Figure 15 according to the sixth embodiment is similar to the electronic device 1 in Figure 14 in that it transmits position / orientation information from the display device 2 to the display control device 3, but the processing content of the GPU 11 in the display control device 3 is different.

[0096] The GPU 11 in Figure 15 performs rendering by downsampling image data in directions other than the orientation center direction based on position / orientation information. This reduces the processing load on the GPU 11 when performing rendering, thereby improving rendering speed and reducing power consumption. The process of downsampling image data may involve compression, which combines multiple pixels into one, or a process that reduces the number of bits in the pixel data of each pixel.

[0097] When the position / orientation information changes, the display device 2 performs trimming and time warp processing again within the range of already received input image data if the change is within that range, and then displays the image. In this case, the resolution in the direction of the orientation center may decrease due to the change in position / orientation information, but the image may be displayed as is, or super-resolution processing may be performed as needed to increase the resolution for display.

[0098] The display control device 3 transmits new input image data to the display device 2 only if the change in position / orientation information exceeds the range of input image data already received. This reduces the amount of input image data transmitted from the display control device 3 to the display device 2.

[0099] (Seventh Embodiment) Figure 16 is a block diagram showing the schematic configuration of the electronic device 1 according to the seventh embodiment. The electronic device 1 according to the seventh embodiment comprises a display device 2 and a display control device 3. The display device 2 in Figure 16 is the same as the display device 2 in Figure 12 in that it has a frame memory 19. The frame memory 19 in Figure 16 may store various data other than image data, similar to the data storage unit 33 in Figure 12.

[0100] In Figure 16, the GPU 11 in the display control device 3 performs rendering processing on the 3D model to be displayed and generates 3D image data. For example, the GPU 11 generates multiple 3D image data of the 3D model viewed from multiple different directions. In the seventh embodiment, since it is assumed that position / orientation information is not transmitted from the display device 2 to the display control device 3, the GPU 11 pre-generates multiple 3D image data viewed from multiple directions, regardless of the position / orientation of the user 30.

[0101] The display control device 3 transmits multiple 3D image data generated by the GPU 11 to the display device 2. The display device 2 stores the received multiple 3D image data in the frame memory 19. The trimming unit 7 selects one of the multiple 3D image data stored in the frame memory 19 based on the position / orientation information and performs trimming. The image processing unit 8 performs deformation processing on the trimmed 3D image data based on the position / orientation information and displays it on the display unit 9.

[0102] Thus, in the seventh embodiment, the GPU 11 generates multiple 3D image data viewed from multiple directions, regardless of the user 30's position / orientation information. These images are transmitted from the display control device 3 to the display device 2 and stored in the frame memory 19. Based on the position / orientation information, one of the 3D image data is selected and subjected to trimming and time warp processing. This allows the display device 2 to transmit position / orientation information to the display control device 3 and display a 3D image oriented to match the user 30's posture.

[0103] The display devices 2 according to the first to seventh embodiments are applicable not only to the HMD 1001 shown in Figure 1A or the HMD 1101 shown in Figure 1B, but also to HMDs of various shapes and functions. Furthermore, the display devices 2 according to the first to third embodiments are applicable to display devices other than HMDs, such as electronic viewfinders. Several representative examples to which the display device 2 according to this disclosure can be applied will be described in order below.

[0104] (First Application Example) Figure 17 is an external view of the HMD 110 according to the first application example. The HMD 110 in Figure 17 has, for example, an eyeglass-shaped display unit 111 and ear hooks 112 on both sides for being attached to the user's head. The technical features of the display devices according to the first to seventh embodiments described above can be applied to such an HMD 110.

[0105] (Second Application Example) Figure 18 is an external view of the HMD 120 according to the second application example. The HMD 120 in Figure 18 is a transmissive HMD having a main body 121, an arm 122, and a lens barrel 123. This HMD 120 is attached to eyeglasses 128. The main body 121 has a control board and a display unit for controlling the operation of the HMD 120. This display unit emits image light of the displayed image. The arm 122 connects the main body 121 and the lens barrel 123 and supports the lens barrel 123. The lens barrel 123 projects the image light supplied from the main body 121 via the arm 122 towards the user's eyes through the lenses 129 of the eyeglasses 128. The technology according to the above embodiment can be applied to such an HMD 120.

[0106] This HMD120 is a so-called light guide plate type HMD, but it is not limited to this, and for example, it may be a so-called birdbath type HMD. This birdbath type HMD includes, for example, a beam splitter and a partially transparent mirror. The beam splitter outputs light encoded with image information toward the mirror, and the mirror reflects the light toward the user's eyes. Both the beam splitter and the partially transparent mirror are partially transparent. This allows light from the surrounding environment to reach the user's eyes.

[0107] (Third Application Example) Figures 19A and 19B show an example of the external appearance of the digital still camera 130, with Figure 19A showing a front view and Figure 19B showing a rear view. This digital still camera 130 is a single-lens reflex type camera with interchangeable lenses and has a camera body 131, a shooting lens unit 132, a grip 133, a monitor 134, and an electronic viewfinder 135. The shooting lens unit 312 is an interchangeable lens unit and is located near the center of the front of the camera body 311. The grip 133 is located on the left side of the front of the camera body 311, and the photographer holds this grip 133. The monitor 134 is located to the left of the center of the rear of the camera body 131. The electronic viewfinder 135 is located on the rear of the camera body 131, above the monitor 134. The photographer can look through the electronic viewfinder 135 to see the light image of the subject guided by the shooting lens unit 132 and determine the composition. The technology according to the above embodiment can be applied to the electronic viewfinder 135.

[0108] There are several candidate circuit configurations for each pixel PX arranged in the display unit 9 of the display device 2 according to the first to seventh embodiments. Below, the first to ninth configuration examples of the circuit configurations for each pixel PX arranged in the display unit 9 of the display device 2 according to the first to seventh embodiments will be described in order. Note that pixel PX with circuit configurations other than the first to ninth configuration examples shown below are also applicable. In the following, pixel PX may be referred to as pixel PIX.

[0109] (First Pixel Configuration Example) Figure 20 is a circuit diagram of a first pixel configuration example. The pixel PIX includes a capacitor C01, transistors MN02 to MN03, and a light-emitting element EL. Transistors MN02 to MN03 are N-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). The gate of transistor MN02 is connected to the control line WSL, the other of its source and drain is connected to the signal line SGL, and one of its source and drain is connected to the gate of transistor MN03 and one end of capacitor C01. One end of capacitor C01 is connected to one of the source and drain of transistor MN02 and the gate of transistor MN03, and the other end is connected to one of the source and drain of transistor MN03 and the anode of the light-emitting element EL. The gate of transistor MN03 is connected to one of the source and drain of transistor MN02 and one end of capacitor C01, the other source and drain is connected to the power line VCCP, and one of the source and drain is connected to the other end of capacitor C01 and the anode of light-emitting element EL. The anode of light-emitting element EL is connected to one of the source and drain of transistor MN03 and the other end of capacitor C01, and its cathode is connected to the power line Vcath. The voltage of the power line VCCP is switched as appropriate between a first voltage and a second voltage lower than the first voltage.

[0110] In this configuration, when transistor MN02 is turned on in a pixel PIX, the voltage across capacitor C01 is set based on the pixel signal supplied from signal line SGL. During the period when the voltage of power line VCCP is the first voltage, transistor MN03 supplies a current to the light-emitting element EL corresponding to the voltage across capacitor C01. The light-emitting element EL emits light based on the current supplied from transistor MN03. In this way, the pixel PIX emits light with a brightness corresponding to the pixel signal. During the period when the voltage of power line VCCP is the second voltage, the light-emitting element EL is extinguished.

[0111] (Second Pixel Configuration Example) Figure 21 is a circuit diagram of a second pixel configuration example. This pixel PIX has capacitors C11 and C12, transistors MP12 to MP15, and light-emitting element EL. Transistors MP12 to MP15 are P-type MOSFETs. The gate of transistor MP12 is connected to the control line WSL, one of its source and drain is connected to the signal line SGL, and the other of its source and drain is connected to the gate of transistor MP14 and the other end of capacitor C12. One end of capacitor C11 is connected to the power line VCCP, and the other end is connected to one end of capacitor C12, the other of the source and drain of transistor MP13, and one of the source and drain of transistor MP14. One end of capacitor C12 is connected to the other end of capacitor C11, the other of the source and drain of transistor MP13, and one of the source and drain of transistor MP14, and the other end is connected to the other of the source and drain of transistor MP12 and the gate of transistor MP14. The gate of transistor MP13 is connected to the control line DSL, one of its source and drain is connected to the power line VCCP, and the other of its source and drain is connected to one of the source and drain of transistor MP14, the other end of capacitor C11, and one end of capacitor C12. The gate of transistor MP14 is connected to the other of the source and drain of transistor MP12 and the other end of capacitor C12, one of its source and drain is connected to the other of the source and drain of transistor MP13, the other end of capacitor C11, and one end of capacitor C12, and the other of its source and drain is connected to the anode of the light-emitting element EL and one of the source and drain of transistor MP15. The gate of transistor MP15 is connected to the control line AZSL, one of its source and drain is connected to the other of the source and drain of transistor MP14 and the anode of the light-emitting element EL, and the other of its source and drain is connected to the power line VSS.

[0112] In this configuration, in a pixel PIX, when transistor MP12 is turned on, the voltage across capacitor C12 is set based on the pixel signal supplied from signal line SGL. Transistor MP13 is turned on and off based on the signal from control line DSL. Transistor MP14 supplies a current to the light-emitting element EL corresponding to the voltage across capacitor C12 while transistor MP13 is on. The light-emitting element EL emits light based on the current supplied from transistor MP14. In this way, the pixel PIX emits light with brightness corresponding to the pixel signal. Transistor MP15 is turned on and off based on the signal from control line AZSL. While transistor MP15 is on, the voltage of the anode of the light-emitting element EL is initialized by being set to the voltage of power line VSS.

[0113] Furthermore, transistors MP12 to MP15 may be transistors made of low-temperature polycrystalline silicon (LTPS). Also, at least one of transistors MP12 and MP15 may be a transistor made of oxide semiconductor.

[0114] (Third Pixel Configuration Example) Figure 22 is a circuit diagram of a third pixel configuration example. This pixel PIX includes a capacitor C21, transistors MN22 to MN25, and a light-emitting element EL. Transistors MN22 to MN25 are N-type MOSFETs. The gate of transistor MN22 is connected to the control line WSL, the other of its source and drain is connected to the signal line SGL, and one of its source and drain is connected to the gate of transistor MN24 and one end of capacitor C21. One end of capacitor C21 is connected to one of the source and drain of transistor MN22 and the gate of transistor MN24, and the other end is connected to one of the source and drain of transistor MN24, the other of the source and drain of transistor MN25, and the anode of the light-emitting element EL. The gate of transistor MN23 is connected to the control line DSL, the other of its source and drain is connected to the power line VCCP, and one of its source and drain is connected to the other of the source and drain of transistor MN24. The gate of transistor MN24 is connected to one of the source and drain of transistor MN22 and one end of capacitor C21, the other source and drain is connected to one of the source and drain of transistor MN23, and one source and drain is connected to the other end of capacitor C21, the other source and drain of transistor MN25 and the anode of light-emitting element EL. The gate of transistor MN25 is connected to the control line AZSL, the other source and drain is connected to one of the source and drain of transistor MN24, the other end of capacitor C21 and the anode of light-emitting element EL, and one source and drain is connected to the power line VSS.

[0115] In this configuration, in a pixel PIX, when transistor MN22 is turned on, the voltage across capacitor C21 is set based on the pixel signal supplied from signal line SGL. Transistor MN23 is turned on and off based on the signal from control line DSL. Transistor MN24 supplies a current to the light-emitting element EL corresponding to the voltage across capacitor C21 while transistor MN23 is on. The light-emitting element EL emits light based on the current supplied from transistor MN24. In this way, the pixel PIX emits light with brightness corresponding to the pixel signal. Transistor MN25 is turned on and off based on the signal from control line AZSL. While transistor MN25 is on, the voltage at the anode of the light-emitting element EL is initialized by being set to the voltage of power line VSS.

[0116] Transistors MN22 to MN25 may be transistors made of low-temperature polycrystalline silicon (LTPS). Furthermore, at least one of transistors MN22 and MN25 may be a transistor made of oxide semiconductor.

[0117] (Fourth Pixel Configuration Example) Figure 23 is a circuit diagram of the fourth configuration example of a pixel PIX. This pixel PIX has a capacitor C31, transistors MP32 to MP36, and a light-emitting element EL. Transistors MP32 to MP36 are P-type MOSFETs. The gate of transistor MP32 is connected to the control line WSL, one of its source and drain is connected to the signal line SGL, and the other of its source and drain is connected to the gate of transistor MP33, the other of its source and drain of transistor MP34, and the other end of capacitor C31. One end of capacitor C31 is connected to the power line VCCP, and the other end is connected to the other of its source and drain of transistor MP32, the gate of transistor MP33, and the other of its source and drain of transistor MP34. The gate of transistor MP34 is connected to control line AZSL1, one of its source and drain is connected to the other of the source and drain of transistor MP33, and one of the source and drain of transistor MP35, and the other of its source and drain is connected to the other of the source and drain of transistor MP32, the gate of transistor MP33, and the other end of capacitor C31. The gate of transistor MP35 is connected to control line DSL, one of its source and drain is connected to the other of the source and drain of transistor MP33, and one of the source and drain of transistor MP34, and the other of its source and drain is connected to one of the source and drain of transistor MP36 and the anode of the light-emitting element EL. The gate of transistor MP36 is connected to control line AZSL2, one of its source and drain is connected to the other of the source and drain of transistor MP35, and the anode of the light-emitting element EL, and the other of its source and drain is connected to power line VSS.

[0118] In this configuration, in a pixel PIX, when transistor MP32 is turned ON, the voltage across capacitor C31 is set based on the pixel signal supplied from signal line SGL. Transistor MP35 is turned ON or OFF based on the signal from control line DSL. Transistor MP33 supplies a current to the light-emitting element EL corresponding to the voltage across capacitor C31 while transistor MP35 is ON. The light-emitting element EL emits light based on the current supplied from transistor MP33. In this way, the pixel PIX emits light with a brightness corresponding to the pixel signal. Transistor MP34 is turned ON or OFF based on the signal from control line AZSL1. While transistor MP34 is ON, the drain and gate of transistor MP33 are connected to each other. Transistor MP36 is turned ON or OFF based on the signal from control line AZSL2. While transistor MP36 is ON, the voltage of the anode of the light-emitting element EL is initialized by being set to the voltage of power line VSS.

[0119] Transistors MP32 to MP36 may be transistors made of low-temperature polycrystalline silicon (LTPS). Furthermore, at least one of transistors MP32, MP34, and MP36 may be a transistor made of oxide semiconductor.

[0120] (Fifth Pixel Configuration Example) Figure 24 is a circuit diagram of the fifth configuration example of the pixel PIX. One end of capacitor C48 is connected to the signal line SGL1, and the other end is connected to the power line VSS. One end of capacitor C49 is connected to the signal line SGL1, and the other end is connected to the signal line SGL2. Transistor MP49 is a P-type MOSFET, with its gate connected to the control line WSL2, one of its source and drain connected to the signal line SGL1, and the other of its source and drain connected to the signal line SGL2.

[0121] Each pixel PIX includes a capacitor C41, transistors MP42 to MP46, and a light-emitting element EL. Transistors MP42 to MP46 are P-type MOSFETs. The gate of transistor MP42 is connected to the control line WSL1, one of its source and drain is connected to the signal line SGL2, and the other of its source and drain is connected to the gate of transistor MP43 and the other end of capacitor C41. One end of capacitor C41 is connected to the power line VCCP, and the other end is connected to the other of its source and drain of transistor MP42 and the gate of transistor MP43. The gate of transistor MP43 is connected to the other of its source and drain of transistor MP42 and the other end of capacitor C41, one of its source and drain is connected to the power line VCCP, and the other of its source and drain is connected to one of its source and drain of transistors MP44 and MP45. The gate of transistor MP44 is connected to control line AZSL1, one of its source and drain is connected to the other of the source and drain of transistor MP43, and one of the source and drain of transistor MP45, and the other of its source and drain is connected to signal line SGL2. The gate of transistor MP45 is connected to control line DSL, one of its source and drain is connected to the other of the source and drain of transistor MP43, and one of the source and drain of transistor MP44, and the other of its source and drain is connected to one of the source and drain of transistor MP46 and the anode of the light-emitting element EL. The gate of transistor MP46 is connected to control line AZSL2, one of its source and drain is connected to the other of the source and drain of transistor MP45 and the anode of the light-emitting element EL, and the other of its source and drain is connected to power line VSS.

[0122] In this configuration, in a pixel PIX, when transistor MP42 is turned ON, the voltage across capacitor C41 is set based on the pixel signal supplied to signal line SGL1. Transistor MP45 is turned ON or OFF based on the signal on control line DSL. Transistor MP43 supplies a current to the light-emitting element EL corresponding to the voltage across capacitor C41 while transistor MP45 is ON. The light-emitting element EL emits light based on the current supplied by transistor MP43. In this way, the pixel PIX emits light with a brightness corresponding to the pixel signal. Transistor MP44 is turned ON or OFF based on the signal on control line AZSL1. While transistor MP44 is ON, the drain of transistor MP43 and signal line SGL2 are connected to each other. Transistor MP46 is turned ON or OFF based on the signal on control line AZSL2. While transistor MP46 is ON, the voltage of the anode of the light-emitting element EL is initialized by setting it to the voltage of power line VSS.

[0123] Furthermore, transistors MP42 to MP46 and MP49 may be transistors using low-temperature polycrystalline silicon (LTPS). Also, at least one of transistors MP42, MP46, and MP49 may be a transistor using an oxide semiconductor.

[0124] (Sixth Pixel Configuration Example) Figure 25 is a circuit diagram of the sixth pixel configuration example. Multiple pixels are arranged in a matrix in the display area Da, and the display area Da is located between the first control unit Ct1 and the second control unit Ct2.

[0125] The first control unit Ct1 includes transmission gates TG45 and TG46, transistors MP56 and MP57, and capacitor C61. Transistors MP56 and MP57 are P-type MOSFETs. A pixel signal is supplied to one end of transmission gate TG45, and the other end of transmission gate TG45 is connected to signal line SGL1. One end of transmission gate TG46 is connected to signal line SGL2, and the other end of transmission gate TG46 is connected to power line Vorst. One end of capacitor C61 is connected to signal line SGL1, and the other end is connected to power line VSS1. The gate of transistor MP56 is connected to control line INIL, one of its source and drain is connected to power line Vini, and the other of its source and drain is connected to signal line SGL2. The gate of transistor MP57 is connected to control line ELL, one of its source and drain is connected to power line Vel, and the other of its source and drain is connected to signal line SGL2.

[0126] The second control unit Ct2 includes a transmission gate TG72, a transistor MP73, and a capacitor C82. The transistor MP73 is a P-type MOSFET. One end of the transmission gate TG72 is connected to the signal line SGL1, and the other end is connected to the other of the source and drain of the transistor MP73 and to one end of the capacitor C82. The gate of the transistor MP73 is connected to the control line REFL, one of the source and drain is connected to the power line Vref, and the other of the source and drain is connected to the other end of the transmission gate TG72 and one end of the capacitor C82. One end of the capacitor C82 is connected to the other end of the transmission gate TG72 and the other of the source and drain of the transistor MP73, and the other end is connected to the signal line SGL2.

[0127] Each pixel PIX includes a capacitor C132, transistors MP121 to MP125, and a light-emitting element EL. Transistors MP121 to MP125 are P-type MOSFETs. The gate of transistor MP122 is connected to the control line WSL, one of its source and drain is connected to the signal line SGL2, and the other of its source and drain is connected to the gate of transistor MP121 and the other end of capacitor C132. One end of capacitor C132 is connected to the power line Vel, and the other end is connected to the other of its source and drain of transistor MP122 and the gate of transistor MP121. The gate of transistor MP121 is connected to the other of its source and drain of transistor MP122 and the other end of capacitor C132, one of its source and drain is connected to the power line Vel, and the other of its source and drain is connected to one of its source and drain of transistors MP123 and MP124. The gate of transistor MP123 is connected to the control line AZSL, one of its source and drain is connected to the other of the source and drain of transistor MP121, and one of the source and drain of transistor MP124, and the other of its source and drain is connected to the signal line SGL2. The gate of transistor MP124 is connected to the control line DSL, one of its source and drain is connected to the other of the source and drain of transistor MP121, and one of the source and drain of transistor MP123, and the other of its source and drain is connected to one of the source and drain of transistor MP125 and the anode of the light-emitting element EL. The gate of transistor MP125 is connected to the control line AZSL, the other of its source and drain is connected to the power line Vorst, and one of its source and drain is connected to the other of the source and drain of transistor MP124 and the anode of the light-emitting element EL.

[0128] In this configuration, in a pixel PIX, when transistor MP122 is turned ON, the voltage across capacitor C132 is set based on the pixel signal supplied to one end of transmission gate TG45. Transistor MP124 is turned ON or OFF based on the signal on control line DSL. Transistor MP121 supplies a current to the light-emitting element EL corresponding to the voltage across capacitor C132 during the period when transistor MP124 is ON. The light-emitting element EL emits light based on the current supplied from transistor MP121. In this way, the pixel PIX emits light with brightness corresponding to the pixel signal. Transistors MP123 and MP125 are turned ON or OFF based on the signal on control line AZSL. During the period when transistor MP123 is ON, the other of the source and drain of transistor MP121 and one of the source and drain of transistor MP124 are connected to signal line SGL2. During the period when transistor MP125 is ON, the voltage of the anode of the light-emitting element EL is initialized by setting it to the voltage of power line Vorst. Furthermore, transistor MP56 is switched on and off based on the signal of control line INIL, transistor MP57 is switched on and off based on the signal of control line ELL, and transistor MP73 is switched on and off based on the signal of control line REFL. When transistor MP56 is turned on, signal line SGL2 is set to the voltage of power line Vini, and when transistor MP57 is turned on, signal line SGL2 is set to the voltage of power line Vel. When transistor MP73 is turned on, one end of capacitor C82 is initialized by being set to the voltage of power line Vref.

[0129] Furthermore, transistors MP121 to MP125, MP56, and MP57 may be transistors made of low-temperature polycrystalline silicon (LTPS). Also, at least one of transistors MP122 and MP125 may be a transistor made of oxide semiconductor.

[0130] (Seventh Pixel Configuration Example) Figure 26 is a circuit diagram of the seventh pixel configuration example. This pixel PIX includes a capacitor C51, transistors MP52 to MP60, and a light-emitting element EL. Transistors MP52 to MP60 are P-type MOSFETs. The gate of transistor MP52 is connected to the control line WSL, one of its source and drain is connected to the signal line SGL, and the other of its source and drain is connected to the other of its source and drain of transistor MP53 and one of its source and drain of transistor MP54. The gate of transistor MP53 is connected to the control line DSL, one of its source and drain is connected to the power line VCCP, and the other of its source and drain is connected to the other of its source and drain of transistor MP52 and one of its source and drain of transistor MP54. The gate of transistor MP54 is connected to one of the source and drain of transistor MP55, the other of the source and drain of transistor MP57, and the other end of capacitor C51. One of the source and drain is connected to the other of the source and drain of transistors MP52 and MP53, and the other of the source and drain is connected to one of the source and drain of transistors MP58 and MP59. One end of capacitor C51 is connected to the power line VCCP, and the other end is connected to the gate of transistor MP54, one of the source and drain of transistor MP55, and the other of the source and drain of transistor MP57. Capacitor C51 may include two capacitors connected in parallel with each other. The gate of transistor MP55 is connected to the control line AZSL1, one of the source and drain is connected to the gate of transistor MP54, the other of the source and drain of transistor MP57, and the other end of capacitor C51, and the other of the source and drain is connected to one of the source and drain of transistor MP56. The gate of transistor MP56 is connected to control line AZSL1, one of its source and drain is connected to the other of its source and drain of transistor MP55, and the other of its source and drain is connected to power line VSS.The gate of transistor MP57 is connected to the control line WSL, the other of its source and drain is connected to the gate of transistor MP54, one of the source and drain of transistor MP55, and the other end of capacitor C51, and one of its source and drain is connected to the other of its source and drain of transistor MP58. The gate of transistor MP58 is connected to the control line WSL, the other of its source and drain is connected to one of the source and drain of transistor MP57, the other of its source and drain is connected to the other of its source and drain of transistor MP54, and one of its source and drain is connected to one of its source and drain of transistor MP59. The gate of transistor MP59 is connected to the control line DSL, the other of its source and drain is connected to the other of its source and drain of transistor MP54, and one of its source and drain is connected to one of its source and drain of transistor MP58, and the other of its source and drain is connected to one of its source and drain of transistor MP60, and the anode of the light-emitting element EL. The gate of transistor MP60 is connected to the control line AZSL2, one of its source and drain is connected to the other of its source and drain of transistor MP59 and to the anode of the light-emitting element EL, and the other of its source and drain is connected to the power line VSS.

[0131] In this configuration, in the pixel PIX, the voltage across capacitor C51 is set based on the pixel signal supplied from signal line SGL when transistors MP52, MP54, MP58, and MP57 are turned ON. Transistors MP53 and MP59 are turned ON and OFF based on the signal from control line DSL. Transistor MP54 supplies a current to the light-emitting element EL corresponding to the voltage across capacitor C51 while transistors MP53 and MP59 are ON. The light-emitting element EL emits light based on the current supplied from transistor MP54. In this way, the pixel PIX emits light with brightness corresponding to the pixel signal. Transistors MP55 and MP56 are turned ON and OFF based on the signal from control line AZSL1. While transistors MP55 and MP56 are ON, the gate voltage of transistor MP54 is initialized by being set to the voltage of power line VSS. Transistor MP60 is turned ON and OFF based on the signal from control line AZSL2. During the period when transistor MP60 is ON, the voltage of the anode of the light-emitting element EL is initialized by setting it to the voltage of the power line VSS.

[0132] Transistors MP52 to MP60 may be transistors using low-temperature polycrystalline silicon (LTPS). Also, at least one of transistors MP55 to MP58 and MP60 may be a transistor using an oxide semiconductor.

[0133] (Example of the eighth pixel configuration) Figure 27 is a circuit diagram of the eighth example of the pixel PIX configuration. The signals of control line WSNL and control line WSPL are inverted signals of each other.

[0134] Each pixel PIX includes capacitors C61 and C62, transistors MN63, MP64, MN65-MN67, and light-emitting element EL. Transistors MN63, MN65-MN67 are N-type MOSFETs, and transistor MP64 is a P-type MOSFET. The gate of transistor MN63 is connected to the control line WSNL, and the other of its source and drain is connected to the signal line SGL and one of the source and drain of transistor MP64. The other of its source and drain is connected to the other of the source and drain of transistor MP64, one end of capacitors C61 and C62, and the gate of transistor MN65. The gate of transistor MP64 is connected to the control line WSPL, and the other of its source and drain is connected to the signal line SGL and the other of the source and drain of transistor MN63. The other of its source and drain is connected to one of the source and drain of transistor MN63, one end of capacitors C61 and C62, and the gate of transistor MN65. Capacitor C61 is constructed using, for example, a MOM (Metal Oxide Metal) capacitor, with one end connected to one of the source and drain of transistor MN63, the other of the source and drain of transistor MP64, one end of capacitor C62, and the gate of transistor MN65, and the other end connected to the power line VSS2. Capacitor C61 may also be constructed using, for example, a MOS capacitor or a MIM (Metal Insulator Metal) capacitor. Capacitor C62 is constructed using, for example, a MOS capacitor, with one end connected to one of the source and drain of transistor MN63, the other of the source and drain of transistor MP64, one end of capacitor C61, and the gate of transistor MN65, and the other end connected to the power line VSS2. Capacitor C62 may also be constructed using, for example, a MOM capacitor or a MIM capacitor. The other end of capacitor C62 may also be connected to the power line VSS3 (not shown).The gate of transistor MN65 is connected to one of the source and drain of transistor MN63, the other of the source and drain of transistor MP64, and one end of capacitors C61 and C62. The other of the source and drain is connected to the power line VCCP, and the other of the source and drain is connected to the other of the source and drain of transistors MN66 and MN67. The gate of transistor MN66 is connected to the control line AZL, and the other of the source and drain is connected to one of the source and drain of transistor MN65 and the other of the source and drain of transistor MN67, and the other of the source and drain is connected to the power line VSS1. The gate of transistor MN67 is connected to the control line DSL, and the other of the source and drain is connected to one of the source and drain of transistor MN65 and the other of the source and drain of transistor MN66, and the other of the source and drain is connected to the anode of the light-emitting element EL. Alternatively, the transistor MN67 and the control line DSL may be omitted, and one of the source and drain of transistor MN65 may be connected to the other of the source and drain of transistor MN66, and to the anode of the light-emitting element EL.

[0135] In this configuration, at least one of transistors MN63 and MP64 is turned on in the pixel PIX, setting the voltage across capacitors C61 and C62 based on the pixel signal supplied from signal line SGL. Transistor MN67 is turned on and off based on the signal from control line DSL. Transistor MN65 supplies a current to the light-emitting element EL corresponding to the voltage across capacitors C61 and C62 during the period when transistor MN67 is on. The light-emitting element EL emits light based on the current supplied from transistor MP65. In this way, the pixel PIX emits light with a brightness corresponding to the pixel signal. Transistor MN66 may be turned on and off based on the signal from control line AZL. Transistor MN66 may also function as a resistive element having a resistance value corresponding to the signal from control line AZL. In this case, transistors MN65 and MN66 constitute a so-called source follower circuit.

[0136] Transistors MN63, MP64, and MN65-MN67 may be transistors made of low-temperature polycrystalline silicon (LTPS). Furthermore, at least one of transistors MN63, MP64, and MN66 may be a transistor made of oxide semiconductor.

[0137] (Ninth Pixel Configuration Example) Figure 28 is a circuit diagram of the ninth pixel configuration example. This pixel PIX includes a capacitor C71, transistors MN72 to MN77, and a light-emitting element EL. Transistors MN72 to MN77 are N-type MOSFETs. The gate of transistor MN72 is connected to the control line WSL, the other of its source and drain is connected to the signal line SGL, and one of its source and drain is connected to one of the source and drain of transistor MN74 and the other of the source and drain of transistor MN75. One end of capacitor C71 is connected to the gate of transistor MN74 and one of the source and drain of transistor MN76, and the other end is connected to the other of the source and drain of transistor MN77, one of the source and drain of transistor MN75, and the anode of the light-emitting element EL. The gate of transistor MN73 is connected to the control line DLS1, and the other of its source and drain is connected to the power line VCCP. One of its source and drain is connected to the other of its source and drain of transistor MN74 and the other of its source and drain of transistor MN76. The gate of transistor MN74 is connected to one of its source and drain of transistor MN76 and one end of capacitor C71. The other of its source and drain is connected to one of its source and drain of transistor MN73 and the other of its source and drain of transistor MN76. One of its source and drain is connected to one of its source and drain of transistor MN72 and the other of its source and drain of transistor MN75. The gate of transistor MN75 is connected to control line DSL2, the other of its source and drain is connected to one of the source and drain of transistor MN72 and one of the source and drain of transistor MN74, and one of its source and drain is connected to the other end of capacitor C71, the other of the source and drain of transistor MN77 and the anode of light-emitting element EL.The gate of transistor MN76 is connected to the control line AZSL, and the other of its source and drain is connected to one of the source and drain of transistor MN73 and the other of the source and drain of transistor MN74, with one of its source and drain connected to the gate of transistor MN74 and one end of capacitor C71. The gate of transistor MN77 is connected to the control line AZSL, and the other of its source and drain is connected to the other end of capacitor C71, one of the source and drain of transistor MN75 and the anode of light-emitting element EL, with one of its source and drain connected to the power line VSS.

[0138] In this configuration, in the pixel PIX, the voltage across capacitor C71 is set based on the pixel signal supplied from signal line SGL when transistors MN72, MN74, and MN76 are turned on. Transistor MN73 is turned on and off based on the signal from control line DSL1, and transistor MN75 is turned on and off based on the signal from control line DSL2. Transistor MN74 supplies a current to the light-emitting element EL corresponding to the voltage across capacitor C71 while transistors MN73 and MN75 are turned on. The light-emitting element EL emits light based on the current supplied from transistor MN74. In this way, the pixel PIX emits light with brightness corresponding to the pixel signal. Transistor MN77 is turned on and off based on the signal from control line AZSL. While transistor MN77 is turned on, the voltage of the anode of the light-emitting element EL is initialized by being set to the voltage of power line VSS.

[0139] Transistors MN72 to MN77 may be transistors made of low-temperature polycrystalline silicon (LTPS). Transistor MN76 may be a transistor made of oxide semiconductor.

[0140] The technology can take the following configurations: (1) A display device comprising: a display unit having a plurality of light-emitting element groups arranged in a first direction and a second direction that intersect each other; a trimming unit that extracts a portion of input image data to generate trimmed image data; and an image processing unit that performs time warp processing to transform the trimmed image data based on at least one of the position or orientation of a user viewing the display unit to generate image data to be displayed on the display unit. (2) The display device according to (1), wherein the input image data is data with a wider field of view than the image data displayed on the display unit. (3) The display device according to (1), wherein the input image data is data with the same resolution as the image data displayed on the display unit. (4) The display device according to (1), wherein the input image data is data with a lower resolution than the image data displayed on the display unit, or data with a lower frame rate than the image data displayed on the display unit. (5) The display device according to (4), wherein the image processing unit performs processing to increase the resolution of low-resolution image data or to increase the frame rate, together with the time warp processing. (6) The display device according to (1), wherein the input image data includes data with the same resolution as the image data displayed on the display unit and data with a lower resolution than the image data displayed on the display unit. (7) The display device according to (6), wherein the data with the same resolution as the image data displayed on the display unit includes data in the direction of the user's posture center. (8) The display device according to (1), further comprising a tracking unit that tracks at least one of the user's position or posture, wherein the trimming unit generates trimmed image data based on at least one of the user's position or posture tracked by the tracking unit, and the image processing unit performs the time warp processing based on at least one of the user's position or posture tracked by the tracking unit. (9) The display device according to (8), wherein the tracking unit tracks changes in the user's posture in multiple axial directions based on detection information from multiple sensors that detect changes in the user's posture.(10) The display device according to (8), further comprising a storage unit for storing the input image data, wherein the trimming unit generates trimmed image data by cutting out a portion of the input image data stored in the storage unit based on at least one of the user's position or posture tracked by the tracking unit. (11) The display device according to (10), wherein the storage unit stores a plurality of input image data, each having a different orientation of the user's posture center, and the trimming unit generates trimmed image data by selecting any of the input image data stored in the storage unit based on at least one of the user's position or posture tracked by the tracking unit. (12) Electronic device comprising a display device and a display control device that performs rendering processing to generate input image data to be input to the display device, wherein the display device comprises a display unit having a plurality of light-emitting element groups arranged in a first direction and a second direction that intersect each other, respectively, a trimming unit that generates trimmed image data by cutting out a portion of the input image data, and an image processing unit that performs time warp processing to transform the trimmed image data and generate image data to be displayed on the display unit based on at least one of the position or posture of a user viewing the display unit. (13) The electronic device according to (12), wherein the display device has a tracking unit that tracks at least one of the user's position or posture, and the information of at least one of the user's position or posture tracked by the tracking unit is not sent to the display control device but is sent to the trimming unit and the image processing unit. (14) The electronic device according to (13), wherein the display device has a storage unit that stores the input image data, and the trimming unit generates the trimmed image data by cutting out a portion of the input image data stored in the storage unit based on at least one of the user's position or posture tracked by the tracking unit.(15) The electronic device according to (14), wherein the display control device transmits to the display device differential data with respect to transmission data including the input image data already transmitted to the display device, the storage unit updates the input image data based on the differential data, and the trimming unit generates trimmed image data by cutting out a portion of the updated input image data stored in the storage unit. (16) The electronic device according to (12), wherein the display control device transmits to the display device input image data having a lower resolution than the image data displayed on the display unit, or a lower frame rate than the image data displayed on the display unit, and the image processing unit performs time warp processing and super-resolution processing on the input image data to generate image data with a higher resolution than the input image data, or performs time warp processing and upscaling processing on the input image data to increase the frame rate of the input image data. (17) The electronic device according to (12), wherein the display device has a tracking unit that tracks at least one of the user's position or posture, and the information of at least one of the user's position or posture tracked by the tracking unit is sent to the display control device, the trimming unit, and the image processing unit. (18) The electronic device according to (17), wherein the display control device has a rendering unit that performs rendering processing on the original image data to generate the input image data based on at least one of the user's position or posture tracked by the tracking unit. (19) The electronic device according to (18), wherein the rendering unit generates the input image data including first image data in the direction of the user's posture center and second image data located outside the direction of the user's posture center and having a lower resolution or lower frame rate than the first image data, based on at least one of the user's position or posture tracked by the tracking unit. (20) The electronic device according to (18), wherein the display control device stops transmitting new input image data to the display device if the trimming range of the trimming unit, which is set based on at least one of the user's position or posture tracked by the tracking unit, is included in the input image data transmitted to the display device.(21) A semiconductor device to be mounted on a display device, comprising: a trimming unit that extracts a portion of input image data to generate trimmed image data; an image processing unit that performs a time warp process to transform the trimmed image data based on at least one of the position or orientation of a user viewing the display device to generate image data to be displayed on the display device; and an interface unit that sends the image data generated by the time warp process to a control unit that performs at least one of the writing timing or light emission timing for the display device.

[0141] The aspects of this disclosure are not limited to the individual embodiments described above, but include various modifications that a person skilled in the art could conceive, and the effects of this disclosure are not limited to those described above. In other words, various additions, modifications, and partial deletions are possible, as long as they do not depart from the conceptual idea and spirit of this disclosure derived from the claims and their equivalents.

[0142] 1 Electronic device, 2 Display device, 3 Display control device, 4 HMD, 5 Receiving unit, 6 Tracking unit (tracker), 7 Trimming unit, 8 Image processing unit, 9 Display unit, 10 Warp, 11 GPU, 12 Transmitter, 13 Rendering unit (renderer), 14 Spherical view, 14a Range, 14b Image data, 15 Vertical scanning control circuit, 16 Signal line driving circuit, 19 Frame memory, 20 Image storage unit, 21 Scanning control circuit, 22 Light emission control circuit, 23 First address decoder, 24 First latch circuit, 25 Second address decoder, 26 Second latch circuit, 27 AND circuit, 31 Region, 31a Region, 31a Non-light-emitting region (first background region), 31b Region (second background region), 32 Camera, 33 Data storage unit

Claims

1. A display device comprising: a display unit having a plurality of light-emitting groups arranged in a first direction and a second direction that intersect each other; a trimming unit that extracts a portion of input image data and generates trimmed image data; and an image processing unit that performs time warp processing to transform the trimmed image data based on at least one of the position or orientation of a user viewing the display unit and generates image data to be displayed on the display unit.

2. The display device according to claim 1, wherein the input image data is data with a wider field of view than the image data displayed on the display unit.

3. The display device according to claim 1, wherein the input image data is data with the same resolution as the image data displayed on the display unit.

4. The display device according to claim 1, wherein the input image data is data with a lower resolution than the image data displayed on the display unit, or data with a lower frame rate than the image data displayed on the display unit.

5. The display device according to claim 4, wherein the image processing unit performs a process to increase the resolution of low-resolution image data or a process to increase the frame rate, in addition to the time warp processing.

6. The display device according to claim 1, wherein the input image data includes data with the same resolution as the image data displayed on the display unit and data with a lower resolution than the image data displayed on the display unit.

7. The display device according to claim 6, wherein the data having the same resolution as the image data displayed on the display unit includes data in the direction of the user's posture center.

8. The display device according to claim 1, comprising a tracking unit for tracking at least one of the user's position or posture, a trimming unit for generating trimmed image data based on at least one of the user's position or posture tracked by the tracking unit, and an image processing unit for performing the time warp processing based on at least one of the user's position or posture tracked by the tracking unit.

9. The display device according to claim 8, wherein the tracking unit tracks changes in the user's posture in multiple axial directions based on detection information from multiple sensors that detect changes in the user's posture.

10. The display device according to claim 8, further comprising a storage unit for storing the input image data, wherein the trimming unit generates trimmed image data by cutting out a portion of the input image data stored in the storage unit based on at least one of the user's position or posture tracked by the tracking unit.

11. The display device according to claim 10, wherein the storage unit stores a plurality of input image data, each having a different orientation of the user's posture center, and the trimming unit selects any of the input image data stored in the storage unit based on at least one of the user's position or posture tracked by the tracking unit to generate the trimmed image data.

12. Electronic device comprising: a display device; a display control device that performs rendering processing to generate input image data to be input to the display device, wherein the display device comprises: a display unit having a plurality of light-emitting groups arranged in a first direction and a second direction that intersect each other, respectively; a trimming unit that cuts out a portion of the input image data to generate trimmed image data; and an image processing unit that performs time warp processing to deform the trimmed image data based on at least one of the position or orientation of a user viewing the display unit to generate image data to be displayed on the display unit.

13. The electronic device according to claim 12, wherein the display device has a tracking unit that tracks at least one of the user's position or posture, and the information of at least one of the user's position or posture tracked by the tracking unit is not sent to the display control device, but is sent to the trimming unit and the image processing unit.

14. The electronic device according to claim 13, wherein the display device has a storage unit for storing the input image data, and the trimming unit generates trimmed image data by cutting out a portion of the input image data stored in the storage unit based on at least one of the user's position or posture tracked by the tracking unit.

15. The electronic device according to claim 14, wherein the display control device transmits to the display device differential data with respect to transmission data including the input image data already transmitted to the display device, the storage unit updates the input image data based on the differential data, and the trimming unit generates trimmed image data by cutting out a portion of the updated input image data stored in the storage unit.

16. The electronic device according to claim 12, wherein the display control device transmits input image data having a lower resolution or a lower frame rate than the image data displayed on the display unit to the display device, and the image processing unit performs time warp processing and super-resolution processing on the input image data to generate image data with a higher resolution than the input image data, or performs time warp processing and upscaling processing on the input image data to increase the frame rate of the input image data.

17. The electronic device according to claim 12, wherein the display device has a tracking unit that tracks at least one of the user's position or posture, and the information of at least one of the user's position or posture tracked by the tracking unit is sent to the display control device, the trimming unit, and the image processing unit.

18. The electronic device according to claim 17, wherein the display control device has a rendering unit that generates input image data by performing rendering processing on the original image data based on at least one of the user's position or orientation tracked by the tracking unit.

19. The electronic device according to claim 18, wherein the display control device stops transmitting new input image data to the display device if the trimming range of the trimming unit, which is set based on at least one of the user's position or posture tracked by the tracking unit, is included in the input image data transmitted to the display device.

20. A semiconductor device to be mounted on a display device, comprising: a trimming unit that extracts a portion of input image data to generate trimmed image data; an image processing unit that performs time warp processing to transform the trimmed image data based on at least one of the position or orientation of a user viewing the display device to generate image data to be displayed on the display device; and an interface unit that sends the image data generated by the time warp processing to a control unit that performs at least one of the writing timing or light emission timing for the display device.

Images