Multi-temperature methods of forming semiconductor devices, and related devices and apparatus
A multi-temperature method forms semiconductor devices with reduced bowing and defects, enhancing throughput and performance by alternating silicon and silicon germanium layers in a superlattice structure.
WO2026151612A1PCT designated stage Publication Date: 2026-07-16APPLIED MATERIALS INC
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- APPLIED MATERIALS INC
- Filing Date
- 2025-12-22
- Publication Date
- 2026-07-16
AI Technical Summary
Technical Problem
Existing methods for forming semiconductor devices face challenges with device bowing, defects, and reduced throughput, particularly in forming silicon and silicon germanium superlattice structures.
Method used
A multi-temperature method involving the formation of semiconductor layers at different temperature ratios, with a first semiconductor layer formed at a first temperature and a second semiconductor layer formed at a ratio of the first temperature ranging from 1.05 to 1.15, using alternating layers of silicon and silicon germanium to create a superlattice structure.
Benefits of technology
The method achieves reduced bowing, eliminated defects, and increased throughput, with high growth rates and enhanced device performance, particularly in forming 3D DRAM devices.
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Smart Images
Figure US2025061008_16072026_PF_FP_ABST
Abstract
Embodiments of the present disclosure generally relate to multi-temperature methods of forming semiconductor devices. In one or more embodiments, the methods form silicon and silicon germanium superlattice structures. In one or more embodiments, a method of forming a semiconductor device includes forming a first semiconductor layer using a first temperature. The first semiconductor layer has a first composition. The method includes forming a second semiconductor layer using a second temperature. The second temperature is a ratio of the first temperature and the ratio is at least 1.05, and the second semiconductor layer has a second composition different than the first composition.
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