PTAT circuit and co-packaged optical modules containing the same

Abstract

Methods, devices, and systems for circuits that generate temperature sensitive voltages. In one aspect, a device includes a first and second transistor, and an amplifier having a first input and a second input. The first input is coupled to the first transistor and the second input is coupled to the second transistor. A third transistor includes a first gate and a first drain, the first drain coupled to the first transistor and the first gate coupled to the amplifier. A fourth transistor includes a second gate and a second drain, the second drain coupled to the second transistor and the second gate coupled to the amplifier. A fifth transistor includes a third gate and a third drain, the third gate coupled to the second gate and the third drain coupled to a controller. The controller produces a signal for a variable resistor using current from the fifth transistor.

Description

[0001] Attorney Docket No. t>7136-0128WOl

[0002] PT AT CIRCUIT AND CO-PACKAGED OPTICAL MODULES CONTAINING THE SAME

[0003] CROSS REFERENCE TO RELATED APPLICATION

[0004] This application claims the benefit of U.S. Provisional Application No. 63 / 744,691 filed on January 13, 2025, and titled “Systems and Methods for PTAT Circuits Compensation.” The disclosure of the prior application is considered part of (and is incorporated by reference in) the disclosure of this application.

[0005] TECHNICAL FIELD

[0006] This specification generally relates to electrical circuits, and more specifically, enhancing stability and performance of Proportional to Absolute Temperature (PTAT) circuits and copackaged optical modules containing PTAT circuits.

[0007] BACKGROUND

[0008] Demands for artificial intelligence (Al) computing, such as machine learning (ML) and deep learning (DL), are increasing faster than they can be met by increases in available processing capacity. This rising demand and the growing complexity of Al models drive the need to connect many chips into a system where the chips can send data between each other with low latency and at high speed. Performance when processing a workload is limited by memory and interconnect bandwidth. In many conventional systems, data movement leads to significant power consumption, poor performance, and excessive latency. Co-Packaged Optics (CPO) refers to packaging technology that integrates photonics devices with conventional integrated circuits, such as application-specific integrated circuit (ASIC) devices. CPO solutions are candidates for data interconnects for Al data centers and other high performance computing applications.

[0009] In high-speed communication systems and other digital applications, such as those described above, the timing, accuracy, and precision of devices are crucial for ensuring reliable data transmission and reception. Many of the devices in these systems can exhibit non-linearities that can introduce distortions during transmission and reception of data. These problems can be exacerbated during data transmission at high data rates, such as when device tolerances areAttorney Docket No. 37136-0128001

[0010] exposed to high temperatures produced by the high-speeds, device imperfections, and environmental challenges, all of which can interfere with signal integrity and system reliability.

[0011] SUMMARY

[0012] Proportional to Absolute Temperature (PTAT) circuits are widely used in integrated circuits for generating currents of voltages that vary linearly with temperature. Such predictable temperature dependency is often needed for applications that demand precise thermal compensation and stable operation across varying environmental conditions, such as high-speed communication systems. PTAT circuits are commonly employed in various applications, such as temperature sensors, reference voltage generators, and other analog circuitry where accurate, temperature-dependent resources are critical to application accuracy and performance.

[0013] In some implementations, the techniques described herein provide for PTAT circuits with enhanced stability and controllability. For example, a PTAT circuit can include a pair of input transistors to generate temperature sensitive voltages, along with one or more current transistors that are driven by an output of an operational amplifier to regulate an operation of the PTAT circuit. The current transistors can connect to a different, output transistor, that provides a current that is temperature dependent. The PTAT circuit can further include a variable resistor coupled to a feedback path. For example, a controller can receive a current derived from the output transistor and generate a control signal that adjusts a resistance of the variable resistor based on a magnitude of the received current. In some examples, the controller increases the resistance of the variable resistor when the magnitude of the received current is below a threshold value, and decreases the resistance when the magnitude of the received current exceeds a threshold value. By selectively adjusting the resistance of the PTAT circuit, the overall stability and phase margin of the PTAT circuit can be improved.

[0014] A challenge exists in designing PTAT circuits for certain applications, such as ensuring stability across different operating conditions in particularly low load currents where a loop gain may be high. Under these conditions, insufficient phase margin may cause oscillation or undesirable transient behavior. The techniques described herein address these challenges by dynamically modifying circuit parameters in response to measured current levels, and ultimately improving the stability of the PTAT circuit.Attorney Docket No. 37136-0128001

[0015] In particular, to address this challenge and others, the PTAT circuits can incorporate frequency compensation techniques. The frequency compensation techniques can involve the use of lead-lag networks that introduce a zero in the frequency response of the circuit, for example, to counteract any dominant pole that might otherwise destabilize the circuit system. For example, the compensation network may be implemented using a resistor-capacitor (RC) network and a parasitic capacitance at a critical node. Consequently, this created zero by the RC network can be positioned to cancel out the second dominant pole partially or fully and can improve the phase margin and ensure stability in the PTAT circuit.

[0016] However, when the bias current is low, the loop gain of the PTAT circuit can become excessively high, causing that zero to be ineffective at precisely canceling the pole. This elevated loop gain at low bias currents can compromise the overall PTAT circuit stability, leading to poor phase margins and increasing the risk of oscillations. To mitigate these effects, the techniques described herein dynamically adjust an effective resistance and / or bias condition of the PTAT circuit based on a measured current level. Moreover, by maintaining a reliable and stable PTAT circuit maintains reliable temperature dependent biasing of other downstream circuits, such as transimpedance amplifiers coupled to photodiodes in a receiver, across a wide range of conditions.

[0017] In one general aspect, a device includes: a controller configured to receive a current and produce a signal based on the received current; a first transistor and a second transistor, the first transistor having a first size and the second transistor having a second, different size; an amplifier having a first input and a second input, the first input coupled to the first transistor and the second input coupled to the second transistor, wherein the amplifier is configured to produce an output voltage based on a voltage difference between the first input and the second input; a third transistor comprising a first gate and a first drain, the first drain coupled to the first transistor and the first gate coupled to an output of the amplifier; a fourth transistor comprising a second gate and a second drain, the second drain coupled to the second transistor and the second gate coupled to the output of the amplifier; a variable resistor coupled to the first gate and the second gate, wherein the variable resistor is configured to adjust a resistive value according to a signal received from the controller; and a fifth transistor comprising a third gate and a third drain, the third gate coupled to the second gate and the third drain coupled to an input of the controller, wherein the controller is coupled to the third drain and configured to (i) receive theAttorney Docket No. 37136-0128001

[0018] current from the third drain and (ii) produce the signal for the variable resistor based on the received current.

[0019] The foregoing and other embodiments can each optionally include one or more of the following features, alone or in combination. For example, one embodiment includes all the following features in combination.

[0020] In some implementations, the amplifier is configured to produce the output voltage that adjusts current, using the third transistor and the fourth transistor, through the first transistor and the second transistor to reduce the voltage difference between the first input and the second input.

[0021] In some implementations, the device further includes a resistor coupled between the second transistor and the second drain of the fourth transistor.

[0022] In some implementations, a current that flows through the resistor is proportional to a temperature associated with the device.

[0023] In some implementations, the proportionality to the temperature associated with the device is based on the first size of the first transistor and the second, different size of the second transistor.

[0024] In some implementations, the resistor is coupled to one or more components of a transimpedance amplifier, and the current that flows through the resistor is configured to bias the one or more components of the transimpedance amplifier based on a temperature associated with the device.

[0025] In some implementations, the device further includes a capacitor coupled to the variable resistor and to a supply voltage.

[0026] In some implementations, the first transistor is a bipolar junction transistor.

[0027] In some implementations, the amplifier is a differential amplifier.

[0028] In some implementations, the third transistor is a metal-oxide-semiconductor field effect transistor (MOSFET).

[0029] In some implementations, the fourth transistor is a MOSFET.

[0030] In some implementations, the fifth transistor is a MOSFET.

[0031] In some implementations, the third transistor, the fourth transistor, and the fifth transistor operate in a triode region.Attorney Docket No. 37136-0128001

[0032] In some implementations, the first transistor and the second transistor operate in a saturation region.

[0033] In some implementations, the current received by controller is produced in response to the output voltage provided by the amplifier.

[0034] In some implementations, the controller is configured to adjust the resistive value of the variable resistor according to the current received from the fifth transistor.

[0035] In some implementations, the controller is configured to adjust the resistive value of the variable resistor to (i) modify a current provided to at least one of the first transistor and the second transistor and (ii) cause a change in transistor voltages provided by the first transistor and the second transistor to the first input and the second input of the amplifier.

[0036] In some implementations, the controller includes a current-to-digital converter and is configured to: convert the current received from the fifth transistor to an TV bit digital control signal; and provide the TV bit digital control signal to the variable resistor to adjust the resistive value.

[0037] In some implementations, the amplifier, the third transistor, the fourth transistor, and the variable resistor form a closed loop to regulate a first current through the first transistor and a second current through the second transistor.

[0038] In some implementations, the first transistor and the second transistor comprise different emitter areas, the amplifier, the first transistor, the second transistor, the third transistor, and the fourth transistor are coupled in a closed loop configuration to regulate a first current through the first transistor and a second current through the second transistor such that a first voltage at the first input and a second voltage at the second input of the amplifier are within a threshold value of one another, and the resistor coupled between the fourth transistor and the second transistor converts a current produced by the configuration to a voltage that is proportional to a temperature of the device.

[0039] In some implementations, the fifth transistor is coupled to the third transistor and the fourth transistor, and is configured to sense a current generated in response to the voltage produced by the amplifier, and the controller is configured to receive the sensed current from the fifth transistor, and the sensed current is proportional to the voltage produced by the amplifier.Attorney Docket No. 37136-0128001

[0040] In another general aspect, a device includes: a logic gate configured to receive a current and produce a signal based on the received current; a first transistor and a second transistor, the first transistor having a first size and the second transistor having a second, different size; an amplifier having a first input and a second input, the first input coupled to the first transistor and the second input coupled to the second transistor, wherein the amplifier is configured to produce an output voltage based on a voltage difference between the first input and the second input; a third transistor comprising a first gate and a first drain, the first drain coupled to the first transistor and the first gate coupled to an output of the amplifier; a fourth transistor comprising a second gate and a second drain, the second drain coupled to the second transistor and the second gate coupled to the output of the amplifier; a capacitor coupled to the first gate and the second gate; a first resistor coupled in series to a second resistor, the second resistor coupled between the first resistor and the capacitor; a fifth transistor comprising a third gate and a third drain, the third gate being coupled to the second gate and the third drain being coupled to a first input of a logic gate; and a sixth transistor comprising a fourth gate and a fourth drain, wherein the fourth gate is coupled to an output of the logic gate and the fourth drain is coupled to the first resistor and the second resistor, wherein the logic gate comprises the first input and a second input, wherein the first input is coupled to the third drain, the second input is coupled to an enable signal, and the logic gate is configured to output a first voltage to the fourth gate in response to receiving a first current from the fifth transistor.

[0041] The foregoing and other embodiments can each optionally include one or more of the following features, alone or in combination. For example, one embodiment includes all the following features in combination.

[0042] In some implementations, the logic gate is a NOR gate.

[0043] In some implementations, the sixth transistor is in parallel to the first resistor.

[0044] In some implementations, the logic gate is configured to enable the sixth transistor in response to an activation of the enable signal.

[0045] In some implementations, the logic gate is configured to generate the first voltage based on a magnitude of the first current received from the fifth transistor.

[0046] In some implementations, the first current received from the fifth transistor is proportional to a temperature associated with the device.Attorney Docket No. 37136-0128001

[0047] In some implementations, the sixth transistor is configured to bypass at least one of the first resistor and the second resistor in a first operating mode.

[0048] In some implementations, the sixth transistor is configured to not bypass at least one of the first resistor and the second resistor in a second operating mode.

[0049] In some implementations, the sixth transistor is configured to switch between the first operating mode and the second operating mode based on a temperature dependent current received by the logic gate from the fifth transistor.

[0050] In some implementations, the sixth transistor is configured to bypass the first resistor in response to a first magnitude of current received by the logic gate from the fifth transistor.

[0051] In some implementations, the sixth transistor is not configured to bypass the first resistor in response to a second magnitude of current received by the logic gate from the fifth transistor, wherein the first magnitude of current is greater than a second magnitude of current.

[0052] In some implementations, the sixth transistor is configured to bypass the first resistor at a first temperature associated with the device and to not bypass the first resistor at a second temperature of the device, wherein the first temperature is higher than the second temperature.

[0053] In some implementations, the sixth transistor is configured to selectively reduce a resistance of the first resistor and the second resistor by bypassing the first resistor when a current received by the logic gate exceeds a threshold value.

[0054] The subject matter described in this specification can be implemented in various embodiments and may result in one or more of the following advantages. In some implementations, the PTAT circuit described throughout this application can provide improved stability across a variety of operating conditions, including low bias current regimes. By dynamically modifying an overall resistance of the PTAT circuit based on a measured current level, the PTAT circuits can maintain adequate phase margin and minimize the amount of oscillation or transient behavior. Moreover, the techniques described herein can use minimal circuit footprints to dynamically adjust the PTAT circuit parameters to compensate for loop gain dynamics without the use of complex circuitry. As a result, the PTAT circuits can produce stable temperature dependent currents and voltages in high performance communication systems with minimal circuit systems.

[0055] The details of one or more embodiments of the subject matter of this specification are set forth in the accompanying drawings and the description below. Other features, aspects, andAttorney Docket No. 37136-0128001

[0056] advantages of the subject matter will become apparent from the description, the drawings, and the claims.

[0057] BRIEF DESCRIPTION OF THE DRAWINGS

[0058] FIG. 1 is a diagram schematically illustrating an example of circuit packages for data communication over an optical network.

[0059] FIG. 2A is a diagram illustrating an example bi-directional photonic channel for light with a single wavelength.

[0060] FIG. 2B is a diagram illustrating an example bi-directional photonic channel for light with multiple wavelengths using wavelength-division multiplexing (WDM) technology.

[0061] FIG. 2C is a diagram illustrating an example tile including multiple photonic channels. FIG. 2D is a diagram illustrating an example system including multiple tiles.

[0062] FIG. 3A is a diagram schematically illustrating an example structural circuit package. FIG. 3B is a diagram schematically illustrating an example of a circuit package implementing an intra-chip bidirectional photonic channel.

[0063] FIG. 3C is a diagram schematically illustrating an example circuit package implementing an inter-chip bidirectional photonic channel.

[0064] FIG. 3D is a diagram schematically illustrating another example circuit package implementing intra-chip unidirectional lanes for a single wavelength

[0065] FIG. 3E is a diagram schematically illustrating another example circuit package implementing inter-chip unidirectional lanes for multiple wavelengths.

[0066] FIG. 4 is a diagram is a diagram schematically illustrating an example analog-mixed signal (AMS) module including an example interface circuitry coupled between an AMS circuitry and a flow control unit (FLIT) circuitry.

[0067] FIG. 5 is a diagram schematically illustrating an example of the AMS circuitry of FIG. 4. FIG. 6 is a diagram schematically illustrating an example of a transmitter circuit of the AMS circuitry of FIG. 4.

[0068] FIG. 7 is a diagram schematically illustrating an example of a receiver circuit of the AMS circuitry of FIG. 4.

[0069] FIG. 8 is a diagram schematically illustrating an example of a Proportional to Absolute Temperature (PTAT) circuit.Attorney Docket No. 37136-0128001

[0070] FIG. 9 is a diagram schematically illustrating another example of a PTAT circuit with controllable resistance.

[0071] FIG. 10 is a diagram schematically illustrating another example of a PTAT circuit that includes logic gates.

[0072] FIG. 11 is a plot that illustrates a performance margin implemented using a PTAT circuit, in accordance with the present disclosure.

[0073] FIG. 12 is a diagram schematically illustrating an electro-photonic network with a PTAT circuit coupled to or included within a TIA.

[0074] Like reference numbers and designations in the various drawings indicate like elements. The components shown here, their connections and relationships, and their functions, are meant to be examples only, and are not meant to limit the implementations described and / or claimed in this document.

[0075] DETAILED DESCRIPTION FIG. 1 is a diagram schematically illustrating an example of the circuit packages 140 and 160. Each circuit package can include a corresponding PIC 150, 170. Each PIC can include a number of components, e.g., optical couplers such as grating couplers, optical guiding system, optical modulators such as EAMs, photodetectors such as photodiodes (PDs), optical multiplexer(s), and / or optical demultiplexer(s), that can be integrated in the PIC. For illustration, the photodetectors and the photodiodes may be used interchangeably in the specification. These components can be implemented at least partially as waveguides.

[0076] In some implementations, a circuit package, e.g., 140, 160, can include a photonic integrated circuit (PIC), and an electronic integrated circuit (EIC) such as a digital and mixed-signal application-specific integrated circuit (ASIC). The EIC and PIC can be formed in different layers of the circuit package, which can be referred to as “electronic circuit layer” and “photonic circuit layer,” respectively, one stacked above the other, for example, using copper pillars, bump attachments, or other means to create an electrical interconnect to transmit and receive messages, packets, and / or other data between the EIC and the PIC.

[0077] In some implementations, the EIC includes multiple compute nodes. The compute nodes can communicate with each other over one or more intra-chip bidirectional channels. The intrachip bidirectional channels can include one or more bidirectional photonic channels, e.g.,Attorney Docket No. 37136-0128001

[0078] implemented with optical waveguides in the PIC, and / or one or more electronic channels, e.g., implemented in the circuitry of the EIC. The compute nodes may but need not in all examples be electronic circuits identical or at least substantially similar in design, and as shown, may form “tiles” of the same size arranged in a grid or any other arrangement suitable for performing the computations described herein. Each compute node in the EIC can include one or more circuit blocks serving as processing engines, e.g., a dot product engine, DNN, or a tensor engine.

[0079] In some examples, the compute node can have any combination of processing units (or processing elements or processing devices or processing systems) such as CPUs, GPUs, TPUs, and the like, and the DNN and tensor engine can also be included or omitted depending on the application. Each compute node can include a message router. The message routers interface with channels, e.g., electronic and / or photonic channels to facilitate data flow to and from the compute nodes. Further, the compute node can have a memory system, e.g., including level-one static random-access memory (LI SRAM) and lev el -two static random access memory (L2SRAM). In some implementations, a compute node includes a compute block which may include various processing, storage, and / or communication functions, and an Analog Mixed Signal (AMS) block that can include analog / mixed signal circuits for interfacing with the PIC. The compute block can include an interface for communicating with the AMS block, or more specifically, with the componentry of the AMS block.

[0080] A photonic integrated circuit (PIC) can include optical modulators and photodiodes, and an electronic integrated circuit (EIC), e g., including an AMS block, can include modulator drivers and transimpedance amplifiers (TIAs). An optical modulator and a modulator driver can form an optical transmitter (TX), and a photodiode and a TIA can form an optical receiver (RX). In such a way, the circuit package can have at least one photonic transceiver (TX and RX) whose functionality resides partially in the PIC and / or partially in the EIC, which enables the photonic transceivers to send and receive data packets in the optical domain as modulated electromagnetic waves via photonic channels and / or as digital packets via electrical interconnections.

[0081] A photonic interface can include one or more transmitters and / or one or more receivers. The one or more transmitters can be referred to as an electrical-to-optical (EO) interface, and the one or more receivers can be referred to as an optical-to-electrical (OE) interface. That is, a photonic interface can include at least one of an EO interface or an OE interface. A transmitter in one photonic interface can connect with a receiver in another photonic interface to form a one-Attorney Docket No. 37136-0128001

[0082] to-one unidirectional optical path or an optical lane. Unidirectional optical paths form between the two photonic interfaces can be independent from each other, which can avoid crosstalk between different optical paths and / or avoid path length compensation between different optical paths, e.g., when light is continuous wave - CW light.

[0083] When each of the photonic interfaces includes both EO interface and OE interface, the photonic interface can provide bi-directional optical paths for optical signals modulated with data. A bi-directional optical path can include two unidirectional optical paths. As discussed with further details below, a photonic channel can include one or more unidirectional optical paths or one or more bidirectional optical paths.

[0084] To provide a large number of optical paths for high bandwidth data communication between photonic interfaces, circuit packages, e.g., 140, 160, and / or systems, wavelengthdivision multiplexing (WDM) or Dense wavelength-division multiplexing (DWDM) technology can be utilized, such that light with multiple wavelengths can be utilized. In some examples, a photonic channel includes multiple bidirectional optical paths, and a number of the multiple bidirectional optical paths is identical to a number of the multiple wavelengths. A number of unidirectional optical paths can be twice of the number of multiple wavelengths.

[0085] To further increase the number of optical paths, optical splitting or optical dividing technology can be utilized, such that a light beam with a same wavelength can be split into multiple light portions with the same wavelength. In some examples, with the optical splitting technology, a same light source can provide input light for multiple photonic channels and / or multiple tiles each including multiple photonic channels.

[0086] In some implementations, each photonic interface or PIC can receive input light from a corresponding light source 102, 106 via corresponding optical fibers 104, 108, respectively. Each light source 102, 106 can include multiple light elements each providing a corresponding single wavelength of the multiple wavelengths. A number of the multiple light elements can be the number of the multiple wavelengths or multiple times of the number of the multiple wavelengths. A light element can be a laser diode or a laser. In some examples, the light element is configured to emit continuous wave (CW) light. In some examples, the light element is configured to emit pulsed light. In some examples, the multiple wavelengths are in a range from 1,500 nm to 1,600 nm, e.g., in the band of the spectrum referred to as the C-band and / or L-band. In some examples, a difference between adjacent wavelengths is about 10 nm. LightAttorney Docket No. 37136-0128001

[0087] transmitted in a unidirectional optical path can be polarized (e.g., with s polarization) in single mode. An optical fiber, e g., 104, 108, 130, for transmission can be polarization-maintaining single-mode fibers (PM-SMFs).

[0088] In some implementations, a light source can be implemented into the PIC or implemented separately from the PIC either within or externally to the circuit package and coupled to the PIC by suitable optical couplers. For example, the light source can be integrated in a chip or a printed circuit board (PCB) coupled to the circuit package or the PIC, e.g., by suitable optical couplers.

[0089] An optical modulator can be an electro-absorption modulator (EAM), which is a semiconductor device that modulates the intensity of an optical signal by varying absorption of the optical signal as it traverses the modulator based on an electric voltage applied to the EAM. An operation of an EAM can be based on the Franz-Keldysh effect, e.g., a change in the absorption spectrum caused by an applied electric field, which changes the bandgap energy, and thus the photon energy of an absorption edge, but usually does not involve the excitation of carriers by the electric field. EAMs can be made in the form of a waveguide with electrodes for applying an electric field in a direction perpendicular to the modulated optical signal. In some examples, the EAM is implemented in a layer of germanium silicon, e.g., an epitaxially-grown layer of GeSi. Germanium can stoichiometrically constitute 90% or more of the GeSi material, e.g., 95% or more, 96% or more, 97% or more, 98% or more, or 99% or more.

[0090] As illustrated in FIG. 1, one or more photonic channels (unidirectional optical paths and / or bidirectional optical paths) can be formed between the circuit packages 140, 160, or the photonic interfaces 112, 122. For example, light from a first light source 102 can be coupled through optical fibers 104 and grating couplers 151a into a first PIC 150 of the first circuit package 140 and be further guided to optical modulators 153 such as EAMs through an optical guiding system 152a. The optical modulators 153 can modulate the light with data by corresponding modulator drivers in a first EIC of the circuit package 140 to generate modulated light.

[0091] When the light includes multiple light beams each with a single wavelength of multiple wavelengths, modulated light beams with single wavelengths from the optical modulators 153 can be guided or optionally through an optical guiding system 152b to a multiplexer 154. The multiplexer 154 can multiplex the multiple light beams into a multiplexed light beam. TheAttorney Docket No. 37136-0128001

[0092] multiplexed light beam can be coupled out of the first PIC 150 through grating couplers 151b into the optical fibers 130, e.g., PM-SMFs, and then to the second circuit package 160. The multiplexed light beam can be coupled into a second PIC 170 in the second circuit package 160 through grating couplers 171c into a demultiplexer 175. The demultiplexer 175 can demultiplex the multiplexed light beam into multiple light portions each with a corresponding single wavelength. The multiple light portions each with the corresponding single wavelength can be guided, or optionally through an optical guiding system 172c, to photodiodes 176. The photodiodes 176 can convert detected light into electrical data that can be transmitted to corresponding TIAs, e.g., TIAs 177, in the second EIC of the second circuit package 160. In such a way, one or more inter-chip unidirectional optical paths or lanes are formed from the optical modulators 153 in the first PIC 150 to the corresponding PDs 176 in the second PIC 170. Accordingly, one or more inter-package unidirectional data paths are formed from the modulator drivers in the first EIC to the TIAs 177 in the second EIC.

[0093] In some implementations, each of the corresponding TIAs 177 include a PTAT circuit 179. The PTAT circuit 179 can be coupled to or incorporated within the TIA 177. The TIAs 177 are configured to receive an input current from the photodiodes 176. The PTAT circuit 179 can generate a temperature dependent current and supply the temperature dependent current to the TIA to bias its components. Specifically, the PTAT circuit 179 can adjust bias currents, operating points, and other regions of one or more stages of the TIA based on the detected temperature current. In this manner, the PTAT circuit 179 can ensure stable operation of the TIA 177 across varying conditions, such as changes in temperature. In some implementations, the PTAT circuit 179 can influence one or more performance characteristics of the TIA 177, such as saturation behavior and linearity behavior, according to the temperature dependent current.

[0094] In some implementations, one or more intra-chip unidirectional optical paths or lanes can be also formed from optical modulators to corresponding PDs in a same PIC, and accordingly, one or more intra-package unidirectional data paths can be also formed in a same circuit package.

[0095] In some implementations, the first PIC 150 can include a further optical guiding system 152d, e.g., channel waveguides, that can be coupled with one or more EAMs 153 to one or more corresponding PDs 156. Each of the one or more E AM 153 can modulate light with a single wavelength with data from a corresponding modulator driver in a corresponding EIC stackedAttorney Docket No. 37136-0128001

[0096] with the PIC 150 in the same first circuit package 140 and transmit the modulated light through a corresponding channel waveguide of the optical guiding system 152d to a corresponding PD 156 of the one or more corresponding PDs 156 in the same PIC 150. The corresponding PD 156 can convert detected light into electrical data that can be electrically transmitted to a corresponding TIA 167 in the corresponding EIC of the first circuit package 140. Thus, an intra-chip unidirectional optical path or lane is formed from the EAM 153 to the corresponding PD 156 in the first PIC 150, and accordingly, an intra-package unidirectional data path is formed from the corresponding modulator driver in the corresponding EIC through the EAM 153, the corresponding channel waveguide in the optical guiding system 152d, the corresponding PD 156 to the corresponding TIA 167 in the corresponding EIC of the first circuit package 140.

[0097] Similarly, light from a second light source 106 can be coupled through optical fibers 108 and grating couplers 171a into the second PIC 170 of the second circuit package 160 and be further guided to optical modulators 173 such as EAMs through an optical guiding system 172a. The optical modulators 173 modulates the light with data by corresponding modulator drivers in the second EIC of the second circuit package 160 to generate modulated light. When the light includes multiple light beams each with a single wavelength of multiple wavelengths, modulated light beams with single wavelengths from the optical modulators 173 can be guided or optionally through an optical guiding system 172b to a multiplexer 174. The multiplexer 174 can multiplex the multiple light beams into a multiplexed light beam.

[0098] The multiplexed light beam can be coupled out of the second PIC 170 through grating couplers 171b into the optical fibers 130, e.g., PM-SMFs, and then to the first circuit package 140. The multiplexed light beam can be coupled into the first PIC 150 in the first circuit package 140 through grating couplers 151c into a demultiplexer 155. The demultiplexer 155 can demultiplex the multiplexed light beam into multiple light portions each with a corresponding single wavelength. The multiple light portions each with the corresponding single wavelength can be guided or optionally through an optical guiding system 152c to photodiodes 156. The photodiodes 156 can convert detected light into electrical data that can be transmitted to corresponding TIAs 167 in the EIC of the first circuit package 140. In such a way, one or more unidirectional optical paths or lanes are formed from the optical modulators 173 in the second PIC 170 to the corresponding PDs 156 in the first PIC 150. Accordingly, one or moreAttorney Docket No. 37136-0128001

[0099] unidirectional data paths are formed from the modulator drivers in the second ETC to the TIAs 167 in the first EIC.

[0100] In some implementations, each of the corresponding TIAs 167 include a PTAT circuit 169. The PTAT circuit 169 can be coupled to or incorporated within the TIA 167. The TIAs 167 are configured to receive an input current from the photodiodes 156. The PTAT circuit 169 can generate a temperature dependent current and supplies the temperature dependent current to the TIA to bias its components. Specifically, the PTAT circuit 169 can adjust bias currents, operating points, and other regions of one or more stages of the TIA based on the detected current. In this manner, the PTAT circuit 169 can ensure stable operation of the TIA 167 across varying conditions, such as changes in temperature. In some implementations, the PTAT circuit 169 can influence one or more performance characteristics of the TIA 167, such as saturation behavior and linearity behavior, according to the temperature dependent current.

[0101] In some implementations, the second PIC 170 can include a further optical guiding system 172d, e.g., channel waveguides, that can be coupled with one or more EAMs 173 to one or more corresponding PDs 176 in the second PIC 170. Each of the one or more EAM 173 can modulate light with a single wavelength with data from a corresponding modulator driver in a corresponding EIC stacked with the second PIC 170 in the same second circuit package 160 and transmit the modulated light through a corresponding channel waveguide of the optical guiding system 172d to a corresponding PD 176 of the one or more corresponding PDs 176 in the same second PIC 170. The corresponding PD 176 can convert detected light into electrical data that can be electrically transmitted to a corresponding TIA in the corresponding EIC in the second circuit package 160. Thus, an intra-chip unidirectional optical path or lane is formed from the EAM 173 to the corresponding PD 176 in the second PIC 170. Accordingly, an intra-package unidirectional data path is formed from the corresponding modulator driver in the corresponding EIC through the EAM 173, the corresponding channel waveguide in the optical guiding system 172d, the corresponding PD 176 to the corresponding TIA in the corresponding EIC of the second circuit package 160.

[0102] In some implementations, the grating couplers 151a, 151b, 151c in the first PIC 150 can be arranged in an array, that can be coupled, e.g., in and out, with the optical fibers 130, 104 together using a first fiber array unit (FAU) or any other suitable coupling method, e.g., using V grooves for edge-coupled fibers. Similarly, the grating couplers 171a, 171b, 171c in the secondAttorney Docket No. 37136-0128001

[0103] PIC 170 can be arranged in an array, that can be coupled with the optical fibers 130, 106 together using a second fiber array unit (FAU) or any other suitable coupling method, e.g., using V grooves for edge-coupled fibers.

[0104] In some implementations, the optical guiding systems 152a, 152b, and 152c in the first PIC 150 can be configured such that light can be guided in or out from corresponding components in the first PIC 150 in an ordered, efficient way and in a miniaturized area. For example, optical modulators 153 and PDs 156 for each photonic channel are positioned in a same corresponding channel area, and light beams with corresponding single wavelengths can be guided as two groups respectively to the optical modulators 153 and the PDs 156 in the corresponding channel area. Channel areas for different photonic channels are arranged adjacent to each other. The multiplexers 154 and the demultiplexers 155 are arranged further from the channel areas and closer to the grating couplers 151a, 151b, 151c, and can be arranged parallel to one another.

[0105] A multiplexer 154 and a demultiplexer 155 for a same photonic channel can be arranged adjacent to each other. In such a way, light from the optical modulators 153 to the multiplexer 154 and light from the demultiplexer 155 to the PDs 156 can be guided in corresponding waveguides adjacent to each other between a corresponding channel area and an area close to the grating couplers. Similarly, the optical guiding systems 172a, 172b, and 172c in the second PIC 170 can be configured such that light can be guided in or out from corresponding components in the second PIC 170 in an ordered, efficient way and in a miniaturized area.

[0106] FIG. 2A is a diagram illustrating an example bi-directional photonic channel 200 for light with a single wavelength, e.g., Ao. The bi-directional photonic channel 200 includes two unidirectional optical paths or lanes 201a, 201b along opposite directions.

[0107] In a first optical path 201a, first light with the single wavelength Ao from a first light source such as a laser diode 202a is coupled through an optical fiber 203a, e.g., the optical fiber 104 or 108 of FIG. 1, to a first optical modulator 204a, e.g., the optical modulator 153 or 173 of FIG. 1, of a first transmitter. The first optical modulator 204a modulates the first light with data by a corresponding first modulator driver to provide modulated first light. The modulated first light is transmitted through a first optical fiber 205a, e.g., the optical fiber 130 of FIG. 1, to a first photodetector 206b of a first receiver, e.g., the PD 176 or 156 of FIG. 1. The first photodetector 206b can be connected to a corresponding first TIA, e.g., TIA 167 with a PTATAttorney Docket No. 37136-0128001

[0108] circuit 169 from FIG. 1. Thus, the first optical path 201a is formed from the optical modulator 204a to the first photodetector 206b.

[0109] In a second optical path 201b, second light with the single wavelength A from a second light source such as a laser diode 202b is coupled through an optical fiber 203b, e.g., the optical fiber 104 or 108 of FIG. 1, to a second optical modulator 206a, e.g., the optical modulator 153 or 173 of FIG. 1, of a second transmitter. The second optical modulator 206a modulates the second light with data by a corresponding second modulator driver to provide modulated second light. The modulated second light is transmitted through a second optical fiber 205b, e g., the optical fiber 130 of FIG. 1, to a second photodetector 204b of a second receiver, e.g., the PD 176 or 156 of FIG. 1. The second photodetector 204b can be connected to a corresponding second TIA, e.g., TIA 177 with a PTAT circuit 179 from FIG. 1. Thus, the second optical path 201b is formed from the second optical modulator 206a to the second photodetector 204b.

[0110] As discussed above and below, the first optical modulator 204a and the second photodetector 204b can be integrated in a first PIC 204, e.g., the PIC 150 or 170 of FIG. 1, or in a first photonic interface and be connected to the first modulator driver and the second TIA that can be integrated in a corresponding first EIC. The second optical modulator 206a and the first photodetector 206b can be integrated in a second PIC 206, e.g., the PIC 150 or 170 of FIG. 1, or in a second photonic interface and be connected to the second modulator driver and the first TIA that can be integrated in a corresponding second EIC.

[0111] FIG. 2B is a diagram illustrating an example bi-directional photonic channel 210 for light with multiple wavelengths using wavelength-division multiplexing (WDM) technology. The bidirectional photonic channel 200 includes multiple bidirectional optical paths each with a corresponding single wavelength, or multiple pairs of unidirectional optical paths or lanes each with a corresponding single wavelength along opposite directions. For illustration, four wavelengths, e.g., Ao, Xi, X2, X3, are described in the present disclosure. It is understood that a larger or smaller number of wavelengths can be also implemented.

[0112] A first circuit 214 in a first PIC, e.g., the PIC 150 or 170 of FIG. 1, can include multiple modulators 214a, e.g., the optical modulators 153 or 173 of FIG. 1, and multiple photodetectors 214b, e.g., the PDs 156 or 176 ofFIG. 1. The first circuit 214 can also include an optical multiplexer 217a, e.g., the multiplexer 154 or 174 ofFIG. 1, and an optical demultiplexer 218b, e g., the demultiplexer 155 or 175 ofFIG. 1. Each of the multiple photodetectors 214b areAttorney Docket No. 37136-0128001

[0113] coupled to a corresponding TIA, e.g., TIA 167 and PTAT circuit 169 of FIG. 1. A second circuit 216 in a second PIC, e.g., the PIC 150 or 170 of FIG. 1, can include multiple modulators 216a, e.g., the optical modulators 153 or 173 of FIG. 1, and multiple photodetectors 216b, e.g., the PDs 156 or 176 of FIG. 1. The second circuit 216 can also include an optical multiplexer 217b, e.g., the multiplexer 154 or 174 of FIG. 1, and an optical demultiplexer 218a, e.g., the demultiplexer 155 or 175 of FIG. 1. Each of the multiple photodetectors 216b are coupled to a corresponding TIA, e.g., TIA 177 and PTAT circuit 179 of FIG. 1.

[0114] Each optical modulator 214a in the first circuit 214 is configured to receive a light beam with a corresponding single wavelength, e.g., Xo, Xi, i, or X3, from a corresponding laser diode 212a through a corresponding optical fiber 213a. The optical multiplexer 217a in the first circuit 214 multiplexes the multiple light beams from the multiple optical modulators 214a to obtain a multiplexed light beam that can be transmitted through an optical fiber 215a to the corresponding demultiplexer 218a in the second PIC 216. The demultiplexer 218a demultiplexes the multiplexed light beam into multiple light portions each with a corresponding single wavelength to corresponding photodetectors 216b, e.g., Xo, Xi, X2, or X3. Thus, a first group 210a of unidirectional optical paths with the multiple wavelengths is formed between the first circuit 214 and the second circuit 216.

[0115] Similarly, in the second PIC 216, each optical modulator 216a in the second circuit 216 is configured to receive a light beam with a corresponding single wavelength, e.g., Xo, Xi, X2, or X3, from a corresponding laser diode 212b through a corresponding optical fiber 213b. The optical multiplexer 217b in the second circuit 216 multiplexes the multiple light beams from the multiple optical modulators 216a to obtain a multiplexed light beam that can be transmitted through an optical fiber 215b to the corresponding demultiplexer 218b in the first circuit 214. The demultiplexer 218b demultiplexes the multiplexed light beam into multiple light portions each with a corresponding single wavelength to corresponding photodetectors 214b, e.g., Xo, Xi, X2, or X3. Thus, a second group 210b of unidirectional optical paths with the multiple wavelengths is formed between the first circuit 214 and the second circuit 216.

[0116] In some examples, the number of wavelengths is 4. For a photonic channel 210, there can include 4 optical modulators, 4 photodetectors, one optical multiplexer, and one optical demultiplexer in each of the first circuit 214 and the second circuit 216.Attorney Docket No. 37136-0128001

[0117] FIG. 2C is a diagram illustrating an example tile 220 including multiple photonic channels. Each photonic channel, e.g., 210-1, 210-2, 210-3, 210-4 (referred to generally as photonic channels 210 and individually as photonic channel 210), can be the same as, or similar to, the photonic channel 210 of FIG. 2B. For each photonic channel, there are multiple modulators, multiple photodetectors, an optical multiplexer and an optical demultiplexer in a first circuit 214, e.g., the first circuit 214 of FIG. 2B, and a second circuit 216, e.g., the second circuit 216 of FIG. 2B. A first PIC 221a can include multiple first circuits 214 for the multiple photonic channels 210. A second PIC 221b can include multiple second circuits 216 for the multiple photonic channels 210.

[0118] Different from FIG. 2B, for the tile 220, each PIC includes an optical splitting system configured to split light into multiple portions such that a same laser diode can provide light for multiple optical paths or lanes in different photonic channels. For example, a first optical splitting system 222a in the first PIC 221a can split light with a single light beam with a single wavelength, e.g., Ao, Ai, A2, or A3, from each corresponding laser diode 212a into multiple light portions with the same single wavelength for the multiple photonic channels 210-1, 210-2, 210-3, 210-4. A number of the multiple light portions is identical to a number of the multiple photonic channels 210, e.g., 4. Similarly, a second optical splitting system 222b in the second PIC 221b can split light with a single light beam with a single wavelength, e.g., Ao, Ai, A2, or A3, from each corresponding laser diode 212b into multiple light portions with the same single wavelength for the multiple photonic channels 210. A number of the multiple light portions is identical to a number of the multiple photonic channels 210, e.g., 4.

[0119] In some examples, the number of wavelengths is 4 and the tile 220 includes 4 photonic channels 210 corresponding to 32 optical lanes. For a tile, there can include 16 optical modulators, 16 photodiodes, 4 optical multiplexers, and 4 optical demultiplexers in each of the first PIC 221a and the second PIC 221b. That is, for the tile, there are total 32 optical modulators, 32 photodiodes, 8 optical multipliers, and 8 optical demultiplexers. In this instance, for each tile, each of the 32 photodiodes would be coupled to a respective TIA having a PTAT circuit, for a total of 32 TIAs.

[0120] FIG. 2D is a diagram illustrating an example system 230 including multiple tiles. Each tile 220-1, 220-2 (referred to generally as tiles 220 and individually as tile 220) can include multiple photonic channels 210, e.g., 4. For each photonic channel, there are multipleAttorney Docket No. 37136-0128001

[0121] modulators, multiple photodetectors, an optical multiplexer and an optical demultiplexer in a first circuit 214, e.g., the first circuit 214 of FIG. 2B, and a second circuit 216, e.g., the second circuit 216 of FIG. 2B. A first PIC 231a can include multiple first circuits 214 for the multiple photonic channels 210 in the multiple tiles 220. A second PIC 221b can include multiple second circuits 216 for the multiple photonic channels 210 in the multiple tiles 220.

[0122] Similar to FIG. 2C, for the system, each PIC includes an optical splitting system configured to split light into multiple portions such that a same laser diode can provide light for multiple optical paths or lanes in different photonic channels. Different from the optical splitting system in FIG. 2C, the optical splitting system in FIG. 2D is configured to split light into more portions such that each lane in the multiple tiles can receive a light portion.

[0123] For example, a first optical splitting system 232a in the first PIC 231a can split light with a single light beam with a single wavelength, e g., Ao, Xi, X2, or A3, from each corresponding laser diode 212a into multiple light portions, e.g., 8, with the same single wavelength for the total multiple photonic channels 210, e.g., 8, in the multiple tiles 220-1, 220-2, e.g., 2. Similarly, a second optical splitting system 232b in the second PIC 23 lb can split light with a single light beam with a single wavelength, e.g., Ao, Xi, X2, or A3, from each corresponding laser diode 212b into multiple light portions with the same single wavelength for the multiple photonic channels 210.

[0124] In some examples, the number of the multiple wavelengths is 4, and each title 220 includes 4 photonic channels 210, and each channel 210 corresponds to 4 bi-directional optical paths or 8 unidirectional optical paths or lanes. If the system 230 includes two tiles 220, which corresponds to 8 photonic channels 210 and 64 unidirectional optical lanes, the system 230 can include 32 optical modulators, 32 photodiodes, 8 optical multiplexers, and 8 optical demultiplexers in each of the first PIC 231a and the second PIC 23 lb. That is, the system 230 include total 64 optical modulators, 64 photodiodes, 16 optical multipliers, and 16 optical demultiplexers. If the system 230 includes four tiles 220, which corresponds to 16 photonic channels 210 and 128 unidirectional optical lanes, the system 230 can include 64 optical modulators, 64 photodiodes, 16 optical multiplexers, and 16 optical demultiplexers in each of the first PIC 231a and the second PIC 231b. That is, the system 230 include total 128 optical modulators, 128 photodiodes, 32 optical multipliers, and 32 optical demultiplexers. In this case, the system 230 can include a similar number of TIAs as the number of photodiodes.Attorney Docket No. 37136-0128001

[0125] FIG. 3A is a diagram schematically illustrating an example circuit package 300 with more details. In this example, an EIC 310 and a PIC 320, e.g., the PIC 150 or 170 of FIG. 1, are formed in separate semiconductor chips, e.g., silicon chips, although other semiconductor materials may be used. The PIC 320 can be disposed directly on a substrate for subsequent mounting to a printed circuit board (PCB). The EIC 310 and FAUs 302 that connect the PIC 320 to external waveguides 301, e.g., optical fibers, are disposed on top of and optically connected to the PIC 320. The EIC 310 can include ASIC that can be a 5 nm system-on-chip (SOC).

[0126] Optionally, the circuit package 300 can further include an on-chip memory positioned on top of the PIC 320 adjacent to the EIC 310.

[0127] The depicted structure of the circuit package 300 is merely one of several possible ways to assemble and package the various components. In some examples, some or all of the EIC 310 is disposed on the substrate. In some examples, some or all of the PIC 320 is placed on top of the EIC 310. In some examples, it is also possible to create the EIC 310 and PIC 320 in different layers of a single semiconductor chip. In some examples, the photonic circuit layer includes or is made of multiple PICs 320 in multiple sub-layers. Multiple layers of PICs 320, or a multi-layer PIC 320, may help to reduce waveguide crossings. Moreover, the structure may be modified to included multiple EICs 301 connected to a single PIC 320. For example, the multiple EICs 301 may be connected to each other by photonic channels in the PIC 320.

[0128] In some implementations, the EICs and PICs can be manufactured using standard wafer fabrication processes. Further, in some examples, heterogeneous material platforms and integration processes are used. For example, various active photonic components, e.g., the laser light sources and / or optical modulators and photodetectors used in the photonic channels, may be implemented using group III-V semiconductor components.

[0129] The laser light source(s) can be implemented either in the circuit package 300 or externally. When implemented externally, a connection to the circuit package 300 may be made optically using a grating coupler in the PIC 320 underneath an FAU 302 as shown and / or using an edge coupler. In some cases, lasers are implemented in the circuit package 300 by using an interposer containing several lasers that can be co-packaged and edge-coupled with the PIC 320. In some cases, the lasers are integrated directly into the PIC 320 using heterogenous or homogenous integration. Homogenous integration allows lasers to be directly implemented in the silicon substrate in which the waveguides of the PIC 320 are formed, and allows for lasers ofAttorney Docket No. 37136-0128001

[0130] different materials, such as indium phosphide (TnP), and architectures such as quantum dot lasers. Heterogenous assembly of lasers on the PIC 320 allows for group III-V semiconductors or other materials to be precision-attached onto the PIC 320 and optically coupled to a waveguide implemented on the PIC 320.

[0131] Light from fibers or to fibers can be coupled into and out of a PIC using a number of different ways. In some examples, multiple fibers 301, e.g., in an array, and grating couplers in the PIC 320 can be coupled by a FAU 302 which attaches to a surface of the PIC, e.g., the same surface as the EIC, as illustrated. In some examples, the PIC can include edge couplers with V-grooves and the fibers can be positioned on the V-grooves and coupled with their edges to waveguides in the PIC. In some examples, light is coupled in or out from a side of the PIC 320 or in or out from a top surface of the PIC 320.

[0132] In some implementations, multiple circuit packages 300 may be interconnected to result in a single system providing a large electro-photonic network, e.g., by connecting several chiplevel electro-photonic networks. Multiple circuit packages configured as ML processors may be interconnected to form a larger ML accelerator. For example, the photonic channels within the several circuit packages or ML processors, the optical connections, the laser light sources, the passive optical components, and the external optical fibers on the PCB, may be utilized in various combinations and configurations along with other photonic elements to form the photonic fabric of a multi-package system or multi-ML -processor accelerator.

[0133] The PIC 320 can be included in an interposer, and the EIC 210 can be stacked on the PIC 320. As illustrated in FIG. 3A, the PIC 320 can include an optical guiding system 323, e.g., made of channel waveguides. The optical guiding system 323 can include one or more grating couplers 321 attached to the FAU 302, one or more splitter trees 326, and one or more optical modulators, e.g., EAMs, 322 having contacts 325 with one or more modulator drivers, e.g., EAM drivers, 312 in the EIC 310 via attachments 313. In various embodiments, the attachment 313 is a pillar attachment, such as a 50 pm pillar. The PIC 320 can also include one or more photodiodes 324 that can be electronically connected to one or more corresponding transimpedance amplifiers (TIAs) 314 in the EIC 210, e.g., by the attachment 215. The TIAs 314 may integrate corresponding PTAT circuits or may be coupled to the PTAT circuits.

[0134] In various embodiments, in a design like the circuit package 300, an EIC is directly coupled to a PIC, such as shown in FIG. 3A. While FIG. 3 A shows a particular configuration ofAttorney Docket No. 37136-0128001

[0135] a direct coupling between electronic and photonic elements, many other examples are possible. For example, while a copper pillar attachment connects an EAM driver to an EAM as well as connects a photodiode to a TIA, other embodiments for direct coupling, e.g., chip-to-chip packaging, can be used.

[0136] In various embodiments, the EAM is an optical modulation element that enables light to pass between a cathode and an anode. Additionally, the EAM provides thermal stability at over 30 degrees Centigrade and enables the PIC 320 to be packaged directly with one or more processors of the EIC 310 and / or memory chips. The EAM can provide optical connectivity both within a chip and chip-to-chip. In some examples, the EAM can be about 50 microns in size and / or operate at data rates between 50-115 Gbps, at less than 1.0 volt of power, e.g., but up to 2.0 volts.

[0137] FIG. 3B illustrates an example of a circuit package 330 implementing an intra-chip bidirectional photonic channel between a first compute node 334-1 and a second compute node 334-2. The circuit package 330 can be same as or similar to the circuit package 140 or 160 of FIG. 1. The circuit package 330 can include various electronic and optical components implemented across an EIC 210 and a PIC 320.

[0138] The circuit package 330 includes two compute nodes 334-1 and 334-2, collectively, compute nodes 334, which each include a respective compute block 358-1 and 358-2 which may include various processing, storage, and / or communication functions. The compute nodes 334 each include an Analog Mixed Signal (AMS) block 360-1 and 360-2, collectively AMS blocks 360, that includes analog / mixed signal circuits for interfacing with the PIC 320. The compute blocks 358 each include an interface 357-1 and 357-2, collectively interfaces 357, for communicating with the AMS blocks 360, or more specifically, with the componentry of the AMS blocks 360. Each compute block 358 including 358-1 and 358-2 can include a flow control unit (FLIT) circuitry 359 including 359-1 and 359-2, coupled to the interface 357 including 357-1 and 357-2. The FLIT circuitry is configured to create flits or segment data from large data packets, which allows for efficient and reliable data transfer across interconnect networks. The AMS block 360-1, 360-2 can receive data from or transmit data to a processing unit or a memory unit through the FLIT circuitry 359-1, 359-2 and the interface 357-1, 357-2, e.g., as illustrated with further details in FIG. 4.Attorney Docket No. 37136-0128001

[0139] The AMS blocks 360 each include a modulator driver 362-1 and 362-2, collectively drivers 362, and each include a transimpedance amplifier (TIA) 364-1 and 364-2, collectively TIAs 364. Each of the TIAs 364 can include a corresponding PTAT circuit 169 or be coupled to a corresponding PTAT circuit 169. The PIC 320 includes a pair of modulators 356-1 and 356-2 and a pair of photodetectors 366-1 and 366-2. The PIC 320 also includes a grating coupler 354 or other optical interface (OI) configured to receive and pass on light to one or more components and an optical splitter 326.

[0140] In some implementations, e.g., as illustrated with further details in FIG. 5, the EIC 310 includes a reference clock source 331 configured to provide a reference clock signal, e.g., with a clock frequency 200 MHz, to one or more AMS blocks 360-1, 360-2 in the EIC 310. Each AMS block 360-1, 360-2 can generate an operation clock signal, e.g., with an operation frequency of 14 GHz, using the reference clock signal. The operation clock signal can be shared by a plurality of receiver circuits, including the TIAs, and transmitter circuits, including the modulator drivers, to generate TX data signals embedded with clock information to transmit over a photonic network or decode data signals received from a photonic network.

[0141] A light engine 350 can provide light as an optical carrier signal for communication between the first compute node 334-1 and second compute node 334-2. The light engine 350 provides the carrier signal to a FAU 332 of the circuit package 330, such as through an optical fiber. The FAU 332 is optically coupled to the grating coupler 354 which directs the optical carrier signal on to other components of the circuit package 330. The splitter 326 receives the optical carrier signal from the grating coupler 354 and splits the optical signal along two optical paths 370 and 372. More generally, the splitter 326 may distribute the optical carrier signal over any number of photonic paths. The optical paths 370 and 372 may be implemented as any suitable optical transmission medium and may include a mixture of waveguides and optical fibers, or any other suitable transmission medium. In the present example, the optical paths 370 and 372 can be implemented as waveguides in the PIC 320.

[0142] The optical paths 370 and 372 pass from the splitter 326 to the optical modulators 356-1 and 356-2, respectively. Each optical modulator modulates the optical carrier signal it receives from the splitter 326 based on information from its respective optical driver 362-1 and 362-2 and transmits the modulated signal along the respective optical path. A first photodetector 366-1 receives the modulated signal from the optical path, e.g., from the associated modulator 356-2.Attorney Docket No. 37136-0128001

[0143] As depicted, the optical path from modulator 356-1 connects to photodetector 366-2 and the optical path from modulator 356-2 connects to photodetector 366-1. The photodetectors 366-1, 366-2 convert the received modulated signal into respective electrical signal and pass the electrical signals to a transimpedance amplifier 364-1, 364-2 through which the compute nodes 334-1 and 334-2 receive the information encoded in the signals. In this way, communication occurs between the compute nodes through the various components just described. Accordingly, the PIC 320 described here includes an intra-chip bidirectional photonic channel, including two unidirectional photonic links for communicating both to and from each compute node.

[0144] Here, the first unidirectional photonic link is defined by the modulator driver 362-1, the optical modulator 356-1, the optical path 370, the photodiode 366-2, and the transimpedance amplifier 364-2. Similarly, the second unidirectional link is defined by the modulator driver 362-2, the optical modulator 356-2, the optical path 370, the photodiode 366-1, and the transimpedance amplifier 364-1. The first and second unidirectional links operate in opposite directions. Additionally, one or more of the compute nodes 334 may include one or more serializers and / or deserializers for communicating signals between the compute nodes 334. In this way, the two unidirectional photonic links form the intra-chip bidirectional photonic channel.

[0145] FIG. 3C illustrates an example circuit package 340a implementing an inter-chip bidirectional photonic channel between a compute node 334a and an additional compute node 334b located on an additional circuit package 340b, such as a memory node on a memory circuit package. The circuit package 340a, 340b can be same as or similar to the circuit package 140, 160 of FIG. 1, 300 of FIGS. 3A-3B. The compute node 334a and / or the circuit package 340a may include the EIC 310 and the PIC 320 including the components described above with reference to FIG. 3B. Further, the PIC 320 can include a multiplexer 374, e.g., the multiplexer 154, 174 of FIG. 1, or 217a, 217b of FIG. 2B, and a demultiplexer 376, e.g., the demultiplexer 155, 175 of FIG. 1, or 218a, 218b of FIG. 2B. A demultiplexer and multiplexer can be used in a PIC for wavelength division multiplexing of optical signals, e.g., as described in FIGS. 1 and 2B-2D.

[0146] In the inter-chip configuration shown in FIG. 3C, the optical modulator 356 transmits a modulated signal along an optical path 371 to the grating coupler 354. The modulated signal is passed through the multiplexer 374 prior to passing to the grating coupler 354. From the gratingAttorney Docket No. 37136-0128001

[0147] coupler 354, the modulated signal travels through the FAU 332 and along an optical fiber to another grating coupler of the additional circuit package 340b, where the receiving componentry of the additional circuit package 340b receives and processes the incoming signal. The receiving componentry may be the same as or similar to the receiving componentry of the circuit package 330 described above or may include any other means for receiving and processing the incoming signal.

[0148] Similarly, the additional circuit package 340b can generate and transmit a signal to the compute node 334a. The additional circuit package 340b may generate and transmit the signal using transmitting componentry that may include transmitting componentry similar to or the same as that of the circuit package 300 described above, or any other means. The additional circuit package 340b transmits a signal, for example, along an optical fiber to the FAU 332 and grating coupler 354. The signal travels along an optical path 373 to the photodetector 366 which converts the optical signal to an electrical signal as described herein. The received signal passes through the demultiplexer 376 prior to passing to the photodetector 366. In this way, an interchip bidirectional photonic channel is defined by two unidirectional photonic links.

[0149] Here, the first unidirectional photonic link is defined by the modulator driver 362, the optical modulator 356, the optical path 371, the multiplexer 374, the grating coupler 354, the FAU 332, an optical fiber, and receiving componentry of the additional circuit package 340b. Similarly, the second unidirectional photonic link is defined by the transmitting components of the additional circuit package 340b, the optical fiber, the FAU 332, the grating coupler 354, the demultiplexer 376, the optical path 373, the photodetector 366, and the transimpedance amplifier 364, including or coupling to the PTAT circuit 169. The first and second unidirectional photonic links operate in opposite directions. In this way, the two unidirectional photonic links forms the inter-chip bidirectional photonic channel.

[0150] FIG. 3D is a diagram schematically illustrating another example circuit package 380 implementing multiple intra-chip unidirectional lanes for a single wavelength. Note that, as illustrated in FIG. 1, the intra-chip unidirectional lanes for individual wavelengths can be also formed in circuit packages that can implement inter-chip bidirectional photonic channels.

[0151] As illustrated in FIG. 3D, the PIC 320 receives light from a light source 384 that can include a light element, e.g., a laser diode, configured to emit light with a single wavelength . The light source 384 can be internally integrated in the circuit package 380 or externally coupledAttorney Docket No. 37136-0128001

[0152] to the circuit package 380. For example, the light source 384 can be integrated in a printed circuit board (PCB) 382 that can be integrated with the circuit package 380, e.g., through PCIe.

[0153] In some implementations, light with the single wavelength can be split into multiple light portions, e.g., four, as illustrated, with the same single wavelength by a splitter tree 326. Each light portion with the single wavelength can be transmitted through a corresponding channel waveguide 381 to a corresponding EAM 322 in the PIC 320. The corresponding EAM 322 can modulate the light portion with the single wavelength with data from a corresponding EAM driver 312 in the EIC 310 stacked with the PIC 320 in the same circuit package 380, and then transmit the modulated light through another corresponding channel waveguide 383 to a corresponding PD 324 in the same PIC 320. The corresponding PD 324 can convert detected light into electrical data that can be electrically transmitted, e.g., through copper pillar, to a corresponding TIA 314 in the EIC 210 of the circuit package 380. Thus, an intra-chip unidirectional optical path or lane is formed from the EAM 322 to the corresponding PD 324 in the PIC 320, and accordingly, an intra-package unidirectional data path is formed from the corresponding EAM driver 312 in the corresponding EIC 310 through the EAM 322, the corresponding channel waveguides 381, 383 in the PIC 320, the corresponding PD 324 to the corresponding TIA 314 in the corresponding EIC 310 of the circuit package 380. Each of the Lane TIAs 314 can include a corresponding PTAT circuit 315. For example, multiple PTAT circuit 315 can be included within the Lane TIAs 314. If the Lane TIAs 314 include 4 TIAs, then there are 4 PTAT circuits, one PTAT circuit included within or coupled to each TIA.

[0154] For the multiple light portions, e.g., 4, with the same single wavelength, multiple corresponding intra-chip unidirectional optical paths or lanes, e.g., 4, can be formed in the PIC 320, and multiple intra-package unidirectional data paths, e.g., 4, can be formed in the circuit package 380. It is noted that the circuit package 380 can also receive multiple light beams each with a corresponding single wavelength of multiple wavelengths, e.g., X0, I, X2, X3. For each single wavelength of the multiple wavelengths, one or more intra-chip unidirectional optical paths can be formed in the PIC 320 and / or one or more intra-package unidirectional data paths can be formed in the circuit package 380.

[0155] FIG. 3E is a diagram schematically illustrating another example circuit package 390 implementing inter-chip unidirectional lanes for multiple wavelengths. Note that, as illustrated in FIG. 1, FIGS. 2A-2D, and FIGS. 3A-3D, inter-chip bidirectional channels including pairs ofAttorney Docket No. 37136-0128001

[0156] inter-chip unidirectional lanes for each of the multiple wavelengths can be also formed in the circuit package 390.

[0157] As illustrated in FIG. 3E, a first PIC 320a can receive light from a light source 394 that can include multiple light elements, e.g., laser diodes, each configured to emit light with a single wavelength of multiple wavelengths, e.g., 10, XI, X2, X3. The light source 394 can be internally integrated in the circuit package 390 or externally coupled to the circuit package 390. For example, the light source 394 can be integrated in a printed circuit board (PCB) 392 that can be integrated with the circuit package 390, e.g., through PCIe.

[0158] In some implementations, for each light beam with a corresponding single wavelength of the multiple wavelengths, e.g., X0, XI, X2, or X3, an optical guiding system 396 in the first PIC 320a can guide the light beam to one or more corresponding EAMs 322. The optical guiding system 396 can split the light beam into one or more light portions with the same corresponding single wavelength, e.g., using a splitter tree 326 of FIG. 3D. Each light portion with the corresponding single wavelength can be transmitted through a corresponding channel waveguide to a corresponding EAM 322 in the first PIC 320a. The corresponding EAM 322 can modulate the light portion with the single wavelength with data from a corresponding EAM driver 312 in a corresponding EIC 310a stacked with the first PIC 320a in the same circuit package 390. Then corresponding EAMs 322 for the multiple wavelengths can transmit the modulated light portions each with a respective single wavelength of the multiple wavelengths to an optical multiplexer 374 to obtain a multiplexed light beam with the multiple wavelengths. The multiplexed light beam with the multiple wavelengths can be transmitted, e.g., through optical fibers 391, to an optical demultiplexer 376 in a second PIC 320b. The optical demultiplexer 376 can demultiplex the multiplexed light beam into multiple light portions each with a corresponding single wavelength that can be transmitted to corresponding PDs 324 in the second PIC 320b. Each corresponding PD 324 can convert detected light into electrical data that can be electrically transmitted, e.g., through copper pillar, to a corresponding TIA 314 in a second EIC 310b stacked with the second PIC 320b. Each of the Lane TIAs 314 can include a corresponding PTAT circuit 315, similar to the functionality described with respect to FIG. 3D.

[0159] The second PIC 320b and the second EIC 310b can be in a second circuit package different from the circuit package 390, or in the same circuit package 390 as the first PIC 320a and the first EIC 310a. Thus, multiple inter-chip unidirectional optical paths or lanes for theAttorney Docket No. 37136-0128001

[0160] multiple wavelengths, e.g., X0, XI , X2, X3, can be formed from the EAMs 322 in the first PIC 320a to the corresponding PDs 324 in the second PIC 320b, and accordingly, multiple inter-chip or inter-package unidirectional data paths for the multiple wavelengths can be formed from the corresponding EAM drivers 312 in the first EIC 310a through the EAMs 322 in the first PIC 320a to the corresponding PDs 324 in the second PIC 320b then to the corresponding TIAs 314 in the second EIC 310b.

[0161] FIGS. 4 to 7 are diagrams schematically illustrating an example analog-mixed signal (AMS) module 400 that can include a flow control unit (FLIT) circuitry 402, an interface circuitry 404, and an AMS circuitry or AMS block 406. The AMS module 400 can be integrated in an EIC. The EIC can be co-packaged with a PIC in a circuit package. The AMS circuitry 406 can be similar to, or same as, the AMS block 360-1, 360-2 of FIG. 3B. The FLIT circuitry 402 can be similar to, or same as, the FLIT circuitry 359-1 or 359-2 of FIG. 3B. The interface circuitry 304 can be similar to, or same as, the interface 357-1 or 357-2 of FIG. 3B.

[0162] In some implementations, the FLIT circuitry 402 receives data, e.g., TX data in [255:0], from a processing unit or a memory unit, e.g., through a transmission bus 401a, and transmit the data to the AMS circuitry 406 through the interface circuitry 404. The AMS circuitry 406 can further process the data to be an TX analog signal that can be encoded by an optical signal using an optical modulator in the PIC for optical transmission. In some implementations, the AMS circuitry 406 receives an RX analog signal from a photodiode in the PIC and process the RX analog signal to be a RX data signal that can be transferred to the FLIT circuitry 402 through the interface circuitry 404. The FLIT circuitry 402 can further transfer data, e.g., RX data out [255:0], to a memory unit or a processing unit, e.g., through a transmission bus 401b. The interface circuitry 404 can be configured for data transmission between the AMS circuitry 406 and the FLIT circuitry 402. The FLIT circuitry 402 can be configured for efficient and reliable data transfer to / from a processing unit or a memory unit.

[0163] With reference to FIG. 4, the FLIT circuitry 402 includes a FLIT generator 402a coupled to the interface circuitry 404 and configured to transmit a data signal, e.g., from a processing unit or a memory unit, to the interface circuitry 404. The interface circuitry 404 is coupled between the FLIT generator 402a and the AMS circuitry 406. The FLIT generator 402a can be configured to convert input data packets into segmented data in a FLIT format for data transfer.Attorney Docket No. 37136-0128001

[0164] The segmented data in the FLIT format can include control information for routing and error detection and correction. A flit is the smallest unit of data used in network-on-chip (NoC) and other high-performance computing interconnects, and is a part of a larger packet. Each packet can be divided into multiple flits for efficient data transfer. A structure of the Flits can include a header Flit that contains routing information and sets up the path for the subsequent flits, body Flits: carry the actual payload or data, and a tail Flit that marks the end of the packet and may include error-checking information. In some examples, for data with 256 bits, in the FLIT format, cyclic redundancy check (CRC) codes can be arranged in a middle of the 256 bits, and error correction code (ECC) codes and / or other CRC codes can be arranged at the end of the 256 bits.

[0165] In some implementations, e.g., as illustrated in FIG. 4, the interface circuitry 404 includes a medium access control (MAC) sublayer 404a coupled to the FLIT generator 402a, and a plurality of physical coding sublayers (PCSs) 404b coupled between the MAC sublayer 404a and the AMS circuitry 406. Each of the plurality of PCSs 404b is coupled to a respective second AMS circuit of the plurality of second AMS circuits in the AMS circuitry 406. A number of the plurality of PCSs 404b can be identical to a number of second AMS circuits, e.g., 4. For transferring data with 256 bits, each PCS 404b can transmit 64 bits to the respective second AMS circuit.

[0166] The MAC sublayer 404a and the plurality of PCSs 404b are configured for data transmission from the FLIT generator 402a to the plurality of second AMS circuits. In some implementations, the MAC sublayer 404a is configured to identify and correct transmission errors, acknowledge transmission, and / or retransmit data. The MAC sublayer 404a can be coupled to an external memory device 403, e.g., SRAM, that is configured to store data for the MAC sublayer 404a. The external memory device 403 can include a first SRAM for odd bits and a second SRAM for even bits. The PCS 404b can be configured for at least one of data encoding and decoding, scrambling and descrambling, alignment marker insertion and removal, block and symbol redistribution, or lane block synchronization and deskew. For example, the PCS 404b can be configured to encode data to get sufficient rising / falling edges for transmission.

[0167] In some implementations, each of the plurality of PCSs 404b is configured to output a corresponding TX data signal to a corresponding second AMS circuit of the plurality of second AMS circuits. The corresponding second AMS circuit can be configured to generate aAttorney Docket No. 37136-0128001

[0168] transmission clock signal, e.g., with 875 Mbps, and send the transmission clock signal to the PCS 404b, and the PCS 404b can be configured to transfer the corresponding TX data signal to the corresponding second AMS circuit using the transmission clock signal. In such a way, the local frequency of the clock signals of the second AMS circuit and the PCS 404b matches, and signals are synchronized between the AMS circuitry 406 and the interface circuitry 404.

[0169] In some implementations, the FLIT circuitry 402 includes a flow control unit (FLIT) reader 402b coupled to the interface circuitry 404 and configured to convert a data signal from the interface circuitry 404 into segmented data in a FLIT format for data transfer. The interface circuitry 404 is coupled between the FLIT reader 402b and the AMS circuitry 406. The segmented data in the FLIT format can include control information for routing and error detection and correction.

[0170] As illustrated in FIG. 4, the interface circuitry 404 can include a medium access control (MAC) sublayer 404d coupled to the FLIT reader 402b and a plurality of physical coding sublayers (PCSs) 404c coupled between the MAC sublayer 404d and the AMS circuitry 406.

[0171] Each of the plurality of PCSs 404c is coupled to a respective first AMS circuit or RX circuit of the plurality of first AMS circuits. A number of the PCSs 404c can be identical to a number of the first AMS circuits, e.g., 4. In some examples, each PCS 404c can receive 64 bits from the respective first AMS circuit, and the data from 4 PCSs 404c can be converted into 256 bits data.

[0172] The plurality of PCSs 404c and the MAC sublayer 404d are configured for data transmission from the plurality of first AMS circuits to the FLIT reader 402b. In some implementations, the MAC sublayer 404d is configured to identify and correct transmission errors, acknowledge transmission, and / or retransmit data. The MAC sublayer 404d can be coupled to an external memory device 405, e.g., SRAM, that is configured to store data for the MAC sublayer 404d. The PCS 404c is configured for at least one of data encoding and decoding, scrambling and descrambling, alignment marker insertion and removal, block and symbol redistribution, or lane block synchronization and deskew.

[0173] In some implementations, each of the plurality of PCSs 404c is configured to receive a corresponding RX data signal from a corresponding first AMS circuit of the plurality of first AMS circuits, and the MAC sublayer 404d is configured to integrate corresponding RX dataAttorney Docket No. 37136-0128001

[0174] signals, e.g., data with 64 bits, from the plurality of PCSs into an integrated data signal, e.g., data with 256 bits.

[0175] In some implementations, the interface circuitry 404 includes one or more other components, e.g., an interrupt request controller (IRQ) controller 404e, control / status registers 404f, and / or a finite state machine (FSM) 404g. The IRQ controller 404e can receive hardware interrupt events from various sources and presents them to a processing unit, which allows the processing unit to handle real-time events efficiently without constantly polling.

[0176] In some implementations, the FLIT circuitry 402 and the interface circuitry 404 can be connected through an Advanced extensible Interface (AXI) interface 408. The AXI is a communication bus protocol that connects on-chip peripheral circuits to processor cores. The AXI interface 408 can include a first AXI bus 408a, through which the FLIT generator 402a transfer segmented data to the MAC sublayer 404a, and a second AXI bus 408b, through which the MAC sublayer 404d transfers data to the FLIT reader 402b.

[0177] FIG. 5 is a diagram schematically illustrating an example of the AMS circuitry 406 of FIG. 4. As illustrated in FIG. 5, the AMS circuitry 406 includes a plurality of first AMS circuits 504, e.g., RX circuit, and a plurality of second AMS circuits 506, e.g., TX circuit. Each AMS circuit 504 can be coupled to a respective photodiode in the PIC to form a receiver (RX). Each AMS circuit 506 can be coupled to a respective optical modulator, e.g., EAM, in the PIC to form a transmitter (RX). FIG. 6 is a diagram schematically illustrating an example of the second AMS circuit or TX circuit 506 of FIG. 5, and FIG. 7 is a diagram schematically illustrating an example of the first AMS circuit or RX circuit 504 of the AMS circuitry 406 of FIG. 5. There may be fewer or additional transmitters (TX) and receivers (RX) in the AMS block 306 than those shown in FIG. 4.

[0178] In some examples, the AMS circuitry 406 is associated with a channel that can include 4 bi-directional optical paths or 8 unidirectional optical paths or lanes. For example, a first AMS circuit 504, e.g., RX1, and a second AMS circuit 506, e.g., TX1, can be associated with a bidirectional optical path, e.g., as illustrated in FIG. 3B. Similarly, RX2 and TX2, RX3 and TX3, RX4 and TX4 can be associated with respective bi-directional optical paths.

[0179] In some implementations, each first AMS circuit (or RX circuit) 504 is configured to receive a respective RX analog signal from a corresponding photodiode in the PIC and convert the respective RX analog signal into a corresponding RX data signal, and the interface circuitryAttorney Docket No. 37136-0128001

[0180] is configured to convert the corresponding RX data signal into a data signal that can be delivered to the FLIT circuitry 402. In some implementations, the interface circuitry 404 is configured to convert the second data signal into a plurality of TX data signals for the plurality of second AMS circuits 506, and each of the plurality of second AMS circuits 506 is configured to convert a respective TX data signal into a corresponding TX analog signal and deliver the corresponding TX analog signal to a corresponding optical modulator in the PIC for modulating an optical signal with the corresponding TX analog signal.

[0181] In some implementations, e.g., as illustrated in FIG. 5, the AMS circuitry 406 includes a clock signal generator 502 configured to receive a reference clock signal from a reference clock source 501, e.g., the reference clock source 331 of FIG. 3B. The reference clock source 501 can be integrated in the EIC and configured to provide the reference clock signal to one or more AMS circuitries 406 in the EIC, e.g., as illustrated in FIG. 3B.

[0182] The clock signal generator 502 is configured to generate an operation clock signal based on the reference clock signal. The operation clock signal has an operation frequency greater than a clock frequency of the reference clock signal. In some examples, the clock frequency of the reference clock signal is about 200 MHz, and the operation frequency is about 14 GHz. In some examples, the clock signal generator 502 includes an inductor-capacitor phase-locked loop (LCPLL) circuit. The LCPLL circuit can use an LC tank circuit to generate a stable oscillation frequency. The LCPLL circuit includes a closed-loop system that ensures that an output signal remains in phase with an input signal, maintaining a stable and accurate frequency. The LCPLL circuit can include a single-ended LCPLL, a differential LCPLL, a quadrature LCPLL, an injecti on-Locked LCPLL, or a fractional -N LCPLL.

[0183] In the AMS circuitry 406, each first AMS circuit or RX circuit 504 or second AMS circuit or TX circuit 506 can receive the operation clock signal with the operation frequency, e.g., 14 GHz, and can generate corresponding RX signal or TX signal with a corresponding frequency. For example, the second AMS circuit 506 can generate a high speed TX signal, e.g., with a frequency of 56 GHz, for the PIC, while the first AMS circuit 504 can generate a low speed RX signal, e.g., with a speed of 875 Mbps, for a processing unit or a memory unit.

[0184] In some implementations, e.g., as illustrated in FIG. 6, a second AMS circuit or TX circuit 506 is configured to receive the operation clock signal and a TX data signal, e.g., from a processing unit or a memory unit through the FLIT circuitry 402 and the interface circuitry 404,Attorney Docket No. 37136-0128001

[0185] and generate a corresponding TX analog signal using the operation clock signal and the TX data signal. Thus, the corresponding TX analog signal includes both clock information and data information. The operation frequency of the operation clock signal can be greater than a frequency associated with the TX data signal, and smaller than a frequency associated with the corresponding TX analog signal.

[0186] In some examples, the operation clock frequency is 14 GHz, the TX data signal is transferred with 875 Mbps, and the TX analog signal is 56 GHz. As noted above, the corresponding TX analog signal can be delivered to a corresponding optical modulator in the PIC for modulating an optical signal with the corresponding TX analog signal. Thus, the AMS circuitry 406 can combine a low speed data signal from the processing unit or the transmitting unit into a high speed optical signal for the PIC, and the high speed optical signal includes data information embedded clock information. The clock information can be distributed over the photonic network, which can save a lot of power and cost compared to distributing the clock information electronically. The photonic network can connect a number of compute nodes. A compute node can be connected to a remote node, and each compute node is connected to the photonic network. Thus, as long as the photonic network has the clock information, every compute node can have the clock information.

[0187] In some implementations, e.g., as illustrated in FIG. 6, the second AMS circuit or TX circuit 506 includes a first multiplexer 603, an oscillator circuit 601, a second multiplexer 605, and a modulator driver 608. The first multiplexer 603 is configured to convert the TX data signal into a plurality of digital data signals associated with a same transmission speed. The first multiplexer 603 can be a 64:4 multiplexer that can, for example, convert 875 Mbps data into 14 Gbps data. The oscillator circuit 601 is configured to convert the operation clock signal into a plurality of clock signals having the operation frequency with different phases, e.g., 4 clock signals having 14 GHz and 4 different phases. The oscillator circuit 601 can include an integrated logic oscillator (ILO) circuit.

[0188] The second multiplexer 605 is configured to generate an integrated data signal based on the plurality of digital data signals, e.g., 4 digital data signals with 14 Gbps speed, and the plurality of clock signals, e.g., 4 clock signals having 14 GHz and 4 different phases. The second multiplexer 605 can be a 4: 1 multiplexer, and the integrated data signal can be 56 Gbps data. The modulator driver 608 is configured to generate the corresponding TX analog signalAttorney Docket No. 37136-0128001

[0189] based on the integrated data signal. The modulator driver 608 can be an EAM driver, and the TX analog signal can be delivered to a corresponding optical modulator, e.g., EAM, in the PIC for modulating an optical signal with the TX analog signal.

[0190] In some implementations, as the modulator driver 608 in the second AMS circuit can be in direct electrical connection, e.g., by conductive pillars, with the corresponding optical modulator in the PIC, the modulator driver 608 can directly transfer the corresponding TX analog signal to the corresponding optical modulator in the PIC, without data processing on the corresponding TX analog signal, which can increase the transmission speed. The second AMS circuit can include no data processing unit, e.g., no digital signal processor (DSP). As discussed below with further details, a corresponding RX circuit that receives an RX analog signal generated based on the corresponding TX analog signal without processing can include a Feed-Forward Equalizer (FFE) circuit to process, e.g., correct, equalize, or compensate, the RX analog signal.

[0191] In some implementations, the second AMS circuit 506 further includes a correction circuitry 602 coupled to the oscillator circuit 601 and configured to correct timing among the plurality of clock signals having the operation frequency with the different phases. The correction circuitry 602 can include one or more duty cycle correction (DCC) circuits, one or more quadrature error correction (QEC) circuits, or a combination thereof. The second AMS circuit 506 can further include a retimer6504 that has inputs coupled to the correction circuitry 602 and the first multiplexer 603 and an output coupled to the second multiplexer 605. The retimer 604 is configured to retime the plurality of data signals and the plurality of clock signals and output the retimed data signals and the clock signals to the second multiplexer 605. The retimer 604 can include flip-flop logics. The second AMS circuit 506 can further include a data buffer 606 coupled between the second multiplexer 605 and the modulator driver 608. In some examples, the data buffer 606 includes 4 inverters with a fan out of 2 to allow the 4: 1 multiplexer to drive the EAM driver input.

[0192] The correction circuitry 602 and the retimer 604 are configured to get the clock signals, e.g., 4-phase 14GHz clock signals, and the data signal, e.g., 14 Gbps data signals, to the second multiplexer 605, e.g., 4:1 multiplexer, with correct timing. The correction circuitry 02 can be a DCC-QEC circuit that includes capacitance based programmable delays, for correcting quadrature error, and programmable loads for skewing a P / N ratio of an inverter for correctingAttorney Docket No. 37136-0128001

[0193] duty cycle error. The DCC-QEC circuit can include one or more DCC sub-circuits and one or more QEC sub-circuits that are coupled together. The retimer 604 can include one or more levelshifters for shifting data from the 64:4 p2s and flops for selecting the correct time slot for the data and clocks going to the second multiplexer 505, e.g., 4:1 multiplexer.

[0194] The 4: 1 multiplexer can include 25% duty cycle select clock generator and uses gated inverters to multiplex the data. The second multiplexer 605 can also use a dummy multiplexer to route clocks via a low pass filter (LPF) to a probe point that can be measured at a probe pad. Using this probe point, the average values of all clocks (or Duty Cycle) and the average delay between clocks (or skew) can be measured. Based on this measurement, selective delay can be applied to clocks to allow for duty-cycle and quadrature error correction.

[0195] With reference to FIG. 7, a first AMS circuit, e.g., RX circuit, 504 can receive the operation clock signal from the clock signal generator 502, e.g., LCPLL, and a RX analog signal, e.g., from a corresponding photodiode in the PIC, and generate a corresponding RX data signal using the operation clock signal and the RX analog signal. The corresponding RX data signal can be provided to a processing unit or a memory unit through the interface circuitry 404 and the FLIT circuitry 402, e.g., as illustrated in FIG. 4. The operation frequency of the operation clock signal can be greater than a frequency associated with the corresponding RX data signal and smaller than a frequency associated with the RX analog signal. In some examples, the operation frequency is 14 GHz, the RX analog signal has a transfer speed of 56 Gbps, and the RX analog signal has a transfer speed of 875 MHz. The first AMS circuit or RX circuit 504 is configured to convert a high speed optical signal to low speed digital signal for the processing unit or the memory unit.

[0196] In some implementations, e.g., as illustrated in FIG. 7, the first AMS circuit or RX circuit 504 includes a transimpedance amplifier (TIA) 701, a feed-forward equalizer (FFE) circuit 702, a plurality of samplers 704, and a serial-to-parallel (S2P) interface 707 that are coupled in series along a signal path.

[0197] The TIA 701 is configured to amplify a RX analog signal from the corresponding photodiode in the PIC. The FFE circuit 702 is coupled to the TIA 701 and configured to convert the RX analog signal into a plurality of data signals with different phases. The TIA 701 can include or be coupled to a corresponding PTAT circuit 715. The functionality and components of the PTAT circuit 715 will be further described below. The TX analog signal has a higherAttorney Docket No. 37136-0128001

[0198] transfer speed than the plurality of data signals. In some examples, the TX analog signal has a transfer speed of 56 Gbps, while the plurality of data signals has a transfer speed of 14 Gbps. The number of the plurality of data signals can be 4. The 4 data signals can have respective phases, e.g., 0°, 90°, 180°, 270°. The plurality of samplers 704 are coupled to the FFE circuit 702 and each sampler 704 is configured to sample a respective data signal with a corresponding phase.

[0199] A number of the samplers 704 can be identical to a number of the data signals, e.g., for non-retum-to-zero (NRZ) applications, or greater than the number of the data signals, e.g., for duobinary applications. For example, as the first AMS circuit or RX circuit 704 has a quarter rate architecture, each lane needs 4 data path samplers for NRZ applications. To support the duobinary each lane needs 12 samplers. That is, a data signal is sent to 3 samplers 704. A sampler 704 driven by a single phase clock signal can include a double-tail dynamic comparator followed by an SR latch. The comparator determines input differential data either high or low, and generates differential retum-to-zero (RZ) shaped output signals. Then, the SR latch converts comparator outputs to the single-ended rail-to-rail non-return-to-zero (NRZ) data.

[0200] The serial-to-parallel (S2P) interface 707 is coupled to the plurality of samplers 704 and configured to generate a corresponding RX data signal based on outputs from the plurality of samplers 704. The S2P interface 707 can include a digital circuit that converts serial data, data sent one bit at a time, into parallel data, e.g., multiple bits sent simultaneously. In some examples, the first AMS circuit 504 further includes a retimer between the samplers 704 and the S2P interface 707. The retimer can align 4-phase output data from the samplers 704 to support synchronized operation. Incoming Data stream can be demultiplexed by either 8 or 16. There can be 12 input streams for 4 phases, each phase having 3 samples. Output words can be retimed on a common word clock and sent to digital. The S2P interface 707 can feature a 1 : 16 deserializer core, and the 12 data streams can go into 12 cores to generate 192 parallel bits to the digital. With the 1:16 deserializer core, data with 14 Gbps can be converted into data with 875 Mbps.

[0201] In some implementations, the first AMS circuit, e.g., RX circuit, 504 further includes a reference signal generator 705 configured to generate a reference direct current (DC) signal for the plurality of samplers 704.Attorney Docket No. 37136-0128001

[0202] In some implementations, the FFE circuit 702 includes a plurality of thread circuits 703 coupled to the plurality of samplers 704, and each thread circuit 703 is configured to convert the RX analog signal into a respective data signal with a corresponding phase and output the respective data signals with the corresponding phase to one or more corresponding samplers. In some implementations, e.g., as illustrated in FIG. 7, the first AMS circuit or RX circuit 504 includes a first oscillator circuit 710, a phase integrator (PI) 711, and a second oscillator circuit 712. The first oscillator circuit 710 is configured to convert the operation clock signal from the clock signal generator, e.g., LCPLL, 502 into a plurality of first clock signals having the operation frequency with first different phases. The phase integrator (PI) 711 is coupled to the first oscillator circuit 710 and configured to generate a single-phase, adjustable clock signal based on the plurality of first clock signals. The second oscillator circuit 712 is configured to generate a plurality of second clock signals with second different phases based on the singlephase, adjustable clock signal from the phase integrator 711. Each of the plurality of thread circuits 703 is configured to generate the respective data signal based on a corresponding second clock signal.

[0203] In some examples, each of the first oscillator circuit 710 and the second oscillator circuit 712 can be an integrated logic oscillator (ILO) circuit, e.g., the oscillator circuit 601 of FIG. 6. In some examples, the first oscillator circuit 710 receives the operation clock signal from LCPLL to create 8 phases 14 GHz clock signal, which are sent to the PI 611. The PI 611 takes in the 8 phases provided by the first oscillator circuit 710, and produces a single-phase, adjustable clock based on interpolation input codes and subsequently transmits it to the second oscillator circuit 712. The second oscillator circuit 712 receive the operation clock signal from the PI 611 and create 4 phases 14 GHz clock and supply for the FFE circuit 702 / samplers 704.

[0204] In some implementations, the first AMS circuit 504 further includes: a first correction circuitry 714 and a second correction circuitry 716. The first correction circuitry 714 is coupled between the second oscillator circuit 712 and each of the plurality of thread circuits 703 in the FFE circuit 702 and configured to perform correction on the corresponding second clock signal. The first correction circuitry 714 can include a quadrature clock correction (QCC) circuit that corrects duty cycle distortion and phase error. The second correction circuitry 716 is coupled to an input of the first correction circuitry 714 and an output of the S2P interface 707 and configured to balance the second difference phases of the plurality of second clock signals. TheAttorney Docket No. 37136-0128001

[0205] second correction circuitry 716 can include one or more QCC circuits and / or one or more DCC circuits that improve clock signal quality and reduce duty cycle distortion. Each of the plurality of samplers 704 is coupled to the first correction circuitry 714 and configured to receive an output of the first correction circuitry 714 based on the corresponding second clock signal.

[0206] In some implementations, e.g., as illustrated in FIG. 7, the thread circuit 703 includes a pulse generator 703a, a track and hold (T&H) circuit 703b, a variable gain amplifier (VGA) 703c, and a summer 703d. The pulse generator 703a is coupled to an output of the first correction circuitry 714 and configured to generate timing pulses based on the corresponding second clock signal. The track and hold (T&H) circuit 703b is coupled to the pulse generator 703a and configured to smooth the RX analog signal using the timing pulses. The variable gain amplifier (VGA) 703c is coupled to the T&H circuit 703b and configured to amplify the respective RX analog signal with a corresponding gain. The summer 703d is coupled to the VGA 703c and the pulse generator 703a and configured to perform weighted summing on the respective RX analog signal.

[0207] In some implementations, the first AMS circuit 504 further includes a clock data recovery (CDR) circuit 706 configured to receive the corresponding RX data signal and recover a clock signal associated with the corresponding RX data signal. The CDR circuit 706 is coupled to the phase integrator 711 and configured to feed the recovered clock signal back to the phase integrator 711. The plurality of second clock signals can be generated based on the recovered clock signal.

[0208] In some implementations, the first AMS circuit 504 further includes an FFE feedback circuit 708 coupled between an output of the S2P interface 707 and the FFE circuit 702 and configured to feed the corresponding RX data signal back to the FFE circuit 702. The FFE feedback circuit 708 can include an FFE Tap adaption configured for improving a quality of an optical eye diagram from a corresponding optical modulator.

[0209] FIG. 8 is a diagram schematically illustrating an example of a Proportional to Absolute Temperature (PTAT) circuit 800. The PTAT circuit 800 can correspond to PTAT circuit 169 and PTAT circuit 179 of FIG. 1, PTAT circuit 169 of FIG. 3B, PTAT circuit 169 of FIG. 3C, PTAT circuit 315 ofFIG. 3D, PTAT circuit 315 of FIG. 3E, or PTAT circuit 715 ofFIG. 7.

[0210] In some implementations, the PTAT circuit 800 includes an input transistor QI and an input transistor Q2. The input transistors QI and Q2 are configured to generate a pair ofAttorney Docket No. 37136-0128001

[0211] temperature sensitive input voltages. For example, these transistors are arranged to provide input voltages that vary with temperature and form the basis for the PTAT current generation. In some implementations, these input transistors QI and Q2 may be implemented as bipolar junction transistors that provide high sensitivity to temperature variations and enable precise temperature dependent current generation.

[0212] Depending on the implementations, input transistors QI and Q2 can be implemented using various transistor types. For example, input transistors QI and Q2 can be implemented using bipolar junction transistors (BJTs) or metal-oxide-semiconductor field-effect transistors (MOSFETs). For example, by utilizing BJTs, the input transistors QI and Q2 capitalize on the inherent temperature sensitivity of the base-emitter voltage. In some implementations, the input transistors QI and Q2 can include different effective emitter areas. For example, Q2 may include an emitter area that 24x the emitter area included in QI . The different emitter areas can cause the input transistors to operate at with different current densities whne biased, and provide for different base emitter voltages that depend on temperature. Moreover, by utilizing BJTs with different emitter areas, the input transistors QI and Q2 can capitalize on the inherent temperature sensitivity of the base emitter voltage. The different in base emitter voltages between transistors QI and Q2 can vary predictably with temperature, and provide for the generation of PTAT voltage or current. As a result, the use of input transistors QI and Q2 with different emitter areas allow for precise control over temperature dependent current generation.

[0213] BJTs can be particularly effective for PTAT circuits because their base-emitter voltage decreases predictably as temperature increases, producing a voltage that varies substantially linearly with temperature. For example, the use of BJTs for input transistors QI and Q2 allow for precise control over the temperature dependent current output, while enhancing the accuracy and stability of the PTAT circuit 800 across a wide range of operating conditions.

[0214] An operational amplifier, e.g., op amp 30, is configured as a differential amplifier to produce a reference voltage based on the input voltages provided from the input transistors QI and Q2. The op amp 30 outputs a reference voltage by comparing a difference between the input voltages. The reference voltage is provided to the gates of two current source transistors, e.g., Ml and M2, which are configured to generate the main source of PTAT current. These current source transistors each include a gate and a drain, where the drains are coupled to their corresponding input transistors to ensure accurate temperature tracking behavior. For example,Attorney Docket No. 37136-0128001

[0215] the drain of the current source transistor M2 connects or couples to the emitter of the input transistor QI and the drain of the current source transistor Ml connects or couples to the emitter of the input transistor Q2.

[0216] In some implementations, the op amp 30 operates in a closed loop configuration and generates an output reference voltage based on a difference between the first input voltage and the second input voltage from the input transistors QI and Q2. The output reference voltage is continuously adjusted to regulate currents in the PTAT circuit such that the voltage difference between the first input voltage and the second input voltage is minimized. For example, op amp 30 may continue to output the reference voltage to maintain the minimized voltage difference between the first input voltage and the second input voltage from the input transistors QI and Q2.

[0217] By basing the reference voltage output from the op amp 30 on the pair of input voltages from the input transistors QI and Q2, the op amp 30 can stabilize the current source transistors Ml and M2 and ensure that the output current across the resistor Rp accurately reflects changes in temperature associated with the PTAT circuit 800. The resistor Rp can convert the PTAT current generated by the current source transistors into a voltage or current that is proportional to temperature associated with the PTAT circuit 800.

[0218] In some implementations, the current that flows through the resistor Rp, which represents the current derived from temperature, can be supplied to one or more biasing nodes of a transimpedance amplifier coupled to the PTAT circuit 800. As a result, this supplied current is configured to bias one or more components of the transimpedance amplifier, including its various gain stages and current mirrors, so that the transimpedance amplifier is regulated based on temperature.

[0219] In some implementations, the PTAT circuit 800 includes a compensation network that includes a compensation capacitor Cc and a compensation resistor Rc. The compensation network is configured to provide frequency compensation for the PTAT circuit 800, with Cc and Rc forming a lead lag network that introduces a zero in the PTAT circuit 800’ s frequency response. This zero counteracts a dominant pole that would otherwise compromise the PTAT circuit 800’s stability and thereby, improving the PTAT circuit 800’s phase margin. In some implementations, the compensation network can adjust the resistance of RC using the current produced by the current source transistors Ml and M2 to maintain stability. Specifically, whenAttorney Docket No. 37136-0128001

[0220] the current from the current source transistors is low, the compensation network increases Rc to lower the zero frequency of the loop gain. This enhances the PTAT circuit 800’ s stability. At higher load current, loop gain is naturally reduced and a smaller resistance of Rc is utilized, which allows the PTAT circuit 800 to improve, e.g., optimize, phase margin across a wide range of load or temperature conditions.

[0221] In some implementations, the compensation network enhances stability by improving the phase margin across varying load currents. The compensation network is useful in improving the phase margin, especially at low load currents where high loop gain affect the stability in the PTAT circuit 800. For example, the zero introduced by the compensation network is configured to counteract the second dominant pole in the circuit’s frequency response. The zero’s location in the frequency domain is influenced by the inverse product of Rc and the parasitic capacitance Cl at node X, which is calculated and approximated by - . Using this calculated zero, the

[0222]

[0223] compensation network can cancel the effects of the second dominant pole, and as a result, increase the phase margin and improve the stability of the PTAT circuit 800. An increased phase margin can result in a reduced likelihood of oscillations and an improved transient response characteristics. This is important for maintaining reliable performance in applications that rely on stable temperature dependent current outputs.

[0224] In some implementations, the PTAT circuit 800 can operate in different regiments depending on a magnitude of the generated PTAT current. At lower current levels, such as during circuit startup or low temperature operation, the compensation network can increase the resistance Rc to reduce loop gain and maintain adequate phase margin. However, at higher current levels, the resistance Rc is reduced to improve transient response without compromising the circuit stability, e g., which shifts the compensation zero to a higher frequency.

[0225] As a result, the compensation network illustrated in PTAT circuit 800 can address various challenges when PTAT circuits are destabilized due to poles in the circuits frequency response. For many PTAT circuits, challenges do arise at low load currents, where the loop gain of the PTAT circuit is elevated due to the high impedance of the current source transistors Ml and M2. At these low load currents, the loop gain may be so high that the zero created by the Cc and Rc network is insufficiently to completely cancel the dominant pole. This results in a reduction in phase margin. More specifically, the phase margin is usually low at low load currents, and gradually improving as the load current increases and the loop gain decreases. As a result, theAttorney Docket No. 37136-0128001

[0226] PTAT circuits utilized and described in this application seeks to ensure they remain stable during startup and low current conditions, and protect that circuit from undesirable oscillations which can reduce the accuracy of the circuit producing temperature dependent voltages and currents.

[0227] FIG. 9 is a diagram schematically illustrating another example of a PTAT circuit 900 with controllable resistance. The PTAT circuit 900 can correspond to PTAT circuit 169 and PTAT circuit 179 of FIG. 1, PTAT circuit 169 of FIG. 3B, PTAT circuit 169 of FIG. 3C, PTAT circuit 315 of FIG. 3D, PTAT circuit 315 of FIG. 3E, or PTAT circuit 715 of FIG. 7.

[0228] In some implementations, the PTAT circuit 900 is similar to the PTAT circuit 800.

[0229] However, the PTAT circuit 900 includes a feedback controller 902 and a variable resistor 904. In some implementations, the PTAT circuit 900 dynamically adjusts the compensation network in order to maintain stability across varying current loads. In particular, and as illustrated in FIG.

[0230] 9, the PTAT circuit 900 leverages a feedback-controlled variable resistance to improve the phase margin and ensure stable operation.

[0231] As illustrated in FIG. 9, the PTAT circuit 900 is coupled to a supply voltage Vdd, which provides the operating potential for powering the various components of the PTAT circuit 900. The PTAT circuit 900 includes the two input transistors QI and Q2, which are configured to generate the temperature sensitive voltages. Here, the input transistors QI and Q2 provide a voltage differential proportional to the absolute temperature. The voltage differential serves as the basis for generating a stable, temperature dependent output current. The input transistors QI and Q2 are coupled to two current source transistors Ml and M2, which are configured to provide the PTAT current. As illustrated in FIG. 9, the gates of Ml and M2 are driven by a reference voltage produced by an operational amplifier, e.g., op amp 30, based on a difference between the inputs provided to the op amp 30 from the input transistors QI and Q2. For example, the op amp 30 is configured as a differential amplifier, which ensures that the reference voltage is derived from the temperature dependent input voltages.

[0232] In some implementations, the PTAT circuit 900 includes a compensation network, which includes a variable resistor (VR) 904 and a compensation capacitor Cc. The variable resistor VR 904 may be implemented as a digitally controlled resistor array, allowing its resistance to be adjusted in response to a control signal provided by the feedback controller 902. The compensation capacitor Cc works in conjunction with the variable resistor 904 to introduce a zero in the frequency response, which improves the phase margin of the PTAT circuit 900. TheAttorney Docket No. 37136-0128001

[0233] zero cancels a dominant pole in the loop gain, enhancing stability, especially at low load currents where the loop gain is naturally higher.

[0234] The PTAT circuit 900 also includes an output transistor M3, which is coupled to the current source transistors Ml and M2. The gate of the output transistor M3 is coupled to the gates of the current source transistors Ml and M2. The drain of the output transistor M3 provides a sensed current representative of the PTAT current 900 produced by the current source transistors Ml and M2 to the feedback controller 902 without substantially affecting the operation of the PTAT circuit 900. In some implementations, the output transistor M3 forms part of a current mirror with the current source transistors Ml and M2, such that the current provided at the drain of M3 is representative of the PTAT current generated by the circuit. In this manner, the output reference voltage from the op amp 30 controls the gate voltages of the current source transistors Ml and M2, which causes a current sensed by the output transistor M3 to vary proportionally with the reference voltage output by the op amp 30.

[0235] The output current is provided to and monitored by the feedback controller 902, which generates a control signal to dynamically adjust the variable resistor 904 according to a magnitude of the received current. The control signal increases the resistance of the variable resistor 904 when the input current to the feedback controller 902 is low or below a threshold value and shifts the zero in the PTAT circuit 900’ s frequency response to improve the phase margin of the PTAT circuit 900. Conversely, the control signal decreases the resistance of the variable resistor 904 when the input current to the feedback controller 902 is high or meets or exceeds the threshold value, which allows for maintaining stability of the PTAT circuit 900 under different load conditions.

[0236] In some implementations, the feedback controller 902 includes a current-to-digital converter that measures a magnitude of the received current and converts the magnitude into a digital code. The feedback controller 902 utilizes the digital code to adjust the resistance of the variable resistor 904, which ensures precise control over the compensation network in the PTAT circuit 900. Depending on the current range and the desired phase margin, the current-to-digital converter can output an n-bit digital control signal. A single bit signal may be utilized to ensure stability across various operating conditions of the PTAT circuit, such as different process, voltage, and temperature (PVT) variations. Using the feedback control signal that is based on the output current, the feedback controlled compensation network allows the PTAT circuit toAttorney Docket No. 37136-0128001

[0237] adapt its stability mechanism to varying operation conditions. This adaptability ensures that the PTAT circuit 900 maintains an optimal phase margin across a range of load currents and temperature variations, which prevent oscillations and improve performance. The inclusion of a digitally controlled variable resistor can add flexibility to the design of the PTAT circuit 900 and enable precise tuning of the compensation network for specific applications. This technique ensures that the PTAT circuit is suitable for use in environments requiring high stability and reliability.

[0238] In some implementations, the PTAT circuit 900 may employ different methods for adjusting the resistance of the variable resistor 904 based on the output current or another operation condition. For example, the feedback controller 902 may output an analog control signal to continuously adjust the variable resistance of the variable resistor 904. This analog control signal can vary proportionally with changes in the output current.

[0239] In some implementations, the feedback controller 902 can include an analog-to-digital converter (ADC) and a voltage controlled resistor in place of a digitally controlled resistor array. In these configurations, the output current is converted into an analog voltage that directly adjusts the variable resistor’s resistance. This alternative allows the PTAT circuit 900 to continuously adapt to changes in output current and provide stability improvements with lower latency than purely digital control methods.

[0240] FIG. 10 is a diagram schematically illustrating another example of a PTAT circuit 1000 that utilizes logic gates. The PTAT circuit 1000 can correspond to PTAT circuit 169 and PTAT circuit 179 of FIG. 1, PTAT circuit 169 of FIG. 3B, PTAT circuit 169 of FIG. 3C, PTAT circuit 315 of FIG. 3D, PTAT circuit 315 of FIG. 3E, or PTAT circuit 715 of FIG. 7.

[0241] In some implementations, the PTAT circuit 1000 is similar to the PTAT circuits 800 and 900. However, the PTAT circuit 1000 includes a compensation network with a selectable resistor and a logic gate 1002 to improve phase margin at low load currents. The logic gate 1002 can include, for example, a NAND gate, a NOR gate, an AND gate, an inverter, or another type of logic gate. The PTAT circuit 1000 is coupled to a supply voltage Vaa, which provides the operating potential for the circuit components.

[0242] In some implementations, the PTAT circuit 1000 includes a pair of input transistors QI and Q2, which are configured to generate a pair of temperature sensitive input voltages. These input voltages are utilized by the PTAT circuit 1000 to provide a temperature dependent outputAttorney Docket No. 37136-0128001

[0243] current. For example, the input transistors QI and Q2 are coupled to the current source transistors Ml and M2, which are driven by a reference voltage generated by an operational amplifier, e.g., op amp 30. For example, the op amp 30 is configured as a differential amplifier, which ensures accurate derivation of the reference voltage from the input voltages provided by the input transistors QI and Q2. For example, the reference voltage produced by the op amp 30 stabilizes the operation of the current source transistors Ml and M2 and enables control of the PTAT circuit 1000.

[0244] The compensation network shown in the PTAT circuit 1000 includes two compensation resistors R1 and R2. The compensation resistors R1 and R2 are configured in series with a compensation capacitor Cc. The resistor R1 is always active in the compensation network, while resistor R2 can be selectively bypassed by a compensation transistor MS. The compensation transistor MS functions as a selectively enabled bypass transistor that modifies a resistance of the compensation network in the PTAT circuit 1000. As shown, the gate of MS is controlled by the output of the logic gate 1002. When MS is active, the transistor MS bypasses R2, leaving only R1 in the PTAT circuit 1000. When MS is inactive, both R1 and R2 are included in the PTAT circuit 1000, which increases the total resistance. For example, the selective control of R2 enables the PTAT circuit 1000 to adjust its compensation resistance based on load current conditions.

[0245] The compensation capacitor Cc is coupled to resistor R2 and to the gate of Ml. Together with the compensation resistors, compensation capacitor Cc introduces a zero in the frequency response of the PTAT circuit 1000. The introduced zero counteracts a dominant pole in the loop gain and improves the PTAT circuit 1000’s phase margin. This compensation mechanism is particularly effective at low load currents, where high loop gain can compromise stability.

[0246] The PTAT circuit 1000 includes an output transistor M3, which is coupled to Ml and provides the PTAT output current. The drain of M3 is connected to the output resistor RS, which converts the output current into a voltage. This voltage serves as an input to the logic gate 1002. Another input of the logic gate 1002 is the enable signal En. For example, the logic gate 1002 enables or disables the bypass of R2 by activating or deactivating the MS based on the load current from the output transistor M3. When the load current is high, the voltage across RS is high, which causes the output of the logic gate 1002 to be low. When the output of the logic gate 1002 is low, the transistor MS is activated. An activation of the transistor MS bypasses resistorAttorney Docket No. 37136-0128001

[0247] R2 and leaves only resistor R1 in the compensation network. For example, the resistance values of resistors R1 and R2 are predetermined, and the reduction in overall compensation resistance is sufficient to maintain stability at higher load currents due to the naturally lower loop gain in these conditions. Conversely, the load current is low, the voltage across RS is low, causing the output of the logic gate 1002 to be high. When the output of the logic gate 1002 is high, the transistor MS is deactivated. A deactivation of the transistor MS enables R2 in series with Rl, and increases the total compensation resistance. For example, the increased resistance shifts the zero in the frequency response to a lower frequency, improving the phase margin at low load currents and enhancing the PTAT circuit 1000’s stability. By switching the effective compensation resistance based on the load current, the PTAT circuit 1000 can adjust a location of a zero in the frequency response relative to the loop gain.

[0248] In some implementations, one or more of the transistors Ml, M2, M3, and MS are operated in a linear region or triode region. In this region, these transistors function as controllable resistive elements that translate a gate controlled voltage into a proportional current. By operating these transistors in a linear operating region, the PTAT circuits, e.g., PTAT circuit 800, 900, and 1000, can accurately sense current levels that are indicative of temperature associated with the circuit. In some implementations, the input transistors QI and Q2, which are bipolar junction transistors, can operate in a forward active region. By operating the input transistors QI and Q2 in a forward active region, these transistors produce predictable baseemitter voltages that vary with temperature. In this manner, the input transistors QI and Q2 can accurately generate voltages and currents used by the PTAT circuit based on temperature.

[0249] The PTAT circuit 1000 provides an efficient method for adjusting the compensation resistance using a single bit control mechanism. By selectively enabling or disabling resistor R2 based on the load current across RS, the PTAT circuit 1000 can maintain stability across a wide range of operating conditions. Accordingly, the PTAT circuit 1000 operates in a first mode in which resistor R2 is bypassed at higher load currents input to the logic gate 1002 and a second mode in which resistors Rl and R2 are both active at lower load currents input to the logic gate 1002.

[0250] FIG. 11 is a plot that illustrates a performance margin of a PTAT circuit. In particular, the plot illustrates a comparison of the phase margin of a potential PTAT circuit and a PTATAttorney Docket No. 37136-0128001

[0251] circuit with adjustable compensation. The x-axis represents the load current in microamperes (uA), while the y-axis shows the phase margin in degrees.

[0252] The phase margin is an important metric in circuit stability, with higher values indicating a preferable design less prone to circuit oscillations. The conventional design, represented by the diamond in FIG. 11, illustrates a significant reduction in phase margin at low load currents. Specifically, at load currents below 10 uA, the phase margin for conventional design deteriorates rapidly, reaching values as low as about 7 degrees. This degradation is due to insufficient compensation at low currents, where the loop gain is higher, and leads to PTAT circuit instability.

[0253] In contrast, a PTAT circuit according to the techniques described in this specification, represented by the square line, maintains a consistently high phase margin across all load currents. The PTAT circuits described in this specification can utilize a compensation network with dynamically adjustable resistance, controlled by a feedback mechanism. At low load currents, the compensation resistance is increased by enabling a second resistor in series with the compensation network, effectively shifting the zero in frequency response to counteract the dominant pole. This adjustment improves the phase margin elevating it from 7 degrees in the conventional design to approximately 50 degrees in the enhanced PTAT circuit design, as described throughout this specification, at low load currents, for example.

[0254] For example, using the PTAT circuit 1000 as an example, as the load current increases beyond the threshold of 10 uA, the logic gate 1002, e.g., the NOR gate, deactivates the second resistor R2, which reduces the compensation resistance to its lower value. This reduction is sufficient to maintain stability at higher currents, where the loop gain is naturally lower.

[0255] FIG. 12 is a diagram schematically illustrating an electro-photonic network with a PTAT circuit coupled to or included within a TIA. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

[0256] As an example, FIG. 12 shows the configuration of an application-specific integrated circuit (ASIC) 1201 situated above a photonic integrated circuit (PIC) 1202. Various tiles 1203 A, 1203B, 1203C, and 1203D within the ASIC are shown, along with the electro-optic (EO) and optoelectronic (OE) interface components that facilitate communication between these tiles through optical links in the PIC. The optical signals in the PIC are coupled to external systemsAttorney Docket No. 37136-0128001

[0257] via an optical fiber 1233 connected to the fiber array unit (FAU) 1232. For example, the light is coupled into the PIC using a grating coupler 1220, which directs the light to the EAMs 1204 A, 1204B, 1204C via waveguides 1222.

[0258] The modulator drivers, e.g., 1202A, 1202B, 1202C, and 1203D are electronic components situated within the ASIC 1201 in tiles 1203 A, 1203B, 1203C, and 1203D. These drivers are responsible for generating the electrical signals that modulate light within the EAMs, e.g., 1204A, 1204B, 1204C, which are configured directly beneath the drivers in the PIC 1202. For example, the EAMs convert the electrical signals from the modulator drivers into modulated optical signals that can be transmitted through the optical waveguides, e.g., 1200AB, 1200BC, 1200CD, embedded in the PIC. As shown, the waveguides form the optical links between the tiles, enabling high-speed intrachip communication.

[0259] In FIG. 12, TIAs, e g., 1206B, 1206C, 1206D, transimpedance amplifiers for converting small current signals generated by the photodetectors, e.g., PDs 1208B, 1208C, 1208D, into amplified voltage signals that can be further processed by the system. For example, the photodetectors first convert incoming optical signals into electrical current. For example, the PDs are located in the PIC directly beneath the TIAs, ensuring that the distance between the optical and electronic components is minimal. In some implementations, one or more PTAT circuits 1209B, 1209C, and 1209D are respectively coupled to or integrated within the TIAs 1206B, 1206C, and 1206D. The PTAT circuits 1209B, 1209C, and 1209D are configured to generate temperature dependent bias currents or voltages to regulate the operation of the corresponding TIAs 1206B, 1206C, and 1206D. This ensures that the TIAs remain in stable condition as temperature and load changes based on the photodetector current.

[0260] It is to be appreciated that the close alignment between the electronic components, e.g., modulator drivers, TIAs, in the ASIC 1201 and the photonic components, e.g., EAMs, PDs, in the PIC 1202 is important for reducing or minimizing, the distance over which electrical and optical signals travel. This reduces, e.g., minimizes, latency and reduces the power needed for signal conversion. Additionally, the heat generated by the electronic components in the ASIC can help maintain the EAMs and PDs in the PIC at favorable, e.g., optimal, operating temperatures, enhancing the overall thermal stability and performance of the system.

[0261] EMBODIMENTSAttorney Docket No. 37136-0128001

[0262] Although the present invention is defined in the claims, it should be understood that the present invention can also (alternatively) be defined in accordance with the following embodiments:

[0263] 1. A system for enhancing PTAT circuits, the system comprising:

[0264] a controller configured to receive a current and produce a signal based on the received current;

[0265] a first transistor and a second transistor, the first transistor having a first size and the second transistor having a second, different size;

[0266] an amplifier having a first input and a second input, the first input coupled to the first transistor and the second input coupled to the second transistor, wherein the amplifier is configured to produce an output voltage based on a voltage difference between the first input and the second input;

[0267] a third transistor comprising a first gate and a first drain, the first drain coupled to the first transistor and the first gate coupled to an output of the amplifier;

[0268] a fourth transistor comprising a second gate and a second drain, the second drain coupled to the second transistor and the second gate coupled to the output of the amplifier;

[0269] a variable resistor coupled to the first gate and the second gate, wherein the variable resistor is configured to adjust a resistive value according to a signal received from the controller; and

[0270] a fifth transistor comprising a third gate and a third drain, the third gate coupled to the second gate and the third drain coupled to an input of the controller,

[0271] wherein the controller is coupled to the third drain and configured to (i) receive the current from the third drain and (ii) produce the signal for the variable resistor based on the received current.

[0272] 2. The system of embodiment 1, wherein the amplifier is configured to produce the output voltage that adjusts current, using the third transistor and the fourth transistor, through the first transistor and the second transistor to reduce the voltage difference between the first input and the second input.

[0273] 3. The system of any one of embodiments 1-2, further comprising a resistor coupled between the second transistor and the second drain of the fourth transistor.Attorney Docket No. 37136-0128001

[0274] 4. The system of embodiment 3, wherein a current that flows through the resistor is proportional to a temperature associated with the device.

[0275] 5. The system of embodiment 4, wherein the proportionality to the temperature associated with the device is based on the first size of the first transistor and the second, different size of the second transistor.

[0276] 6. The system of embodiment 4, wherein the current that flows through the resistor is configured to bias one or more components of a transimpedance amplifier based on a temperature associated with the device.

[0277] 7. The system of any one of embodiments 1-6, further comprising a capacitor coupled to the variable resistor and to a supply voltage.

[0278] 8. The system of any one of embodiments 1-7, wherein the first transistor is a bipolar junction transistor.

[0279] 9. The system of any one of embodiments 1-8, wherein the amplifier is a differential amplifier.

[0280] 10. The system of any one of embodiments 1-9, wherein the third transistor is a metal -oxide-semiconductor field effect transistor (MOSFET).

[0281] 11. The system of any one of embodiments 1-10, wherein the fourth transistor is a MOSFET.

[0282] 12. The system of any one of embodiments 1-11, wherein the fifth transistor is a MOSFET.

[0283] 13. The system of any one of embodiments 1-12, wherein the current received by controller is produced in response to the output voltage provided by the amplifier.

[0284] 14. The system of embodiment 13, wherein the controller is configured to adjust the resistive value of the variable resistor according to the current received from the fifth transistor.

[0285] 15. The system of embodiment 13, wherein the controller is configured to adjust the resistive value of the variable resistor to (i) modify a current provided to at least one of the first transistor and the second transistor and (ii) cause a change in transistor voltages provided by the first transistor and the second transistor to the first input and the second input of the amplifier.

[0286] 16. The system of any one of embodiments 1-15, wherein the controller comprises a current-to-digital converter and is configured to: convert the current received from the fifthAttorney Docket No. 37136-0128001

[0287] transistor to an N bit digital control signal; and provide the N bit digital control signal to the variable resistor to adjust the resistive value.

[0288] 17. The system of any one of embodiments 1-16, wherein the amplifier, the third transistor, the fourth transistor, and the variable resistor form a closed loop to regulate a first current through the first transistor and a second current through the second transistor.

[0289] 18. The system of any one of embodiments 1-17, wherein the first transistor and the second transistor comprise different emitter areas, the amplifier, the first transistor, the second transistor, the third transistor, and the fourth transistor are coupled in a closed loop configuration to regulate a first current through the first transistor and a second current through the second transistor such that a first voltage at the first input and a second voltage at the second input of the amplifier are within a threshold value of one another, and the resistor coupled between the fourth transistor and the second transistor converts a current produced by the configuration to a voltage that is proportional to a temperature of the device.

[0290] 19. The system of any one of embodiments 1-18, wherein the fifth transistor is coupled to the third transistor and the fourth transistor, and is configured to sense a current generated in response to the voltage produced by the amplifier, and the controller is configured to receive the sensed current from the fifth transistor, and the sensed current is proportional to the voltage produced by the amplifier.

[0291] 20. A system for enhancing PTAT circuits, the system comprising:

[0292] a logic gate configured to receive a current and produce a signal based on the received current;

[0293] a first transistor and a second transistor, the first transistor having a first size and the second transistor having a second, different size;

[0294] an amplifier having a first input and a second input, the first input coupled to the first transistor and the second input coupled to the second transistor, wherein the amplifier is configured to produce an output voltage based on a voltage difference between the first input and the second input;

[0295] a third transistor comprising a first gate and a first drain, the first drain coupled to the first transistor and the first gate coupled to an output of the amplifier;

[0296] a fourth transistor comprising a second gate and a second drain, the second drain coupled to the second transistor and the second gate coupled to the output of the amplifier;Attorney Docket No. 37136-0128001

[0297] a capacitor coupled to the first gate and the second gate;

[0298] a first resistor coupled in series to a second resistor, the second resistor coupled between the first resistor and the capacitor;

[0299] a fifth transistor comprising a third gate and a third drain, the third gate being coupled to the second gate and the third drain being coupled to a first input of a logic gate; and

[0300] a sixth transistor comprising a fourth gate and a fourth drain, wherein the fourth gate is coupled to an output of the logic gate and the fourth drain is coupled to the first resistor and the second resistor,

[0301] wherein the logic gate comprises the first input and a second input, wherein the first input is coupled to the third drain, the second input is coupled to an enable signal, and the logic gate is configured to output a first voltage to the fourth gate in response to receiving a first current from the fifth transistor.

[0302] 21. The system of embodiment 20, wherein the logic gate is a NOR gate.

[0303] 22. The system of any one of embodiments 20-21, wherein the sixth transistor is in parallel to the first resistor.

[0304] 23. The system of any one of embodiments 20-22, wherein the logic gate is configured to enable the sixth transistor in response to an activation of the enable signal.

[0305] 24. The system of any one of embodiments 20-23, wherein the logic gate is configured to generate the first voltage based on a magnitude of the first current received from the fifth transistor.

[0306] 25. The system of any one of embodiments 20-24, wherein the first current received from the fifth transistor is proportional to a temperature associated with the device.

[0307] 26. The system of any one of embodiments 20-25, wherein the sixth transistor is configured to bypass at least one of the first resistor and the second resistor in a first operating mode.

[0308] 27. The system of embodiment 26, wherein the sixth transistor is configured to not bypass at least one of the first resistor and the second resistor in a second operating mode.

[0309] 28. The system of embodiment 27, wherein the sixth transistor is configured to switch between the first operating mode and the second operating mode based on a temperature dependent current received by the logic gate from the fifth transistor.Attorney Docket No. 37136-0128001

[0310] 29. The system of any one of embodiments 20-28, wherein the sixth transistor is configured to bypass the first resistor in response to a first magnitude of current received by the logic gate from the fifth transistor.

[0311] 30. The system of embodiment 29, wherein the sixth transistor is not configured to bypass the first resistor in response to a second magnitude of current received by the logic gate from the fifth transistor, wherein the first magnitude of current is greater than a second magnitude of current.

[0312] 31. The system of embodiment 30, wherein the sixth transistor is configured to bypass the first resistor at a first temperature associated with the device and to not bypass the first resistor at a second temperature of the device, wherein the first temperature is higher than the second temperature.

[0313] 32. The system of any one of embodiments 20-31, wherein the sixth transistor is configured to selectively reduce a resistance of the first resistor and the second resistor by bypassing the first resistor when a current received by the logic gate exceeds a threshold value.

[0314] 33. A system for enhancing aPTAT circuit, comprising:

[0315] a bias circuit configured to generate a bias signal;

[0316] a feedback controller coupled to the bias circuit and configured to:

[0317] receive a signal indicative of an operating condition of the bias circuit; and generate a control signal based on the operating condition of the bias circuit; and a compensation circuit coupled to the bias circuit and configured to adjust a frequency compensation characteristic of the bias circuit by modifying a resistive component of the compensation circuit using the control signal generated by the feedback controller.

[0318] 34. A method for enhancing a PTAT circuit performed by a circuit, the method comprising:

[0319] generating a bias signal that varies with temperature;

[0320] sensing an operating condition of the circuit;

[0321] generating a control signal based on the sensed operating condition; and

[0322] modifying a resistive component of a compensation circuit using the generated control signal to adjust a frequency characteristic of the circuit.

[0323] 35. A method for enhancing a PTAT circuit performed by a circuit, the method comprising:Attorney Docket No. 37136-0128001

[0324] generating a bias signal that varies with temperature;

[0325] determining a magnitude of the bias signal;

[0326] comparing the determined magnitude to a threshold value; and

[0327] selectively adjusting a resistance of a compensation circuit of the circuit based on a result of the comparison.

[0328] This specification uses the term “configured to” in connection with systems, apparatus, and computer program components. That a system is configured to perform particular operations or actions means that the system has installed on it software, firmware, hardware, or a combination of them that in operation cause the system to perform the operations or actions. That one or more computer programs is configured to perform particular operations or actions means that the one or more programs include instructions that, when executed, perform the operations or actions. That special -purpose circuitry is configured to perform particular operations or actions means that the circuitry circuit elements that, when put into operation, perform the operations or actions.

[0329] This specification uses the term “configured to” in connection with systems, apparatus, and computer program components. That a system is configured to perform particular operations or actions means that the system has installed on it software, firmware, hardware, or a combination of them that in operation cause the system to perform the operations or actions. That one or more computer programs is configured to perform particular operations or actions means that the one or more programs include instructions that, when executed, perform the operations or actions. That special-purpose circuitry is configured to perform particular operations or actions means that the circuitry circuit elements that, when put into operation, perform the operations or actions.

[0330] The articles “a,” “an,” and “the” are intended to mean that there are one or more of the elements in the preceding descriptions. The terms “comprising,” “including,” and “having” are intended to be inclusive and mean that there may be additional elements other than the listed elements. Additionally, it should be understood that references to “one example” or “an example” of the present disclosure are not intended to be interpreted as excluding the existence of additional examples that also incorporate the recited features. For example, any element described in relation to an example herein may be combinable with any element of any other example described herein. Numbers, percentages, ratios, or other values stated herein areAttorney Docket No. 37136-0128001

[0331] intended to include that value, and also other values that are “about” or “approximately” the stated value, as would be appreciated by one of ordinary skill in the art encompassed by examples of the present disclosure. A stated value should therefore be interpreted broadly enough to encompass values that are at least close enough to the stated value to perform a desired function or achieve a desired result. The stated values include at least the variation to be expected in a suitable manufacturing or production process, and may include values that are within 5%, within 1%, within 0.1%, or within 0.01% of a stated value.

[0332] A person having ordinary skill in the art should realize in view of the present disclosure that equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations may be made to examples disclosed herein without departing from the spirit and scope of the present disclosure. Equivalent constructions, including functional “means-plus-function” clauses are intended to cover the structures described herein as performing the recited function, including both structural equivalents that operate in the same manner, and equivalent structures that provide the same function. It is the express intention of the applicant not to invoke means-plus-function or other functional claiming for any claim except for those in which the words ‘means for’ appear together with an associated function. Each addition, deletion, and modification to the examples that falls within the meaning and scope of the claims is to be embraced by the claims.

[0333] The terms “approximately,” “about,” and “substantially” as used herein represent an amount close to the stated amount that still performs a desired function or achieves a desired result. For example, the terms “approximately,” “about,” and “substantially” may refer to an amount that is within less than 5% of, within less than 1% of, within less than 0.1% of, and within less than 0.01% of a stated amount. Further, it should be understood that any directions or reference frames in the preceding description are merely relative directions or movements. For example, any references to “up” and “down” or “above” or “below” are merely descriptive of the relative position or movement of the related elements.

[0334] While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any invention or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely,Attorney Docket No. 37136-0128001

[0335] various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

[0336] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system modules and components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0337] Particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. As one example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain implementations, multitasking and parallel processing may be advantageous.

[0338] What is claimed is:

Claims

Attorney Docket No. 37136-0128001CLAIMS1. A device comprising:a controller configured to receive a current and produce a signal based on the received current;a first transistor and a second transistor, the first transistor having a first size and the second transistor having a second, different size;an amplifier having a first input and a second input, the first input coupled to the first transistor and the second input coupled to the second transistor, wherein the amplifier is configured to produce an output voltage based on a voltage difference between the first input and the second input;a third transistor comprising a first gate and a first drain, the first drain coupled to the first transistor and the first gate coupled to an output of the amplifier;a fourth transistor comprising a second gate and a second drain, the second drain coupled to the second transistor and the second gate coupled to the output of the amplifier;a variable resistor coupled to the first gate and the second gate, wherein the variable resistor is configured to adjust a resistive value according to a signal received from the controller; anda fifth transistor comprising a third gate and a third drain, the third gate coupled to the second gate and the third drain coupled to an input of the controller,wherein the controller is coupled to the third drain and configured to (i) receive the current from the third drain and (ii) produce the signal for the variable resistor based on the received current.

2. The device of claim 1, wherein the amplifier is configured to produce the output voltage that adjusts current, using the third transistor and the fourth transistor, through the first transistor and the second transistor to reduce the voltage difference between the first input and the second input.

3. The device of claim 1, further comprising a resistor coupled between the second transistor and the second drain of the fourth transistor.Attorney Docket No. 37136-01280014. The device of claim 3, wherein a current that flows through the resistor is proportional to a temperature associated with the device.

5. The device of claim 4, wherein the proportionality to the temperature associated with the device is based on the first size of the first transistor and the second, different size of the second transistor.

6. The device of claim 4, wherein the resistor is coupled to one or more components of a transimpedance amplifier, and the current that flows through the resistor is configured to bias the one or more components of the transimpedance amplifier based on a temperature associated with the device.

7. The device of claim 1, further comprising a capacitor coupled to the variable resistor and to a supply voltage.

8. The device of claim 1, wherein the first transistor is a bipolar junction transistor.

9. The device of claim 1, wherein the amplifier is a differential amplifier.

10. The device of claim 1, wherein the third transistor is a metal-oxide-semiconductor field effect transistor (MOSFET).

11. The device of claim 1 , wherein the fourth transistor is a MOSFET.

12. The device of claim 1, wherein the fifth transistor is a MOSFET.

13. The device of claim 1, wherein the current received by controller is produced in response to the output voltage provided by the amplifier.

14. The device of claim 13, wherein the controller is configured to adjust the resistive value of the variable resistor according to the current received from the fifth transistor.Attorney Docket No. 37136-012800115. The device of claim 13, wherein the controller is configured to adjust the resistive value of the variable resistor to (i) modify a current provided to at least one of the first transistor and the second transistor and (ii) cause a change in transistor voltages provided by the first transistor and the second transistor to the first input and the second input of the amplifier.

16. The device of claim 1, wherein the controller comprises a current-to-digital converter and is configured to:convert the current received from the fifth transistor to an V bit digital control signal; and provide the N bit digital control signal to the variable resistor to adjust the resistive value.

17. The device of claim 1, wherein the amplifier, the third transistor, the fourth transistor, and the variable resistor form a closed loop to regulate a first current through the first transistor and a second current through the second transistor.

18. The device of claim 1, whereinthe first transistor and the second transistor comprise different emitter areas,the amplifier, the first transistor, the second transistor, the third transistor, and the fourth transistor are coupled in a closed loop configuration to regulate a first current through the first transistor and a second current through the second transistor such that a first voltage at the first input and a second voltage at the second input of the amplifier are within a threshold value of one another, andthe resistor coupled between the fourth transistor and the second transistor converts a current produced by the configuration to a voltage that is proportional to a temperature of the device.

19. The device of claim 1, whereinthe fifth transistor is coupled to the third transistor and the fourth transistor, and is configured to sense a current generated in response to the voltage produced by the amplifier, and the controller is configured to receive the sensed current from the fifth transistor, and the sensed current is proportional to the voltage produced by the amplifier.Attorney Docket No. 37136-012800120. A device comprising:a logic gate configured to receive a current and produce a signal based on the received current;a first transistor and a second transistor, the first transistor having a first size and the second transistor having a second, different size;an amplifier having a first input and a second input, the first input coupled to the first transistor and the second input coupled to the second transistor, wherein the amplifier is configured to produce an output voltage based on a voltage difference between the first input and the second input;a third transistor comprising a first gate and a first drain, the first drain coupled to the first transistor and the first gate coupled to an output of the amplifier;a fourth transistor comprising a second gate and a second drain, the second drain coupled to the second transistor and the second gate coupled to the output of the amplifier;a capacitor coupled to the first gate and the second gate;a first resistor coupled in series to a second resistor, the second resistor coupled between the first resistor and the capacitor;a fifth transistor comprising a third gate and a third drain, the third gate being coupled to the second gate and the third drain being coupled to a first input of a logic gate; anda sixth transistor comprising a fourth gate and a fourth drain, wherein the fourth gate is coupled to an output of the logic gate and the fourth drain is coupled to the first resistor and the second resistor,wherein the logic gate comprises the first input and a second input, wherein the first input is coupled to the third drain, the second input is coupled to an enable signal, and the logic gate is configured to output a first voltage to the fourth gate in response to receiving a first current from the fifth transistor.

21. The device of claim 20, wherein the logic gate is a NOR gate.

22. The device of claim 20, wherein the sixth transistor is in parallel to the first resistor.Attorney Docket No. 37136-012800123. The device of claim 20, wherein the logic gate is configured to enable the sixth transistor in response to an activation of the enable signal.

24. The device of claim 20, wherein the logic gate is configured to generate the first voltage based on a magnitude of the first current received from the fifth transistor.

25. The device of claim 20, wherein the first current received from the fifth transistor is proportional to a temperature associated with the device.

26. The device of claim 20, wherein the sixth transistor is configured to bypass at least one of the first resistor and the second resistor in a first operating mode.

27. The device of claim 26, wherein the sixth transistor is configured to not bypass at least one of the first resistor and the second resistor in a second operating mode.

28. The device of claim 27, wherein the sixth transistor is configured to switch between the first operating mode and the second operating mode based on a temperature dependent current received by the logic gate from the fifth transistor.

29. The device of claim 20, wherein the sixth transistor is configured to bypass the first resistor in response to a first magnitude of current received by the logic gate from the fifth transistor.

30. The device of claim 29, wherein the sixth transistor is not configured to bypass the first resistor in response to a second magnitude of current received by the logic gate from the fifth transistor, wherein the first magnitude of current is greater than a second magnitude of current.

31. The device of claim 30, wherein the sixth transistor is configured to bypass the first resistor at a first temperature associated with the device and to not bypass the first resistor at a second temperature of the device, wherein the first temperature is higher than the second temperature.Attorney Docket No. 37136-012800132. The device of claim 20, wherein the sixth transistor is configured to selectively reduce a resistance of the first resistor and the second resistor by bypassing the first resistor when a current received by the logic gate exceeds a threshold value.

Images