Array substrate and display apparatus

Abstract

An array substrate and a display apparatus. The array substrate comprises a base substrate, a first transistor and a second transistor, the first transistor and the second transistor being provided on one side of the base substrate. The first transistor comprises a first active layer, the first active layer comprises a first conductor portion, a first channel portion and a second conductor portion that are sequentially connected, the first active layer comprises first grain boundaries, and in a connection direction of the first conductor portion, the first channel portion and the second conductor portion, a distance between two adjacent first grain boundaries is a first distance. The second transistor comprises a second active layer, the second active layer comprises a third conductor portion, a second channel portion and a fourth conductor portion that are sequentially connected, the second active layer comprises second grain boundaries, and in a connection direction of the third conductor portion, the second channel portion and the fourth conductor portion, a distance between two adjacent second grain boundaries is a second distance. The first distance is greater than the second distance, and the first transistor at least functions as a driving transistor. The first transistor has a higher mobility and a larger on-state current.

Description

Array substrate and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, in particular to an array substrate and a display device. BACKGROUND

[0002] Low Temperature Poly-Silicon (LTPS) material has a higher mobility 50cm 2 / V·s~200cm 2 / V·s, which is beneficial to the miniaturization of Thin Film Transistor (TFT), thereby improving the aperture ratio of the display device, strengthening the definition, etc.; however, with the development of the display industry, there is an increasing demand for higher resolution VR (Virtual Reality) / AR (Augmented Reality) products, and higher resolution means that a TFT with higher mobility is needed. In particular, with the rise of micro-LED (micro-Light Emitting Diode) display technology, a TFT with higher performance, especially higher mobility, is needed to drive micro-LED, which puts higher requirements on the performance of LTPS-TFT. SUMMARY

[0003] The present disclosure aims to overcome the shortcomings of the prior art and provide an array substrate and a display device.

[0004] According to one aspect of the present disclosure, an array substrate is provided, comprising:

[0005] a substrate substrate;

[0006] a first transistor and a second transistor arranged on one side of the substrate substrate; the first transistor comprises a first active layer, the first active layer comprises a first conductor portion, a first channel portion and a second conductor portion connected in sequence, the first active layer comprises a first grain boundary, and the distance between two adjacent first grain boundaries in the connection direction of the first conductor portion, the first channel portion and the second conductor portion is a first distance; the second transistor comprises a second active layer, the second active layer comprises a third conductor portion, a second channel portion and a fourth conductor portion connected in sequence, the second active layer comprises a second grain boundary, and the distance between two adjacent second grain boundaries in the connection direction of the third conductor portion, the second channel portion and the fourth conductor portion is a second distance; the first distance is greater than the second distance, and the first transistor is used as at least a driving transistor.

[0007] In one example embodiment of the present disclosure, the first distance is greater than or equal to 0.7 micrometers and less than or equal to 10 micrometers, and / or the second distance is greater than or equal to 100 nanometers and less than or equal to 500 nanometers.

[0008] In one example embodiment of the present disclosure, a maximum dimension of the first channel portion in an extension direction of the first active layer is greater than or equal to a maximum dimension of the second channel portion in an extension direction of the second active layer; the second channel portion includes the second grain boundary, and the first channel portion does not include the first grain boundary; or, the second channel portion includes the second grain boundary, and the first channel portion includes the first grain boundary, a number of the second grain boundaries included in the second channel portion is greater than or equal to a number of the first grain boundaries included in the first channel portion, and the extension direction of the first active layer and the extension direction of the second active layer are parallel to a side of the substrate on which the first transistor and the second transistor are disposed.

[0009] In one example embodiment of the present disclosure, the array substrate has a display region and a non-display region, and the first transistor is disposed in the display region and the non-display region, or the first transistor is disposed in the display region.

[0010] In one example embodiment of the present disclosure, the first conductor portion and / or the second conductor portion include a first grain boundary, and the third conductor portion and / or the fourth conductor portion include a second grain boundary.

[0011] In one example embodiment of the present disclosure, a distance between the first active layer and the substrate in a second direction is equal to a distance between the second active layer and the substrate in the second direction, and the second direction is perpendicular to a side of the substrate on which the second transistor and the first transistor are disposed; and the array substrate further includes:

[0012] a first gate insulating layer disposed on a side of the first active layer and the second active layer away from the substrate;

[0013] a first gate electrode layer disposed on a side of the first gate insulating layer away from the substrate, the first gate electrode layer including a first gate electrode and a second gate electrode, a footprint of the first channel portion on the substrate is within a footprint of the first gate electrode on the substrate, and a footprint of the second channel portion on the substrate is within a footprint of the second gate electrode on the substrate;

[0014] a first interlayer dielectric layer disposed on a side of the first gate electrode layer away from the substrate;

[0015] A first interlayer dielectric layer is disposed on a side of the first gate insulating layer facing away from the substrate. A first connection conductor layer is disposed on a side of the first interlayer dielectric layer facing away from the substrate. The first connection conductor layer includes a first connection portion, a second connection portion, a third connection portion, and a fourth connection portion. The first connection portion is connected to the first conductor portion. The second connection portion is connected to the second conductor portion. The third connection portion is connected to the third conductor portion. The fourth connection portion is connected to the fourth conductor portion.

[0016] In one example embodiment of the present disclosure, the second active layer is disposed on a side of the first active layer facing away from the substrate. A projection of the first active layer on the substrate overlaps with a projection of the second active layer on the substrate.

[0017] In one example embodiment of the present disclosure, the array substrate further includes:

[0018] A first gate insulating layer is disposed on a side of the first active layer facing away from the substrate.

[0019] A first gate layer is disposed on a side of the first gate insulating layer facing away from the substrate. The first gate layer includes a first gate. A projection of the first channel portion on the substrate is located within a projection of the first gate on the substrate.

[0020] A second buffer layer is disposed on a side of the first gate layer facing away from the substrate. The second active layer is disposed on a side of the second buffer layer facing away from the substrate. The third conductor portion is connected to the first conductor portion or the second conductor portion.

[0021] A second gate insulating layer is disposed on a side of the second active layer facing away from the substrate.

[0022] A second gate layer is disposed on a side of the second gate insulating layer facing away from the substrate. The second gate layer includes a second gate. A projection of the second channel portion on the substrate is located within a projection of the second gate on the substrate.

[0023] A first interlayer dielectric layer is disposed on a side of the second gate layer facing away from the substrate.

[0024] A first connection conductor layer is disposed on a side of the first interlayer dielectric layer facing away from the substrate. The first connection conductor layer includes a first connection portion and a second connection portion. The first connection portion is connected to the third conductor portion. The second connection portion is connected to the fourth conductor portion.

[0025] In an example embodiment of the present disclosure, the first active layer is disposed on a side of the second active layer away from the substrate, and a projection of the first active layer on the substrate overlaps with a projection of the second active layer on the substrate.

[0026] In an example embodiment of the present disclosure, the array substrate further comprises:

[0027] A third transistor comprising a third active layer, the third active layer being disposed on a side of the first active layer away from the substrate, and a projection of the third active layer on the substrate not overlapping with a projection of the first active layer on the substrate, the third transistor being a metal-oxide transistor.

[0028] In an example embodiment of the present disclosure, a projection of the third active layer on the substrate does not overlap with a projection of the second active layer on the substrate.

[0029] In an example embodiment of the present disclosure, the array substrate further comprises:

[0030] A first gate insulating layer disposed on a side of the first active layer away from the substrate;

[0031] A first gate layer disposed on a side of the first gate insulating layer away from the substrate, the first gate layer comprising at least a first gate, and a projection of the first channel portion on the substrate being located within a projection of the first gate on the substrate;

[0032] An insulating layer group disposed on a side of the first gate layer away from the substrate, the third active layer being disposed on a side of the insulating layer group away from the substrate, the third active layer comprising a fifth conductor portion, a third channel portion, and a sixth conductor portion connected in sequence;

[0033] A third gate insulating layer disposed on a side of the third active layer away from the substrate;

[0034] A third gate layer disposed on a side of the third gate insulating layer away from the substrate, the third gate layer comprising a third gate, and a projection of the third channel portion on the substrate being located within a projection of the third gate on the substrate;

[0035] A second interlayer dielectric layer disposed on a side of the third gate layer away from the substrate;

[0036] A first connecting conductor layer is disposed on a side of the second interlayer dielectric layer away from the substrate substrate, and includes a first connecting portion, a second connecting portion, a third connecting portion, and a fourth connecting portion. The first connecting portion is connected to the first conductor portion, the second connecting portion is connected to the second conductor portion, the third connecting portion is connected to the fifth conductor portion, and the fourth connecting portion is connected to the sixth conductor portion.

[0037] In an exemplary embodiment of the present disclosure, the array substrate further includes:

[0038] A third transistor includes a third active layer disposed on a side of the first active layer away from the substrate substrate. A projection of the third active layer on the substrate substrate overlaps a projection of the first active layer on the substrate substrate. The third transistor is a metal oxide transistor.

[0039] In an exemplary embodiment of the present disclosure, the array substrate further includes:

[0040] A first gate insulating layer is disposed on a side of the first active layer away from the substrate substrate.

[0041] A first gate layer is disposed on a side of the first gate insulating layer away from the substrate substrate. The first gate layer includes at least a first gate. A projection of the first channel portion on the substrate substrate is located within a projection of the first gate on the substrate substrate.

[0042] An insulating layer group is disposed on a side of the first gate layer away from the substrate substrate. The third active layer is disposed on a side of the insulating layer group away from the substrate substrate. The third active layer includes a fifth conductor portion, a third channel portion, and a sixth conductor portion connected in sequence.

[0043] A third gate insulating layer is disposed on a side of the third active layer away from the substrate substrate.

[0044] A third gate layer is disposed on a side of the third gate insulating layer away from the substrate substrate. The third gate layer includes a third gate. A projection of the third channel portion on the substrate substrate is located within a projection of the third gate on the substrate substrate.

[0045] A second interlayer dielectric layer is disposed on a side of the third gate layer away from the substrate substrate.

[0046] A first connection conductor layer is disposed on a side of the second interlayer dielectric layer away from the substrate, the first connection conductor layer includes a first connection portion and a second connection portion, the first connection portion is connected to the first conductor portion and the fifth conductor portion, and / or the second connection portion is connected to the second conductor portion and the sixth conductor portion.

[0047] In an exemplary embodiment of the present disclosure, the array substrate further includes:

[0048] A first gate insulating layer is disposed on a side of the first active layer away from the substrate;

[0049] A first gate electrode layer is disposed on a side of the first gate insulating layer away from the substrate, the first gate electrode layer includes at least a first gate electrode, and a projection of the first channel portion on the substrate is within a projection of the first gate electrode on the substrate;

[0050] An insulating layer group is disposed on a side of the first gate electrode layer away from the substrate;

[0051] A first connection conductor layer is disposed between two insulating layers in the insulating layer group, the first connection conductor layer includes a first connection portion and a second connection portion, the first connection portion is connected to the first conductor portion, and the second connection portion is connected to the second conductor portion; a third active layer is disposed on a side of the insulating layer group away from the substrate, the third active layer includes a fifth conductor portion, a third channel portion, and a sixth conductor portion connected in sequence, the fifth conductor portion is connected to the first connection portion, and the sixth conductor portion is connected to the second connection portion;

[0052] A third gate insulating layer is disposed on a side of the third active layer away from the substrate;

[0053] A third gate electrode layer is disposed on a side of the third gate insulating layer away from the substrate, the third gate electrode layer includes a third gate electrode, and a projection of the third channel portion on the substrate is within a projection of the third gate electrode on the substrate;

[0054] A second interlayer dielectric layer is disposed on a side of the third gate electrode layer away from the substrate;

[0055] A second connection conductor layer is disposed on a side of the second interlayer dielectric layer away from the substrate, the second connection conductor layer includes a seventh connection portion and an eighth connection portion, the seventh connection portion is connected to the fifth conductor portion, and the eighth connection portion is connected to the sixth conductor portion.

[0056] In an exemplary embodiment of this disclosure, the insulating layer group includes a second gate insulating layer, a first interlayer dielectric layer, and a second buffer layer stacked sequentially; the array substrate further includes:

[0057] A shielding layer is disposed between the second gate insulating layer and the first interlayer dielectric layer. The shielding layer includes a shielding portion, the orthographic projection of the shielding portion on the substrate overlaps with the orthographic projections of the first gate and the third gate on the substrate.

[0058] In one exemplary embodiment of this disclosure, the insulating layer group includes a second gate insulating layer, a first interlayer dielectric layer, an electromagnetic shielding layer, and a second buffer layer stacked sequentially.

[0059] In an exemplary embodiment of this disclosure, the distance between the first active layer and the substrate in a second direction is equal to the distance between the second active layer and the substrate in the second direction, and the second direction is perpendicular to the side of the substrate on which the second transistor and the first transistor are disposed; the first gate layer further includes a second gate, and the orthographic projection of the second channel portion on the substrate is located within the orthographic projection of the second gate on the substrate.

[0060] In one exemplary embodiment of this disclosure, the first grain boundary is a first protrusion formed in the first active layer, and the second grain boundary is a second protrusion formed in the second active layer.

[0061] According to another aspect of this disclosure, a display device is provided, comprising: an array substrate as described in any one of the preceding claims.

[0062] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0063] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0064] Figure 1 is a schematic diagram of the structure of a first example embodiment of the array substrate disclosed herein.

[0065] Figure 2 is an electron microscope schematic diagram of an example embodiment of the first active layer in Figure 1.

[0066] Figure 3 is an electron microscope schematic diagram of another example embodiment of the first active layer in Figure 1.

[0067] Figure 4 is a schematic diagram of the electron microscope structure of the second active layer in Figure 1.

[0068] Figure 5 is a schematic diagram of the structure after the formation of the second polysilicon layer during the formation of the array substrate in Figure 1.

[0069] Figure 6 is a schematic diagram of the structure after the formation of the first polysilicon layer during the formation of the array substrate in Figure 1.

[0070] Figure 7 is a schematic cross-sectional view of the section cut according to section AA in Figure 6.

[0071] Figures 8 and 9 are schematic diagrams of the two steps involved in forming the array substrate in Figure 1 based on Figure 7.

[0072] Figure 10 is a schematic diagram of the structure of a second exemplary embodiment of the array substrate disclosed herein.

[0073] Figures 11-13 are schematic diagrams of some steps in forming the array substrate in Figure 10.

[0074] Figure 14 is a schematic diagram of the structure of a third exemplary embodiment of the array substrate disclosed herein.

[0075] Figure 15 is a schematic diagram of the structure of a fourth exemplary embodiment of the array substrate disclosed herein.

[0076] Figure 16 is a schematic diagram of the structure of a fifth exemplary embodiment of the array substrate disclosed herein.

[0077] Figure 17 is a schematic diagram of the structure of a sixth exemplary embodiment of the array substrate disclosed herein.

[0078] Figure 18 is a schematic diagram of the structure of the seventh exemplary embodiment of the array substrate of this disclosure.

[0079] Figures 19-21 are schematic diagrams of some steps in forming the array substrate in Figure 18.

[0080] Figure 22 is a schematic diagram of the structure of the eighth exemplary embodiment of the array substrate of this disclosure.

[0081] Figure 23 is a schematic diagram of the structure of polycrystalline silicon formed when the crystallization energy is too low during excimer laser annealing.

[0082] Figure 24 is a schematic diagram of the structure of polycrystalline silicon formed when the crystallization energy is appropriate during excimer laser annealing.

[0083] Figure 25 is a schematic diagram of the structure of polycrystalline silicon formed when the crystallization energy is too high during excimer laser annealing.

[0084] Figure 26 is a schematic diagram of a first example embodiment of a driving circuit in the array substrate of this disclosure.

[0085] Figure 27 is a schematic diagram of a second example embodiment of a driving circuit in the array substrate of this disclosure.

[0086] Figure 28 is a schematic diagram of a third example embodiment of a driving circuit in the array substrate of this disclosure.

[0087] Figure 29 is a schematic diagram of the structure after the formation of the first active layer and the first gate insulating layer in the array substrate of this disclosure.

[0088] Explanation of reference numerals in the attached drawings: 1. Substrate; 2. First buffer layer; 31a. First polysilicon layer; 31b. First active material layer; 31. First active layer; 311. First conductor portion; 312. First channel portion; 313. Second conductor portion; 314. First grain boundary; 315. First grain; 32a. Second polysilicon layer; 32b. Second active material layer; 32. Second active layer; 321. Third conductor portion; 322. Second channel portion; 323. Fourth conductor portion; 324. Second grain boundary; 325. Second grain; 4. First gate insulating layer; 5. First gate layer; 51. First gate; 52. Second gate; 6. Insulating layer group; 61. First interlayer dielectric layer; 62. Second gate insulating layer; 63. Electromagnetic shielding layer; 64. Second buffer layer; 7. Third active layer; 71. Fifth conductor portion; 72. Third channel portion; 73. Sixth conductor portion; 8. Third gate insulating layer; 9. Third gate layer; 91. Third gate; 10. Second interlayer dielectric layer; 111. First connecting conductor layer; 1111. First connecting portion; 1112. Second connecting portion; 1113. Third connecting portion; 1114. Fourth connecting portion; 1115. Fifth connecting portion; 1116. Sixth connecting portion; 112. Second connecting conductor layer; 1121. Seventh connecting portion; 1122. Eighth connecting portion; 1123. Ninth connecting portion; 1124. Tenth connecting portion; 12. Shielding layer; 121. Shielding portion; T1. First transistor; T2. Second transistor; T3. Third transistor; X. Extension direction of the first active layer / Extension direction of the second active layer; Y. Second direction. Detailed Implementation

[0089] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0090] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0091] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0092] In this application, unless otherwise expressly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. "And / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Furthermore, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0093] This disclosure provides an array substrate, as shown in Figures 1-22 and 26-29. The array substrate includes a substrate 1, a first transistor T1, and a second transistor T2. The first transistor T1 and the second transistor T2 are disposed on one side of the substrate 1. The first transistor T1 may include a first active layer 31, which may include a first conductor portion 311, a first channel portion 312, and a second conductor portion 313 connected in sequence. The first active layer 31 may include a first grain boundary 314. In the connection direction, the distance between two adjacent first grain boundaries 314 is a first distance H1; the second transistor T2 may include a second active layer 32, which may include a third conductor portion 321, a second channel portion 322, and a fourth conductor portion 323 connected in sequence. The second active layer 32 may include a second grain boundary 324. In the connection direction of the third conductor portion 321, the second channel portion 322, and the fourth conductor portion 323, the distance between two adjacent second grain boundaries 324 is a second distance H2; the first distance H1 is greater than the second distance H2, and the first transistor T1 is used as at least a driving transistor.

[0094] In the array substrate disclosed herein, on the one hand, the first transistor T1 is used as a driving transistor. The driving transistor requires a higher field-effect mobility and on-state current. The first distance H1 is greater than the second distance H2, thereby reducing the number of first grain boundaries 314 included in the first active layer 31. This results in a larger carrier mobility and a larger on-state current for the formed first transistor T1, meeting the requirements for a driving transistor, and reducing the power consumption of the array substrate while improving the overall performance. On the other hand, the number of second grain boundaries 324 included in the multiple second active layers 32 is basically the same, thereby making the field-effect mobility and on-state current of the multiple second transistors T2 basically the same, so as to ensure the uniformity of the array substrate.

[0095] In this exemplary embodiment, the material of the substrate 1 may include inorganic materials, such as glass, quartz, or metal. The material of the substrate 1 may also include organic materials, such as resins like polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate. The substrate 1 may be formed from multiple material layers; for example, the substrate 1 may include multiple substrate layers, and the substrate layers may be made of any of the materials described above. Of course, the substrate 1 may also be a single layer, and may be any of the materials described above.

[0096] Referring to Figures 1 and 5-22, a first buffer layer 2 is disposed on one side of the substrate 1. The first buffer layer 2 serves to block water vapor and impurity ions in the substrate 1 (especially organic materials) and to increase hydrogen ions for the subsequently formed active layer. The first buffer layer 2 can be a single-layer structure. For example, the material of the first buffer layer 2 is SiO (silicon oxide). The thickness of the first buffer layer 2 is greater than or equal to 500 angstroms and less than or equal to 5000 angstroms. For example, the thickness of the first buffer layer 2 can be 1000 angstroms, 1500 angstroms, 2000 angstroms, 2500 angstroms, 3000 angstroms, 3500 angstroms, 4000 angstroms, 4500 angstroms, etc. The first buffer layer 2 can also be a two-layer structure. For example, the first buffer layer 2 may include a first film layer and a second film layer. The material of the first film layer is SiN (silicon nitride), and the thickness of the first film layer is greater than or equal to 500 angstroms and less than or equal to 1000 angstroms. For example, the thickness of the first film layer can be 550 angstroms, 600 angstroms, 650 angstroms, 700 angstroms, 750 angstroms, 800 angstroms, 850 angstroms, 900 angstroms, 950 angstroms, etc. The material of the second film layer is SiO (silicon oxide), and the thickness of the second film layer is greater than or equal to 5000 angstroms and less than or equal to 5000 angstroms. For example, the thickness of the second film layer can be 1000 angstroms, 1500 angstroms, 2000 angstroms, 2500 angstroms, 3000 angstroms, 3500 angstroms, 4000 angstroms, 4500 angstroms, etc.

[0097] In this example embodiment, a first transistor T1 and a second transistor T2 are disposed on one side of the substrate 1. Specifically, the first transistor T1 and the second transistor T2 are disposed on the side of the first buffer layer 2 opposite to the substrate 1.

[0098] The first transistor T1 serves at least as a driving transistor. Referring to Figures 2 and 3, the whitish areas on the surface represent grain boundaries, and the areas surrounding the grain boundaries represent grains. The first transistor T1 may include a first active layer 31, which may include a first conductor portion 311, a first channel portion 312, and a second conductor portion 313 connected in sequence. The first active layer 31 may also include first grain boundaries 314. In the connection direction of the first conductor portion 311, the first channel portion 312, and the second conductor portion 313, the distance between two adjacent first grain boundaries 314 is a first distance H1. The first conductor portion 311, the first channel portion 312, and the second conductor portion 313 may be connected in sequence along a straight line or along a curve. When the first conductor portion 311, the first channel portion 312, and the second conductor portion 313 are connected in sequence along a straight line, the first distance H1 is the distance along the straight line direction. When the first conductor portion 311, the first channel portion 312, and the second conductor portion 313 are connected in sequence along a curve, the first distance H1 is the distance along the curve direction.

[0099] Referring to Figure 4, the blackened and whitish areas on the surface are grain boundaries. The grain boundaries connect to form a grid structure, and the areas surrounding the grain boundaries are grains. The second transistor T2 may include a second active layer 32, which may include a third conductor portion 321, a second channel portion 322, and a fourth conductor portion 323 connected in sequence. The second active layer 32 may also include second grain boundaries 324. In the connection direction of the third conductor portion 321, the second channel portion 322, and the fourth conductor portion 323, the distance between two adjacent second grain boundaries 324 is a second distance H2. The third conductor portion 321, the second channel portion 322, and the fourth conductor portion 323 can be connected sequentially along a straight line or along a curve. When the third conductor portion 321, the second channel portion 322, and the fourth conductor portion 323 are connected sequentially along a straight line, the second distance H2 is the distance along the straight line direction; when the third conductor portion 321, the second channel portion 322, and the fourth conductor portion 323 are connected sequentially along a curve, the second distance H2 is the distance along the curve direction.

[0100] It should be noted that when the first distance H1 is a distance along a straight line, the second distance H2 is also a distance along a straight line; when the first distance H1 is a distance along a curve, the second distance H2 is also a distance along a curve. That is, the first transistor T1 and the second transistor T2 have basically the same structure, but may differ in size. The curve can be a broken line or an arc.

[0101] Referring to Figure 29, grain boundaries are the cause of increased roughness in polycrystalline silicon materials. Grain boundaries have obvious protrusions, namely, the first grain boundary 314 is the first protrusion formed in the first active layer 31, and the second grain boundary 324 is the second protrusion formed in the second active layer 32. They cause undulations and are the main defects for carrier trapping, which is the most important factor affecting mobility. Subgrain boundaries do not cause obvious undulations and do not have a significant impact on mobility.

[0102] The first transistor T1 is used as a driving transistor. The driving transistor requires a higher field-effect mobility and on-state current. The first distance H1 is greater than the second distance H2, which makes the number of first grain boundaries 314 included in the first active layer 31 less. This results in the first transistor T1 having a larger carrier mobility and a larger on-state current, which meets the requirements of being a driving transistor. It also reduces the power consumption of the array substrate and improves the overall performance.

[0103] In addition, the maximum size of the second active layer 32 of the second transistor T2 is relatively small. Specifically, the maximum size of the second active layer 32 is greater than or equal to 4 micrometers and less than or equal to 15 micrometers. For example, the maximum size of the second active layer 32 can be 4.3 micrometers, 4.5 micrometers, 4.8 micrometers, 5 micrometers, 5.2 micrometers, 5.5 micrometers, 5.7 micrometers, 6 micrometers, 6.5 micrometers, 7 micrometers, 7.5 micrometers, 8 micrometers, 8.5 micrometers, 9 micrometers, 9.5 micrometers, 10 micrometers, 10.5 micrometers, 11 micrometers, 11.5 micrometers, 12 micrometers, 12.5 micrometers, 13 micrometers, 13.5 micrometers, 14 micrometers, 14.5 micrometers, etc. If the number of second transistors T2 is large, and the second active layer 32 is also configured to include the first grain boundary 314, then the second active layer 32 of some second transistors T2 may include grain boundaries, while the second active layer 32 of other second transistors T2 may not include grain boundaries. This would result in different field-effect mobility and on-state current of the multiple second transistors T2, leading to poor uniformity of the array substrate. However, if the first distance H1 is greater than the second distance H2, then the number of second grain boundaries 324 included in the multiple second active layers 32 will be basically the same, thus ensuring that the field-effect mobility and on-state current of the multiple second transistors T2 are basically the same, thereby ensuring the uniformity of the array substrate.

[0104] Optionally, the first distance is greater than or equal to 0.7 micrometers and less than or equal to 10 micrometers. For example, the first distance can be 1 micrometer, 1.5 micrometers, 2 micrometers, 2.5 micrometers, 3 micrometers, 3.5 micrometers, 4 micrometers, 4.5 micrometers, 5 micrometers, 5.5 micrometers, 6 micrometers, 6.5 micrometers, 7 micrometers, 7.5 micrometers, 8 micrometers, 8.5 micrometers, 9 micrometers, 9.5 micrometers, etc.

[0105] The second distance is greater than or equal to 100 nanometers and less than or equal to 500 nanometers. For example, the second distance can be 150 nanometers, 200 nanometers, 250 nanometers, 300 nanometers, 350 nanometers, 400 nanometers, 450 nanometers, etc.

[0106] In this example embodiment, referring to Figures 2 and 3, the first channel portion 312 may include a first grain 315. The maximum size of the first grain 315 in the extension direction X of the first active layer is at the micrometer level. Specifically, the maximum size of the first grain 315 in the extension direction X of the first active layer is greater than or equal to 0.7 micrometers and less than or equal to 10 micrometers. For example, the maximum size of the first grain 315 in the extension direction X of the first active layer may be 1 micrometer, 1.5 micrometers, 2 micrometers, 2.5 micrometers, 3 micrometers, 3.5 micrometers, 4 micrometers, 4.5 micrometers, 5 micrometers, 5.5 micrometers, 6 micrometers, 6.5 micrometers, 7 micrometers, 7.5 micrometers, 8 micrometers, 8.5 micrometers, 9 micrometers, 9.5 micrometers, etc.

[0107] The first transistor T1 is used as a driving transistor. The driving transistor requires a higher field-effect mobility and on-state current. The maximum size of the first die 315 in the extension direction X of the first active layer is at the micrometer level, which makes the carrier mobility of the formed first transistor T1 larger and the on-state current larger, thus meeting the requirements of the driving transistor, and reducing the power consumption of the array substrate and improving the overall performance.

[0108] Referring to FIG4, the second channel portion 322 may include a second grain 325. The maximum size of the second grain 325 in the extension direction X of the second active layer is on the order of hundreds of nanometers. Specifically, the maximum size of the second grain 325 in the extension direction X of the second active layer is greater than or equal to 100 nanometers and less than or equal to 500 nanometers. For example, the maximum size of the second grain 325 in the extension direction X of the second active layer may be 150 nanometers, 200 nanometers, 250 nanometers, 300 nanometers, 350 nanometers, 400 nanometers, 450 nanometers, etc.

[0109] In addition, the maximum size of the second channel portion 322 of the second transistor T2 in the extension direction X of the second active layer is relatively small. Specifically, the maximum size of the second channel portion 322 in the extension direction X of the second active layer is greater than or equal to 1 micrometer and less than or equal to 4 micrometers. For example, the maximum size of the second channel portion 322 in the extension direction X of the second active layer can be 1.2 micrometers, 1.5 micrometers, 1.7 micrometers, 2 micrometers, 2.3 micrometers, 2.5 micrometers, 2.8 micrometers, 3 micrometers, 3.2 micrometers, 3.5 micrometers, 3.7 micrometers, etc. If the number of second transistors T2 is large, and the second channel portion 322 is also configured to include the first grain 315, then the second channel portion 322 of some second transistors T2 may include grain boundaries, while the second channel portion 322 of other second transistors T2 may not include grain boundaries. This would result in different field-effect mobility and on-state current of the multiple second transistors T2, leading to poor uniformity of the array substrate. However, the maximum size of the second grain 325 in the extension direction X of the second active layer is on the order of hundreds of nanometers, so that the number of second grains 325 included in the multiple second channel portions 322 is basically the same. This would result in the field-effect mobility and on-state current of the multiple second transistors T2 being basically the same, thus ensuring the uniformity of the array substrate.

[0110] It should be noted that the extension direction of the first active layer and the extension direction X of the second active layer are parallel to the side of the substrate 1 where the first transistor T1 and the second transistor T2 are disposed. For the first transistor T1, the extension direction X of the first active layer is the connection direction of the first conductor portion 311, the first channel portion 312, and the second conductor portion 313. The extension direction X of the first active layer can also be described as the direction from the source to the drain of the first transistor T1, or the direction of current or voltage transmission on the first channel portion 312. For the second transistor T2, the extension direction X of the second active layer is the connection direction of the third conductor portion 321, the second channel portion 322, and the second conductor portion 313. The connection direction of the fourth conductor portion 323, and the extension direction X of the second active layer can also be described as the direction from the source to the drain of the second transistor T2, or the direction of current or voltage transmission on the second channel portion 322; therefore, the extension direction of the first active layer and the extension direction X of the second active layer are countless directions parallel to the largest surface of the substrate 1. Only one extension direction of the first active layer and the extension direction X of the second active layer are shown in the figure for illustration; the extension direction of the first active layer and the extension direction X of the second active layer shown in the figure are the same, but in actual products, the extension direction of the first active layer and the extension direction of the second active layer may be different. The second direction Y is perpendicular to the side of the substrate 1 where the first transistor T1 and the second transistor T2 are disposed.

[0111] Grain boundaries are the most important factor affecting the mobility of the first channel portion 312 and the second channel portion 322. However, the first conductor portion 311, the second conductor portion 313, the third conductor portion 321, and the fourth conductor portion 323 are conductors formed by doping polycrystalline silicon formed by crystallization. Therefore, even if grain boundaries are formed in the first conductor portion 311, the second conductor portion 313, the third conductor portion 321, and the fourth conductor portion 323, their conductivity will not be affected.

[0112] Therefore, the first conductor portion 311 and the second conductor portion 313 may include the first grain boundary 314, or the first conductor portion 311 may include the first grain boundary 314 and the second conductor portion 313 may not include the first grain boundary 314, or the first conductor portion 311 may not include the first grain boundary 314 and the second conductor portion 313 may include the first grain boundary 314. The third conductor portion 321 and the fourth conductor portion 323 may include the second grain boundary 324, or the third conductor portion 321 may not include the second grain boundary 324 and the fourth conductor portion 323 may include the second grain boundary 324.

[0113] The maximum dimension of the first channel portion 312 in the extension direction X of the first active layer is greater than or equal to the maximum dimension of the second channel portion 322 in the extension direction X of the second active layer. Specifically, the maximum dimension of the first channel portion 312 in the extension direction X of the first active layer may be greater than or equal to 2 micrometers and less than or equal to 10 micrometers. For example, the maximum dimension of the first channel portion 312 in the extension direction X of the first active layer may be 2.5 micrometers, 3 micrometers, 3.5 micrometers, 4 micrometers, 4.5 micrometers, 5 micrometers, 5.5 micrometers, 6 micrometers, 6.5 micrometers, 7 micrometers, 7.5 micrometers, 8 micrometers, 8.5 micrometers, 9 micrometers, 9.5 micrometers, etc. Alternatively, the maximum dimension of the first channel portion 312 in the extension direction X of the first active layer may be greater than or equal to 10 micrometers and less than or equal to 30 micrometers. For example, the maximum dimension of the first channel portion 312 in the extension direction X of the first active layer may be 13 micrometers, 15 micrometers, 18 micrometers, 20 micrometers, 22 micrometers, 25 micrometers, 27 micrometers, etc.

[0114] Alternatively, if the maximum dimension of the first channel portion 312 in the extension direction X of the first active layer is slightly greater than or equal to the maximum dimension of the second channel portion 322 in the extension direction X of the second active layer, the second channel portion 322 may include a second grain boundary 324, and the first channel portion 312 may not include a first grain boundary 314. Grain boundaries are the cause of increased roughness in polycrystalline silicon materials. Grain boundaries have prominent protrusions, which cause undulations and are the main defects causing carrier trapping, making them the most important factor affecting mobility. Subgrain boundaries do not cause significant undulations and do not have a significant impact on mobility. Since the maximum dimension of the first channel portion 312 in the extension direction X of the first active layer is small, the first channel portion 312 does not include a first grain boundary 314, thereby further increasing the carrier mobility and on-state current of the formed first transistor T1, meeting the requirements for a driving transistor, and reducing the power consumption of the array substrate and improving overall performance.

[0115] Referring to Figures 2-4, when the maximum dimension of the first channel portion 312 in the extension direction X of the first active layer is greater than the maximum dimension of the second channel portion 322 in the extension direction X of the second active layer, the second channel portion 322 may include a second grain boundary 324, and the first channel portion 312 may also include a first grain boundary 314. The number of second grain boundaries 324 included in the second channel portion 322 is greater than or equal to the number of first grain boundaries 314 included in the first channel portion 312. Since the maximum dimension of the first channel portion 312 in the extension direction X of the first active layer is large, if the grains included in the first channel portion 312 are second grains 325, the number of first grain boundaries 314 included in the first channel portion 312 will be too large, resulting in a lower carrier mobility and a lower on-state current in the formed first transistor T1, which cannot meet the requirements for a driving transistor, and also increases the power consumption of the array substrate and reduces the overall performance. The first channel portion 312 of this disclosure includes a first grain 315, which reduces the number of first grain boundaries 314 included in the first channel portion 312. This results in a larger carrier mobility and a larger on-state current for the formed first transistor T1, meeting the requirements for a driving transistor. Furthermore, it reduces the power consumption of the array substrate and improves the overall performance.

[0116] In this example embodiment, the array substrate has a display area and a non-display area. The non-display area may surround the outer periphery of the display area. For example, the display area may be set as a rectangle and the non-display area may be set as a rectangular frame; the display area may be set as a circle and the non-display area may be set as a circular frame.

[0117] In some exemplary embodiments of this disclosure, the first transistor T1 may be disposed in both the display area and the non-display area. Specifically, for an array substrate in which a gate driver on array (GOA) circuit is disposed in the non-display area, the first transistor T1 may be disposed in the display area as a driving transistor in the pixel driving circuit, and the first transistor T1 may also be disposed in the non-display area as a driving transistor in the gate driving circuit.

[0118] In addition, in some other example embodiments of this disclosure, the first transistor T1 may be located only in the display area, and the first transistor T1 may be located in the display area as a driving transistor in the pixel driving circuit.

[0119] In some exemplary embodiments of this disclosure, in the driving circuit of a sub-pixel, at least two first transistors T1 may be configured, one of which serves as a driving transistor and at least one other first transistor T1 serves as a brightness control transistor. For example, one first transistor T1 may serve as a brightness control transistor, or two, three, or more first transistors T1 may serve as brightness control transistors. At least two second transistors T2 may be configured, at least one of which serves as a switching transistor. For example, one second transistor T2 may serve as a switching transistor, or two, three, or more second transistors T2 may serve as a switching transistor. At least one other second transistor T2 serves as a reset transistor. For example, one second transistor T2 may serve as a reset transistor, or two, three, or more second transistors T2 may serve as a reset transistor.

[0120] Referring to FIG1, the distance between the second active layer 32 and the substrate 1 in the second direction Y is equal to the distance between the first active layer 31 and the substrate 1 in the second direction Y, that is, the second active layer 32 and the first active layer 31 are disposed in the same layer.

[0121] The specific fabrication process is as follows: Referring to FIG5, an amorphous silicon film layer (a-Si) is formed on the side of the first buffer layer 2 facing away from the substrate 1. The thickness of the amorphous silicon film layer is greater than or equal to 300 angstroms and less than or equal to 1000 angstroms. For example, the thickness of the amorphous silicon film layer can be 350 angstroms, 400 angstroms, 450 angstroms, 500 angstroms, 550 angstroms, 600 angstroms, 650 angstroms, 700 angstroms, 750 angstroms, 800 angstroms, 850 angstroms, 900 angstroms, 950 angstroms, etc. A second polycrystalline silicon layer 32a is formed by full-surface crystallization using an ELA (Excimer Laser Annealing) process. Referring to FIG4, the second polycrystalline silicon layer 32a includes a second grain 325. The specific structure of the second grain 325 has been described in detail above, therefore, it will not be repeated here. Referring to Figures 6 and 7, selective localized large grain fabrication is performed to form a transition layer. This transition layer includes a second polysilicon layer 32a and a first polysilicon layer 31a. Specifically, a mask is placed on the second polysilicon layer 32a, and laser irradiation is performed on the light-transmitting area of ​​the mask. This causes the second polysilicon layer 32a opposite to the light-transmitting area to completely melt, while the second polysilicon layer 32a not opposite to the light-transmitting area remains solid. During cooling, a supercooled interface is formed at the solid-liquid interface, where crystal nuclei are formed, serving as the starting point for the lateral growth of large grains. During the lateral grain growth process, the growth of most grains is terminated by collisions, ultimately forming a smaller number but larger lateral large grains as shown in Figure 2 or Figure 3, resulting in the overall structure shown in Figure 6. Referring to Figure 8, the transition layer is patterned to form a first active material layer 31b and a second active material layer 32b.

[0122] Excimer laser annealing is a technique that uses an excimer laser to heat the active material layer of amorphous silicon, transforming it into a polycrystalline silicon thin film. It offers advantages such as low processing temperature and short processing time. The key to improving grain size using excimer laser annealing lies in three points: ① forming a moderate or even small number of crystal nuclei; ② reducing the rate of crystallization and solidification; ③ the presence of a supercooled interface for nucleation. The polycrystalline silicon grains formed using excimer laser annealing have a size of approximately 300 nm and a field-effect mobility of 80–160 cm² / V·s. Referring to Figure 23, when the crystallization energy is too low, the amorphous silicon film (a-Si) partially melts. The unmelted portion at the bottom of the film acts as a crystal nucleus during cooling. At this time, the nucleus density is high, and the grains grow vertically, forming small columnar crystals. The second grain 325 is relatively small. Referring to Figure 24, when the crystallization energy is appropriate, the amorphous silicon film (a-Si) is nearly completely melted, but a moderate amount of unmelted portion remains as a crystal nucleus. The growth directions of the nuclei are transverse and longitudinal, eventually pressing against each other to form a second grain 325 with a size of approximately 300 nm. Referring to Figure 25, when the crystallization energy is too high, the amorphous silicon film (a-Si) completely melts. During cooling, an excessive number of crystal nuclei are randomly formed, eventually resulting in very small microcrystals of the second grain 325.

[0123] Solid-phase crystallization is a traditional annealing method that uses an annealing furnace for heating. It generally involves high heating temperatures and long annealing times. Metal-induced crystallization uses metal-induced nucleation to lower the crystallization temperature, but it suffers from metal contamination and cannot be used in large-scale production at present.

[0124] Referring to Figure 8, a first gate insulating layer 4 is disposed on the side of the first active layer 31 and the second active layer 32 facing away from the substrate 1. The thickness of the first gate insulating layer 4 is greater than or equal to 800 angstroms and less than or equal to 2000 angstroms. For example, the thickness of the first gate insulating layer 4 can be 1000 angstroms, 1200 angstroms, 1500 angstroms, 1700 angstroms, etc. The first gate insulating layer 4 can be configured as a single-layer structure. For example, the material of the first gate insulating layer 4 can be a single-layer structure of SiN or SiO. The first gate insulating layer 4 can be configured as a double-layer or multi-layer stacked structure. For example, the first gate insulating layer 4 can be a double-layer stacked structure of SiN and SiO.

[0125] Referring to FIG9, a first gate layer 5 is disposed on the side of the first gate insulating layer 4 facing away from the substrate 1. The first gate layer 5 may include a first gate 51 and a second gate 52. The orthographic projection of the first gate 51 on the substrate 1 overlaps with the first channel portion 312, and the orthographic projection of the second gate 52 on the substrate 1 overlaps with the second channel portion 322. Generally, the first active material layer and the second active material layer 32b are doped with the first gate layer 5 as a shield, so that the first active material layer 31b forms a first active layer 31 including a first conductor portion 311, a first channel portion 312 and a second conductor portion 313 connected in sequence, and the second active material layer 32b forms a first active layer 31 including a third conductor portion 321, a second channel portion 322 and a fourth conductor portion 323 connected in sequence. Therefore, the orthographic projection of the first channel portion 312 on the substrate 1 is located within the orthographic projection of the first gate 51 on the substrate 1, and the orthographic projection of the second channel portion 322 on the substrate 1 is located within the orthographic projection of the second gate 52 on the substrate 1.

[0126] The first gate layer 5 can be made of a high-temperature resistant metal material. For example, the material of the first gate layer 5 can include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first gate layer 5 can be a single-layer film or a multilayer film. The thickness of the first gate layer 5 is greater than or equal to 2000 angstroms and less than or equal to 5000 angstroms. For example, the thickness of the first gate layer 5 can be 2200 angstroms, 2500 angstroms, 2700 angstroms, 3000 angstroms, 3300 angstroms, 3500 angstroms, 3800 angstroms, 4000 angstroms, 4200 angstroms, 4500 angstroms, 4700 angstroms, etc. A plurality of first vias are provided on the first gate insulating layer 4, and the first vias are respectively connected to the first conductor portion 311, the second conductor portion 313, the third conductor portion 321 and the fourth conductor portion 323.

[0127] Referring to FIG1, a first interlayer dielectric layer 61 is disposed on the side of the first gate layer 5 facing away from the substrate 1. The first interlayer dielectric layer 61 can be configured as a single-layer structure, for example, the material of the first interlayer dielectric layer 61 can be a single-layer structure of SiN film or SiO film. The first interlayer dielectric layer 61 can be configured as a double-layer or multi-layer stacked structure, for example, the first interlayer dielectric layer 61 can be a double-layer stacked structure of SiN film and SiO film. The thickness of the SiN film is greater than or equal to 500 angstroms and less than or equal to 5000 angstroms, for example, the thickness of the SiN film can be 800 angstroms, 1000 angstroms, 1200 angstroms, 1500 angstroms, 1700 angstroms, 2000 angstroms, 2200 angstroms, 2500 angstroms, 2700 angstroms, 3000 angstroms, 3300 angstroms, 3500 angstroms, 3800 angstroms, 4000 angstroms, 4200 angstroms, 4500 angstroms, 4700 angstroms, etc. The thickness of the SiO film is greater than or equal to 500 angstroms and less than or equal to 5000 angstroms. For example, the thickness of the SiO film can be 800 angstroms, 1000 angstroms, 1200 angstroms, 1500 angstroms, 1700 angstroms, 2000 angstroms, 2200 angstroms, 2500 angstroms, 2700 angstroms, 3000 angstroms, 3300 angstroms, 3500 angstroms, 3800 angstroms, 4000 angstroms, 4200 angstroms, 4500 angstroms, 4700 angstroms, etc.

[0128] A plurality of second vias are provided on the first interlayer dielectric layer 61, and the second vias are connected to the first vias, so that the second vias are also connected to the first conductor portion 311, the second conductor portion 313, the third conductor portion 321 and the fourth conductor portion 323 respectively.

[0129] Referring to FIG1, a first connection conductor layer 111 is provided on the side of the first interlayer dielectric layer 61 facing away from the substrate 1. The first connection conductor layer 111 may include a first connection portion 1111, a second connection portion 1112, a third connection portion 1113, and a fourth connection portion 1114. The first connection portion 1111 is connected to the first conductor portion 311. Specifically, the first connection portion 1111 is connected to the first conductor portion 311 through a first via and a second via. The second connection portion 1112 is connected to the second conductor portion 313. Specifically, the second connection portion 1112 is connected to the second conductor portion 313 through a first via and a second via. The third connection portion 1113 is connected to the third conductor portion 321. Specifically, the third connection portion 1113 is connected to the third conductor portion 321 through a first via and a second via. The fourth connection portion 1114 is connected to the fourth conductor portion 323. Specifically, the fourth connection portion 1114 is connected to the fourth conductor portion 323 through a first via and a second via.

[0130] Referring to FIG10, in some exemplary embodiments of this disclosure, the second active layer 32 may be disposed on the side of the first active layer 31 away from the substrate 1, and the orthographic projection of the first active layer 31 on the substrate 1 overlaps with the orthographic projection of the second active layer 32 on the substrate 1. For example, the orthographic projection of the first active layer 31 on the substrate 1 and the orthographic projection of the second active layer 32 on the substrate 1 may completely coincide, or the orthographic projection of the first active layer 31 on the substrate 1 may be located within the orthographic projection of the second active layer 32 on the substrate 1, or the orthographic projection of the second active layer 32 on the substrate 1 may be located within the orthographic projection of the first active layer 31 on the substrate 1, or a portion of the orthographic projection of the second active layer 32 on the substrate 1 may overlap with a portion of the orthographic projection of the first active layer 31 on the substrate 1.

[0131] In this case, referring to Figure 11, the first active material layer 31b is first formed. Specifically, an amorphous silicon film layer (a-Si) is formed on the side of the first buffer layer 2 facing away from the substrate 1. The thickness of the amorphous silicon film layer has been described in detail above and will not be repeated here. A mask is placed on the amorphous silicon film layer, and laser irradiation is performed on the light-transmitting area of ​​the mask, so that the amorphous silicon film layer opposite to the light-transmitting area is completely melted, while the amorphous silicon film layer not opposite to the light-transmitting area remains in a solid state. During cooling, an undercooled interface is formed at the solid-liquid interface, and crystal nuclei are formed at the undercooled interface, serving as the starting point for the lateral growth of large grains. During the lateral growth of grains, the growth of most grains is terminated by collisions, eventually forming a small number of large lateral grains as shown in Figure 2 or Figure 3. Then, patterning processing is performed to form the first active material layer 31b.

[0132] Referring to Figure 10, the array substrate may further include a first gate insulating layer 4, a first gate layer 5, a second buffer layer 64, a second gate insulating layer 62, a second gate layer 52, a first interlayer dielectric layer 61, and a first interconnecting conductor layer 111. Referring to Figures 10 and 11, the first gate insulating layer 4 is disposed on the side of the first active layer 31 facing away from the substrate 1. The material and thickness of the first gate insulating layer 4 have been described in detail above and will not be repeated here. A plurality of first vias are provided on the first gate insulating layer 4, and the first vias connect to the first conductor portion 311.

[0133] Referring to Figures 10 and 12, the first gate layer 5 is disposed on the side of the first gate insulating layer 4 facing away from the substrate 1. The material and thickness of the first gate layer 5 have been described in detail above and will not be repeated here. The first gate layer 5 may include a first gate 51.

[0134] After the first gate 51 is formed, the first active material layer 31b is doped with the first gate 51 as a shield. That is, the part that is shielded by the first gate 51 is not doped and is still a semiconductor as the first channel portion 312. The part that is not shielded by the first gate 51 is doped to form the first conductor portion 311 and the second conductor portion 313. Therefore, the orthogonal projection of the first channel portion 312 on the substrate 1 is located within the orthogonal projection of the first gate 51 on the substrate 1.

[0135] Referring to Figures 10 and 13, a second buffer layer 64 is disposed on the side of the first gate layer 5 facing away from the substrate 1. The material of the second buffer layer 64 can be silicon oxide, and the thickness of the second buffer layer 64 is greater than or equal to 1000 angstroms and less than or equal to 4000 angstroms. For example, the thickness of the second buffer layer 64 can be 1200 angstroms, 1500 angstroms, 1700 angstroms, 2000 angstroms, 2200 angstroms, 2500 angstroms, 2700 angstroms, 3000 angstroms, 3300 angstroms, 3500 angstroms, 3800 angstroms, etc. A via communicating with the first via is also provided on the second buffer layer 64.

[0136] The second active layer 32 is disposed on the side of the second buffer layer 64 facing away from the substrate 1. The second active layer 32 may further include a third conductor portion 321 and a fourth conductor portion 323 connected to the second channel portion 322, wherein the third conductor portion 321 is connected to the first conductor portion 311. Of course, in some other exemplary embodiments of this disclosure, the third conductor portion 321 may be connected to the second conductor portion 313, or the third conductor portion 321 may be connected to the first conductor portion 311, and the fourth conductor portion 323 may be connected to the second conductor portion 313.

[0137] In this case, a second active material layer 32b is first formed. Specifically, an amorphous silicon film layer (a-Si) is formed on the side of the second buffer layer 64 facing away from the substrate 1. The thickness of the amorphous silicon film layer has been described in detail above and will not be repeated here. The amorphous silicon film layer is crystallized on its entire surface using an ELA (Excimer Laser Annealing) process to form a second polycrystalline silicon layer 32a, and the second polycrystalline silicon layer 32a is patterned to form the second active material layer 32b.

[0138] Please refer to Figures 10 and 13. The second gate insulating layer 62 is disposed on the side of the second active layer 32 away from the substrate 1. The material of the second gate insulating layer 62 can be the same as that of the first gate insulating layer 4, and the thickness of the second gate insulating layer 62 can also be basically the same as that of the first gate insulating layer 4. This will not be elaborated further here.

[0139] The second gate 52 layer is disposed on the side of the second gate insulating layer 62 away from the substrate 1, and the second gate 52 layer may include the second gate 52.

[0140] After the second gate 52 is formed, the second active material layer 32b is doped with the second gate 52 as a shield. That is, the part that is shielded by the second gate 52 is not doped and is still a semiconductor as the second channel portion 322. The part that is not shielded by the second gate 52 is doped to form the third conductor portion 321 and the fourth conductor portion 323. Therefore, the orthogonal projection of the second channel portion 322 on the substrate 1 is located within the orthogonal projection of the second gate 52 on the substrate 1.

[0141] The first interlayer dielectric layer 61 is disposed on the side of the second gate 52 layer away from the substrate 1. The thickness and material of the first interlayer dielectric layer 61 have been described in detail above and will not be repeated here.

[0142] The first connecting conductor layer 111 is disposed on the side of the first interlayer dielectric layer 61 facing away from the substrate 1. The first connecting conductor layer 111 may include a first connecting portion 1111 and a second connecting portion 1112. The first connecting portion 1111 is connected to the third conductor portion 321. Specifically, the first connecting portion 1111 is connected to the third conductor portion 321 through vias on the first interlayer dielectric layer 61 and the second gate insulating layer 62. The second connecting portion 1112 is connected to the fourth conductor portion 323. Specifically, the second connecting portion 1112 is connected to the fourth conductor portion 323 through vias on the first interlayer dielectric layer 61 and the second gate insulating layer 62. This allows the first connecting portion 1111 to be indirectly connected to the first conductor portion 311 through the third conductor portion 321, thereby reducing the number of vias used to connect the first conductor portion 311, reducing the number and total area of ​​vias, thereby improving the aperture ratio and light extraction efficiency; and also helping to improve the resolution of the array substrate.

[0143] This configuration allows the first transistor T1 and the second transistor T2 to be stacked in the second direction Y, reducing the area occupied by the transistors and thus increasing the aperture ratio and light extraction efficiency; it also helps to improve the resolution of the array substrate.

[0144] Moreover, since the maximum size of the first grain 315 included in the first active layer 31 is at the micrometer level in the extension direction X of the first active layer, and the number of first grain boundaries 314 included in the first active layer 31 is small, the side of the first active layer 31 facing away from the substrate 1 is relatively flat, which is conducive to the formation of the second active layer 32 and helps to ensure the stable performance of the second transistor T2.

[0145] Referring to FIG10, when there are two or more second transistors T2, the two or more second transistors T2 are formed by the same process, such that the corresponding film layers of the two or more second transistors T2 are located in the same layer; a portion of the second transistors T2 may not be stacked with the first transistor T1. The first connection conductor layer 111 may also include a third connection portion 1113 and a fourth connection portion 1114. The third connection portion 1113 is connected to the third conductor portion 321 of the second transistor T2 that is not stacked with the first transistor T1 through vias on the first interlayer dielectric layer 61 and the second gate insulating layer 62. The fourth connection portion 1114 is connected to the fourth conductor portion 323 of the second transistor T2 that is not stacked with the first transistor T1 through vias on the first interlayer dielectric layer 61 and the second gate insulating layer 62.

[0146] Of course, in some other example embodiments of this disclosure, the first active layer 31 may be disposed on the side of the second active layer 32 away from the substrate 1. Compared with the example embodiment in FIG10, other film layers may be interchanged accordingly, which will not be described in detail here; other film layers may not be interchanged accordingly; the first transistor T1 may also be disposed on the side of the second transistor T2 away from the substrate 1.

[0147] Referring to FIG14, in some exemplary embodiments of this disclosure, the array substrate may further include a third transistor T3. The third transistor T3 may include a third active layer 7, which is disposed on the side of the first active layer 31 facing away from the substrate 1. The orthographic projection of the third active layer 7 on the substrate 1 does not overlap with the orthographic projection of the first active layer 31 on the substrate 1. The third transistor T3 is a metal oxide transistor, that is, the material of the third active layer 7 is a metal oxide, such as indium gallium zinc oxide (IGZO), indium tin oxide (ITO), gallium oxide (Ga2O3), etc. Metal oxide transistors have advantages such as high mobility, transparency in the visible light region, simple fabrication process, and low cost.

[0148] The first active layer 31 requires high temperature during fabrication, while the material of the third active layer 7 is not heat resistant. Therefore, the third active layer 7 is placed on the side of the first active layer 31 away from the substrate 1. That is, the first active layer 31 is formed first, and then the third active layer 7 is formed. This avoids the high temperature during the fabrication of the first active layer 31 from affecting the third active layer 7 and ensures the electrical performance of the third transistor T3.

[0149] Specifically, the first active layer 31 is disposed on the side of the first buffer layer 2 facing away from the substrate 1. The first active layer 31 may include a first conductor portion 311 and a second conductor portion 313 connected to the first channel portion 312. For example, the first conductor portion 311 and the second conductor portion 313 are connected to opposite sides of the first channel portion 312. The array substrate may also include a first gate insulating layer 4, a first gate layer 5, an insulating layer group 6, a third gate insulating layer 8, a third gate layer 9, a second interlayer dielectric layer 10, and a first connection conductor layer 111.

[0150] The first gate insulating layer 4 is disposed on the side of the first active layer 31 facing away from the substrate 1; the material and thickness of the first gate insulating layer 4 have been described in detail above and will not be repeated here. The first gate insulating layer 4 is provided with a plurality of first vias, which are connected to the first conductor portion 311 and the second conductor portion 313.

[0151] The first gate layer 5 is disposed on the side of the first gate insulating layer 4 facing away from the substrate 1. The first gate layer 5 includes at least a first gate 51. For example, if the array substrate does not include the second transistor T2, the first gate layer 5 includes the first gate 51; if the array substrate also includes the second transistor T2, the first gate layer 5 includes the first gate 51 and the second gate 52. The specific structure and fabrication method of the first gate 51 and the second gate 52 can be the same as those in the first example embodiment, and therefore will not be described again here.

[0152] An insulating layer group 6 is disposed on the side of the first gate layer 5 facing away from the substrate 1. The insulating layer group 6 may include a second gate insulating layer 62, a first interlayer dielectric layer 61, and a second buffer layer 64, which are sequentially stacked. The material of the second gate insulating layer 62 may be the same as that of the first gate insulating layer 4, and the thickness of the second gate insulating layer 62 may also be substantially the same as the thickness of the first gate insulating layer 4. The material and thickness of the first interlayer dielectric layer 61 have been described in detail in the first exemplary embodiment, and therefore will not be repeated here. The material and thickness of the second buffer layer 64 have also been described in detail in the second exemplary embodiment, and will not be repeated here either.

[0153] The third active layer 7 is disposed on the side of the insulating layer group 6 away from the substrate 1. The third active layer 7 may include a fifth conductor portion 71, a third channel portion 72 and a sixth conductor portion 73 connected in sequence. For example, the fifth conductor portion 71 and the sixth conductor portion 73 may be connected to opposite sides of the third channel portion 72.

[0154] The third gate insulating layer 8 is disposed on the side of the third active layer 7 away from the substrate 1; vias may also be disposed on the third gate insulating layer 8. The third gate layer 9 is disposed on the side of the third gate insulating layer 8 away from the substrate 1. The third gate layer 9 may include a third gate 91, which is disposed opposite to the third channel portion 72. Specifically, the orthogonal projection of the third channel portion 72 on the substrate 1 is located within the orthogonal projection of the third gate 91 on the substrate 1.

[0155] The second interlayer dielectric layer 10 is disposed on the side of the third gate layer 9 away from the substrate 1; vias may also be disposed on the second interlayer dielectric layer 10.

[0156] The first connecting conductor layer 111 is disposed on the side of the second interlayer dielectric layer 10 facing away from the substrate 1. The first connecting conductor layer 111 may include a first connecting portion 1111, a second connecting portion 1112, a third connecting portion 1113, and a fourth connecting portion 1114. The first connecting portion 1111 is connected to the first conductor portion 311. Specifically, the first connecting portion 1111 is connected to the first conductor portion 311 through vias on the second interlayer dielectric layer 10, the third gate insulating layer 8, the insulating layer group 6, and the first gate insulating layer 4. The second connecting portion 1112 is connected to the second conductor portion 313. The second connection portion 1112 is connected to the second conductor portion 313 through vias on the second interlayer dielectric layer 10, the third gate insulating layer 8, the insulating layer group 6, and the first gate insulating layer 4; the third connection portion 1113 is connected to the fifth conductor portion 71, specifically, the third connection portion 1113 is connected to the fifth conductor portion 71 through vias on the second interlayer dielectric layer 10 and the third gate insulating layer 8; the fourth connection portion 1114 is connected to the sixth conductor portion 73, specifically, the fourth connection portion 1114 is connected to the sixth conductor portion 73 through vias on the second interlayer dielectric layer 10 and the third gate insulating layer 8.

[0157] When a second transistor T2 is provided, the first connection conductor layer 111 may further include a fifth connection portion 1115 and a sixth connection portion 1116. The fifth connection portion 1115 is connected to the third conductor portion 321 through vias on the second interlayer dielectric layer 10, the third gate insulating layer 8, the insulating layer group 6, and the first gate insulating layer 4. The sixth connection portion 1116 is connected to the fourth conductor portion 323 through vias on the second interlayer dielectric layer 10, the third gate insulating layer 8, the insulating layer group 6, and the first gate insulating layer 4.

[0158] Referring to Figures 15-18 and 22, in some exemplary embodiments of this disclosure, the array substrate may further include a third transistor T3. The third transistor T3 may include a third active layer 7, which is disposed on the side of the first active layer 31 facing away from the substrate 1. The orthographic projection of the third active layer 7 on the substrate 1 overlaps with the orthographic projection of the first active layer 31 on the substrate 1. For example, the orthographic projection of the third active layer 7 on the substrate 1 may be located within the orthographic projection of the first active layer 31 on the substrate 1; a portion of the orthographic projection of the third active layer 7 on the substrate 1 may overlap with a portion of the orthographic projection of the first active layer 31 on the substrate 1; or the orthographic projection of the first active layer 31 on the substrate 1 may be located within the orthographic projection of the third active layer 7 on the substrate 1. The third transistor T3 is a metal-oxide transistor, that is, the material of the third active layer 7 is a metal oxide, such as indium gallium zinc oxide (IGZO), indium tin oxide (ITO), gallium oxide (Ga2O3), etc. Metal-oxide transistors have advantages such as high mobility, transparency in the visible light region, simple fabrication process, and low cost.

[0159] The first active layer 31 requires high temperature during fabrication, while the material of the third active layer 7 is not heat resistant. Therefore, the third active layer 7 is placed on the side of the first active layer 31 away from the substrate 1. That is, the first active layer 31 is formed first, and then the third active layer 7 is formed. This avoids the high temperature during the fabrication of the first active layer 31 from affecting the third active layer 7 and ensures the electrical performance of the third transistor T3.

[0160] In some exemplary embodiments of this disclosure, in the driving circuit of a sub-pixel, at least two first transistors T1 may be configured, one of which serves as a driving transistor and at least one other first transistor T1 serves as a brightness control transistor. For example, one first transistor T1 may serve as a brightness control transistor, or two, three, or more first transistors T1 may serve as brightness control transistors. At least two third transistors T3 may be configured, at least one of which serves as a switching transistor. For example, one third transistor T3 may serve as a switching transistor, or two, three, or more third transistors T3 may serve as a switching transistor. At least one other third transistor T3 serves as a reset transistor. For example, one third transistor T3 may serve as a reset transistor, or two, three, or more third transistors T3 may serve as a reset transistor.

[0161] Since the maximum size of the first grain 315 included in the first active layer 31 is at the micrometer level in the extension direction X of the first active layer, and the number of the first grain boundaries 314 included in the first active layer 31 is small, the first protrusion formed on the side of the first active layer 31 away from the substrate 1 is less and flatter, which is conducive to the formation of the third active layer 7 and helps to ensure the stable performance of the third transistor T3.

[0162] However, the second active layer 32 includes a second grain 325 whose maximum size in the extension direction X of the second active layer is on the order of hundreds of nanometers. The second active layer 32 includes a large number of second grain boundaries 324, which results in more second protrusions on the side of the second active layer 32 away from the substrate 1, and poor flatness. This is not conducive to the formation of the third active layer 7 and is not conducive to ensuring the stable performance of the third transistor T3.

[0163] With the second transistor T2 provided, the orthographic projection of the third active layer 7 on the substrate 1 does not overlap with the orthographic projection of the second active layer 32 on the substrate 1; this avoids the unfavorable formation of the third active layer 7 caused by the poor flatness of the second active layer 32, thus ensuring the stable performance of the third transistor T3.

[0164] Furthermore, by stacking the first transistor T1 and the third transistor T3 in the second direction Y, the area occupied by the transistors is reduced, thereby increasing the aperture ratio and light extraction efficiency; it also helps to improve the resolution of the array substrate.

[0165] Specifically, referring to FIG15, the first active layer 31 is disposed on the side of the first buffer layer 2 facing away from the substrate 1. The first active layer 31 may include a first conductor portion 311 and a second conductor portion 313 connected to the first channel portion 312. For example, the first conductor portion 311 and the second conductor portion 313 are connected to opposite sides of the first channel portion 312. The array substrate may also include a first gate insulating layer 4, a first gate layer 5, an insulating layer group 6, a third gate insulating layer 8, a third gate layer 9, a second interlayer dielectric layer 10, and a first connection conductor layer 111.

[0166] The first gate insulating layer 4 is disposed on the side of the first active layer 31 facing away from the substrate 1; the material and thickness of the first gate insulating layer 4 have been described in detail above and will not be repeated here. The first gate insulating layer 4 is provided with a plurality of first vias, which are connected to the first conductor portion 311 and the second conductor portion 313.

[0167] The first gate layer 5 is disposed on the side of the first gate insulating layer 4 facing away from the substrate 1. The first gate layer 5 includes at least a first gate 51. For example, if the array substrate does not include the second transistor T2, the first gate layer 5 includes the first gate 51; if the array substrate also includes the second transistor T2, the first gate layer 5 includes the first gate 51 and the second gate 52. The specific structure and fabrication method of the first gate 51 and the second gate 52 can be the same as those in the first example embodiment, and therefore will not be described again here.

[0168] An insulating layer group 6 is disposed on the side of the first gate layer 5 facing away from the substrate 1. The insulating layer group 6 may include a second gate insulating layer 62, a first interlayer dielectric layer 61, and a second buffer layer 64, which are sequentially stacked. The material of the second gate insulating layer 62 may be the same as that of the first gate insulating layer 4, and the thickness of the second gate insulating layer 62 may also be substantially the same as the thickness of the first gate insulating layer 4. The material and thickness of the first interlayer dielectric layer 61 have been described in detail in the first exemplary embodiment, and therefore will not be repeated here. The material and thickness of the second buffer layer 64 have also been described in detail in the second exemplary embodiment, and will not be repeated here either.

[0169] The third active layer 7 is disposed on the side of the insulating layer group 6 away from the substrate 1. The third active layer 7 may include a fifth conductor portion 71, a third channel portion 72 and a sixth conductor portion 73 connected in sequence. For example, the fifth conductor portion 71 and the sixth conductor portion 73 may be connected to opposite sides of the third channel portion 72.

[0170] The third gate insulating layer 8 is disposed on the side of the third active layer 7 away from the substrate 1; vias may also be disposed on the third gate insulating layer 8. The third gate layer 9 is disposed on the side of the third gate insulating layer 8 away from the substrate 1. The third gate layer 9 may include a third gate 91, which is disposed opposite to the third channel portion 72. Specifically, the orthogonal projection of the third channel portion 72 on the substrate 1 is located within the orthogonal projection of the third gate 91 on the substrate 1.

[0171] The second interlayer dielectric layer 10 is disposed on the side of the third gate layer 9 away from the substrate 1; vias may also be disposed on the second interlayer dielectric layer 10.

[0172] The first connecting conductor layer 111 is disposed on the side of the second interlayer dielectric layer 10 facing away from the substrate 1. The first connecting conductor layer 111 may include a first connecting portion 1111 and a second connecting portion 1112. The first connecting portion 1111 is connected to the first conductor portion 311 and the fifth conductor portion 71. Specifically, one branch of the first connecting portion 1111 is connected to the first conductor portion 311 through a via on the second interlayer dielectric layer 10, the third gate insulating layer 8, the insulating layer group 6, and the first gate insulating layer 4. The second interlayer dielectric layer 10 and the vias on the third gate insulating layer 8 are connected to the fifth conductor portion 71; the second connection portion 1112 is connected to the second conductor portion 313 and the sixth conductor portion 73. Specifically, one branch of the second connection portion 1112 is connected to the second conductor portion 313 through vias on the second interlayer dielectric layer 10, the third gate insulating layer 8, the insulating layer group 6, and the first gate insulating layer 4, and the other branch of the second connection portion 1112 is connected to the sixth conductor portion 73 through vias on the second interlayer dielectric layer 10 and the third gate insulating layer 8. This arrangement allows the first conductor portion 311 to be connected to the fifth conductor portion 71 through the first connection portion 1111, avoiding the need for numerous connecting wires; the second conductor portion 313 to be connected to the sixth conductor portion 73 through the second connection portion 1112, also avoiding the need for numerous connecting wires; thereby improving the aperture ratio and light extraction efficiency; and also improving the resolution of the array substrate.

[0173] In other example embodiments of this disclosure, the first connecting portion 1111 may be connected to the first conductor portion 311 and the fifth conductor portion 71, the second connecting portion 1112 may be connected to the second conductor portion 313, and the first connecting conductor layer 111 may also include a seventh connecting portion connected to the sixth conductor portion 73, that is, the second conductor portion 313 and the sixth conductor portion 73 are connected by different connecting portions; or the second connecting portion 1112 may be connected to the second conductor portion 313 and the sixth conductor portion 73, the first connecting portion 1111 may be connected to the first conductor portion 311, and the first connecting conductor layer 111 may also include a seventh connecting portion connected to the fifth conductor portion 71, that is, the first conductor portion 311 and the fifth conductor portion 71 are connected by different connecting portions.

[0174] Referring to FIG15, when the second transistor T2 is provided, the first connection conductor layer 111 may further include a fifth connection portion 1115 and a sixth connection portion 1116. The fifth connection portion 1115 is connected to the third conductor portion 321 through vias on the second interlayer dielectric layer 10, the third gate insulating layer 8, the insulating layer group 6 and the first gate insulating layer 4. The sixth connection portion 1116 is connected to the fourth conductor portion 323 through vias on the second interlayer dielectric layer 10, the third gate insulating layer 8, the insulating layer group 6 and the first gate insulating layer 4.

[0175] Referring to FIG16, the array substrate may further include a shielding layer 12, which is disposed between the second gate insulating layer 62 and the first interlayer dielectric layer 61. The shielding layer 12 may include a shielding portion 121, the orthographic projection of the shielding portion 121 on the substrate 1 overlapping with the orthographic projections of the first gate 51 and the third gate 91 on the substrate 1. For example, the edge line of the orthographic projection of the shielding portion 121 on the substrate 1 may coincide with the edge line of the orthographic projection of the first gate 51 on the substrate 1, or the orthographic projection of the first gate 51 on the substrate 1 may be located within the orthographic projection of the shielding portion 121 on the substrate 1, so that the orthographic projection of the shielding portion 121 on the substrate 1 completely covers the orthographic projection of the first gate 51 on the substrate 1. Electromagnetic shielding can be performed between the first gate 51 and the third gate 91 by the shielding portion 121, avoiding signal crosstalk problems between the first gate 51 and the third gate 91.

[0176] Of course, in some other exemplary embodiments of this disclosure, a portion of the orthogonal projection of the first gate 51 on the substrate 1 may overlap with a portion of the orthogonal projection of the shielding portion 121 on the substrate 1; the orthogonal projection of the shielding portion 121 on the substrate 1 may completely cover the orthogonal projection of the third gate 91 on the substrate 1; or a portion of the orthogonal projection of the shielding portion 121 on the substrate 1 may overlap with a portion of the orthogonal projection of the third gate 91 on the substrate 1.

[0177] Referring to FIG17, in some other exemplary embodiments of this disclosure, the shielding layer 12 may be omitted. In this case, the insulating layer group 6 may include a second gate insulating layer 62, a first interlayer dielectric layer 61, an electromagnetic shielding layer 63, and a second buffer layer 64 stacked sequentially. The electromagnetic shielding layer 63 (Silicone Oxide Glass, abbreviated as SOG) has excellent electrical insulation, thermal stability, weather resistance, and biocompatibility, which can reduce electromagnetic interference (EMI) and improve the electromagnetic compatibility (EMC) of the device. Therefore, the electromagnetic shielding layer 63 can provide electromagnetic shielding between the first gate 51 and the third gate 91, avoiding signal crosstalk between the first gate 51 and the third gate 91. The electromagnetic shielding layer 63 can be set as a single layer without patterning, thus saving one patterning process and reducing costs.

[0178] Referring to FIG18, in some exemplary embodiments of this disclosure, a first active layer 31 is disposed on the side of the first buffer layer 2 facing away from the substrate 1. The first active layer 31 may include a first conductor portion 311 and a second conductor portion 313 connected to the first channel portion 312. For example, the first conductor portion 311 and the second conductor portion 313 are connected to opposite sides of the first channel portion 312. The array substrate may also include a first gate insulating layer 4, a first gate layer 5, an insulating layer group 6, a first connection conductor layer 111, a third gate insulating layer 8, a third gate layer 9, a second interlayer dielectric layer 10, and a second connection conductor layer 112.

[0179] The first gate insulating layer 4 is disposed on the side of the first active layer 31 facing away from the substrate 1; the material and thickness of the first gate insulating layer 4 have been described in detail above and will not be repeated here. The first gate insulating layer 4 is provided with a plurality of first vias, which are connected to the first conductor portion 311 and the second conductor portion 313.

[0180] The first gate layer 5 is disposed on the side of the first gate insulating layer 4 facing away from the substrate 1. The first gate layer 5 includes at least a first gate 51. For example, if the array substrate does not include the second transistor T2, the first gate layer 5 includes the first gate 51; if the array substrate also includes the second transistor T2, the first gate layer 5 includes the first gate 51 and the second gate 52. The specific structure and fabrication method of the first gate 51 and the second gate 52 can be the same as those in the first example embodiment, and therefore will not be described again here.

[0181] An insulating layer group 6 is disposed on the side of the first gate layer 5 facing away from the substrate 1. The insulating layer group 6 may include a second gate insulating layer 62, a first interlayer dielectric layer 61, and a second buffer layer 64 stacked sequentially. The material of the second gate insulating layer 62 may be the same as that of the first gate insulating layer 4, and the thickness of the second gate insulating layer 62 may also be substantially the same as the thickness of the first gate insulating layer 4. The first interlayer dielectric layer 61 may be a single-layer structure, for example, the material of the first interlayer dielectric layer 61 may be a single-layer structure of SiN film or SiO film. The first interlayer dielectric layer 61 may be a double-layer or multi-layer stacked structure, for example, the first interlayer dielectric layer 61 may be a double-layer stacked structure of SiN film and SiO film. The thickness of the SiN film is greater than or equal to 800 angstroms and less than or equal to 2000 angstroms, for example, the thickness of the SiN film may be 1000 angstroms, 1200 angstroms, 1500 angstroms, 1700 angstroms, etc. The thickness of the SiO film is greater than or equal to 800 angstroms and less than or equal to 2000 angstroms. For example, the thickness of the SiO film can be 1000 angstroms, 1200 angstroms, 1500 angstroms, 1700 angstroms, etc.

[0182] The second buffer layer 64 can be made of silicon oxide, and its thickness is greater than or equal to 500 angstroms and less than or equal to 3000 angstroms. For example, the thickness of the second buffer layer 64 can be 800 angstroms, 1000 angstroms, 1200 angstroms, 1500 angstroms, 1700 angstroms, 2000 angstroms, 2200 angstroms, 2500 angstroms, 2700 angstroms, etc. The second buffer layer 64 can also be a double-layer stacked structure of SiN film and SiO film, with the SiN film thickness greater than or equal to 500 angstroms and less than or equal to 1000 angstroms. For example, the thickness of the SiN film can be 600 angstroms, 700 angstroms, 800 angstroms, 900 angstroms, etc. Through-holes are also provided on the second buffer layer 64.

[0183] A first connecting conductor layer 111 is provided between two insulating layers in insulating layer group 6. For example, as shown in FIG18, the first connecting conductor layer 111 can be provided between the second gate insulating layer 62 and the first interlayer dielectric layer 61. As shown in FIG22, the first connecting conductor layer 111 can also be provided between the first interlayer dielectric layer 61 and the second buffer layer 64.

[0184] Referring to Figures 18 and 19, the first connecting conductor layer 111 may include a first connecting portion 1111 and a second connecting portion 1112. The first connecting portion 1111 is connected to the first conductor portion 311. Specifically, the first connecting portion 1111 is connected to the first conductor portion 311 through the second gate insulating layer 62 and the vias on the first gate insulating layer 4. The second connecting portion 1112 is connected to the second conductor portion 313. Specifically, the second connecting portion 1112 is connected to the second conductor portion 313 through the second gate insulating layer 62 and the vias on the first gate insulating layer 4.

[0185] When a second transistor T2 is provided, the first connection conductor layer 111 may further include a third connection portion 1113 and a fourth connection portion 1114. The third connection portion 1113 is connected to the third conductor portion 321 through vias on the second gate insulating layer 62 and the first gate insulating layer 4, and the fourth connection portion 1114 is connected to the fourth conductor portion 323 through vias on the second gate insulating layer 62 and the first gate insulating layer 4.

[0186] Referring to Figures 18 and 21, the third active layer 7 is disposed on the side of the insulating layer group 6 facing away from the substrate 1. The third active layer 7 may include a fifth conductor portion 71, a third channel portion 72, and a sixth conductor portion 73 connected in sequence. For example, the fifth conductor portion 71 and the sixth conductor portion 73 may be connected to opposite sides of the third channel portion 72. The fifth conductor portion 71 is connected to the first connection portion 1111. Specifically, the fifth conductor portion 71 is connected to the first connection portion 1111 through vias on the second buffer layer 64 and the first interlayer dielectric layer 61. The sixth conductor portion 73 is connected to the second connection portion 1112. Specifically, the sixth conductor portion 73 is connected to the second connection portion 1112 through vias on the second buffer layer 64 and the first interlayer dielectric layer 61.

[0187] The third active layer 7 is formed by sputtering. In the vias, the fifth conductor portion 71 and the sixth conductor portion 73 generally do not have defects such as broken wires. Therefore, the connection effect can be guaranteed by connecting the first connection portion 1111 through the fifth conductor portion 71 and connecting the second connection portion 1112 through the sixth conductor portion 73.

[0188] The third gate insulating layer 8 is disposed on the side of the third active layer 7 away from the substrate 1; vias may also be disposed on the third gate insulating layer 8. The third gate layer 9 is disposed on the side of the third gate insulating layer 8 away from the substrate 1, and the third gate layer 9 may include a third gate 91, which is disposed opposite to the third channel portion 72.

[0189] Since the third active material layer deposited by sputtering is still a semiconductor, after the third gate 91 is formed, the third active material layer is heavily doped using the third gate 91 as a shield. Common doping agents include B, P, H, and Ar ions, with doping concentrations typically ranging from 5E14 to 5E15 ions / cm³. 3 That is, the portion of the third gate 91 that is not doped is still a semiconductor and forms the third channel portion 72, while the portion that is not doped is doped to form the fifth conductor portion 71 and the sixth conductor portion 73. Therefore, the orthogonal projection of the third channel portion 72 on the substrate 1 is located within the orthogonal projection of the third gate 91 on the substrate 1.

[0190] Referring to FIG18, the second interlayer dielectric layer 10 is disposed on the side of the third gate layer 9 away from the substrate 1; vias may also be disposed on the second interlayer dielectric layer 10.

[0191] The second connection conductor layer 112 is disposed on the side of the second interlayer dielectric layer 10 facing away from the substrate 1. The second connection conductor layer 112 may include a seventh connection portion 1121 and an eighth connection portion 1122. The seventh connection portion 1121 is connected to the fifth conductor portion 71. Specifically, the seventh connection portion 1121 is connected to the fifth conductor portion 71 through vias on the second interlayer dielectric layer 10 and the third gate insulating layer 8. The eighth connection portion 1122 is connected to the sixth conductor portion 73. Specifically, the eighth connection portion 1122 is connected to the sixth conductor portion 73 through vias on the second interlayer dielectric layer 10 and the third gate insulating layer 8.

[0192] This configuration allows the seventh connecting portion 1121 to be indirectly connected to the first conductor portion 311 via the fifth conductor portion 71, thereby reducing the number of vias used to connect the first conductor portion 311; the eighth connecting portion 1122 can be indirectly connected to the second conductor portion 313 via the sixth conductor portion 73, thereby reducing the number of vias used to connect the second conductor portion 313; reducing the number and total area of ​​vias can improve the aperture ratio and increase the light extraction efficiency; and it is also beneficial to improve the resolution of the array substrate.

[0193] When a second transistor T2 is provided, the second connection conductor layer 112 may further include a ninth connection portion 1123 and a tenth connection portion 1124. The ninth connection portion 1123 is connected to the third connection portion 1113 through vias on the second interlayer dielectric layer 10, the third gate insulating layer 8, the second buffer layer 64, and the first interlayer dielectric layer 61. The tenth connection portion 1124 is connected to the fourth connection portion 1114 through vias on the second interlayer dielectric layer 10, the third gate insulating layer 8, the second buffer layer 64, and the first interlayer dielectric layer 61.

[0194] Referring to FIG22, when the first connecting conductor layer 111 is disposed between the first interlayer dielectric layer 61 and the second buffer layer 64, the first connecting portion 1111 is connected to the first conductor portion 311 through the first interlayer dielectric layer 61, the second gate insulating layer 62 and the vias on the first gate insulating layer 4; the second connecting portion 1112 is connected to the second conductor portion 313 through the first interlayer dielectric layer 61, the second gate insulating layer 62 and the vias on the first gate insulating layer 4.

[0195] When a second transistor T2 is provided, the first connection conductor layer 111 may further include a third connection portion 1113 and a fourth connection portion 1114. The third connection portion 1113 is connected to the third conductor portion 321 through vias on the first interlayer dielectric layer 61, the second gate insulating layer 62 and the first gate insulating layer 4. The fourth connection portion 1114 is connected to the fourth conductor portion 323 through vias on the first interlayer dielectric layer 61, the second gate insulating layer 62 and the first gate insulating layer 4.

[0196] The fifth conductor portion 71 is connected to the first connecting portion 1111 through a through hole on the second buffer layer 64; the sixth conductor portion 73 is connected to the second connecting portion 1112 through a through hole on the second buffer layer 64.

[0197] In some exemplary embodiments of this disclosure, the array substrate may further include a shielding layer 12 disposed between the second gate insulating layer 62 and the first interlayer dielectric layer 61. The shielding layer 12 may include a shielding portion 121, the orthographic projection of the shielding portion 121 on the substrate 1 overlapping with the orthographic projections of the first gate 51 and the third gate 91 on the substrate 1. For example, the edge line of the orthographic projection of the shielding portion 121 on the substrate 1 may coincide with the edge line of the orthographic projection of the first gate 51 on the substrate 1, or the orthographic projection of the first gate 51 on the substrate 1 may be located within the orthographic projection of the shielding portion 121 on the substrate 1, such that the orthographic projection of the shielding portion 121 on the substrate 1 completely covers the orthographic projection of the first gate 51 on the substrate 1. Electromagnetic shielding can be performed between the first gate 51 and the third gate 91 by the shielding portion 121, avoiding signal crosstalk problems between the first gate 51 and the third gate 91.

[0198] Of course, in some other exemplary embodiments of this disclosure, a portion of the orthogonal projection of the first gate 51 on the substrate 1 may overlap with a portion of the orthogonal projection of the shielding portion 121 on the substrate 1; the orthogonal projection of the shielding portion 121 on the substrate 1 may completely cover the orthogonal projection of the third gate 91 on the substrate 1; or a portion of the orthogonal projection of the shielding portion 121 on the substrate 1 may overlap with a portion of the orthogonal projection of the third gate 91 on the substrate 1.

[0199] Referring to Figures 18, 20, and 22, in some other exemplary embodiments of this disclosure, the shielding layer 12 may be omitted. In this case, the insulating layer group 6 may include a second gate insulating layer 62, a first interlayer dielectric layer 61, an electromagnetic shielding layer 63, and a second buffer layer 64 stacked sequentially. The electromagnetic shielding layer 63 may be made of silicone oxide glass (SOG), which has excellent electrical insulation, thermal stability, weather resistance, and biocompatibility. It can reduce electromagnetic interference (EMI) and improve the electromagnetic compatibility (EMC) of the device. Therefore, the electromagnetic shielding layer 63 can provide electromagnetic shielding between the first gate 51 and the third gate 91, avoiding signal crosstalk between the first gate 51 and the third gate 91. The electromagnetic shielding layer 63 can be a single layer without patterning, thus saving a patterning process and reducing costs. The electromagnetic shielding layer 63 may also be made of other organic or inorganic materials with electromagnetic shielding properties, which will not be described in detail here.

[0200] It should be noted that, when an electromagnetic shielding layer 63 is provided, as shown in FIG22, the first connecting conductor layer 111 can be provided between the electromagnetic shielding layer 63 and the second buffer layer 64. A via is also provided on the electromagnetic shielding layer 63, and the first connecting conductor layer 111 needs to be connected to the conductor portion of the lower layer through the via on the electromagnetic shielding layer 63.

[0201] Of course, in some other exemplary embodiments of this disclosure, when an electromagnetic shielding layer 63 is provided, the first connecting conductor layer 111 may be disposed between the electromagnetic shielding layer 63 and the first interlayer dielectric layer 61. The third connecting portion 1113 is connected to the third conductor portion 321 through vias on the first interlayer dielectric layer 61, the second gate insulating layer 62, and the first gate insulating layer 4; the fourth connecting portion 1114 is connected to the fourth conductor portion 323 through vias on the first interlayer dielectric layer 61, the second gate insulating layer 62, and the first gate insulating layer 4. The fifth conductor portion 71 is connected to the first connecting portion 1111 through vias on the second buffer layer 64 and the electromagnetic shielding layer 63; the sixth conductor portion 73 is connected to the second connecting portion 1112 through vias on the second buffer layer 64 and the electromagnetic shielding layer 63; the via depth on the second buffer layer 64 and the electromagnetic shielding layer 63 is approximately 1.36 micrometers, and the overlap resistance is in the hundreds of ohms range.

[0202] When the fifth conductor portion 71 is connected to the first connecting portion 1111 and the sixth conductor portion 73 is connected to the second connecting portion 1112, the overlap resistance is approximately 533 ohms when the aperture of the via is 2.1 micrometers, approximately 208 ohms when the aperture of the via is 3.5 micrometers, and approximately 187 ohms when the aperture of the via is 5 micrometers.

[0203] Referring to Figures 14-18 and 22, when both the second transistor T2 and the third transistor T3 are simultaneously provided, the distance between the second active layer 32 and the substrate 1 in the second direction Y is equal to the distance between the first active layer 31 and the substrate 1 in the second direction Y, that is, the second active layer 32 and the first active layer 31 are disposed in the same layer. Of course, in some other exemplary embodiments of this disclosure, a portion of the second active layer 32 may be disposed on the side of the first active layer 31 facing away from the substrate 1, that is, a portion of the first transistor T1 and the second transistor T2 are stacked, and another portion of the first transistor T1 and the third transistor T3 are stacked.

[0204] It should be noted that the labels of the first transistor T1, the second transistor T2, and the third transistor T3 in the figure are only exemplary labels. Since the connection part may be shared, the connection part may not be included in the label of the transistor.

[0205] The array substrate may include multiple driving circuits, each driving circuit driving one sub-pixel. Referring to FIG26, a driving circuit may include seven thin-film transistors and a storage capacitor Cs. The seven thin-film transistors are designated as a first thin-film transistor M1, a second thin-film transistor M2, a third thin-film transistor M3, a fourth thin-film transistor M4, a fifth thin-film transistor M5, a sixth thin-film transistor M6, and a seventh thin-film transistor M7. The driving circuit has a first node N1, a second node N2, a third node N3, a fourth node N4, and a fifth node N5. The first node N1 is connected to the initialization voltage signal line Vinit, the fifth node N5 is connected to the first electrode of the light-emitting unit OLED, and the second electrode of the light-emitting unit OLED is grounded to VSS. The first thin-film transistor M1 has its first terminal connected to the first node N1, its second terminal connected to the second node N2, and its gate connected to the reset signal line RST. The second thin-film transistor M2 has its first terminal connected to the second node N2, its second terminal connected to the third node N3, and its gate connected to the gate line Gate. The third thin-film transistor M3 has its first terminal connected to the third node N3, its second terminal connected to the fourth node N4, and its gate connected to the second node N2. The fourth thin-film transistor M4 has its first terminal connected to the fourth node N4, its second terminal connected to the data line Data. The gate of transistor M4 is connected to the gate line Gate; the gate of the fifth thin-film transistor M5 is connected to the enable signal line EM, the first connection terminal of the fifth thin-film transistor M5 is connected to the fourth node N4, the second connection terminal of the fifth thin-film transistor M5 is connected to the first terminal of the storage capacitor Cs and connected to the power supply line VDD, and the second terminal of the storage capacitor Cs is connected to the second node N2; the first connection terminal of the sixth thin-film transistor M6 is connected to the third node N3, the second connection terminal of the sixth thin-film transistor M6 is connected to the fifth node N5, and the gate of the sixth thin-film transistor M6 is connected to the enable signal line EM; the first connection terminal of the seventh thin-film transistor M7 is connected to the first node N1, the second connection terminal of the seventh thin-film transistor M7 is connected to the fifth node N5, and the gate of the seventh thin-film transistor M7 is connected to the reset signal line RST.

[0206] In some exemplary embodiments of the present disclosure, for the driving circuit shown in Figure 26, the third thin-film transistor M3 is the driving transistor and the third thin-film transistor M3 is the first transistor T1; any one, any two, any more or all of the first thin-film transistor M1, the second thin-film transistor M2, the fourth thin-film transistor M4, the fifth thin-film transistor M5, the sixth thin-film transistor M6 and the seventh thin-film transistor M7 can be the second transistor T2, and the rest are the first transistor T1.

[0207] In some exemplary embodiments of this disclosure, the third thin-film transistor M3, the fourth thin-film transistor M4, the fifth thin-film transistor M5, and the sixth thin-film transistor M6 may be the first transistor T1; the first thin-film transistor M1, the second thin-film transistor M2, and the seventh thin-film transistor M7 may be the third transistor T3.

[0208] Referring to Figure 27, based on Figure 26, the driving circuit may further include an eighth thin-film transistor M8, a ninth thin-film transistor M9, a tenth thin-film transistor M10, and a first capacitor C1. The driving circuit may also have a sixth node N6 and a seventh node N7. In this case, the gate of the sixth thin-film transistor M6 is connected to the sixth node N6; the first connection terminal of the eighth thin-film transistor M8 is connected to the sixth node N6; the second connection terminal of the eighth thin-film transistor M8 is connected to the light-emitting control line Hf; and the gate of the eighth thin-film transistor M8 is connected to the seventh node N7. The first connection terminal of the ninth thin-film transistor M9 is connected to the sixth node N6; the second connection terminal of the ninth thin-film transistor M9 is connected to the enable signal line EM; and the gate of the ninth thin-film transistor M9 is connected to the seventh node N7. The first connection terminal of the tenth thin-film transistor M10 is connected to the seventh node N7; the second connection terminal of the tenth thin-film transistor M10 is connected to the data line Data; and the gate of the tenth thin-film transistor M10 is connected to the reset signal line RST. The first terminal of the first capacitor C1 is connected to the seventh node N7; and the second terminal of the first capacitor C1 is connected to the initialization voltage signal line Vinit.

[0209] For the driving circuit shown in Figure 27, based on Figure 26, the eighth thin-film transistor M8 can be the first transistor T1; the ninth thin-film transistor M9 and the tenth thin-film transistor M10 can be the third transistor T3, or the ninth thin-film transistor M9 and the tenth thin-film transistor M10 can both be the second transistor T2.

[0210] Referring to Figure 28, based on Figure 26, the driving circuit may further include an eighth thin-film transistor M8, a ninth thin-film transistor M9, a tenth thin-film transistor M10, an eleventh thin-film transistor M11, a first capacitor C1, and a second capacitor C2. The driving circuit may also have a sixth node N6, a seventh node N7, and an eighth node N8. In this case, the gate of the sixth thin-film transistor M6 is connected to the sixth node N6; the first connection terminal of the eighth thin-film transistor M8 is connected to the sixth node N6; the second connection terminal of the eighth thin-film transistor M8 is connected to the light-emitting control line Hf; and the gate of the eighth thin-film transistor M8 is connected to the seventh node N7. The first connection terminal of the ninth thin-film transistor M9 is connected to the sixth node N6; and the second connection terminal of the ninth thin-film transistor M9 is connected to the enable signal line EM. The gate of thin-film transistor M9 is connected to the eighth node N8; the first terminal of the tenth thin-film transistor M10 is connected to the eighth node N8, the second terminal of the tenth thin-film transistor M10 is connected to the data line Data, and the gate of the tenth thin-film transistor M10 is connected to the reset signal line RST; the first terminal of the eleventh thin-film transistor M11 is connected to the seventh node N7, the second terminal of the eleventh thin-film transistor M11 is connected to the data line Data, and the gate of the tenth thin-film transistor M10 is connected to the reset signal line RST; the first terminal of the first capacitor C1 is connected to the seventh node N7, and the second terminal of the first capacitor C1 is connected to the initialization voltage signal line Vinit; the first terminal of the second capacitor C2 is connected to the eighth node N8, and the second terminal of the second capacitor C2 is connected to the initialization voltage signal line Vinit.

[0211] For the driving circuit shown in Figure 27, based on Figure 26, the eighth thin-film transistor M8 and the eleventh thin-film transistor M11 can be the first transistor T1; the ninth thin-film transistor M9 and the tenth thin-film transistor M10 can be the third transistor T3, or the ninth thin-film transistor M9 and the tenth thin-film transistor M10 can both be the second transistor T2.

[0212] Of course, the above are just examples. The driving circuit can be configured with other structures as needed, and the types of transistors in the driving circuit can also be set as needed.

[0213] Based on the same inventive concept, this disclosure provides a display device that may include the array substrate described in any of the above-described embodiments. The specific structure of the array substrate has been described in detail above, and therefore will not be repeated here.

[0214] The display device can be a liquid crystal display panel, an OLED (Organic Electroluminescence Display) display panel, a QLED (Quantum Dot Light Emitting Diodes) display panel, a micro-LED (micro-Light Emitting Diode) display panel, a mini-LED (mini-Light Emitting Diode) display panel, and so on.

[0215] The specific type of display device is not particularly limited; any type of display device commonly used in the field is acceptable, such as mobile devices like mobile phones, wearable devices like watches, VR devices, etc. Those skilled in the art can make the appropriate selection based on the specific purpose of the display device, which will not be elaborated further here.

[0216] It should be noted that, in addition to the array substrate, the display device also includes other necessary components and parts. Taking the display as an example, these include, for instance, the casing, circuit board, power cord, etc. Those skilled in the art can supplement these components according to the specific usage requirements of the display device, and will not be elaborated here.

[0217] Compared with the prior art, the beneficial effects of the display device provided by the exemplary embodiments of the present invention are the same as the beneficial effects of the array substrate provided by the above exemplary embodiments, and will not be repeated here.

[0218] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. An array substrate, wherein, include: Substrate; A first transistor and a second transistor are disposed on one side of the substrate. The first transistor includes a first active layer, which includes a first conductor portion, a first channel portion, and a second conductor portion connected in sequence. The first active layer includes a first grain boundary, and the distance between two adjacent first grain boundaries in the connection direction of the first conductor portion, the first channel portion, and the second conductor portion is a first distance. The second transistor includes a second active layer, which includes a third conductor portion, a second channel portion, and a fourth conductor portion connected in sequence. The second active layer includes a second grain boundary, and the distance between two adjacent second grain boundaries in the connection direction of the third conductor portion, the second channel portion, and the fourth conductor portion is a second distance. The first distance is greater than the second distance, and the first transistor is used as at least a driving transistor.

2. The array substrate according to claim 1, wherein, The first distance is greater than or equal to 0.7 micrometers and less than or equal to 10 micrometers, and / or the second distance is greater than or equal to 100 nanometers and less than or equal to 500 nanometers.

3. The array substrate according to claim 1, wherein, The maximum dimension of the first channel portion in the extension direction of the first active layer is greater than or equal to the maximum dimension of the second channel portion in the extension direction of the second active layer; the second channel portion includes the second grain boundary, and the first channel portion does not include the first grain boundary; or, the second channel portion includes the second grain boundary, the first channel portion includes the first grain boundary, the number of second grain boundaries included in the second channel portion is greater than or equal to the number of first grain boundaries included in the first channel portion, and the extension directions of the first active layer and the second active layer are parallel to the side of the substrate on which the first transistor and the second transistor are disposed.

4. The array substrate according to claim 1, wherein, The array substrate has a display area and a non-display area, and the first transistor is disposed in the display area and the non-display area, or the first transistor is disposed in the display area.

5. The array substrate according to claim 1, wherein, The first conductor portion and / or the second conductor portion includes a first grain boundary, and the third conductor portion and / or the fourth conductor portion includes a second grain boundary.

6. The array substrate according to any one of claims 1 to 5, wherein, The distance between the first active layer and the substrate in the second direction is equal to the distance between the second active layer and the substrate in the second direction, and the second direction is perpendicular to the side of the substrate on which the second transistor and the first transistor are disposed; The array substrate further includes: A first gate insulating layer is disposed on the side of the first active layer and the second active layer away from the substrate. A first gate layer is disposed on the side of the first gate insulating layer opposite to the substrate. The first gate layer includes a first gate and a second gate. The orthographic projection of the first channel portion on the substrate is located within the orthographic projection of the first gate on the substrate, and the orthographic projection of the second channel portion on the substrate is located within the orthographic projection of the second gate on the substrate. The first interlayer dielectric layer is disposed on the side of the first gate layer away from the substrate. A first connecting conductor layer is disposed on the side of the first interlayer dielectric layer facing away from the substrate. The first connecting conductor layer includes a first connecting portion, a second connecting portion, a third connecting portion and a fourth connecting portion. The first connecting portion is connected to the first conductor portion, the second connecting portion is connected to the second conductor portion, the third connecting portion is connected to the third conductor portion, and the fourth connecting portion is connected to the fourth conductor portion.

7. The array substrate according to any one of claims 1 to 5, wherein, The second active layer is disposed on the side of the first active layer away from the substrate, and the orthographic projection of the first active layer on the substrate overlaps with the orthographic projection of the second active layer on the substrate.

8. The array substrate according to claim 7, wherein, The array substrate further includes: A first gate insulating layer is disposed on the side of the first active layer away from the substrate. A first gate layer is disposed on the side of the first gate insulating layer opposite to the substrate. The first gate layer includes a first gate, and the orthographic projection of the first channel portion on the substrate is located within the orthographic projection of the first gate on the substrate. The second buffer layer is disposed on the side of the first gate layer away from the substrate, the second active layer is disposed on the side of the second buffer layer away from the substrate, and the third conductor portion is connected to the first conductor portion or the second conductor portion. The second gate insulating layer is disposed on the side of the second active layer away from the substrate. The second gate layer is disposed on the side of the second gate insulating layer opposite to the substrate. The second gate layer includes a second gate, and the orthogonal projection of the second channel portion on the substrate is located within the orthogonal projection of the second gate on the substrate. The first interlayer dielectric layer is disposed on the side of the second gate layer away from the substrate. A first connecting conductor layer is disposed on the side of the first interlayer dielectric layer away from the substrate. The first connecting conductor layer includes a first connecting portion and a second connecting portion. The first connecting portion is connected to the third conductor portion, and the second connecting portion is connected to the fourth conductor portion.

9. The array substrate according to any one of claims 1 to 5, wherein, The first active layer is disposed on the side of the second active layer away from the substrate, and the orthographic projection of the first active layer on the substrate overlaps with the orthographic projection of the second active layer on the substrate.

10. The array substrate according to any one of claims 1, wherein, The array substrate further includes: The third transistor includes a third active layer, which is disposed on the side of the first active layer away from the substrate. The orthographic projection of the third active layer on the substrate does not overlap with the orthographic projection of the first active layer on the substrate. The third transistor is a metal-oxide transistor.

11. The array substrate according to claim 10, wherein, The array substrate further includes: A first gate insulating layer is disposed on the side of the first active layer away from the substrate. A first gate layer is disposed on the side of the first gate insulating layer opposite to the substrate. The first gate layer includes at least a first gate, and the orthogonal projection of the first channel portion on the substrate is located within the orthogonal projection of the first gate on the substrate. An insulating layer group is disposed on the side of the first gate layer away from the substrate, and a third active layer is disposed on the side of the insulating layer group away from the substrate. The third active layer includes a fifth conductor portion, a third channel portion, and a sixth conductor portion connected in sequence. A third gate insulating layer is disposed on the side of the third active layer away from the substrate. A third gate layer is disposed on the side of the third gate insulating layer opposite to the substrate. The third gate layer includes a third gate, and the orthogonal projection of the third channel portion on the substrate is located within the orthogonal projection of the third gate on the substrate. The second interlayer dielectric layer is disposed on the side of the third gate layer away from the substrate. A first connecting conductor layer is disposed on the side of the second interlayer dielectric layer away from the substrate. The first connecting conductor layer includes a first connecting portion, a second connecting portion, a third connecting portion and a fourth connecting portion. The first connecting portion is connected to the first conductor portion, the second connecting portion is connected to the second conductor portion, the third connecting portion is connected to the fifth conductor portion, and the fourth connecting portion is connected to the sixth conductor portion.

12. The array substrate according to any one of claims 1, wherein, The array substrate further includes: The third transistor includes a third active layer, which is disposed on the side of the first active layer away from the substrate. The orthographic projection of the third active layer on the substrate overlaps with the orthographic projection of the first active layer on the substrate. The third transistor is a metal-oxide transistor.

13. The array substrate according to claim 12, wherein, The orthographic projection of the third active layer on the substrate does not overlap with the orthographic projection of the second active layer on the substrate.

14. The array substrate according to claim 12, wherein, The array substrate further includes: A first gate insulating layer is disposed on the side of the first active layer away from the substrate. A first gate layer is disposed on the side of the first gate insulating layer opposite to the substrate. The first gate layer includes at least a first gate, and the orthogonal projection of the first channel portion on the substrate is located within the orthogonal projection of the first gate on the substrate. An insulating layer group is disposed on the side of the first gate layer away from the substrate, and a third active layer is disposed on the side of the insulating layer group away from the substrate. The third active layer includes a fifth conductor portion, a third channel portion, and a sixth conductor portion connected in sequence. A third gate insulating layer is disposed on the side of the third active layer away from the substrate. A third gate layer is disposed on the side of the third gate insulating layer opposite to the substrate. The third gate layer includes a third gate, and the orthogonal projection of the third channel portion on the substrate is located within the orthogonal projection of the third gate on the substrate. The second interlayer dielectric layer is disposed on the side of the third gate layer away from the substrate. A first connecting conductor layer is disposed on the side of the second interlayer dielectric layer opposite to the substrate. The first connecting conductor layer includes a first connecting portion and a second connecting portion. The first connecting portion is connected to the first conductor portion and the fifth conductor portion, and / or the second connecting portion is connected to the second conductor portion and the sixth conductor portion.

15. The array substrate according to claim 12, wherein, The array substrate further includes: A first gate insulating layer is disposed on the side of the first active layer away from the substrate. A first gate layer is disposed on the side of the first gate insulating layer opposite to the substrate. The first gate layer includes at least a first gate, and the orthogonal projection of the first channel portion on the substrate is located within the orthogonal projection of the first gate on the substrate. An insulating layer group is disposed on the side of the first gate layer opposite to the substrate. A first connecting conductor layer is disposed between two insulating layers in the insulating layer group. The first connecting conductor layer includes a first connecting portion and a second connecting portion, wherein the first connecting portion is connected to the first conductor portion and the second connecting portion is connected to the second conductor portion. A third active layer is disposed on the side of the insulating layer group opposite to the substrate. The third active layer includes a fifth conductor portion, a third channel portion, and a sixth conductor portion connected in sequence. The fifth conductor portion is connected to the first connecting portion and the sixth conductor portion is connected to the second connecting portion. A third gate insulating layer is disposed on the side of the third active layer away from the substrate. A third gate layer is disposed on the side of the third gate insulating layer opposite to the substrate. The third gate layer includes a third gate, and the orthogonal projection of the third channel portion on the substrate is located within the orthogonal projection of the third gate on the substrate. The second interlayer dielectric layer is disposed on the side of the third gate layer away from the substrate. The second connecting conductor layer is disposed on the side of the second interlayer dielectric layer away from the substrate. The second connecting conductor layer includes a seventh connecting portion and an eighth connecting portion. The seventh connecting portion is connected to the fifth conductor portion, and the eighth connecting portion is connected to the sixth conductor portion.

16. The array substrate according to claim 14 or 15, wherein, The insulating layer group includes a second gate insulating layer, a first interlayer dielectric layer, and a second buffer layer stacked sequentially; the array substrate further includes: A shielding layer is disposed between the second gate insulating layer and the first interlayer dielectric layer. The shielding layer includes a shielding portion, the orthographic projection of the shielding portion on the substrate overlaps with the orthographic projections of the first gate and the third gate on the substrate.

17. The array substrate according to claim 14 or 15, wherein, The insulating layer group includes a second gate insulating layer, a first interlayer dielectric layer, an electromagnetic shielding layer, and a second buffer layer stacked sequentially.

18. The array substrate according to claim 11, 14 or 15, wherein, The distance between the first active layer and the substrate in the second direction is equal to the distance between the second active layer and the substrate in the second direction, and the second direction is perpendicular to the side of the substrate on which the second transistor and the first transistor are disposed; the first gate layer further includes a second gate, and the orthographic projection of the second channel portion on the substrate is located within the orthographic projection of the second gate on the substrate.

19. The array substrate according to any one of claims 1 to 5, wherein, The first grain boundary is a first protrusion formed in the first active layer, and the second grain boundary is a second protrusion formed in the second active layer.

20. A display device, wherein, include: The array substrate according to any one of claims 1 to 19.

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