Display panel and display device

Abstract

Provided in embodiments of the present disclosure are a display panel and a display device. The display panel comprises: a display area and a non-display area. The display area comprises a plurality of pixel units, each pixel unit comprises a pixel circuit, the pixel circuit comprises a driving transistor and an initialization transistor, and a second electrode of the initialization transistor is coupled to the driving transistor. The non-display area comprises a plurality of switch circuits, the pixel circuits in at least two pixel units in one row share one switch circuit, and first electrodes of the initialization transistors in one row of pixel circuits are coupled to the shared switch circuit. Each switch circuit is configured to output an initialization signal to the first electrodes of the corresponding initialization transistors in response to a gate driving signal. Inputting of an initialization signal is controlled by means of a switch circuit, such that the initialization signal cannot be inputted to first electrodes of initialization transistors of pixel circuits in a non-initialization stage, thereby reducing the voltage difference between sources and drains of the initialization transistors, reducing leakage current, improving display quality, and enhancing the display effect.

Description

Display panel and display device Technical Field

[0001] This invention relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs), quantum dot light-emitting diodes (QLEDs), micro light-emitting diodes (Micro LEDs), and mini light-emitting diodes (Mini LEDs) possess advantages such as self-illumination and low energy consumption, making them a hot topic in current display panel application research. Typically, pixel circuits are used to drive one or more light-emitting devices to emit light, enabling the display panel to display images. However, during the initialization phase of the pixel circuit's transistors, a significant voltage difference still exists between the source and drain, resulting in leakage current and affecting display quality. Summary of the Invention

[0003] This disclosure provides a display panel, including: a display area and a non-display area;

[0004] The display area includes multiple pixel units, each pixel unit includes a pixel circuit, and the pixel circuit includes a driving transistor and an initialization transistor, with the second terminal of the initialization transistor coupled to the driving transistor.

[0005] The non-display area includes multiple switching circuits, with at least two pixel units in a row sharing one of the switching circuits, and the first terminal of the initialization transistor in a row of pixel units being coupled to the shared switching circuit; the switching circuit is configured to output an initialization signal to the first terminal of the initialization transistor in response to a gate drive signal.

[0006] In some possible implementations, the initialization transistor includes a first initialization transistor, and the switching circuit includes a first switching circuit;

[0007] The gate of the first initialization transistor is used to receive a first reset control signal, the first terminal of the first initialization transistor is coupled to the first switching circuit, and the second terminal of the first initialization transistor is coupled to the second terminal of the driving transistor.

[0008] In some possible implementations, the first switching circuit includes a first switching transistor; the gate drive signal includes a first gate drive signal; and the initialization signal includes a first initialization signal.

[0009] The gate of the first switching transistor is used to receive the first gate drive signal, the first terminal of the first switching transistor is used to receive the first initialization signal, and the second terminal of the first switching transistor is coupled to the first terminal of the first initialization transistor.

[0010] In some possible implementations, the display area further includes a plurality of first gate lines, and the non-display area further includes a first gate driving circuit electrically connected to each of the first gate lines; wherein, the gate of a first switching transistor electrically connected to a row of pixel circuits and the gates of each first initialization transistor electrically connected to the first switching transistors are electrically connected.

[0011] In some possible implementations, the non-display area further includes a first initialization signal line; the first terminal of the first switching transistor of each of the first switching circuits is coupled to the first initialization signal line.

[0012] In some possible implementations, the first initialization transistors in at least two adjacent pixel units in the same row share a single first switching circuit.

[0013] In some possible implementations, the first initialization transistors in all pixel circuits in the same row share a single first switching circuit.

[0014] In some possible implementations, the initialization transistor further includes a second initialization transistor, and the switching circuit further includes a second switching circuit;

[0015] The gate of the second initialization transistor is used to receive the second reset control signal, the first terminal of the second initialization transistor is coupled to the second switching circuit, and the second terminal of the second initialization transistor is coupled to the first terminal of the driving transistor.

[0016] In some possible implementations, the second switching circuit includes a second switching transistor; the gate drive signal includes a second gate drive signal; and the initialization signal includes a second initialization signal.

[0017] The gate of the second switching transistor is used to receive the second gate drive signal, the first terminal of the second switching transistor is used to receive the second initialization signal, and the second terminal of the second switching transistor is coupled to the first terminal of the second initialization transistor.

[0018] In some possible implementations, the display area further includes a plurality of second gate lines, and the non-display area further includes a second gate driving circuit electrically connected to each of the second gate lines; wherein, the gate of a second switching transistor electrically connected to a row of pixel circuits and the gates of each second initialization transistor electrically connected to the second switching transistors are electrically connected.

[0019] In some possible implementations, the non-display area further includes a second initialization signal line, wherein the first terminal of the second switching transistor of each of the second switching circuits is coupled to the second initialization signal line.

[0020] In some possible implementations, the second initialization transistors in at least two adjacent pixel units in the same row share a single second switching circuit.

[0021] In some possible implementations, the second initialization transistors in all pixel circuits in the same row share a single second switching circuit.

[0022] In some possible implementations, the initialization transistor further includes a third initialization transistor, and the switching circuit further includes a third switching circuit;

[0023] The pixel circuit further includes a light-emitting control transistor and a light-emitting device, wherein the first terminal of the light-emitting control transistor is coupled to the second terminal of the driving transistor, and the second terminal of the light-emitting control transistor is connected to the first terminal of the light-emitting device;

[0024] The gate of the third initialization transistor is used to receive the third reset control signal. The first terminal of the third initialization transistor is coupled to the third switching circuit, and the second terminal of the third initialization transistor is coupled to the first terminal of the light-emitting device.

[0025] In some possible implementations, the third switching circuit includes a third switching transistor; the gate drive signal includes a third gate drive signal; and the initialization signal includes a third initialization signal.

[0026] The gate of the third switching transistor is used to receive the third gate drive signal, the first terminal of the third switching transistor is used to receive the third initialization signal, and the second terminal of the third switching transistor is coupled to the first terminal of the third initialization transistor.

[0027] In some possible implementations, the display area further includes multiple third gate lines, and the non-display area further includes a third gate driving circuit electrically connected to each of the third gate lines; wherein, the gate of a third switching transistor electrically connected to a row of pixel circuits and the gates of each third initialization transistor electrically connected to the third switching transistors are electrically connected.

[0028] In some possible implementations, the non-display area further includes a third initialization signal line, wherein the first terminal of the third switching transistor of each of the third switching circuits is coupled to the third initialization signal line.

[0029] In some possible implementations, the third initialization transistors in at least two adjacent pixel units in the same row share a single third switching circuit.

[0030] In some possible implementations, the third initialization transistors in all pixel circuits in the same row share a single third switching circuit.

[0031] In some possible implementations, the initialization transistor includes a first initialization transistor and a second initialization transistor, and the switching circuit includes a first switching circuit and a second switching circuit; the first initialization transistors in all pixel circuits in the same row share one first switching circuit, and the second initialization transistors in all pixel circuits in the same row share one second switching circuit.

[0032] The display area also includes multiple first connecting lines, and the first electrode of each of the first initialization transistors and the first electrode of the second initialization transistor in a row of pixel units are coupled to the corresponding first switching circuit and second switching circuit through the same first connecting line.

[0033] In some possible implementations, the initialization transistor includes a first initialization transistor and a third initialization transistor, and the switching circuit includes a first switching circuit and a third switching circuit; the first initialization transistors in all pixel circuits in the same row share one first switching circuit, and the third initialization transistors in all pixel circuits in the same row share one third switching circuit.

[0034] The display area also includes multiple second connecting lines. The first electrode of each first initialization transistor and the first electrode of each third initialization transistor in a row of pixel units are coupled to the corresponding first switching circuit and the third switching circuit through the same second connecting line.

[0035] In some possible implementations, the initialization transistor includes a second initialization transistor and a third initialization transistor, and the switching circuit includes a second switching circuit and a third switching circuit; the second initialization transistors in all pixel circuits in the same row share one second switching circuit, and the third initialization transistors in all pixel circuits in the same row share one third switching circuit;

[0036] The display area also includes multiple third connecting lines. The first pole of each second initialization transistor and the first pole of each third initialization transistor in a row of pixel units are coupled to the corresponding second switching circuit and the third switching circuit through the same third connecting line.

[0037] This disclosure also provides a display device, including the display panel described above. Attached Figure Description

[0038] Figure 1 is a schematic diagram of some structures of the pixel circuit provided in the embodiments of this disclosure;

[0039] Figures 2 to 9 are schematic diagrams of some structures of the display panel provided in the embodiments of this disclosure;

[0040] Figures 10 to 15 are schematic diagrams of some structures of the display area of ​​the display panel provided in the embodiments of this disclosure;

[0041] Figures 16 and 16(a) to 16(e) are some flowcharts of the method for preparing a display panel according to the embodiments of this disclosure;

[0042] Figure 17 is a schematic diagram of some structures of the display device provided in the embodiments of this disclosure;

[0043] Figure 18 is a schematic diagram of some structures of the pixel circuit provided in the embodiments of this disclosure;

[0044] Figure 19 is a signal timing diagram of a pixel circuit provided in an embodiment of this disclosure;

[0045] Figures 20 and 21 are potential diagrams of the first electrode of the initialization transistor of the pixel circuit provided in the embodiments of this disclosure. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0047] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0048] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0049] Typically, a display panel may include multiple pixel units, each pixel unit including pixel circuitry. For example, the pixel circuitry may include transistors, capacitors, and light-emitting devices, with the transistors and capacitors working together to drive the light-emitting devices to emit light.

[0050] For example, the light-emitting device may include: organic light-emitting diode (OLED), quantum dot light-emitting diode (QLED), micro light-emitting diode (Micro LED), and mini light-emitting diode (Mini LED).

[0051] For example, as shown in Figure 1, the pixel circuit may include an 8T1C circuit, specifically including: three initialization transistors M1, M7, and M8; a scan transistor M2; a drive transistor M3; a data write transistor M4; two light-emitting control transistors M5 and M6; and a storage capacitor Cs. Specifically, the first terminal of the initialization transistor M1 is coupled to the first initialization signal line Vinit1, the second terminal is coupled to the third node N3, and the gate is used to receive the first reset control signal reset1. The first terminal of the scan transistor M2 is coupled to the first node N1, the second terminal is coupled to the third node N3, and the gate is used to receive the first scan control signal gate1. The first terminal of the drive transistor M3 is coupled to the third node N3, the second terminal is coupled to the second node N2, and the gate is used to receive the signal from the first node N1. The first terminal of the data write transistor M4 is used to receive the data signal Data, the second terminal is coupled to the second node N2, and the gate is used to receive the second scan control signal gate2. The first terminal of the light-emitting control transistor M5 is coupled to the first power supply terminal Vdd, the second terminal is coupled to the second node N2, and the gate is used to receive the light-emitting control signal em. The first terminal of the light-emitting control transistor M6 is coupled to the third node N3, the second terminal is coupled to the anode of the light-emitting device, and the gate is used to receive the light-emitting control signal em. The first terminal of the initialization transistor M7 is coupled to the second initialization signal line Vinit2, the second terminal is coupled to the anode of the light-emitting device, and the gate is used to receive the second reset control signal reset2. The first terminal of the initialization transistor M8 is coupled to the third initialization signal line Vinit3, the second terminal is coupled to the second node N2, and the gate is used to receive the third reset control signal reset3. The first plate of the storage capacitor Cs is coupled to the first power supply terminal Vdd, and the second plate is coupled to the first node N1. The cathode of the light-emitting device is coupled to the second power supply terminal Vss.

[0052] For example, the initialization transistor M1 is turned on under the control of the active level of the first reset control signal reset1, and turned off under the control of the inactive level of the first reset control signal reset1. Optionally, as shown in FIG1, the initialization transistor M1 can be set as a P-type transistor, in which case the active level of the first reset control signal reset1 is low and the inactive level is high. Of course, the initialization transistor M1 can also be set as an N-type transistor, in which case the active level of the first reset control signal reset1 is high and the inactive level is low.

[0053] For example, the scanning transistor M2 is turned on under the control of the effective level of the first scan control signal gate1, and turned off under the control of the ineffective level of the first scan control signal gate1. Optionally, as shown in FIG1, the scanning transistor M2 can be set as a P-type transistor, in which case the effective level of the first scan control signal gate1 is low and the ineffective level is high. Of course, the scanning transistor M2 can also be set as an N-type transistor, in which case the effective level of the first scan control signal gate1 is high and the ineffective level is low.

[0054] For example, the driving transistor M3 is turned on under the control of the effective level of the signal at the first node N1, and turned off under the control of the ineffective level of the signal at the first node N1. Optionally, as shown in Figure 1, the driving transistor M3 can be set as a P-type transistor, in which case the effective level of the signal at the first node N1 is low and the ineffective level is high. Of course, the driving transistor M3 can also be set as an N-type transistor, in which case the effective level of the signal at the first node N1 is high and the ineffective level is low.

[0055] For example, the data writing transistor M4 is turned on under the control of the active level of the second scan control signal gate2, and turned off under the control of the inactive level of the second scan control signal gate2. Optionally, as shown in FIG1, the data writing transistor M4 can be set as a P-type transistor, in which case the active level of the second scan control signal gate2 is low and the inactive level is high. Of course, the data writing transistor M4 can also be set as an N-type transistor, in which case the active level of the second scan control signal gate2 is high and the inactive level is low.

[0056] For example, the light-emitting control transistor M5 is turned on when the light-emitting control signal em is active and turned off when the light-emitting control signal em is inactive. Optionally, as shown in Figure 1, the light-emitting control transistor M5 can be a P-type transistor, in which case the active level of the light-emitting control signal em is low and the inactive level is high. Of course, the light-emitting control transistor M5 can also be an N-type transistor, in which case the active level of the light-emitting control signal em is high and the inactive level is low.

[0057] For example, the light-emitting control transistor M6 is turned on when the light-emitting control signal em is active and turned off when the light-emitting control signal em is inactive. Optionally, as shown in Figure 1, the light-emitting control transistor M6 can be a P-type transistor, in which case the active level of the light-emitting control signal em is low and the inactive level is high. Of course, the light-emitting control transistor M6 can also be an N-type transistor, in which case the active level of the light-emitting control signal em is high and the inactive level is low.

[0058] For example, the initialization transistor M7 is turned on under the control of the active level of the second reset control signal reset2, and turned off under the control of the inactive level of the second reset control signal reset2. Optionally, as shown in FIG1, the initialization transistor M7 can be set as a P-type transistor, in which case the active level of the second reset control signal reset2 is low and the inactive level is high. Of course, the initialization transistor M7 can also be set as an N-type transistor, in which case the active level of the second reset control signal reset2 is high and the inactive level is low.

[0059] For example, the initialization transistor M8 is turned on under the control of the active level of the third reset control signal reset3, and turned off under the control of the inactive level of the third reset control signal reset3. Optionally, as shown in FIG1, the initialization transistor M8 can be set as a P-type transistor, in which case the active level of the third reset control signal reset3 is low and the inactive level is high. Of course, the initialization transistor M8 can also be set as an N-type transistor, in which case the active level of the third reset control signal reset3 is high and the inactive level is low.

[0060] For example, the first initialization signal line Vinit1 provides a negative voltage signal, the second initialization signal line Vinit2 provides a negative voltage signal, and the third initialization signal line Vinit3 provides a positive voltage signal.

[0061] In some embodiments of this disclosure, the first power supply terminal Vdd can be loaded with a constant first power supply voltage, and the first power supply voltage is generally positive. The second power supply terminal Vss can be configured to be loaded with a constant second power supply voltage, and the second power supply voltage is generally ground voltage or a negative value. In practical applications, the specific values ​​of the first and second power supply voltages can be designed and determined according to the actual application environment, and are not limited thereto.

[0062] In some embodiments of this disclosure, the first terminal of the transistor can be used as its source and the second terminal as its drain, depending on the type of transistor and the signal received at its gate; or, conversely, the first terminal of the transistor can be used as its drain and the second terminal as its source. This can be designed and determined according to the actual application environment, and no specific distinction is made here.

[0063] The above are merely examples illustrating the specific structure of the pixel circuit provided in the embodiments of this disclosure. In specific implementations, the pixel circuit is not limited to the structure provided in the embodiments of this disclosure, but may also be other structures known to those skilled in the art. These are all within the protection scope of this disclosure and are not specifically limited here.

[0064] As shown in Figure 1, the pixel circuit contains multiple initialization transistors for receiving initialization signals. The initialization signal is generally a positive or negative voltage signal. However, a positive or negative voltage signal can cause leakage current in the initialization transistors in the pixel circuit. For example, in the non-initialization stage, due to the writing of data voltage, the third node N3 of the initialization transistor M1 is at a positive voltage. That is, the source of the initialization transistor M1 is at a positive voltage, while the drain is still receiving the negative voltage input of the initialization signal. This results in a large voltage difference between the source and drain, forming a leakage current. The existence of leakage current will affect the stability of the current supplied to the light-emitting device, causing changes in the brightness of the displayed image and affecting the display effect.

[0065] To address the aforementioned issues, the display panel provided in this embodiment of the present disclosure incorporates a switching circuit between the first electrode of the initialization transistor in the pixel circuit and the initialization signal line. This circuit controls the initialization signal from being input to the first electrode of the initialization transistor during the non-initialization phase, thereby reducing the voltage difference between the source and drain of the initialization transistor, decreasing leakage current, improving display quality, and enhancing the display effect.

[0066] In this embodiment of the disclosure, as shown in FIG2, the display panel may include: a display area AA and a non-display area BB;

[0067] The display area AA includes multiple pixel units px, each pixel unit px includes a pixel circuit 10, the pixel circuit 10 includes a driving transistor 101 and an initialization transistor 102, and the second terminal of the initialization transistor 102 is coupled to the driving transistor 101.

[0068] The non-display area BB includes multiple switching circuits 20. Pixel circuits 10 in at least two pixel units px in a row share a single switching circuit 20, and the first terminal of the initialization transistor 102 in a row of pixel circuits 10 is coupled to the shared switching circuit 20. The switching circuit 20 is configured to output an initialization signal vinit to the first terminal of the initialization transistor 102 in response to the gate drive signal Gout.

[0069] The display panel provided in this embodiment controls the input of the initialization signal through a switching circuit, so that the initialization signal cannot be input to the first terminal of the initialization transistor of the pixel circuit during the non-initialization stage, thereby reducing the voltage difference between the source and drain of the initialization transistor, reducing leakage current, improving display quality, and enhancing display effect.

[0070] In the display panel provided in the embodiments of this disclosure, as shown in FIG3, the initialization transistor 102 includes a first initialization transistor M1, and the switching circuit 20 includes a first switching circuit 21.

[0071] The gate of the first initialization transistor M1 is used to receive the first reset control signal (not shown in the figure). The first terminal of the first initialization transistor M1 is coupled to the first switching circuit 21, and the second terminal of the first initialization transistor M1 is coupled to the second terminal of the driving transistor 101.

[0072] In the display panel provided in the embodiments of this disclosure, as shown in FIG3, the first switching circuit 21 includes a first switching transistor T1; the gate drive signal Gout includes a first gate drive signal, and the initialization signal vinit includes a first initialization signal;

[0073] The gate of the first switching transistor T1 is used to receive the first gate drive signal (not shown in the figure), the first terminal of the first switching transistor T1 is used to receive the first initialization signal (not shown in the figure), and the second terminal of the first switching transistor T1 is coupled to the first terminal of the first initialization transistor M1.

[0074] In the display panel provided in the embodiments of this disclosure, as shown in FIG3, the display area AA may further include multiple first gate lines S1, and the non-display area BB may further include a first gate driving circuit 30 electrically connected to each first gate line S1. The gate of a first switching transistor T1 electrically connected to a row pixel circuit 10 and the gates of each first initialization transistor M1 electrically connected to the first switching transistor T1 are electrically connected.

[0075] A first reset control signal is provided to the gate of the first initialization transistor M1 through the first gate line S1, and a first gate drive signal is provided to the gate of the first switching transistor T1, that is, the first reset control signal and the first gate drive signal are the same signal.

[0076] In the display panel provided in the embodiments of this disclosure, as shown in FIG3, the non-display area BB may further include a first initialization signal line Vinit1; the first pole of the first switching transistor T1 of each first switching circuit 21 is respectively coupled to the first initialization signal line Vinit1.

[0077] A first initialization signal is provided to the first terminal of each first switching transistor T1 via the first initialization signal line Vinit1. For example, the first initialization signal provided by the first initialization signal line Vinit1 is a negatively biased voltage signal.

[0078] In the display panel provided in the embodiments of this disclosure, as shown in FIG3, the first initialization transistors M1 in at least two adjacent pixel units px in the same row share a first switching circuit 21.

[0079] In the display panel provided in the embodiments of this disclosure, as shown in FIG3, the first initialization transistors M1 in all pixel circuits 10 in the same row share a first switching circuit 21.

[0080] In the display panel provided in the embodiments of this disclosure, as shown in FIG4 or FIG5, the initialization transistor 102 may further include a second initialization transistor M2, and the switching circuit 2 may further include a second switching circuit 22.

[0081] The gate of the second initialization transistor M2 is used to receive the second reset control signal (not shown in the figure). The first terminal of the second initialization transistor M2 is coupled to the second switching circuit 22, and the second terminal of the second initialization transistor M2 is coupled to the first terminal of the driving transistor 101.

[0082] In the display panel provided in the embodiments of this disclosure, as shown in FIG4 or FIG5, the second switching circuit 22 may include a second switching transistor T2; the gate drive signal Gout includes a second gate drive signal, and the initialization signal vinit includes a second initialization signal;

[0083] The gate of the second switching transistor T2 is used to receive the second gate drive signal (not shown in the figure), the first terminal of the second switching transistor T2 is used to receive the second initialization signal (not shown in the figure), and the second terminal of the second switching transistor T2 is coupled to the first terminal of the second initialization transistor M2.

[0084] In the display panel provided in the embodiments of this disclosure, as shown in FIG4 or FIG5, the display area AA may further include multiple second gate lines S2, and the non-display area BB may further include a second gate driving circuit 40 electrically connected to each second gate line S2; wherein, the gate of a second switching transistor T2 electrically connected to a row pixel circuit 10 and the gate of each second initialization transistor M2 electrically connected to the second switching transistor T2 are electrically connected.

[0085] The second reset control signal is provided to the gate of the second initialization transistor M2 through the second gate line S2, and the second gate drive signal is provided to the gate of the second switching transistor T2, that is, the second reset control signal and the second gate drive signal are the same signal.

[0086] In the display panel provided in the embodiments of this disclosure, as shown in FIG4 or FIG5, the non-display area further includes a second initialization signal line Vinit2, and the first pole of the second switching transistor T2 of each second switching circuit 22 is coupled to the second initialization signal line Vinit2.

[0087] A second initialization signal is provided to the first terminal of each second switching transistor T2 via the second initialization signal line Vinit2. For example, the second initialization signal provided by the second initialization signal line Vinit2 is a positively biased voltage signal.

[0088] In the display panel provided in the embodiments of this disclosure, as shown in FIG4 or FIG5, the second initialization transistors M2 in at least two adjacent pixel units px in the same row share a second switching circuit 22.

[0089] In the display panel provided in the embodiments of this disclosure, as shown in FIG4 or FIG5, the second initialization transistors M2 in all pixel circuits 10 in the same row share a second switching circuit 22.

[0090] In the display panel provided in the embodiments of this disclosure, as shown in Figures 6 to 8, the initialization transistor 102 may further include a third initialization transistor M3, and the switching circuit 20 may further include a third switching circuit 23.

[0091] The pixel circuit 10 may also include a light-emitting control transistor 103 and a light-emitting device P. The first terminal of the light-emitting control transistor 103 is coupled to the second terminal of the driving transistor 101, and the second terminal of the light-emitting control transistor 103 is connected to the first terminal of the light-emitting device P.

[0092] The gate of the third initialization transistor M3 is used to receive the third reset control signal (not shown in the figure). The first terminal of the third initialization transistor M3 is coupled to the third switching circuit 23, and the second terminal of the third initialization transistor M3 is coupled to the first terminal of the light-emitting device P.

[0093] In the display panel provided in the embodiments of this disclosure, as shown in Figures 6 to 8, the third switching circuit 23 includes a third switching transistor T3; the gate drive signal Gout includes a third gate drive signal; and the initialization signal vinit includes a third initialization signal.

[0094] The gate of the third switching transistor T3 is used to receive the third gate drive signal (not shown in the figure), the first terminal of the third switching transistor T3 is used to receive the third initialization signal (not shown in the figure), and the second terminal of the third switching transistor T3 is coupled to the first terminal of the third initialization transistor M3.

[0095] In the display panel provided in the embodiments of this disclosure, as shown in Figures 6 to 8, the display area AA may further include multiple third gate lines S3, and the non-display area BB may further include a third gate driving circuit 50 electrically connected to each third gate line S3; wherein, a third gate line S3 is electrically connected to the gate of a third switching transistor T3 electrically connected to a row of pixel circuits and the gates of each third initialization transistor M3 electrically connected to the third switching transistor T3 are electrically connected.

[0096] The third reset control signal is provided to the gate of the third initialization transistor M3 through the third gate line S3, and the third gate drive signal is provided to the gate of the third switching transistor T32. That is, the third reset control signal and the third gate drive signal are the same signal.

[0097] In the display panel provided in the embodiments of this disclosure, as shown in Figures 6 to 8, the non-display area BB may further include a third initialization signal line Vinit3, and the first pole of the third switching transistor T3 of each third switching circuit 23 is coupled to the third initialization signal line Vinit3.

[0098] A third initialization signal is provided to the first terminal of each third switching transistor T3 via the third initialization signal line Vinit3. For example, the third initialization signal provided by the third initialization signal line Vinit3 is a negatively biased voltage signal.

[0099] In the display panel provided in the embodiments of this disclosure, as shown in Figures 6 to 8, at least two adjacent pixel units px in the same row share a third initialization transistor M3.

[0100] In the display panel provided in the embodiments of this disclosure, as shown in Figures 6 to 8, the third initialization transistors M3 in all pixel circuits 10 in the same row share a third switching circuit 23.

[0101] In the display panel provided in this embodiment, as shown in FIG9, the initialization transistor 102 includes a first initialization transistor M1, a second initialization transistor M2, and a third initialization transistor M3. The switching circuit 20 includes a first switching circuit 21, a second switching circuit 22, and a third switching circuit 23; the first switching circuit 21 includes a first switching transistor T1, the second switching circuit 22 includes a second switching transistor T2, and the third switching circuit 23 includes a third switching transistor T3.

[0102] The display area AA includes multiple first gate lines S1 and multiple second gate lines S2, and the non-display area BB includes a first gate driving circuit 30 electrically connected to each first gate line S1 and a second gate driving circuit 40 electrically connected to each second gate line S2.

[0103] The non-display area BB also includes a first initialization signal line Vinit1, a second initialization signal line Vinit2, and a third initialization signal line Vinit3. The first terminal of each first switching transistor T1 is coupled to the first initialization signal line Vinit1, the first terminal of each second switching transistor T2 is coupled to the second initialization signal line Vinit2, and the first terminal of each third switching transistor T3 is coupled to the third initialization signal line Vinit3.

[0104] The gate of the first initialization transistor M1 is coupled to the first gate line S1, the first terminal is coupled to the second terminal of the first switching transistor T1, and the second terminal is coupled to the second terminal of the driving transistor 101. The gate of the first switching transistor T1 is coupled to the first gate line S1, the first terminal is coupled to the first initialization signal line Vinit1, and the second terminal is coupled to the first terminal of the first initialization transistor M1.

[0105] The gate of the second initialization transistor M2 is coupled to the second gate line S2, and its first terminal is coupled to the second terminal of the second switching transistor T2, which in turn is coupled to the first terminal of the driving transistor 101. The gate of the second switching transistor T2 is coupled to the second gate line S2, and its first terminal is coupled to the second initialization signal line Vinit2, which in turn is coupled to the first terminal of the second initialization transistor M2.

[0106] The gate of the third initialization transistor M3 is coupled to the second gate line S2, and its first terminal is coupled to the second terminal of the third switching transistor T3, which in turn is coupled to the first terminal of the light-emitting device P. The gate of the third switching transistor T3 is coupled to the second gate line S2, its first terminal is coupled to the third initialization signal line Vinit3, and its second terminal is coupled to the first terminal of the third initialization transistor M3.

[0107] For example, as shown in FIG9, a first gate line S1 is electrically connected to the gate of a first switching transistor T1 and the gates of each first initialization transistor M1 electrically connected to the first switching transistor T1 are electrically connected; a second gate line S2 is electrically connected to the gates of a second switching transistor T2 and a third switching transistor T3 and the gates of each second initialization transistor M2 and a third initialization transistor M3 electrically connected to the second switching transistor T2 and the third switching transistor T3 are electrically connected.

[0108] For example, as shown in FIG9, a row of pixel circuit 10 is electrically connected to a first switching transistor and a second switching transistor. The second terminals of the two switching transistors are connected through a trace V. The first terminal of the first initialization transistor M1 and the first terminal of the second initialization transistor M2 in each pixel circuit of the row are connected to the trace V through a first connecting line L1.

[0109] For example, as shown in FIG9, at least two adjacent pixel units px in the same row share a first initialization transistor M1, a second initialization transistor M2, a second initialization transistor M2, and a third initialization transistor M3, respectively, a third initialization transistor M3.

[0110] For example, as shown in FIG9, the first initialization transistor M1 in all pixel circuits 10 in the same row shares a first switching circuit 21, the second initialization transistor M2 shares a second switching circuit 22, and the third initialization transistor M3 shares a third switching circuit 23.

[0111] In the display panel provided in the embodiments of this disclosure, as shown in FIG5, the initialization transistor 102 may include a first initialization transistor M1 and a second initialization transistor M2, and the switching circuit 20 includes a first switching circuit 21 and a second switching circuit 22; the first initialization transistor M1 in all pixel circuits 10 in the same row shares a first switching circuit 21, and the second initialization transistor M2 in all pixel circuits in the same row shares a second switching circuit 22.

[0112] The display area AA may also include multiple first connecting lines L1. The first pole of each first initialization transistor M1 and the first pole of each second initialization transistor M2 in a row of pixel units are coupled to the corresponding first switching circuit 21 and second switching circuit 22 through the same first connecting line L1.

[0113] In the display panel provided in the embodiments of this disclosure, as shown in FIG5, a row of pixel circuits electrically connects a first switching transistor T1 and a second switching transistor T2. In the display area AA, the second terminal of the first switching transistor T1 is connected to the second terminal of the second switching transistor T2 through a trace. In this way, the first initialization signal provided by the first initialization signal line and the second initialization signal provided by the second initialization signal line are transmitted in the display area through a trace, reducing the trace density in the display area and reducing signal interference caused by the signal lines.

[0114] In the display panel provided in the embodiments of this disclosure, as shown in FIG7, the initialization transistor 102 includes a first initialization transistor M1 and a third initialization transistor M3, and the switching circuit 20 includes a first switching circuit 21 and a third switching circuit 23; the first initialization transistor M1 in all pixel circuits 10 in the same row shares a first switching circuit 21, and the third initialization transistor M3 in all pixel circuits 10 in the same row shares a third switching circuit 23.

[0115] The display area AA may also include multiple second connecting lines L2. The first pole of each first initialization transistor M1 and the first pole of the third initialization transistor M3 in a row of pixel units px are coupled to the corresponding first switching circuit 21 and third switching circuit 22 through the same second connecting line L2.

[0116] In the display panel provided in the embodiments of this disclosure, as shown in FIG8, the initialization transistor 102 includes a second initialization transistor M2 and a third initialization transistor M3, and the switching circuit 20 includes a second switching circuit 22 and a third switching circuit 23; the second initialization transistors M2 in all pixel circuits 10 in the same row share a second switching circuit 22, and the third initialization transistors M3 in all pixel circuits 10 in the same row share a third switching circuit 23.

[0117] The display area AA may also include multiple third connecting lines L3. The first pole of each second initialization transistor M2 and the first pole of the third initialization transistor M3 in a row of pixel units px are coupled to the corresponding second switching circuit 22 and third switching circuit 23 through the same third connecting line L3.

[0118] In some embodiments of this disclosure, for the display panel shown in FIG5, as shown in FIG10, the display area AA of the display panel may further include:

[0119] Substrate 100;

[0120] The first conductive layer 200 is located on one side of the substrate 100. The first conductive layer 200 includes the active layer 201 of the first initialization transistor M1 and the active layer 202 of the second initialization transistor M2.

[0121] The first gate layer 300 is located on the side of the first conductive layer 200 facing away from the substrate 100. The first gate layer 300 includes the gate 301 of the first initialization transistor M1, the gate 302 of the second initialization transistor M2, and a first gate line S1 and a second gate line S2. The gate 301 of the first initialization transistor M1 is connected to the first gate line S1, and the gate 302 of the second initialization transistor M2 is connected to the second gate line S2.

[0122] The second gate layer 400 is located on the side of the first gate layer 300 away from the substrate 100. The second gate layer 400 includes a first trace V1, which is connected to the active layer of the first switching transistor T1 and the active layer of the second switching transistor T2 through a via (not shown in the figure).

[0123] The second conductive layer 500 is located on the side of the second gate layer 400 away from the substrate 100, and includes a first connecting line L1. The first connecting line L1 is connected to the active layer 201 of the first initialization transistor M1 and the active layer 202 of the second initialization transistor M2 through a first via 001. The first connecting line L1 is connected to the first trace V1 through a second via 002.

[0124] The display panel shown in Figure 5, specifically as shown in Figure 11, may include a display area AA and a non-display area BB, wherein...

[0125] The non-display area BB includes a first initialization signal line Vinit1, a second initialization signal line Vinit2, the active layer of the first switching transistor T1, and the active layer of the second switching transistor T2. The active layer of the first switching transistor T1 is connected to the first initialization signal line Vinit1 through a via, and the first initialization signal line Vinit1 is used to provide a first initialization signal. The active layer of the second switching transistor T2 is connected to the second initialization signal line Vinit2 through a via, and the second initialization signal line Vinit2 is used to provide a second initialization signal.

[0126] The display area AA may include a pixel circuit 10, a first gate line S1, a second gate line S2, a first trace V1, and a first connecting line L1, as shown in Figure 1. The gates of initialization transistor M1 and the first switching transistor T1 are connected to the first gate line S1. The first gate line S1 is used to load a first reset control signal onto the gate of initialization transistor M1, and a first gate drive signal onto the gate of the first switching transistor T1. The gates of initialization transistor M8 and the second switching transistor T2 are connected to the second gate line S2. The second gate line S2 is used to load a second reset control signal onto the gate of initialization transistor M8, and a second gate drive signal onto the gate of the second switching transistor T2. The first trace V1 is connected to the active layers of the first switching transistor T1 and the second switching transistor T2 through vias. The first connecting line L1 is connected to the first trace V1 through vias, and also to the initialization transistors M1 and M8 through vias.

[0127] In some embodiments of this disclosure, for the display panel shown in FIG7, as shown in FIG12, the display area AA of the display panel may further include:

[0128] Substrate 100;

[0129] The first conductive layer 200 is located on one side of the substrate 100. The first conductive layer 200 includes the active layer 201 of the first initialization transistor M1 and the active layer 203 of the third initialization transistor M3.

[0130] The first gate layer 300 is located on the side of the first conductive layer 200 facing away from the substrate 100. The first gate layer 300 includes the gate 301 of the first initialization transistor M1, the gate 303 of the third initialization transistor M3, and the first gate line S1 and the third gate line S3. The gate 301 of the first initialization transistor M1 is connected to the first gate line S1, and the gate 303 of the third initialization transistor M3 is connected to the third gate line S3.

[0131] The second gate layer 400 is located on the side of the first gate layer 300 away from the substrate 100. The second gate layer 400 includes a second trace V2, which is connected to the active layer of the first switching transistor T1 and the active layer of the third switching transistor T3 through vias (not shown in the figure).

[0132] The second conductive layer 500 is located on the side of the second gate layer 400 away from the substrate 100, and includes a second connecting line L2. The second connecting line L2 is connected to the active layer 201 of the first initialization transistor M1 and the active layer 203 of the third initialization transistor M3 through a third via 003. The second connecting line L2 is connected to the second trace V2 through a fourth via 004.

[0133] In some embodiments of this disclosure, for the display panel shown in FIG8, as shown in FIG13, the display area AA of the display panel may further include:

[0134] Substrate 100;

[0135] The first conductive layer 200 is located on one side of the substrate 100. The first conductive layer 200 includes the active layer 202 of the second initialization transistor M2 and the active layer 203 of the third initialization transistor M3.

[0136] The first gate layer 300 is located on the side of the first conductive layer 200 facing away from the substrate 100. The first gate layer 300 includes the gate 302 of the second initialization transistor M2, the gate 303 of the third initialization transistor M3, and the second gate line S2 and the third gate line S3. The gate 302 of the second initialization transistor M2 is connected to the second gate line S2, and the gate 303 of the third initialization transistor M3 is connected to the third gate line S3.

[0137] The second gate layer 400 is located on the side of the first gate layer 300 away from the substrate 100. The second gate layer 400 includes a third trace V3, which is connected to the active layer of the second switching transistor T2 and the third switching transistor T3 through a via (not shown in the figure).

[0138] The second conductive layer 500 is located on the side of the second gate layer 400 away from the substrate 100, and includes a third connecting line L3. The third connecting line L3 is connected to the active layer 202 of the second initialization transistor M2 and the active layer 203 of the third initialization transistor M3 through a fifth via 005. The third connecting line L3 is connected to the third trace V3 through a sixth via 006.

[0139] In some embodiments of this disclosure, for the display panel shown in FIG9, as shown in FIG14, the display area AA of the display panel may further include:

[0140] Substrate 100;

[0141] The first conductive layer 200 is located on one side of the substrate 100. The first conductive layer 200 includes the active layer 201 of the first initialization transistor M1, the active layer 202 of the second initialization transistor M2, and the active layer 203 of the third initialization transistor M3.

[0142] The first gate layer 300 is located on the side of the first conductive layer 200 facing away from the substrate 100. The first gate layer 300 includes the gate 301 of the first initialization transistor M1, the gate 302 of the second initialization transistor M2, the gate 303 of the third initialization transistor M3, and a first gate line S1 and a second gate line S2. The gate 301 of the first initialization transistor M1 is connected to the first gate line S1, and the gate 302 of the second initialization transistor M2 and the gate 303 of the third initialization transistor M3 are connected to the second gate line S2.

[0143] The second gate layer 400 is located on the side of the first gate layer 300 facing away from the substrate 100. The second gate layer 400 includes a first trace V1 and a second trace V2. The first trace V1 is connected to the active layer of the first switching transistor T1 and the active layer of the second switching transistor T2 through a via. The second trace V2 is connected to the active layer of the third switching transistor T3 (not shown in the figure) through a via. The second trace V2 is connected to the active layer of the third initialization transistor M3 through a seventh via 007.

[0144] The second conductive layer 500 is located on the side of the second gate layer 400 away from the substrate 100, and includes a first connecting line L1. The first connecting line L1 is connected to the active layer 201 of the first initialization transistor M1 and the active layer 202 of the second initialization transistor M2 through an eighth via 008, and the first connecting line L1 is connected to the first trace V1 through a ninth via 009.

[0145] In some embodiments of this disclosure, for the display panel shown in Figures 10 to 14, as shown in Figure 15, the display area AA of the display panel may further include an insulating layer 600 and a planarization layer 700, wherein the insulating layer 600 includes a first insulating layer 601, a second insulating layer 602, a third insulating layer 603, and a fourth insulating layer 604.

[0146] The first insulating layer 601 is located between the first gate layer 300 and the first conductive layer 200, and is used to isolate the first gate layer 300 and the first conductive layer 200.

[0147] The second insulating layer 602 is located between the first gate layer 300 and the second gate layer 400 and is used to protect the first gate layer 300.

[0148] The third insulating layer 603 is located between the second insulating layer 602 and the second gate layer 400, and is used to isolate the second gate layer 400 from the first gate layer 300.

[0149] The fourth insulating layer 604 is located between the second gate layer 400 and the second conductive layer 500, and is used to protect the second gate layer 400.

[0150] The planarization layer 700 is located on the side of the second conductive layer 500 away from the substrate 100, and is used to protect the lower circuit film layer and planarize it.

[0151] For example, the pixel circuit described above can be a 7T1C pixel circuit or an 8T1C pixel circuit.

[0152] This disclosure also provides a method for manufacturing a display panel as shown in FIG15, and as shown in FIG16, it may include the following manufacturing steps:

[0153] Step S1601: Provide a substrate 100, as shown in Figure 16(a);

[0154] Step S1602: A first conductive layer 200, a first insulating layer 601, and a first gate layer 300 are sequentially formed on the substrate 100, as shown in FIG16(b);

[0155] For example, the first conductive layer 200 can be made of amorphous silicon (a-Si) or gallium arsenide (GaAs), the first gate layer 300 can be made of molybdenum or copper, and the first insulating layer 601 can be made of silicon oxide (SiO) or silicon nitride (SiN).

[0156] Step S1603: A second insulating layer 602, a third insulating layer 603 and a second gate layer 400 are sequentially formed on the first gate layer 300, as shown in Figure 16(c);

[0157] For example, the second insulating layer 602 and the third insulating layer 603 can be made of silicon oxide (SiO) or silicon nitride (SiN), and the second gate layer 400 can be made of molybdenum or copper.

[0158] Step S1604: A fourth insulating layer 604 is formed on the second gate layer 400, and vias K1 and K2 connected to the first conductive layer 200 and the second gate layer 400 are formed along the thickness direction of the display panel, as shown in FIG16(d).

[0159] For example, the fourth insulating layer 604 can be made of silicon oxide (SiO) or silicon nitride (SiN).

[0160] Step S1605: A second conductive layer 500 and a planarization layer 700 are sequentially formed on the fourth insulating layer 604. The second conductive layer 500 is connected to the first conductive layer 200 through via K1 and to the second gate layer 400 through via K2, as shown in Figure 16(e).

[0161] For example, the material used to fabricate the second conductive layer 500 can be aluminum or a titanium / aluminum / titanium composite material.

[0162] This disclosure also provides a display device, including the display panel described above.

[0163] In specific implementations, in the embodiments of this disclosure, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0164] For example, as shown in FIG17, the display device includes a display panel DP, which may include a display area AA and non-display areas BB distributed on both sides of the display area AA. The display area AA includes multiple rows of pixel circuits 10, and the non-display areas include multiple gate drive circuits GOA, a first initialization signal line Vinit1, a second initialization signal line Vinit2, a third initialization signal line Vinit3, and multiple first switching transistors, second switching transistors, and third switching transistors (not shown in the figure). Each row of pixel circuits corresponds to two gate drive circuits GOA. The signal output terminal of the left gate drive circuit GOA is coupled to a first gate line S1, and the signal output terminal of the right gate drive circuit GOA is coupled to a second gate line S2.

[0165] The operation of the pixel circuit provided in the embodiments of this disclosure will be described below using the pixel circuit shown in Figure 18 as an example and in conjunction with the signal timing diagram shown in Figure 19.

[0166] As shown in Figure 18, the pixel circuit includes three initialization transistors M1, M7, and M8, a scanning transistor M2, a driving transistor M3, a data writing transistor M4, and two light-emitting control transistors M5 and M6. M1 is the first initialization transistor, M8 is the second initialization transistor, and M7 is the third initialization transistor. The first terminal of the first switching transistor T1 is coupled to the first initialization signal line Vinit1, the first terminal of the second switching transistor T2 is coupled to the second initialization signal line Vinit2, and the first terminal of the third switching transistor T3 is coupled to the third initialization signal line Vinit3. The second terminals of the first switching transistor T1 and the second switching transistor T2 are respectively coupled to the first trace V1. The first terminals of the initialization transistors M1 and M8 are coupled to the first connecting line L1, which is connected to the first trace V1. The second terminal of the third switching transistor T3 and the first terminal of the initialization transistor M7 are respectively coupled to the second trace V2. The gates of initialization transistor M1 and the first switching transistor T1 are coupled to the first gate line S1, and the gates of initialization transistors M7 and M8, as well as the gates of the second switching transistor T2 and the third switching transistor T3, are coupled to the second gate line S2. The first gate line S1 and the second gate line S2 are electrically connected to the first gate driving circuit 30 and the second gate driving circuit 40, respectively.

[0167] Specifically, stages T1, T2, T3, and T4 are selected from the signal timing diagram shown in Figure 19. It should be noted that the signal timing diagram shown in Figure 19 only represents the operation of a single pixel circuit within one frame. The operation of this pixel circuit in other frames is essentially the same as in this frame, and will not be elaborated upon here.

[0168] In the first stage T1, a low-level signal reset1 is applied to the first gate line S1, a high-level signal reset2 is applied to the second gate line S2, a low-level signal gate1 is applied to the gate of the scanning transistor M2, a high-level signal gate2 is applied to the gate of the data writing transistor M4, and a high-level signal em is applied to the gates of the light-emitting control transistors M5 and M6.

[0169] The first switching transistor T1 is turned on under the control of the signal input to the first gate line S1. The turned-on first switching transistor T1 provides the first initialization signal input to the first initialization signal line Vinit1 to the first connecting line L1 through the first trace V1.

[0170] The initialization transistor M1 is turned on under the control of the signal input to the first gate line S1, and the scanning transistor M2 is turned on under the control of the low-level signal gate1. The turned-on initialization transistor M1 and scanning transistor M2 provide the first initialization signal input to the first connected line L1 to the first node N1, and charge and reset the storage capacitor Cs.

[0171] In the second stage T2, a high-level signal reset1 is applied to the first gate line S1, a high-level signal reset2 is applied to the second gate line S2, a low-level signal gate1 is applied to the gate of the scanning transistor M2, a low-level signal gate2 is applied to the gate of the data writing transistor M4, and a high-level signal em is applied to the gates of the light-emitting control transistors M5 and M6.

[0172] The scanning transistor M2 is turned on under the control of the low-level signal gate1, and the data writing transistor is turned on under the control of the low-level signal gate2. At the same time, under the storage effect of the storage capacitor, the first node N1 maintains the low level of the previous stage, and controls the driving transistor M3 to turn on. The turned-on scanning transistor M2, driving transistor M3, and data writing transistor M4 provide the data voltage Data to the storage capacitor Cs.

[0173] In the third stage T3, a high-level signal reset1 is applied to the first gate line S1, a low-level signal reset2 is applied to the second gate line S2, a high-level signal gate1 is applied to the gate of the scanning transistor M2, a high-level signal gate2 is applied to the gate of the data writing transistor M4, and a high-level signal em is applied to the gates of the light-emitting control transistors M5 and M6.

[0174] The second switching transistor T2 is turned on under the control of the signal input to the second gate line S2. The turned-on second switching transistor T2 provides the second initialization signal input to the second initialization signal line Vinit2 to the first connecting line L1 through the first trace V1.

[0175] The initialization transistor M8 is turned on under the control of the signal input to the second gate line S2. The turned-on initialization transistor M8 provides the second initialization signal input to the first connecting line L1 to the second node N2. At the same time, under the storage effect of the storage capacitor, the first node N1 maintains the low level of the previous stage, controls the driving transistor M3 to turn on. The turned-on driving transistor M3 provides the signal of the second node N2 to the third node N3 to charge and reset the driving transistor M3.

[0176] The third switching transistor T3 is turned on under the control of the signal input to the second gate line S2. The turned-on third switching transistor T3 provides the third initialization signal input to the third initialization signal line Vinit3 to the first terminal of the initialization transistor M7 through the second trace V2.

[0177] The initialization transistor M7 is turned on under the control of the signal input to the second gate line S2. The turned-on initialization transistor M7 provides the third initialization signal to the anode of the light-emitting device P, and charges and resets the light-emitting device P.

[0178] In the fourth stage T4, a high-level signal reset1 is applied to the first gate line S1, a high-level signal reset2 is applied to the second gate line S2, a high-level signal gate1 is applied to the gate of the scanning transistor M2, a high-level signal gate2 is applied to the gate of the data writing transistor M4, and a low-level signal em is applied to the gates of the light-emitting control transistors M5 and M6.

[0179] Under the control of the low-level signal em, the light-emitting control transistors M5 and M6 are turned on. At the same time, under the storage effect of the storage capacitor Cs, the first node N1 maintains the low level of the previous stage, controlling the driving transistor M3 to turn on. The turned-on light-emitting control transistors M5, M3, and M7 provide the signal of the first power supply terminal Vdd to the anode of the light-emitting device P, controlling the light-emitting device P to emit light.

[0180] During the non-initialization phase, both the first gate line S1 and the second gate line S2 are input with high-level signals, causing the initialization transistor M1, the first switching transistor T1, the initialization transistor M8, and the second switching transistor T2 to be in the off state. The first initialization signal input to the first initialization signal line Vinit1 cannot be written to the first terminal (e.g., the drain) of the initialization transistor M1, and the second initialization signal input to the second initialization signal line Vinit2 cannot be written to the first terminal (e.g., the source) of the initialization transistor M8. At this time, the potential of the first terminal of the initialization transistor M1 and the first terminal of the initialization transistor M8 is close to 0, as shown in Figures 20 and 21. Compared with the 8T1C pixel circuit in the related technology, the potential of the first terminal of the initialization transistor M1 is constant at -3 to -5V, which effectively reduces the source-drain voltage difference of the initialization transistors M1 and M8 during the non-initialization phase, thereby reducing the leakage current of the initialization transistor.

[0181] The display panel and display device provided in this disclosure control the input of the initialization signal through a switching circuit, so that the initialization signal cannot be input to the first terminal of the initialization transistor of the pixel circuit during the non-initialization stage, thereby reducing the voltage difference between the source and drain of the initialization transistor, reducing leakage current, improving display quality, and enhancing display effect.

[0182] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0183] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. A display panel, wherein, include: Display area and non-display area; The display area includes multiple pixel units, each pixel unit includes a pixel circuit, and the pixel circuit includes a driving transistor and an initialization transistor, with the second terminal of the initialization transistor coupled to the driving transistor. The non-display area includes multiple switching circuits, with at least two pixel units in a row sharing one of the switching circuits, and the first terminal of the initialization transistor in a row of pixel units being coupled to the shared switching circuit; the switching circuit is configured to output an initialization signal to the first terminal of the initialization transistor in response to a gate drive signal.

2. The display panel as claimed in claim 1, wherein, The initialization transistor includes a first initialization transistor, and the switching circuit includes a first switching circuit; The gate of the first initialization transistor is used to receive a first reset control signal, the first terminal of the first initialization transistor is coupled to the first switching circuit, and the second terminal of the first initialization transistor is coupled to the second terminal of the driving transistor.

3. The display panel as described in claim 2, wherein, The first switching circuit includes a first switching transistor; the gate drive signal includes a first gate drive signal; and the initialization signal includes a first initialization signal. The gate of the first switching transistor is used to receive the first gate drive signal, the first terminal of the first switching transistor is used to receive the first initialization signal, and the second terminal of the first switching transistor is coupled to the first terminal of the first initialization transistor.

4. The display panel as claimed in claim 3, wherein, The display area further includes multiple first gate lines, and the non-display area further includes a first gate driving circuit electrically connected to each of the first gate lines; wherein, the gate of the first switching transistor electrically connected to a row of pixel circuits and the gates of each first initialization transistor electrically connected to the first switching transistor are electrically connected.

5. The display panel as claimed in claim 3, wherein, The non-display area also includes a first initialization signal line; the first pole of the first switching transistor of each of the first switching circuits is respectively coupled to the first initialization signal line.

6. The display panel as described in any one of claims 2-5, wherein, The first initialization transistors in at least two adjacent pixel units in the same row share a first switching circuit.

7. The display panel as claimed in claim 6, wherein, The first initialization transistors in all pixel circuits in the same row share a single first switching circuit.

8. The display panel according to any one of claims 1-7, wherein, The initialization transistor includes a second initialization transistor, and the switching circuit includes a second switching circuit; The gate of the second initialization transistor is used to receive the second reset control signal, the first terminal of the second initialization transistor is coupled to the second switching circuit, and the second terminal of the second initialization transistor is coupled to the first terminal of the driving transistor.

9. The display panel as claimed in claim 8, wherein, The second switching circuit includes a second switching transistor; the gate drive signal includes a second gate drive signal, and the initialization signal includes a second initialization signal; The gate of the second switching transistor is used to receive the second gate drive signal, the first terminal of the second switching transistor is used to receive the second initialization signal, and the second terminal of the second switching transistor is coupled to the first terminal of the second initialization transistor.

10. The display panel as claimed in claim 9, wherein, The display area further includes multiple second gate lines, and the non-display area further includes a second gate driving circuit electrically connected to each of the second gate lines; wherein, the gate of the second switching transistor electrically connected to a row of pixel circuits and the gates of each of the second initialization transistors electrically connected to the second switching transistors are electrically connected.

11. The display panel as claimed in claim 9, wherein, The non-display area also includes a second initialization signal line, and the first terminal of the second switching transistor of each of the second switching circuits is coupled to the second initialization signal line.

12. The display panel as claimed in any one of claims 8-11, wherein, The second initialization transistors in at least two adjacent pixel units in the same row share a second switching circuit.

13. The display panel as claimed in claim 12, wherein, The second initialization transistors in all pixel circuits in the same row share a single second switching circuit.

14. The display panel according to any one of claims 1-13, wherein, The initialization transistor further includes a third initialization transistor, and the switching circuit further includes a third switching circuit; The pixel circuit further includes a light-emitting control transistor and a light-emitting device, wherein the first terminal of the light-emitting control transistor is coupled to the second terminal of the driving transistor, and the second terminal of the light-emitting control transistor is connected to the first terminal of the light-emitting device; The gate of the third initialization transistor is used to receive the third reset control signal. The first terminal of the third initialization transistor is coupled to the third switching circuit, and the second terminal of the third initialization transistor is coupled to the first terminal of the light-emitting device.

15. The display panel as claimed in claim 14, wherein, The third switching circuit includes a third switching transistor; the gate drive signal includes a third gate drive signal; and the initialization signal includes a third initialization signal. The gate of the third switching transistor is used to receive the third gate drive signal, the first terminal of the third switching transistor is used to receive the third initialization signal, and the second terminal of the third switching transistor is coupled to the first terminal of the third initialization transistor.

16. The display panel as claimed in claim 15, wherein, The display area further includes multiple third gate lines, and the non-display area further includes a third gate driving circuit electrically connected to each of the third gate lines; wherein, the gate of the third switching transistor electrically connected to a row of pixel circuits and the gates of each third initialization transistor electrically connected to the third switching transistor are electrically connected.

17. The display panel as claimed in claim 15, wherein, The non-display area also includes a third initialization signal line, and the first terminal of the third switching transistor of each of the third switching circuits is coupled to the third initialization signal line.

18. The display panel according to any one of claims 14-17, wherein, The third initialization transistors in at least two adjacent pixel units in the same row share a third switching circuit.

19. The display panel as claimed in claim 18, wherein, The third initialization transistors in all pixel circuits in the same row share a single third switching circuit.

20. The display panel according to any one of claims 2-13, wherein, The initialization transistor includes a first initialization transistor and a second initialization transistor, and the switching circuit includes a first switching circuit and a second switching circuit; the first initialization transistors in all pixel circuits in the same row share one first switching circuit, and the second initialization transistors in all pixel circuits in the same row share one second switching circuit. The display area also includes multiple first connecting lines, and the first electrode of each of the first initialization transistors and the first electrode of the second initialization transistor in a row of pixel units are coupled to the corresponding first switching circuit and second switching circuit through the same first connecting line.

21. The display panel as described in any one of claims 2-7 and 14-19, wherein, The initialization transistor includes a first initialization transistor and a third initialization transistor, and the switching circuit includes a first switching circuit and a third switching circuit; the first initialization transistors in all pixel circuits in the same row share one first switching circuit, and the third initialization transistors in all pixel circuits in the same row share one third switching circuit. The display area also includes multiple second connecting lines. The first electrode of each first initialization transistor and the first electrode of each third initialization transistor in a row of pixel units are coupled to the corresponding first switching circuit and the third switching circuit through the same second connecting line.

22. The display panel according to any one of claims 8-19, wherein, The initialization transistor includes a second initialization transistor and a third initialization transistor, and the switching circuit includes a second switching circuit and a third switching circuit; the second initialization transistors in all pixel circuits in the same row share one second switching circuit, and the third initialization transistors in all pixel circuits in the same row share one third switching circuit; The display area also includes multiple third connecting lines. The first pole of each second initialization transistor and the first pole of each third initialization transistor in a row of pixel units are coupled to the corresponding second switching circuit and the third switching circuit through the same third connecting line.

23. A display device, wherein, Includes the display panel as described in any one of claims 1-22.

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