Display substrate and display device

Abstract

A display substrate, comprising: a base (100), a plurality of first pins (21), a plurality of second pins (22), a plurality of third pins (23), and a plurality of first internal connection lines (31). The plurality of first pins (21) are located in a first signal access area (B11), the plurality of second pins (22) and the plurality of third pins (23) are located in a second signal access area (B12), and the plurality of second pins (22) are located on a side of the plurality of third pins (23) away from an active area (AA) in a first direction (D1). At least one first pin (21) is connected to at least one second pin (22) through at least one first internal connection line (31). The plurality of first internal connection lines (31) are located on a side of the plurality of second pins (22) close to the plurality of third pins (23) in the first direction (D1).

Description

Display substrate and display device Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active light-emitting display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a display substrate and a display device.

[0005] On one hand, this embodiment provides a display substrate, including: a substrate, a plurality of first pins, a plurality of second pins, a plurality of third pins, and a plurality of first internal connection lines disposed on the substrate. The substrate includes: a display area and a peripheral area located on at least one side of the display area. The peripheral area may include a first border area located on one side of the display area along a first direction. The first border area may include: at least one first signal access area and at least one second signal access area; the at least one first signal access area may be located on at least one side of the at least one second signal access area along a second direction. The second direction may intersect the first direction, for example, the second direction may be perpendicular to the first direction. The plurality of first pins are located in the at least one first signal access area. The plurality of second pins and the plurality of third pins are located in the at least one second signal access area, and the plurality of second pins may be located on the side of the plurality of third pins away from the display area along the first direction. The plurality of first internal connection lines are located in the first border area, and at least one of the plurality of first pins is connected to at least one of the plurality of second pins through at least one of the plurality of first internal connection lines; the plurality of first internal connection lines are located on the side of the plurality of second pins closer to the plurality of third pins in the first direction.

[0006] In some exemplary embodiments, the at least one second signal access area has a first edge extending along the first direction, a plurality of second pins within the at least one second signal access area are arranged sequentially along the second direction and sequentially away from the first edge, and the corresponding connected first internal connection lines are sequentially close to the plurality of third pins along the first direction.

[0007] In some exemplary embodiments, the first pin connected to the second pin closest to the first edge of the plurality of second pins is located on the side of the first pin connected to the second pin furthest from the first edge that is closer to the first edge.

[0008] In some exemplary embodiments, the at least one first internal connection line includes: a first connection segment extending along the second direction, a second connection segment extending along the first direction, and a third connection segment; the first connection segment is connected between the second connection segment and the third connection segment and extends outward from the second signal access area along the second direction; the second connection segment is located in the second signal access area and is connected to the at least one second pin; the third connection segment is connected to the at least one first pin and is located on the side of the at least one first pin near the display area.

[0009] In some exemplary embodiments, the plurality of first internal connection lines are in the same layer.

[0010] In some exemplary embodiments, in a direction perpendicular to the display substrate, the display substrate includes: a gate metal layer and a source / drain metal layer disposed on the substrate, the source / drain metal layer being located on the side of the gate metal layer away from the substrate; and the plurality of first internal interconnect lines being located on the source / drain metal layer.

[0011] In some exemplary embodiments, the display substrate further includes: a frame organic insulating layer located on the side of the source / drain metal layer away from the substrate and located in the first frame region, wherein the orthographic projection of the frame organic insulating layer on the substrate at least partially overlaps with the orthographic projection of the plurality of first internal connection lines on the substrate, and does not overlap with the orthographic projection of the plurality of first pins, the plurality of second pins and the plurality of third pins on the substrate.

[0012] In some exemplary embodiments, the display substrate further includes: a gate driving circuit, multiple control signal lines, and multiple control leads located in the peripheral region; the multiple control signal lines are connected to the gate driving circuit; the multiple control leads are connected to a portion of the third pins of a plurality of third pins in the second signal access region. The gate driving circuit includes n shift register circuits in a cascaded relationship. The connection positions of the multiple control leads and the multiple control signal lines are adjacent to the i-th stage shift register circuit, where n is an integer greater than 0, and i is an integer not equal to 1 and n.

[0013] In some exemplary embodiments, the plurality of first pins of the at least one first signal access area include: a plurality of first type pins and a plurality of second type pins; the plurality of first type pins are multiplexed as test pins.

[0014] In some exemplary embodiments, the display substrate further includes: at least one set of test pins located in the first frame region, the at least one set of test pins being located along the first direction on the side of the at least one first signal access region near the display region, and being offset from the at least one first signal access region along the second direction.

[0015] In some exemplary embodiments, the at least one set of test pins includes: a plurality of first test pins and a plurality of second test pins, wherein the plurality of first test pins are located on the side of the plurality of second test pins close to the first signal access area; the plurality of first type pins and the plurality of first test pins are aligned one by one along the first direction, and the first type pins and the first test pins aligned along the first direction are an integral structure.

[0016] In some exemplary embodiments, the display substrate further includes: at least one set of test pins located in the first frame region, the at least one set of test pins being aligned with a plurality of first pins in the at least one first signal access region along the second direction, and the plurality of first type pins being adjacent to the at least one set of test pins in the second direction.

[0017] In some exemplary embodiments, the width of at least one of the plurality of first type pins is greater than the width of at least one of the plurality of second type pins, and the spacing between adjacent first type pins is greater than the spacing between adjacent second type pins.

[0018] In some exemplary embodiments, the plurality of first-type pins includes at least one of the following: a plurality of control signal access pins, a plurality of first power access pins, and a plurality of second power access pins.

[0019] In some exemplary embodiments, the display substrate further includes at least one set of test pins located in the first frame region, wherein the number of test signals provided by the at least one set of test pins is less than the number of test signals required by the display substrate.

[0020] On the other hand, this embodiment provides a display device including the display substrate as described above.

[0021] On the other hand, this embodiment provides a display substrate, including: a substrate and a plurality of first pins. The substrate includes a display area and a first border area located on one side of the display area along a first direction, the first border area including: at least one first signal access area. The plurality of first pins are located in the at least one first signal access area and configured to be bonded to an external circuit board. The plurality of first pins include: a plurality of first type pins and a plurality of second type pins, the plurality of first type pins being multiplexed as test pins.

[0022] In some exemplary embodiments, the display substrate further includes: at least one set of test pins located in the first frame region, the at least one set of test pins being located along the first direction on the side of the at least one first signal access region near the display region, and being offset from the at least one first signal access region along the second direction.

[0023] In some exemplary embodiments, the at least one set of test pins includes: a plurality of first test pins and a plurality of second test pins, wherein the plurality of first test pins are located on the side of the plurality of second test pins close to the first signal access area; the plurality of first type pins and the plurality of first test pins are aligned one by one along the first direction, and the first type pins and the first test pins aligned along the first direction are an integral structure.

[0024] In some exemplary embodiments, the display substrate further includes: at least one set of test pins located in the first frame region, the at least one set of test pins being aligned with a plurality of first pins in the at least one first signal access region along the second direction, and the plurality of first type pins being adjacent to the at least one set of test pins in the second direction.

[0025] In some exemplary embodiments, the plurality of second-type pins includes: at least one first group of second-type pins and at least one second group of second-type pins, the plurality of first-type pins being located between the at least one first group of second-type pins and the at least one second group of second-type pins, the first group of second-type pins being configured to transmit control signals, and the second group of second-type pins being configured to transmit data signals.

[0026] In some exemplary embodiments, the width of at least one of the plurality of first type pins is greater than the width of at least one of the plurality of second type pins, and the spacing between adjacent first type pins is greater than the spacing between adjacent second type pins.

[0027] In some exemplary embodiments, the plurality of first-type pins includes at least one of the following: a plurality of control signal access pins, a plurality of first power access pins, and a plurality of second power access pins.

[0028] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0029] Overview of the attached figures

[0030] The accompanying drawings are provided to further understand the technical solutions of this disclosure and constitute a part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0031] Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0032] Figure 2A is a partial cross-sectional schematic diagram of the display area of ​​a display substrate according to at least one embodiment of the present disclosure;

[0033] Figure 2B is another partial cross-sectional view of the display area of ​​a display substrate according to at least one embodiment of the present disclosure;

[0034] Figure 3 is a schematic diagram of the first border region of at least one embodiment of the present disclosure;

[0035] Figures 4A and 4B are schematic diagrams showing the connection of the multiple first pins and multiple second pins in Figure 3;

[0036] Figure 5 is a partial cross-sectional schematic diagram of the second signal access area in at least one embodiment of the present disclosure;

[0037] Figure 6 is a partially enlarged schematic diagram of the second signal access area in Figure 3;

[0038] Figure 7 is a schematic diagram of the first signal access area B11a and the test signal access area B13a in Figure 3;

[0039] Figure 8 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0040] Figure 9 is a partial schematic diagram of the first border area in Figure 8;

[0041] Figure 10 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0042] Figure 11 is a partial schematic diagram of the first border region in Figure 10;

[0043] Figure 12 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0044] Figure 13 is a partial schematic diagram of the first border area in Figure 12;

[0045] Figure 14 is a schematic diagram showing that there are no multiple first-type access pins between the second data access pin and the second control access pin in the first signal access area;

[0046] Figure 15 is a schematic diagram of the cutting of a display substrate according to at least one embodiment of the present disclosure;

[0047] Figure 16 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0048] Detailed Explanation

[0049] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0050] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0051] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0052] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0053] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or joint; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0054] In this specification, "connection" can include "electrical connection." "Electrical connection" includes situations where components are connected together by elements that have some electrical function. There are no particular limitations on the "elements that have some electrical function," as long as they enable the transmission of electrical signals between the connected components. Examples of "elements that have some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other multifunctional elements.

[0055] In this specification, a transistor is a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between its drain (drain terminal, drain region, or drain electrode) and its source (source terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0056] In this specification, the first terminal can be the drain and the second terminal can be the source, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged. Additionally, the gate can also be called the control terminal.

[0057] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0058] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined. They can be approximate circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, such as chamfers, curved edges, and other variations.

[0059] In this disclosure, "about" and "approximately" refer to situations where there are no strict limits and the process and measurement errors are allowed. In this disclosure, "same" can include cases where index values ​​differ by no more than 10%.

[0060] In this disclosure, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped solid. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this disclosure, "A extends along direction B" refers to "the main part of A extends along direction B".

[0061] In this specification, "A and B are of the same layer structure" and "A and B are arranged in the same layer" mean that A and B are formed simultaneously through the same patterning process, or that the surfaces of A and B closest to the substrate are substantially the same distance from the substrate, or that the surfaces of A and B closest to the substrate are in direct contact with the same film layer. "Same layer" does not always mean that the layer thickness or layer height is the same in a cross-sectional view. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection area of ​​A, or the orthographic projection of A covers the orthographic projection of B. The "shape of A" in this disclosure refers to the shape of the orthographic projection of A onto the substrate.

[0062] Organic Light Emitting Diode (OLED) displays have gained widespread application in televisions, smartphones, smart wearables, virtual reality (VR), and automotive displays due to their numerous advantages, including thinness, flexibility, shock resistance, fast response, and compatibility with wearable devices. As consumers increasingly demand portability and optimal viewing angles in display products, narrow-bezel displays are attracting more and more attention, with ultra-narrow bezels and even full-screen displays becoming a new trend in OLED display development. However, further reducing the bottom bezel of OLED displays remains a bottleneck in narrow-bezel design.

[0063] This embodiment provides a display substrate and a display device that can help achieve an extremely narrow bezel.

[0064] This embodiment provides a display substrate, including: a substrate, a plurality of first pins, a plurality of second pins, a plurality of third pins, and a plurality of first internal connection lines disposed on the substrate. The substrate includes: a display area and a peripheral area located on at least one side of the display area. The peripheral area may include a first border area located on one side of the display area along a first direction. The first border area may include: at least one first signal access area and at least one second signal access area; the at least one first signal access area may be located on at least one side of the at least one second signal access area along a second direction. The second direction may intersect the first direction, for example, the second direction may be perpendicular to the first direction. The plurality of first pins are located in the at least one first signal access area. The plurality of second pins and the plurality of third pins are located in the at least one second signal access area, and the plurality of second pins may be located on the side of the plurality of third pins away from the display area along the first direction. The plurality of first internal connection lines are located in the first border area, and at least one of the plurality of first pins is connected to at least one of the plurality of second pins through at least one of the plurality of first internal connection lines; the plurality of first internal connection lines are located on the side of the plurality of second pins closer to the plurality of third pins in the first direction.

[0065] The display substrate provided in this embodiment has a first internal connection line connecting the first pin and the second pin disposed between a plurality of second pins and a plurality of third pins in the second signal access area; that is, by leading out the first internal connection line from the inside of the second signal access area, the length of the first border area of ​​the display substrate along the first direction can be reduced, thereby helping to achieve an extremely narrow border.

[0066] In some exemplary embodiments, at least one second signal access area may have a first edge extending along a first direction. A plurality of second pins within the at least one second signal access area are arranged sequentially along the second direction and sequentially away from the first edge. Corresponding first internal connection lines are sequentially close to the plurality of third pins along the first direction. For example, the first internal connection line connected to the second pin closest to the first edge may be located on the side of the first internal connection line connected to the second pin away from the first edge, away from the plurality of third pins. In some examples, the first pin connected to the second pin closest to the first edge may be located on the side of the first pin connected to the second pin away from the first edge, close to the first edge. In this example, the first pin closest to the first edge is connected to the second pin closest to the first edge, and the first pin away from the first edge is connected to the second pin away from the first edge, i.e., a connection method of connecting near to near and far to far is adopted. This connection method in this example can facilitate the arrangement of multiple first internal connection lines and avoid the situation where overlapping connection lines affect signal transmission.

[0067] In some exemplary embodiments, the multiple first internal interconnects can be on the same layer. For example, the multiple first internal interconnects can be located in the same source / drain metal layer. This example, by placing the multiple first internal interconnects in the same source / drain metal layer, can help reduce the trace impedance of the first internal interconnects.

[0068] In some exemplary embodiments, the display substrate may further include: a frame organic insulating layer located on the side of the source / drain metal layer away from the substrate and located in the first frame region, wherein the orthographic projection of the frame organic insulating layer onto the substrate may cover the orthographic projection of the plurality of first internal interconnect lines onto the substrate, and may not overlap with the orthographic projections of the plurality of first pins and the plurality of second pins onto the substrate. This example, by providing a frame organic insulating layer to cover the plurality of first internal interconnect lines, can prevent the first internal interconnect lines from being broken by the driver chip bonding or from being corroded by reliability corrosion.

[0069] In some exemplary embodiments, at least one first pin in a first signal access area may include a plurality of first-type pins and a plurality of second-type pins; the plurality of first-type pins may be multiplexed as test pins. This example, by multiplexing some of the first pins as test pins, reduces the number of pins arranged along the second direction, which is beneficial for reducing the size of the first frame area along the second direction, thereby facilitating the achievement of a narrow frame.

[0070] In some exemplary embodiments, the plurality of first-type pins may include at least one of the following: a plurality of control signal access pins, a plurality of first power supply access pins, and a plurality of second power supply access pins. The plurality of first power supply access pins may be configured to transmit a first power supply signal, and the plurality of second power supply access pins may be configured to transmit a second power supply signal. The plurality of control signal access pins may include: a plurality of second control access pins configured to transmit signals (e.g., clock signals, voltage signals, etc.) provided to the gate drive circuitry.

[0071] The following examples illustrate the solution of this embodiment.

[0072] Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 1, the display substrate may include: a display area AA, and a peripheral area BB surrounding the display area AA. The peripheral area BB may include: a first border area B1 located on one side of the display area AA along a first direction D1, and other border areas located on other sides of the display area AA. The other border areas may include: a second border area B2 located on the side of the display area AA away from the first border area B1 along the first direction D1, a third border area B3 located on both sides of the display area AA along a second direction D2, and a fourth border area B4. The first border area B1 may be the lower border area of ​​the display substrate, the second border area B2 may be the upper border area of ​​the display substrate, the third border area B3 may include the left border area of ​​the display substrate, a corner area connecting the first border area B1, and a corner area connecting the second border area B2, and the fourth border area B4 may include the right border area of ​​the display substrate, a corner area connecting the first border area B1, and a corner area connecting the second border area B2. In other examples, the peripheral area BB may surround at least one side of the display area AA.

[0073] In some examples, the display area AA can be rectangular. However, this embodiment is not limited to this. For example, the display area AA can be other shapes such as circles or ellipses.

[0074] In some examples, the display area AA can be a flat area, which may include multiple sub-pixels PX, multiple gate lines GL, and multiple data lines DL forming a pixel array. The multiple sub-pixels PX can be configured to display dynamic or still images. The multiple gate lines GL can extend along a second direction D1 and be arranged along a first direction D1; the multiple data lines DL can extend along the first direction D1 and be arranged along the second direction D1. The orthographic projections of the multiple gate lines GL and the multiple data lines DL onto the substrate can intersect to form multiple sub-pixel regions, each of which can contain one sub-pixel PX. The multiple data lines DL can be electrically connected to the multiple sub-pixels PX, and can be configured to provide data signals to the multiple sub-pixels PX. The multiple gate lines GL can be electrically connected to the multiple sub-pixels PX, and can be configured to provide pixel control signals to the multiple sub-pixels PX. In some examples, the pixel control signals may include scan signals and emission control signals, or may include scan signals, or may include scan signals, reset control signals, and emission control signals.

[0075] In some examples, as shown in Figure 1, the second direction D2 can be the extension direction of the grid line GL in the display area AA (e.g., the row direction), and the first direction D1 can be the extension direction of the data line DL in the display area AA (e.g., the column direction). The first direction D1 and the second direction D2 can intersect each other, for example, they can be perpendicular to each other.

[0076] In some examples, a pixel unit of the display area AA may include three sub-pixels, namely a red sub-pixel, a green sub-pixel, and a blue sub-pixel. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, namely a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel.

[0077] In some examples, a sub-pixel may include a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, 8T1C, 8T2C, or 9T2C structure. In these circuit structures, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit simplifies the process flow, reduces the processing difficulty of the display substrate, and improves product yield. In other examples, the multiple transistors in the pixel circuit may include both P-type and N-type transistors.

[0078] In some examples, the multiple transistors in the pixel circuit can be low-temperature polysilicon (LTPS) thin-film transistors (TFTs), oxide thin-film transistors (OPTs), or a combination of both. The active layer of the LTPS TFT is made of low-temperature polysilicon (LTPS), while the active layer of the OPT TFT is made of oxide. LTPS TFTs offer advantages such as high mobility and fast charging, while OPTs offer advantages such as low leakage current. Integrating LTPS and OPTs onto a single display substrate—an LTPS+Oxide (LTPO) display substrate—leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0079] In some examples, the light-emitting element can be any of the following: a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED (including mini-LED or micro-LED). For example, the light-emitting element can be an OLED, which can emit red, green, blue, or white light under the drive of its corresponding pixel circuit. The color of the light emitted by the light-emitting element can be determined as needed. In some examples, the light-emitting element may include an anode, a cathode, and an organic light-emitting layer located between the anode and cathode. The anode of the light-emitting element can be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited in this respect.

[0080] In some examples, the orthographic projection of the light-emitting element of a sub-pixel onto the substrate can be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement; when a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement. However, this embodiment is not limited in this respect.

[0081] Figure 2A is a partial cross-sectional schematic diagram of a display area of ​​a display substrate according to at least one embodiment of the present disclosure. Figure 2A illustrates the structure of a sub-pixel in the display area as an example. In this example, it is described that multiple transistors in the pixel circuit are of the same type; for example, the multiple transistors in the pixel circuit may all be low-temperature polysilicon thin-film transistors (LTPS) or all be oxide thin-film transistors (OTS). In other examples, the multiple transistors in the pixel circuit may be both LPS and OTS.

[0082] In some examples, as shown in FIG2A, in a direction perpendicular to the display substrate, the display substrate may include: a substrate 100, and a circuit structure layer 120, a light-emitting structure layer 130, and an encapsulation structure layer 140 sequentially disposed on the substrate 100. The circuit structure layer 120 may include: pixel circuits of multiple sub-pixels located in the display area AA, each pixel circuit including multiple transistors and at least one capacitor. The light-emitting structure layer 130 may be located in the display area AA and may include: light-emitting elements of multiple sub-pixels. In some possible implementations, the display substrate may include other film layers, such as spacers, touch structure layers, etc., which are not limited in this embodiment.

[0083] In some examples, substrate 100 can be a rigid substrate, such as a glass substrate. In other examples, the substrate can be a flexible substrate, such as one made of an insulating material like resin. In still other examples, the substrate can be a single-layer or multi-layer structure. When the substrate is a multi-layer structure, inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride can be placed in single or multiple layers between the layers.

[0084] In some examples, Figure 2A illustrates a sub-pixel comprising a transistor 16 and a capacitor 17. The circuit structure layer 120 may include: a semiconductor layer, a gate metal layer (e.g., including a first gate metal layer and a second gate metal layer), and a source / drain metal layer (e.g., including a first source / drain metal layer and a second source / drain metal layer) disposed on the substrate 100. A first insulating layer (also referred to as a first gate insulating layer) 101 may be disposed between the semiconductor layer and the first gate metal layer; a second insulating layer (also referred to as a second gate insulating layer) 102 may be disposed between the first gate metal layer and the second gate metal layer; a third insulating layer (also referred to as an interlayer insulating layer) 103 may be disposed between the second gate metal layer and the first source / drain metal layer; a fourth insulating layer (also referred to as a passivation layer) 104 and a fifth insulating layer (also referred to as a first planarization layer) 105 may be disposed between the first source / drain metal layer and the second source / drain metal layer; and a sixth insulating layer (also referred to as a second planarization layer) 106 may be disposed on the side of the second source / drain metal layer away from the substrate 100. In this embodiment, the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, and the fourth insulating layer 104 can be inorganic insulating layers, while the fifth insulating layer 105 and the sixth insulating layer 106 can be organic insulating layers. However, this embodiment is not limited to these. In other examples, a buffer layer can be provided on the side of the semiconductor layer near the substrate. The buffer layer can prevent harmful substances in the substrate from penetrating into the interior of the display substrate and can also increase the adhesion of the film layers in the display substrate to the substrate. In other examples, a bottom shielding metal layer (BSM) can be provided on the side of the buffer layer near the substrate. The bottom shielding metal layer can be configured to at least partially cover the active layer of the thin-film transistor of the pixel circuit to avoid external light affecting the performance of the thin-film transistor. In other examples, the passivation layer between the first source / drain metal layer and the second source / drain metal layer can be omitted, and only a first planarization layer can be provided between the first source / drain metal layer and the second source / drain metal layer.

[0085] In some examples, the first gate metal layer, the second gate metal layer, the first source / drain metal layer, and the second source / drain metal layer can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). These can be single-layer structures or multi-layer composite structures, such as Ti / Al / Ti. The semiconductor layer can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, or polythiophene, etc. That is, this disclosure applies to transistors manufactured based on oxide technology, silicon technology, or organic technology.

[0086] In some examples, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. The semiconductor layer material may, for example, include polysilicon. The channel region may be undoped and possess semiconductor properties. The first and second regions may be doped regions on either side of the channel region and are doped with impurities, thus possessing conductivity. The impurities may vary depending on the type of transistor. In some examples, the doped regions of the active layer may be interpreted as the source or drain electrodes of the transistor. The portion of the active layer between transistors may be interpreted as doped wiring that can be used to electrically connect the transistors. This embodiment is not limited in this respect.

[0087] In some examples, as shown in FIG2A, the semiconductor layer of the display area may include at least the active layer 160 of transistor 16. The active layer 160 of transistor 16 may include a first region 1601, a second region 1602, and a channel region 1600 located between the first region 1601 and the second region 1602. The first gate metal layer may include at least the gate 163 of transistor 16 and the first electrode 171 of capacitor 17. The orthographic projection of the gate 163 of transistor 16 onto the substrate 100 may cover the orthographic projection of the channel region 1600 of the active layer 160 onto the substrate 100. The second gate metal layer may include at least the second electrode 172 of capacitor 17. The orthographic projections of the second electrode 172 and the first electrode 171 of capacitor 17 onto the substrate 100 may at least partially overlap, for example, they may coincide. The first source-drain metal layer may include at least the source 161 and the drain 162 of transistor 16. The third insulating layer 103 may have multiple vias (e.g., including a first pixel via and a second pixel via) in the display area. The third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 within the first pixel via can be removed, exposing at least a portion of the surface of the first region 1601 of the active layer 160. The third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 within the second pixel via can be removed, exposing at least a portion of the surface of the second region 1602 of the active layer 160. The source 161 of the transistor 16 can be electrically connected to the first region 1601 of the active layer 160 through the first pixel via, and the drain 162 can be electrically connected to the second region 1602 of the active layer 160 through the second pixel via. The second source-drain metal layer may include an anode transition electrode 181. The anode transition electrode 181 can be electrically connected to the drain 162 of the transistor 16 of the pixel circuit through the third pixel via formed by the fourth insulating layer 104 and the fifth insulating layer 105. This example demonstrates the electrical connection between the pixel circuitry and the light-emitting element via the anode adapter electrode 181.

[0088] In some examples, the gate line GL of the display area may be located, for example, in the first gate metal layer; the data line DL of the display area may be located, for example, in the second source-drain metal layer; and the high-potential power line of the display area may be located, for example, in the second source-drain metal layer. This embodiment is not limited in this respect. In other examples, the circuit structure layer may include three source-drain metal layers, which can avoid arranging too many traces in a single source-drain metal layer, thereby facilitating the realization of a narrow bezel structure.

[0089] In some examples, as shown in Figure 2A, the light-emitting structure layer 130 may include a pixel definition layer 134 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 131, an organic light-emitting layer 132, and a second electrode 133. The first electrode 131 of the light-emitting element can be an anode, and the first electrode 131 can be disposed on the sixth insulating layer 106 and electrically connected to the anode transition electrode 181 through a third pixel via formed in the sixth insulating layer 106. The pixel definition layer 134 is disposed on the first electrode 131 and the sixth insulating layer 106, and the pixel definition layer 134 may have multiple pixel openings, one pixel opening exposing at least a portion of the surface of a corresponding first electrode 131. At least a portion of the organic light-emitting layer 132 can be disposed within a pixel opening and connected to the corresponding first electrode 131. The second electrode 133 can be a cathode, and can be disposed on and in contact with the organic light-emitting layer 132. The organic light-emitting layer 132 can emit light of a corresponding color under the drive of the first electrode 131 and the second electrode 133. An isolation pillar layer can also be set on the side of the pixel definition layer 134 away from the substrate 100. The isolation pillar layer can include multiple isolation pillars (PS).

[0090] In some examples, the organic light-emitting layer 132 of the light-emitting element may include an emitting layer (EML) and one or more films selected from the following: a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Driven by the voltage of the first electrode 131 and the second electrode 133, the light-emitting properties of the organic material can be utilized to emit light at the required grayscale.

[0091] In some examples, the light-emitting layers of different colored light-emitting elements can be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. To reduce process complexity and improve yield, the hole injection layer and hole transport layer on one side of the light-emitting layer can be common layers, as can the electron injection layer and electron transport layer on the other side. In some examples, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer can be fabricated in a single process (single vapor deposition process or single inkjet printing process), and isolation can be achieved through surface steps of the formed film layers or through surface treatment. For example, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by vapor deposition using a fine metal mask (FMM) or an open mask, or by inkjet printing.

[0092] In some examples, as shown in Figure 2A, the encapsulation structure layer 140 may include a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143 stacked together. The first encapsulation layer 141 and the third encapsulation layer 143 may be made of inorganic materials, while the second encapsulation layer 142 may be made of organic materials. The second encapsulation layer 142 may be disposed between the first encapsulation layer 141 and the third encapsulation layer 143 to prevent external moisture from entering the light-emitting element. However, this embodiment is not limited to this. For example, the encapsulation structure layer may employ a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0093] Figure 2B is another partial cross-sectional schematic diagram of the display area of ​​a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 2B, the circuit structure layer 120 may include: a semiconductor layer, a gate metal layer (e.g., including a first gate metal layer and a second gate metal layer), and a source / drain metal layer (e.g., including a first source / drain metal layer) disposed on the substrate 100. The first electrode 131 of the light-emitting element can be electrically connected to the drain 162 of the transistor 16 through vias formed in the fifth insulating layer 105 and the fourth insulating layer 104. Further descriptions of the display substrate of this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0094] [Corrected according to Rule 91, 10.03.2025] Figure 3 is a schematic diagram of a first border region according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 3, the first border region B1 may include: two first signal access regions B11a and B11b, a second signal access region B12, and a first wiring area (as shown in Figure 6) located on the side of the second signal access region B12 closer to the display area AA. The first signal access region B11a may be located on one side of the second signal access region B12 along the second direction D2, and the first signal access region B11b may be located on the other side of the second signal access region B12 along the second direction D2. The first signal access regions B11a and B11b may be aligned along the second direction D2. The first signal access regions B11a and B11b may not be aligned with the second signal access region B12 along the first direction D1. The first signal access regions B11a and B11b may be symmetrically arranged about the centerline extending from the first border region B1 along the first direction D1. In this example, the first signal access area B11a can be located to the lower left of the second signal access area B12, and the first signal access area B11b can be located to the lower right of the second signal access area B12.

[0095] Compared to a configuration where the first signal access area is located on the side of the second signal access area furthest from the display area along the first direction, and the first and second signal access areas are aligned along the first direction, this example, by setting the first and second signal access areas to be staggered along the first direction, can help reduce the length of the first border area along the first direction D1. In other examples, the first border area may include multiple second signal access areas aligned along the second direction, and each second signal access area may have first signal access areas on both sides along the second direction.

[0096] In some examples, as shown in Figure 3, the first signal access areas B11a and B11b can each be configured with a set of first pins. A set of first pins may include multiple first pins 21 aligned along the second direction D2. The multiple first pins 21 can be configured to be bonded to an external circuit board. The second signal access area B12 may include multiple second pins 22 and multiple third pins 23. The multiple second pins 22 and multiple third pins 23 within the second signal access area B12 can be configured to be bonded to a driver chip (IC). The second signal access area B12 can also be referred to as the driver chip setting area.

[0097] In some examples, within the second signal access area B12, multiple second pins 22 may be located on the side of multiple third pins 23 away from the display area AA. The multiple second pins 22 may be arranged in a single row, and each row may include multiple second pins 22 arranged sequentially along the second direction D2. The multiple third pins 23 may be arranged in two rows, and each row may include multiple third pins 23 arranged sequentially along the second direction D2. The first row of third pins may be located on the side of the second row of third pins closer to the display area AA. The first row of third pins and the second row of third pins may be staggered along the first direction D1. In other examples, the multiple third pins 23 may be arranged in one or more rows, such as three rows. This embodiment is not limited in this respect.

[0098] In some examples, the second signal access area B12 can be a rectangular area. The second signal access area B12 can have two first edges B12-1 and B12-2 extending along a first direction D1, and two second edges B12-3 and B12-4 extending along a second direction D2. The two ends of the first edge B12-1 are connected to the second edges B12-3 and B12-4, respectively, and the two ends of the first edge B12-2 are connected to the second edges B12-3 and B12-4, respectively. The second edge B12-3 can be located on the side of the second edge B12-4 away from the display area AA. Multiple second pins 22 can be adjacent to the second edge B12-3 away from the display area AA, and multiple third pins 23 can be adjacent to the second edge B12-4 closer to the display area AA.

[0099] Figures 4A and 4B are schematic diagrams illustrating the connection of the multiple first pins and multiple second pins in Figure 3. In some examples, as shown in Figures 3, 4A, and 4B, the multiple first pins 21 in the first signal access area B11a can be electrically connected to the multiple second pins 22 in the second signal access area B12 via multiple first internal connection lines 31. The multiple first internal connection lines 31 can be located on the side of the multiple second pins 22 closer to the multiple third pins 23 in the second signal access area B12. The multiple first internal connection lines 31 can be ILB (Inner Lead Bonding) traces.

[0100] In some examples, multiple first internal connection lines 31 may extend outward from the first edge B12-1 (or B12-2) of the second signal access area B12. The first internal connection lines 31 may include: a first connection segment 311 extending along a second direction D2, a second connection segment 312 extending along a first direction D1, and a third connection segment 313. The first connection segment 311 may be connected between the second connection segment 312 and the third connection segment 313. The first connection segment 311 may extend outward from the second signal access area B12 along the second direction D2. The second connection segment 312 may be located in the second signal access area B12 and connected to at least one second pin 22. The third connection segment 313 may be connected to at least one first pin 21 and located on the side of the first signal access area B11a closer to the display area AA. For example, the first connection segment 311 may be a straight strip extending along the second direction D2, and the second connection segment 312 and the third connection segment 313 may be straight strips extending along the first direction D1.

[0101] In some examples, the width of the second connecting segment 312 (e.g., the length along the second direction D2) may be greater than or equal to the width of the first connecting segment 311 (e.g., the length along the first direction D1), and the width of the third connecting segment 313 (e.g., the length along the second direction D2) may be greater than or equal to the width of the first connecting segment 311.

[0102] In some examples, multiple second pins 22 within the second signal access area B12 can be arranged sequentially aligned along the second direction D2. The first internal connection line 31 connected to the second pin 22 near the first edge B12-1 within the second signal access area B12 can be located on the side of the first internal connection line 31 connected to the second pin 22 away from the first edge B12-1, away from the multiple third pins 23. The first pin 21 connected to the second pin 22 near the first edge B12-1 can be located on the side of the first pin 21 connected to the second pin 22 away from the first edge B12-1, near the first edge B12-1. In other words, the multiple first pins 21 and the multiple second pins 22 can be electrically connected in a near-to-near and far-to-far manner.

[0103] In some examples, multiple first internal interconnects 31 can be on the same layer, such as located in the first source / drain metal layer. At least one first pin 21 may include a stacked second sublayer and a first sublayer, with the first sublayer located on the side of the second sublayer away from the substrate. For example, the second sublayer may be located on the first gate metal layer, and the first sublayer may be located on the first source / drain metal layer. The first internal interconnect 31 and the first sublayer of the connected first pin 21 can be an integral structure. At least one second pin 22 may include a stacked fourth sublayer and a third sublayer (as shown in Figure 5, the third sublayer 22-1), with the third sublayer located on the side of the fourth sublayer away from the substrate. For example, the fourth sublayer may be located on the first gate metal layer, and the third sublayer may be located on the first source / drain metal layer. The first internal interconnect 31 and the third sublayer of the connected second pin 22 can be an integral structure. In this example, the resistivity of the source / drain metal layer material is less than the resistivity of the gate metal layer material. By placing multiple first internal interconnects in the source / drain metal layer, trace impedance can be reduced, ensuring signal transmission stability.

[0104] In some examples, as shown in Figure 4B, the first border region may also be provided with a border organic insulating layer 150. The orthographic projection of the border organic insulating layer 150 onto the substrate may at least partially overlap with the orthographic projections of the plurality of first internal connection lines 31 onto the substrate, but may not overlap with the orthographic projections of the plurality of first pins 21, the plurality of second pins 22, and the plurality of third pins 23 onto the substrate. For example, the orthographic projection of the border organic insulating layer 150 onto the substrate may cover the orthographic projection of the first connecting segment 311 of the plurality of first internal connection lines 31 onto the substrate, and may partially overlap with the orthographic projections of the second connecting segment 312 and the third connecting segment 313 onto the substrate.

[0105] In some examples, multiple first internal connection lines 31 are located in the first source / drain metal layer, and the border organic insulating layer 150 may be co-located with the first planarization layer. In other examples, the border organic insulating layer may be co-located with at least one of the first planarization layer, the second planarization layer, and the pixel definition layer.

[0106] Figure 5 is a partial cross-sectional schematic diagram of the second signal access region in at least one embodiment of this disclosure. Figure 5 illustrates the contact position between the driver chip and the second pin of the second signal access region. In some examples, as shown in Figure 5, the driver chip 20 may include a chip body 201 and chip pins 202. Chip pins 202 may protrude from the chip body 201. The thickness of chip pins 202 may be approximately 8 micrometers (µm) to 12 µm. Chip pins 202 may be electrically connected to the third sublayer 22-1 of the second pin 22 via an anisotropic conductive film (ACF) 190. The thickness of the anisotropic conductive film may be approximately 2 µm to 4 µm. The third sublayer 22-1 of the second pin 22 and the first internal connection line 31 may both be located in the first source / drain metal layer, and the frame organic insulating layer 150 may be in the same layer as the first planarization layer; for example, the thickness of the frame organic insulating layer 150 may be approximately 2 µm to 3 µm.

[0107] In some examples, the frame organic insulating layer 150 may cover the first connection segment 311 extending along the second direction D2 of the first internal connection line 31. A first distance H1, greater than 8.4 μm, may exist between the surface of the frame organic insulating layer 150 away from the substrate and the chip body 201 of the driver chip 20. The frame organic insulating layer 150 does not cover the second pin 22. A second distance H2, greater than 10 μm, may exist between the edge of the frame organic insulating layer 150 and the edge of the second pin 22 to ensure effective electrical connection between the second pin 22 and the chip pin 202.

[0108] This example uses a frame organic insulating layer to cover the first connection segment of the first internal connection line extending along the second direction. This prevents the first internal connection line from being broken by the driver chip during bonding or corroded during reliability testing. Furthermore, it ensures that the first internal connection line will not experience breakage or short circuits during the driver chip bonding process.

[0109] Figure 6 is a partially enlarged schematic diagram of the second signal access area in Figure 3. In some examples, as shown in Figures 3 and 6, the multiple third pins 23 within the second signal access area B12 may include multiple first data access pins 231 and multiple first control access pins 232. The multiple first control access pins 232 may be located on both sides of the multiple first data access pins 231 along the second direction D2. The first trace area B14 of the first frame area B1 may be provided with multiple data leads 53 and multiple control leads 54. The multiple data leads 53 may be connected to the multiple first data access pins 231. The multiple control leads 54 may be connected to the multiple first control access pins 232.

[0110] In some examples, as shown in Figure 3, multiple data leads 53 can be arranged in a fan-out routing pattern within the first routing area B14. These multiple data leads 53 can be electrically connected to multiple data lines within the display area AA, configured to provide data signals. In some examples, the first routing area B14 can also be equipped with multiple multiplexing circuits. The multiple data leads 53 can be connected to these multiple multiplexing circuits, which in turn can be connected to multiple data lines. A single multiplexing circuit can transmit one data signal provided by one data lead 53 to multiple data lines.

[0111] In some examples, the multiple data leads 53 may include multiple first data leads and multiple second data leads, which may be arranged at intervals along a second direction D2. The multiple first data leads may be located in a first gate metal layer, and the multiple second data leads may be located in a second gate metal layer. The orthographic projections of the multiple first data leads onto the substrate and the orthographic projections of the multiple second data leads onto the substrate may not overlap. In other examples, the multiple data leads may be a co-layer structure, for example, all of which may be located in either the first gate metal layer or the second gate metal layer.

[0112] In some examples, along the first direction D1, the multiple control leads 54 may be located on the side of the multiple data leads 53 away from the display area AA; along the second direction D2, the multiple control leads 54 may be located on both sides of the multiple data leads 53. For example, the multiple control leads 54 may be located in the gate metal layer, such as in the first gate metal layer.

[0113] In some examples, as shown in Figures 3 and 6, the first bezel region B1 may also be provided with multiple second internal connection lines 32. These multiple second internal connection lines 32 may be located on the side of the multiple second pins 22 away from the display area AA. The second internal connection lines 32 may be connected to multiple second pins 22 that transmit the same signal. For example, the second internal connection line 32 connected to the second pin near the first edge of the second bezel region B12 may be located on the side of the second internal connection line 32 connected to the second pin away from the first edge, away from the display area AA. In other words, the second internal connection lines connected to at least two second pins with a relatively large spacing may wrap around the second internal connection lines connected to at least two second pins with a relatively small spacing from the side away from the display area AA. In some examples, the multiple second internal connection lines 32 may be a co-layer structure, for example, located in the first gate metal layer.

[0114] In some examples, as shown in Figure 3, a set of first pins within the first signal access area B11a may include: a plurality of first signal access pins 211, at least one first power access pin 213, and at least one second power access pin 214. The plurality of first signal access pins 211 can be electrically connected to a plurality of second pins 22 within the second signal access area B12 via a plurality of first internal connection lines 31. The first power access pin 213 and the second power access pin 214 may be located on the side of the plurality of first signal access pins 211 away from the second signal access area B12. The second power access pin 214 may be located on the side of the first power access pin 213 away from the plurality of first signal access pins 211.

[0115] In some examples, as shown in Figure 3, the first frame region B1 may be provided with a first frame power line 51 and two second frame power lines 52a and 52b. The first frame power line 51 may be located between the two second frame power lines 52a and 52b along the second direction D2. The first frame power line 51 may be configured to connect to a high-potential power line of the display area AA, for example, to transmit a first power signal. The second frame power lines 52a may extend from the first frame region B1 to the third frame region B3, and the second frame power lines 52b may extend from the first frame region B1 to the fourth frame region B4. For example, the second frame power lines 52a and 52b may be connected within the second frame region B2 to form a single structure. The second frame power lines 52a and 52b may be configured to be electrically connected to the cathode of the light-emitting element of the display area AA, for example, to transmit a second power signal, which may be less than the first power signal.

[0116] In some examples, as shown in FIG3, the first frame power line 51 may include: a first power body extending along a second direction D2 and a first power extension and a second power extension extending along a first direction D1. The first power extension and the second power extension may be connected to both ends of the first power body, respectively. The first power extension may be electrically connected to at least one first power access pin 213 in the first signal access area B11a, and the second power extension may be electrically connected to at least one first power access pin 213 in the first signal access area B11b. For example, the first frame power line 51 may be located in the first source-drain metal layer, and the first frame power line 51 may be integrally formed with the first sublayer of the first power access pin 213 located in the first source-drain metal layer.

[0117] In some examples, the second frame power line 52a can be electrically connected to at least one second power access pin 214 within the first signal access area B11a, and the second frame power line 52b can be electrically connected to at least one second power access pin 214 within the first signal access area B11b. For example, the second frame power lines 52a and 52b can be on the same layer, such as located in the first source / drain metal layer. The second frame power lines can be integrally formed with the first sublayer of the connected second power access pin 214.

[0118] In some examples, as shown in Figure 3, at least one gate driving circuit 61 may be provided in the surrounding area. The gate driving circuit 61 may include n cascaded shift register circuits (e.g., a first-stage shift register circuit GOA1 and an i-th-stage shift register circuit GOAi). Here, n is an integer greater than 0, and i is an integer not equal to 1 or n. The gate driving circuit 61 may be located in the third border region B3 and the fourth border region B4. For example, the first-stage shift register circuit GOA1 (or the nth-stage shift register circuit) of the gate driving circuit 61 may be located in the corner region connected to the first border region B1.

[0119] In some examples, multiple control signal lines 55 can be provided in the surrounding area. Figure 3 illustrates one control signal line 55 in the third frame area B3 and one control signal line 55 in the fourth frame area B4 as examples. The control signal lines 55 can extend along the edge of the display area AA within the third frame area B3 (or the fourth frame area B4). The shift register circuit of the gate drive circuit 61 can be connected to the control signal lines 55. The multiple control signal lines 55 can, for example, provide clock signals, voltage signals, etc., to the gate drive circuit. The multiple control signal lines 55 can be electrically connected to multiple control leads 54 provided in the first frame area B1. The connection position of the control lead 54 and the corresponding control signal line 55 can be adjacent to the i-th stage shift register electrode GOAi. In other words, the control lead does not need to be connected to the control signal line from the location of the first stage shift register circuit GOA1 or the last stage shift register circuit.

[0120] In some examples, as shown in Figure 3, the first-stage shift register circuit GOA1 can be located at the starting point of the connection between the corner region of the first border region B1 and the third border region B3. The control lead 54 can extend along the first direction D1 towards the middle of the corner region, and the control lead 54 can be electrically connected to the control signal line 55 that intersects with it along the first direction D1, without needing to wind along the second direction D2 to connect to the control signal line at the first-stage shift register circuit GOA1. In this way, the routing space in the corner region can be greatly saved, which is beneficial to the narrowing of the third and fourth border regions.

[0121] In some examples, as shown in Figure 3, the second frame power line 52a may have a notch 520 at the corner of the third frame region B3. The second frame power line 52a is recessed from the edge near the display area AA towards the side away from the display area AA to form the notch 520. This notch 520 can correspond to multiple control leads 54 extending to a position where they are electrically connected to multiple control signal lines 55. This example, by providing a notch facing the display area AA on the second frame power line, facilitates the provision of wiring space for the electrical connection of multiple control leads 54 and multiple control signal lines 55.

[0122] In some examples, as shown in Figure 3, the first border region B1 may also be provided with multiple electrostatic discharge circuits 62. The multiple electrostatic discharge circuits 62 can be electrically connected to multiple control leads 54 to provide electrostatic discharge paths. The multiple electrostatic discharge circuits 62 can be located on the side of the multiple control leads 54 away from the display area AA. For example, the multiple electrostatic discharge circuits 62 can be located in the first direction D1 between the multiple control leads 54 and the multiple first internal connection lines 31.

[0123] In some examples, as shown in Figure 3, the first border region B1 may further include two test signal access regions B13a and B13b. Test signal access region B13a may be located along the first direction D1 on the side of the first signal access region B11a closer to the display area AA, and test signal access region B13b may be located along the first direction D1 on the side of the first signal access region B11b closer to the display area AA. Test signal access region B13a and the first signal access region B11a may be offset along the second direction D2, and test signal access region B13b and the first signal access region B11b may be offset along the second direction D2. The distance between test signal access region B13a and the second signal access region B12 along the second direction D2 may be greater than the distance between the first signal access region B11a and the second signal access region B12 along the second direction D2.

[0124] In some examples, as shown in Figure 1, the width of the first border region B1 (i.e., the length along the second direction D2) can be L1, the width of the third border region B3 (i.e., the length along the second direction D2) can be L2, and the width of the fourth border region B4 (i.e., the length along the second direction D2) can be L3. The width L2 of the third border region B3 is limited by the circuit structure set within the third border region B3, and the width L3 of the fourth border region B4 is limited by the circuit structure set within the fourth border region B4. Moreover, the widths L2 of the third border region B3 and L3 of the fourth border region B4 are closely related to the width L1 of the first border region B1. Taking a small-sized display substrate as an example, since the width L1 of the first border region B1 is much larger than the width of the display region AA (i.e., the maximum length along the second direction D2), it is necessary to widen the widths of the third border region B3 and the fourth border region B4. Therefore, reducing the width of the first border region B1 can help reduce the widths of the third border region B3 and the fourth border region B4, thereby facilitating the achievement of extremely narrow bezels. This example reduces the width of the first border area by adjusting the position of the test signal access area to achieve sharing between the test pin and the first pin.

[0125] Figure 7 is a schematic diagram of the first signal access area B11a and the test signal access area B13a in Figure 3. In some examples, as shown in Figures 3 and 7, the first signal access area B11a is provided with a plurality of first pins 21 arranged sequentially along the second direction D2. The plurality of first pins 21 may include a plurality of first type pins and a plurality of second type pins. The plurality of second type pins may include a plurality of first signal access pins 211. In this example, the number of first type pins may be two, and the two first type pins may include a first power access pin 213 and a second power access pin 314. The plurality of first type pins may be located along the second direction D2 on the side of the plurality of second type pins near the edge B0 of the display substrate. The plurality of first signal access pins 211 may be electrically connected to a plurality of second pins 22 in the second signal access area B12 through a plurality of first internal connection lines 31.

[0126] In some examples, the test signal access area B13a is provided with a set of test pins, which may include a plurality of test pins 25 arranged sequentially along the second direction D2. The plurality of test pins 25 may be configured to contact test probes of a test device (e.g., a flexible circuit board) during electronic testing (ET) to obtain signals from the test probes. The plurality of test pins 25 may be connected to a plurality of control leads 54, configured to provide test signals to the gate drive circuitry during electronic testing.

[0127] In some examples, the control lead 54 may include a first lead 541, a second lead 542, and a third lead 543 connected sequentially. The first lead 541 may extend at least along a second direction D2 and be electrically connected to at least one first control access pin 232 within the second signal access region B12. The second lead 542 may extend along a first direction D1 and connect between the first lead 541 and the third lead 543. The third lead 543 may extend first along the second direction D2 and then along the first direction D1 to connect to a control signal line within a corner region. In some examples, the first lead 541 and the third lead 543 may be in the same layer, for example, located in the first gate metal layer; the second lead 542 may be located on the side of the first lead 541 and the third lead 543 away from the substrate, for example, located in the first source / drain metal layer.

[0128] In some examples, the multiple test pins 25 of the test signal access area B13a may include multiple first test pins 251 and multiple second test pins 252. The multiple first test pins 251 may be located on the side of the multiple second test pins 252 closer to the first signal access area B11a. In this example, the number of first test pins 251 may be two.

[0129] In some examples, the two first test pins 251 in the test signal access area B13a and the two first type pins (including the first power access pin 213 and the second power access pin 214) in the first signal access area B11a can be aligned one-to-one along the first direction D1. The first power access pin 213 and the first test pin 251 aligned along the first direction D1 can be a single structure, and the second power access pin 214 and the first test pin 251 aligned along the first direction D1 can be a single structure. For example, the first pin 21 may include: a stacked second sublayer and a first sublayer, the second sublayer may be located on the first gate metal layer, and the first sublayer may be located on the first source-drain metal layer; the test pin 25 may include: a stacked sixth sublayer and a fifth sublayer, the sixth sublayer may be located on the first gate metal layer, and the fifth sublayer may be located on the first source-drain metal layer. The second sublayer of the first power access pin 213 and the sixth sublayer of the first test pin 251 aligned along the first direction D1 can be a single integrated structure. The orthogonal projection of this integrated structure onto the substrate can be a straight strip extending along the first direction D1. The first sublayer of the first power access pin 213, the fifth sublayer of the first test pin 251 aligned along the first direction D1, and the first frame power line 51 can also be a single integrated structure. The second sublayer of the second power access pin 214 and the sixth sublayer of the first test pin 251 aligned along the first direction D1 can also be a single integrated structure. The first sublayer of the second power access pin 214, the fifth sublayer of the first test pin 251 aligned along the first direction D1, and the second frame power line 52a can also be a single integrated structure.

[0130] In some examples, the first power input pin 213 can provide a first power signal during both electronic testing and normal operation, and the second power input pin 214 can provide a second power signal during both electronic testing and normal operation.

[0131] In this example, the test signal access area can be moved closer to the display area relative to the first signal access area. Multiple first-type pins within the first signal access area can extend along a first direction D1 into the test signal access area, forming multiple first test pins 251 aligned with multiple second test pins along a second direction D2, thereby enabling the sharing of test pins and first pins.

[0132] In some examples, the first signal access pin 211 within the first signal access region B11a may have a first width (i.e., the length along the second direction D2) W1, and adjacent first signal access pins 211 may have a first spacing SP1. The ratio between the first width W1 and the first spacing SP1 may be 1. For example, the first width W1 and the first spacing SP1 may be approximately 45 μm.

[0133] In some examples, the second test pin 252 within the test signal access area B13a may have a second width W2, and there may be a second spacing SP2 between adjacent second test pins 252. The ratio between the second width W2 and the second spacing SP2 may be 3 / 2; for example, the first width W2 may be approximately 120 μm, and the second spacing SP2 may be approximately 80 μm.

[0134] In some examples, a first-type pin (e.g., the second power access pin 214) may have a third width W3, and a third spacing SP3 may exist between adjacent first-type pins (e.g., the first power access pin 213 and the second power access pin 214). The third width W3 may be greater than or equal to the second width W2, and the third spacing SP3 may be greater than or equal to the second spacing SP2. The width of the first power access pin 213 is similar to the width of the second power access pin 214. In this example, the width and spacing of the first power access pin 213 and the second power access pin 214 meet the width and spacing requirements of the test pins, avoiding short circuits on the test board during electronic testing and ensuring the shared functionality between the first pins and the test pins.

[0135] This example, by adjusting the position of the test signal access area relative to the first signal access area, allows the first and second power signals to share pins during both the testing and normal operation phases. In other words, the first and second power access pins can be multiplexed as the first test pin. This reduces the number of pins arranged side-by-side along the second direction D2, thereby reducing the width L1 of the first bezel area and facilitating bezel narrowing. For example, the display substrate of this example can be applied to rigid, small-to-medium-sized display products, achieving an extremely narrow bezel.

[0136] Figure 8 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure. Figure 9 is a partial schematic diagram of the first border region in Figure 8. In some examples, as shown in Figures 8 and 9, the first border region B1 may include: a first signal access region B11, and two test signal access regions B13a and B13b. The two test signal access regions B13a and B13b may be located on opposite sides of the first signal access region B11 along the second direction D2. The two test signal access regions B13a and B13b, and the first signal access region B11 may be aligned along the second direction D2.

[0137] In some examples, the plurality of first pins 21 within the first signal access region B11 may include: a plurality of second data access pins, a plurality of second control access pins 212, a plurality of first power access pins 213, and a plurality of second power access pins 214. The plurality of second control access pins 212 may be located on both sides of the plurality of second data access pins along the second direction D2, the plurality of first power access pins 213 may be located on both sides of the plurality of second control access pins 212 along the second direction D2, and the plurality of second power access pins 214 may be located on both sides of the plurality of first power access pins 213 along the second direction D2. In this example, the plurality of second-type pins among the plurality of first pins may include: a plurality of second data access pins and a plurality of second control access pins 212, and the plurality of first-type pins may include: a plurality of first power access pins 213 and a plurality of second power access pins 214.

[0138] In some examples, multiple second data access pins can be electrically connected to multiple data lines in the display area via multiple data leads, or multiple second data access pins can be connected to multiple multiplexing circuits via multiple data leads, and multiple multiplexing circuits can be electrically connected to multiple data lines in the display area.

[0139] In some examples, multiple second control access pins 212 may be electrically connected to multiple control leads 54. The multiple control leads 54 may extend to be electrically connected to multiple control signal lines and gate drive circuitry within a third bezel region (or a fourth bezel region).

[0140] In some examples, multiple first power access pins 213 and multiple second power access pins 214 can be multipled as multiple first test pins. Multiple second power access pins 213 can be adjacent to the test signal access area B13 along the second direction D2. Multiple first power access pins 213 can be electrically connected to the first frame power line 51 and configured to provide a first power signal; multiple second power access pins 214 can be electrically connected to the second frame power line 52a and configured to provide a second power signal.

[0141] In some examples, the first pin 21 may include a stacked and interconnected second sublayer and a first sublayer, with the first sublayer located on the side of the second sublayer away from the substrate. Taking the first power access pin 213 as an example, the second sublayers of adjacent first power access pins 213 can be independently configured, and the width of each second sublayer along the second direction D2 can be approximately 15µm, and the spacing between the second sublayers of adjacent first power access pins can be approximately 10µm. The first sublayers of adjacent first power access pins 213 and the first border power line 51 can be an integral structure. For example, the first sublayers of adjacent first power access pins 213 can be an integral structure. In other examples, the first sublayers of adjacent first power access pins 213 can be independently configured and integrally configured with the first border power line 51. The second sublayer can be located on the first gate metal layer, and the first sublayer can be located on the first source / drain metal layer.

[0142] In some examples, the test signal access area B13a is provided with a set of test pins, which may include multiple second test pins 252. The multiple second test pins 252 may be electrically connected to multiple control leads 54. The multiple second test pins 252 may be adjacent to the second power access pin 214 in the second direction D2.

[0143] In this example, multiple first power access pins 213 are arranged adjacently, so that the total width of the multiple adjacent first power access pins 213 along the second direction D2 can be greater than or equal to the width of a single second test pin. This avoids the situation of short circuit in the test circuit board during electronic testing and ensures the sharing effect between the first pin and the test pin.

[0144] This example uses a portion of the first pins in the first signal access area as test pins. For example, the first power access pin and the second power access pin can be multiplexed as the first test pins. This reduces the number of pins arranged side-by-side along the second direction D2, and reduces the width of the first border area, thus facilitating a narrower border.

[0145] Figure 10 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure. Figure 11 is a partial schematic diagram of the first border region in Figure 10. Figure 11 is a pin diagram of the first signal access region in Figure 10. In some examples, as shown in Figures 10 and 11, the first border region B1 may include: a first signal access region B11 and a second signal access region B12. The first signal access region B11 may be located along a first direction D1 on the side of the second signal access region B12 away from the display region AA.

[0146] In some examples, the first signal access area B11 is provided with multiple first pins configured to be bonded to an external circuit board. The second signal access area B12 may be provided with multiple second pins and multiple third pins configured to be bonded to a driver chip. The multiple second pins in the second signal access area B12 can be electrically connected to the multiple first pins via multiple third internal connection lines. The multiple third internal connection lines may be located on the side of the multiple second pins away from the display area AA.

[0147] In some examples, as shown in Figure 11, multiple first pins within the first signal access area B11 can be aligned along the second direction D2. The multiple first pins may include: a first group of first-type pins 21-1a, a second group of first-type pins 21-1b, and a group of second-type pins 21-2. The first group of first-type pins 21-1a and the second group of first-type pins 21-1a can be located on either side of the group of second-type pins 21-2 along the second direction D2. The first group of first-type pins 21-1a and the second group of first-type pins 21-1b can be multiplexed as test pins, configured to provide corresponding signals during the electronic testing phase. The group of second-type pins 21-2 can be electrically connected to multiple second pins within the second signal access area B12 via multiple third internal connection lines.

[0148] In some examples, the first group of first-type pins 21-1a may include a first power access pin 213, a second power access pin 214, and a plurality of second control access pins 212. The second power access pin 214, the first power access pin 213, and the plurality of second control access pins 212 may be arranged along the second direction D2 in a direction away from the edge of the display substrate. The pin arrangement in the second group of first-type pins 21-1b is similar, and therefore will not be described again here. In other examples, the first power access pin 213, the second power access pin 214, and the plurality of second control access pins 212 may be arranged along the second direction D2 in a direction away from the edge of the display substrate.

[0149] In some examples, the width (length along the second direction D2) of the first pin within the first group of first type pins 21-1a can be greater than the width of the first pin within the second group of second type pins 21-2. The width of the first power access pin 213 and the second power access pin 214 can be greater than the width of the second control access pin 212. The spacing between adjacent first pins within the first group of first type pins 21-1a can be greater than the spacing between adjacent first pins within the second group of second type pins 21-2. This example, by increasing the width of the first pins within the two groups of first type pins and the spacing between adjacent pins, can avoid reliability corrosion between adjacent pins and achieve the effect of reusing them as test pins.

[0150] In this example, the first type of pin within the first signal access area can be reused as a test pin, thus eliminating the need for test pin configuration. This reduces the number of pins arranged side-by-side along the second direction D2, thereby reducing the width of the first border area and facilitating a narrower border.

[0151] Figure 12 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure. Figure 13 is a partial schematic diagram of the first border region in Figure 12. In some examples, as shown in Figures 12 and 13, the first border region B1 may include a first signal access region B11. The first signal access region B11 may include a plurality of first pins 21. The plurality of first pins 21 may include at least one set of first type pins (e.g., a set of first type pins 21-1a) and a plurality of second type pins. The plurality of second type pins may include at least one first set of second type pins 21-2a and at least one second set of second type pins 21-2b. A set of first type pins 21-1a may be located along the second direction D2 between the first set of second type pins 21-2a and the second set of second type pins 21-2b.

[0152] In some examples, a set of first-type pins 21-1a can be multiplexed as test pins for transmitting test signals. The first set of second-type pins 21-2a may include: multiple second control access pins 212, at least one first power access pin 213, and at least one second power access pin 214. The second power access pin 214 may be located on the side of the first power access pin 213 away from the multiple second control access pins 212, which may be adjacent to the set of first-type pins 21-1a. The first power access pin 213 may be electrically connected to the first frame power line 51, and the second power access pin 214 may be electrically connected to the second frame power line 52a. The multiple second control access pins 212 may be electrically connected to multiple control leads 54. The second set of second-type pins 21-2b may include multiple second data access pins 215, which may be electrically connected to multiple data leads 53.

[0153] In this example, multiple second control access pins, first power access pins, and second power access pins within the first signal access area B11 are moved toward the edge of the display substrate. Multiple first-type pins are arranged between multiple second data access pins and multiple second control access pins within the first signal access area B11. These multiple first-type pins can be multiplexed as test pins and configured to transmit test signals.

[0154] Figure 14 is a schematic diagram showing that no multiple first-type access pins are provided between the second data access pins and the second control access pins of the first signal access area. In some examples, as shown in Figures 13 and 14, by moving the multiple second control access pins 212 away from the multiple second data access pins 215, the extension length of the multiple control leads 54 can be shortened, thereby freeing up space for the circuit structure of the third frame area. This also helps to shorten the extension length of the multiple data leads 53 along the first direction D1, thereby reducing the length of the first frame area B1 along the first direction D1. For example, the length L4 of the first frame area B1 along the first direction D1 shown in Figure 13 can be less than the length L5 of the first frame area B1 along the first direction D1 shown in Figure 14.

[0155] Figure 15 is a schematic diagram of the cutting of a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 15, the first border region B1 may include a first signal access region B11 and test signal access regions B13a and B13b located on both sides of the first signal access region B11 along the second direction D2. The test signal access region B13a has multiple test pins, including a first set of test pins located between the first cutting line CL1 and the second cutting line CL2, and a second set of test pins located on the side of the second cutting line CL2 closer to the display region AA. Before electronic testing of the display substrate, a coarse cut can be made along the first cutting line CL1, preserving the entire test signal access regions B13a and B13b without affecting the electronic testing process. After electronic testing, a fine cut can be made along the second cutting line CL2 to form the edge of the display substrate, cutting off the first set of test pins within the test signal access region, thereby reducing the width of the first border region B1 along the second direction D2, which is beneficial for border narrowing. In this example, after cutting, the number of test signals provided by the test pins remaining in the first border region is less than the number of test signals required by the display substrate. Further descriptions of the display substrate in this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0156] This embodiment also provides a display substrate, including: a substrate and a plurality of first pins disposed on the substrate. The substrate includes a display area and a first border area located on one side of the display area along a first direction, the first border area including: at least one first signal access area. The plurality of first pins are located in the at least one first signal access area and configured to be bonded to an external circuit board. The plurality of first pins include: a plurality of first type pins and a plurality of second type pins, the plurality of first type pins being multiplexed as test pins.

[0157] The display substrate provided in this embodiment reduces the number of pins arranged side by side along the second direction in the first frame area by setting multiple first-type pins as test pins, thereby reducing the length of the first frame area of ​​the display substrate along the second direction, which is beneficial to achieving an extremely narrow bezel.

[0158] In some exemplary embodiments, the display substrate may further include at least one set of test pins located in the first bezel region, the at least one set of test pins being located along the first direction on the side of the at least one first signal access region near the display region, and offset from the at least one first signal access region along the second direction. This example, by setting at least one set of test pins offset from the first signal access region along the second direction, can help reduce the length of the first bezel region of the display substrate along the second direction, thereby facilitating the achievement of a narrow bezel.

[0159] In some exemplary embodiments, the at least one set of test pins includes: a plurality of first test pins and a plurality of second test pins, wherein the plurality of first test pins are located on the side of the plurality of second test pins closer to the first signal access area; the plurality of first type pins and the plurality of first test pins are aligned one-to-one along the first direction, and the first type pins and first test pins aligned along the first direction are of a single integrated structure. This example configuration can effectively achieve the multiplexing of first pins and test pins.

[0160] In some exemplary embodiments, the display substrate may further include: at least one set of test pins located in the first bezel region, the at least one set of test pins being aligned with a plurality of first pins in the at least one first signal access region along the second direction, and the plurality of first type pins being adjacent to the at least one set of test pins in the second direction. This example reduces the length of the first bezel region of the display substrate along the second direction by configuring a portion of the first pins as test pins.

[0161] In some exemplary embodiments, the plurality of second-type pins includes at least one first group of second-type pins and at least one second group of second-type pins, the plurality of first-type pins being located between the at least one first group of second-type pins and the at least one second group of second-type pins, the first group of second-type pins being configured to transmit control signals, and the second group of second-type pins being configured to transmit data signals. This example reduces the length of the first bezel region of the display substrate along the second direction by placing the plurality of first-type pins multiplexed as test pins in the middle of the plurality of second-type pins. Furthermore, by increasing the distance between the first group of second-type pins and the second group of second-type pins, the length of the traces connected to the second-type pins along the first direction can be reduced, thereby facilitating a reduction in the length of the first bezel region of the display substrate along the first direction.

[0162] In some exemplary embodiments, the width of at least one of the plurality of first type pins is greater than the width of at least one of the plurality of second type pins, and the spacing between adjacent first type pins is greater than the spacing between adjacent second type pins.

[0163] In some exemplary embodiments, the plurality of first-type pins includes at least one of the following: a plurality of control signal access pins, a plurality of first power access pins, and a plurality of second power access pins.

[0164] The remaining descriptions of the display substrate in this embodiment can be found in the descriptions of the foregoing embodiments, and therefore will not be repeated here.

[0165] Figure 16 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 16, the display device 91 may include a display substrate 910. The display substrate 910 may be an OLED display substrate. The display device 91 may be any product or component with display function, such as an OLED display device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. However, this embodiment is not limited thereto.

[0166] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0167] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A display substrate, comprising: The substrate includes: a display area and a peripheral area located on at least one side of the display area, the peripheral area including a first border area located on one side of the display area along a first direction, the first border area including: at least one first signal access area and at least one second signal access area; the at least one first signal access area is located on at least one side of the at least one second signal access area along a second direction, the second direction intersecting the first direction; Multiple first pins are located in the at least one first signal access area; A plurality of second pins and a plurality of third pins are located in the at least one second signal access area, wherein the plurality of second pins are located along the first direction on the side of the plurality of third pins away from the display area; Multiple first internal connection lines are located in the first border area, and at least one of the multiple first pins is connected to at least one of the multiple second pins through at least one of the multiple first internal connection lines; the multiple first internal connection lines are located on the side of the multiple second pins closer to the multiple third pins in the first direction.

2. The display substrate according to claim 1, wherein, The at least one second signal access area has a first edge extending along the first direction, and a plurality of second pins within the at least one second signal access area are arranged sequentially along the second direction and move away from the first edge in sequence, and the corresponding first internal connection lines are sequentially close to the plurality of third pins along the first direction.

3. The display substrate according to claim 2, wherein, The first pin connected to the second pin closest to the first edge of the plurality of second pins is located on the side of the first pin connected to the second pin furthest from the first edge that is closer to the first edge.

4. The display substrate according to claim 1, wherein, The at least one first internal connection line includes: a first connection segment extending along the second direction, a second connection segment extending along the first direction, and a third connection segment; the first connection segment is connected between the second connection segment and the third connection segment, and extends outward from the second signal access area along the second direction; the second connection segment is located in the second signal access area and is connected to the at least one second pin; the third connection segment is connected to the at least one first pin and is located on the side of the at least one first pin near the display area.

5. The display substrate according to claim 1, wherein, The multiple first internal connection lines are of the same layer structure.

6. The display substrate according to claim 5, wherein, In a direction perpendicular to the display substrate, the display substrate includes: a gate metal layer and a source / drain metal layer disposed on the substrate, the source / drain metal layer being located on the side of the gate metal layer away from the substrate; and the plurality of first internal interconnect lines being located on the source / drain metal layer.

7. The display substrate according to claim 6, further comprising: A frame organic insulating layer located on the side of the source / drain metal layer away from the substrate and in the first frame region, wherein the orthographic projection of the frame organic insulating layer on the substrate at least partially overlaps with the orthographic projection of the plurality of first internal connection lines on the substrate, and does not overlap with the orthographic projection of the plurality of first pins, the plurality of second pins and the plurality of third pins on the substrate.

8. The display substrate according to claim 1, further comprising: The gate drive circuit, multiple control signal lines, and multiple control leads are located in the surrounding area; The multiple control signal lines are connected to the gate drive circuit; The multiple control leads are connected to a portion of the third pins among the multiple third pins of the second signal access area; The gate drive circuit includes n shift register circuits that are cascaded together. The connection positions of the multiple control leads and the multiple control signal lines are adjacent to the i-th stage shift register circuit, where n is an integer greater than 0 and i is an integer not equal to 1 and n.

9. The display substrate according to any one of claims 1 to 8, wherein, The plurality of first pins in the at least one first signal access area include: a plurality of first type pins and a plurality of second type pins; the plurality of first type pins are multiplexed as test pins.

10. The display substrate according to claim 9, further comprising: At least one set of test pins is located in the first frame area, the at least one set of test pins is located on the side of the at least one first signal access area close to the display area along the first direction, and is offset from the at least one first signal access area along the second direction.

11. The display substrate according to claim 10, wherein, The at least one set of test pins includes: a plurality of first test pins and a plurality of second test pins, wherein the plurality of first test pins are located on the side of the plurality of second test pins that is close to the first signal access area; The plurality of first type pins and the plurality of first test pins are aligned one by one along the first direction, and the first type pins and the first test pins aligned along the first direction are an integral structure.

12. The display substrate according to claim 9, further comprising: At least one set of test pins located in the first frame region, the at least one set of test pins being aligned with a plurality of first pins in the at least one first signal access region along the second direction, the plurality of first type pins being adjacent to the at least one set of test pins in the second direction.

13. The display substrate according to claim 9, wherein, The width of at least one of the plurality of first-type pins is greater than the width of at least one of the plurality of second-type pins, and the spacing between adjacent first-type pins is greater than the spacing between adjacent second-type pins.

14. The display substrate according to claim 9, wherein, The plurality of first-type pins includes at least one of the following: a plurality of control signal access pins, a plurality of first power supply access pins, and a plurality of second power supply access pins.

15. The display substrate according to claim 1, further comprising: At least one set of test pins located in the first frame area, wherein the number of test signals provided by the at least one set of test pins is less than the number of test signals required by the display substrate.

16. A display device comprising a display substrate as claimed in any one of claims 1 to 15.

17. A display substrate, comprising: The substrate includes a display area and a first border area located on one side of the display area along a first direction, the first border area including at least one first signal access area; Multiple first pins, located in the at least one first signal access area, are configured to be bonded to an external circuit board; The plurality of first pins includes: a plurality of first type pins and a plurality of second type pins, wherein the plurality of first type pins are multiplexed as test pins.

18. The display substrate according to claim 17, further comprising: At least one set of test pins is located in the first frame area, the at least one set of test pins is located along the first direction on the side of the at least one first signal access area close to the display area, and is offset from the at least one first signal access area along the second direction, the second direction intersecting the first direction.

19. The display substrate according to claim 18, wherein, The at least one set of test pins includes: a plurality of first test pins and a plurality of second test pins, wherein the plurality of first test pins are located on the side of the plurality of second test pins that is close to the first signal access area; The plurality of first type pins and the plurality of first test pins are aligned one by one along the first direction, and the first type pins and the first test pins aligned along the first direction are an integral structure.

20. The display substrate according to claim 17, further comprising: At least one set of test pins located in the first frame area, the at least one set of test pins being aligned with a plurality of first pins in the at least one first signal access area along a second direction, the plurality of first type pins being adjacent to the at least one set of test pins in the second direction, the second direction intersecting the first direction.

21. The display substrate according to claim 17, wherein, The plurality of second-type pins includes: at least one first group of second-type pins and at least one second group of second-type pins, wherein the plurality of first-type pins are located between the at least one first group of second-type pins and the at least one second group of second-type pins, wherein the first group of second-type pins is configured to transmit control signals and the second group of second-type pins is configured to transmit data signals.

22. The display substrate according to claim 17, wherein, The width of at least one of the plurality of first-type pins is greater than the width of at least one of the plurality of second-type pins, and the spacing between adjacent first-type pins is greater than the spacing between adjacent second-type pins.

23. The display substrate according to claim 17, wherein, The plurality of first-type pins includes at least one of the following: a plurality of control signal access pins, a plurality of first power supply access pins, and a plurality of second power supply access pins.

Images