Growth method for silicon carbide epitaxial layer, silicon carbide epitaxial layer grown on basis of growth method, and silicon carbide crystal
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- MEISHAN BOYA ADVANCED MATERIALS CO LTD
- Filing Date
- 2025-01-15
- Publication Date
- 2026-07-23
Smart Images
Figure CN2025072445_23072026_PF_FP_ABST
Abstract
Description
Method for growing silicon carbide epitaxial layer, silicon carbide epitaxial layer and silicon carbide crystal grown based on the method TECHNICAL FIELD
[0001] The present specification relates to the field of artificial crystal growth, and in particular, to a method for growing silicon carbide epitaxial layer, silicon carbide epitaxial layer and silicon carbide crystal grown based on the method. BACKGROUND
[0002] Due to excellent performance such as wide band gap, high breakdown electric field, high saturated electron drift velocity and high thermal conductivity, semiconductor material silicon carbide (SiC) crystal has attracted extensive attention. However, the silicon carbide substrate used for growing silicon carbide crystal often has some microscopic defects, such as threading screw dislocation (TSD), threading edge dislocation (TED), base plane dislocation (BPD) and stacking fault (SF), etc. These defects can multiply to the epitaxial layer in the epitaxial process, affecting the quality of the final silicon carbide crystal and the performance of the corresponding device. Among the aforementioned defects, stacking fault is a planar defect, which is easily formed in the epitaxial and crystal growth process of silicon carbide crystal. Reducing the formation of stacking fault is of great significance to improve the yield and reliability of silicon carbide crystal.
[0003] Therefore, it is necessary to provide a method for growing silicon carbide epitaxial layer, silicon carbide epitaxial layer, and silicon carbide crystal grown based on the method, so as to reduce the microscopic defects in the epitaxial and crystal growth process of silicon carbide crystal, so that the generated silicon carbide epitaxial layer and silicon carbide crystal have few defects, high quality and stable comprehensive performance. SUMMARY
[0004] One or more embodiments of the present specification provide a method for growing silicon carbide epitaxial layer. The method comprises: performing first in-situ etching on a silicon face of a silicon carbide substrate using a first hydrogen gas flow to generate a first treated substrate, the first hydrogen gas flow having a first flow rate; growing a first buffer layer on the silicon face of the first treated substrate; performing second in-situ etching on the first buffer layer using a second hydrogen gas flow to generate a first treated buffer layer, the second hydrogen gas flow having a second flow rate; growing a first epitaxial layer on the first treated buffer layer at a first rate; and growing a second epitaxial layer on the first epitaxial layer at a second rate.
[0005] In some embodiments, the second flow rate is lower than the first flow rate.
[0006] In some embodiments, the first flow rate is greater than or equal to 80 SLM and less than or equal to 150 SLM.
[0007] In some embodiments, the second flow rate is greater than or equal to 30 SLM and less than 80 SLM.
[0008] In some embodiments, the first buffer layer has a thickness of 0.3 μm to 2 μm.
[0009] In some embodiments, the first buffer layer has a thickness of 0.8 μm to 1.5 μm.
[0010] In some embodiments, the second rate is greater than the first rate.
[0011] In some embodiments, the first rate is greater than or equal to 20 μm / h and less than or equal to 30 μm / h.
[0012] In some embodiments, the second rate is greater than or equal to 60 μm / h and less than or equal to 100 μm / h.
[0013] In some embodiments, the method further comprises: growing a second buffer layer on the first post-treatment buffer layer; performing a third in-situ etching on the second buffer layer using a third hydrogen gas flow to generate a second post-treatment buffer layer, the third hydrogen gas flow having a third flow rate; and growing a first epitaxial layer on the second post-treatment buffer layer at the first rate.
[0014] In some embodiments, the third flow rate is lower than the second flow rate.
[0015] In some embodiments, the method further comprises: growing a third epitaxial layer on the second epitaxial layer at a third rate.
[0016] In some embodiments, the third rate is greater than the second rate.
[0017] One or more embodiments of the present specification provide a silicon carbide epitaxial layer. The silicon carbide epitaxial layer is grown using the method for growing a silicon carbide epitaxial layer described in embodiments of the present specification.
[0018] One or more embodiments of the present specification provide a silicon carbide crystal. The silicon carbide crystal is grown on a silicon carbide epitaxial layer grown using the method for growing a silicon carbide epitaxial layer described in embodiments of the present specification by a physical vapor transport method. BRIEF DESCRIPTION OF DRAWINGS
[0019] The present specification will be further described in the manner of exemplary embodiments, which will be described in detail with reference to the accompanying drawings. These embodiments are not limiting, and in these embodiments, the same reference numbers represent the same structures, in which:
[0020] FIG. 1 is a flowchart of an exemplary method for growing a silicon carbide epitaxial layer according to some embodiments of the present specification;
[0021] FIG. 2 is a schematic diagram of an exemplary silicon carbide crystal structure, according to some embodiments of the present specification;
[0022] FIGS. 3A-3C are surface defect test maps of silicon carbide epitaxial layers;
[0023] FIG. 4 is a flow diagram of a method of growing an exemplary silicon carbide epitaxial layer, according to some embodiments of the present specification;
[0024] FIG. 5 is a schematic diagram of an exemplary silicon carbide crystal structure, according to some embodiments of the present specification;
[0025] FIG. 6 is a schematic diagram of a growth system of an exemplary silicon carbide epitaxial layer, according to some embodiments of the present specification. DETAILED DESCRIPTION
[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present specification, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some examples or embodiments of the present specification, and for those skilled in the art, the present specification can also be applied to other similar scenarios without creative labor. Unless it is clear from the language context or otherwise stated, the same reference numbers in the drawings represent the same structures or operations.
[0027] It should be understood that the "system", "device", "unit" and / or "module" used herein is a method for distinguishing different components, elements, parts, sections or assemblies at different levels. However, if other words can achieve the same purpose, the words can be replaced by other expressions.
[0028] As shown in the specification and claims, unless the context clearly indicates otherwise, the words "one", "an", "a", and / or "the" do not mean to specify a single number, but also include a plurality. Generally speaking, the terms "comprise" and "include" only indicate the inclusion of the steps and elements explicitly identified, and these steps and elements do not constitute an exclusive list, and the method or device can also include other steps or elements.
[0029] Flowcharts are used in the present specification to illustrate the operations performed by the system according to the embodiments of the present specification. It should be understood that the preceding or subsequent operations do not necessarily have to be performed in sequence. Instead, the steps can be processed in reverse order or simultaneously. At the same time, other operations can also be added to these processes, or one or more steps can be removed from these processes.
[0030] FIG. 1 is a flow diagram of a method of growing an exemplary silicon carbide epitaxial layer, according to some embodiments of the present specification. As shown in FIG. 1, the flow 100 includes the following steps.
[0031] Step 110, using a first hydrogen gas flow to perform a first in-situ etching on the silicon face of the silicon carbide substrate to generate a first processed substrate.
[0032] The silicon carbide substrate refers to a silicon carbide base material used to support and build other functional layers in the process of manufacturing a silicon carbide crystal. The silicon carbide substrate has a silicon face and a carbon face. The silicon face refers to the (0001) crystal face of the silicon carbide crystal, that is, the surface cut along the positive direction of the c-axis of the crystal, and the termination atom of the surface is a silicon atom. The carbon face refers to the (000-1) crystal face of the silicon carbide crystal, that is, the surface cut along the negative direction of the growth direction c-axis of the silicon carbide crystal, and the termination atom of the surface is a carbon atom. In some embodiments, the doping concentration of the silicon carbide substrate can be 1×10 19 cm - - 3 3 19 cm -3 -3 19 cm -3 -3 19 cm -3 -3 19 cm -3 -3 19 cm -3 -3 The doping concentration refers to the number of doping atoms per unit volume of the silicon carbide crystal. The doping concentration can affect the electrical conductivity of the silicon carbide crystal. The electrical conductivity refers to the ability of an electric current to pass through a substance per unit time and per unit voltage, that is, a physical quantity that describes the electrical conductivity of a substance. Generally, the higher the doping concentration, the higher the electron concentration or hole concentration in the silicon carbide crystal, and the higher the electrical conductivity.
[0033] The first hydrogen gas flow refers to a hydrogen gas flow used to etch the silicon carbide substrate. Under high temperature conditions, hydrogen molecules (H2) can undergo thermal decomposition to produce individual hydrogen atoms (H), which can be adsorbed on the silicon face of the silicon carbide substrate and react with silicon atoms to form hydrides (such as SiH2, SiH3, etc.), which have good volatility and can be released from the silicon face of the silicon carbide substrate, thereby achieving etching effect. The speed of the hydride formed from the surface of the silicon carbide substrate (i.e., the etching rate) can be controlled by controlling the flow rate, temperature, etc. of the hydrogen gas flow. Generally, the faster the flow rate and the higher the temperature of the hydrogen gas flow, the higher the etching rate. The flow rate unit used in the embodiments of the present specification is standard liters per minute (SLM), which represents the volume of gas (L) flowing per minute under standard conditions (0℃, 1atm).
[0034] In some embodiments, the first hydrogen gas flow can have a first flow rate. The first flow rate refers to the flow rate of the first hydrogen gas flow. In some embodiments, the first flow rate can be greater than or equal to 80 SLM and less than or equal to 150 SLM. The first flow rate can also be greater than or equal to 95 SLM and less than or equal to 135 SLM. The first flow rate can also be greater than or equal to 100 SLM and less than or equal to 120 SLM. It can be understood that if the first flow rate is too high (e.g., greater than 150 SLM), it can easily cause over-etching and result in defects. If the first flow rate is too low (e.g., less than 80 SLM), the etching can not be sufficient to completely remove the native defects of the silicon carbide substrate and the oxide layer, adsorbed impurities, etc. on the surface of the substrate. By setting the first flow rate to be greater than or equal to 80 SLM and less than or equal to 150 SLM, the oxide layer, adsorbed impurities, etc. on the surface of the silicon carbide substrate can be effectively and completely removed, the native defects of the substrate can be reduced, and a clean and flat surface can be provided for the growth of the subsequent buffer layer.
[0035] The first processed substrate refers to a substrate layer obtained after the first in-situ etching of the silicon carbide substrate.
[0036] The first in-situ etching refers to the in-situ etching of the silicon carbide substrate. In some embodiments, the pressure of the reaction chamber (e.g., the vacuum furnace 614 in FIG. 6 below) can be adjusted to a target pressure, and the temperature of the reaction chamber can be adjusted to a target temperature. The first hydrogen gas flow can be adjusted to a first flow rate (i.e., 80 SLM to 150 SLM) and introduced into the reaction chamber. After the pressure and temperature of the reaction chamber are stabilized to the target pressure and target temperature, respectively, the first in-situ etching of the silicon face of the silicon carbide substrate can be performed using the first hydrogen gas flow to generate the first processed substrate. In some embodiments, the target pressure can be 50 mbar to 150 mbar. The target pressure can also be 70 mbar to 130 mbar. The target pressure can also be 90 mbar to 110 mbar. In some embodiments, the target temperature can be 1550°C to 1700°C. The target temperature can also be 1600°C to 1700°C. The target temperature can also be 1600°C to 1650°C. The first in-situ etching can remove the oxide layer or other impurities on the silicon face of the silicon carbide substrate, ensuring that the silicon face of the silicon carbide substrate is clean and providing good conditions for the growth of the subsequent buffer layer.
[0037] In some embodiments, the etching time of the first in-situ etching can be 5 min to 20 min. It can be understood that if the etching time of the first in-situ etching is too long (e.g., greater than 20 min), it can easily cause over-etching defects. If the etching time of the first in-situ etching is too short (e.g., less than 5 min), the etching can not be sufficient to remove the native defects, oxide layer, etc. of the silicon carbide substrate, and the silicon face of the silicon carbide substrate can not be clean. The etching condition can be determined by a defect tester, and an appropriate etching time can be determined based on the etching condition to achieve the desired etching effect.
[0038] Step 120, growing a first buffer layer on the silicon face of the first processed substrate.
[0039] The first buffer layer refers to a transition layer between the silicon carbide substrate and the subsequently grown epitaxial layer. In some embodiments, the crystal structure type of the first buffer layer is a 4H type of silicon carbide crystal (i.e. 4H-SiC) structure. The first buffer layer can reduce the difference in lattice matching and the difference in thermal expansion coefficient between the silicon carbide substrate and the subsequently grown epitaxial layer, prevent the vertical growth of defects while reducing stress during the growth of the subsequent epitaxial layer, and further reduce defects. In addition, the first buffer layer generally has a lower defect density (the number of defects present per unit area or per unit volume), can effectively absorb dislocations in the silicon carbide substrate, reduce the transmission of defects to the epitaxial layer, and thus improve the crystal quality of the epitaxial layer.
[0040] In some embodiments, the thickness of the first buffer layer can be 0.3 μm to 2 μm. Preferably, the thickness of the first buffer layer can be 0.8 μm to 1.5 μm. The thickness of the first buffer layer can also be 1.0 μm to 1.3 μm. The thickness of the first buffer layer can also be 1.1 μm to 1.2 μm. It can be understood that the thickness of the first buffer layer is related to the requirements of the device. For example, for high-power devices, a thicker buffer layer is needed to relieve stress and prevent the generation of cracks and defects. For example, for laser devices, a thinner buffer layer is needed to optimize the emission efficiency and stability of the laser, and if a too thick buffer layer is used, the optical signal may be disturbed during transmission. By setting the thickness of the first buffer layer to be 0.3 μm to 2 μm, and preferably the thickness to be 0.8 μm to 1.5 μm, the first buffer layer can meet the thickness requirements of as many devices as possible while preventing the vertical growth of defects, and can be adapted to a wider range of application scenarios.
[0041] In some embodiments, the reaction chamber pressure can be adjusted to a target pressure, and the reaction chamber temperature can be adjusted to a target temperature; the carbon source, the silicon source and the doping source can be adjusted according to the flow required for growing the first buffer layer and then introduced into the reaction chamber; after the reaction chamber pressure and the reaction chamber temperature are respectively stabilized to the target pressure and the target temperature, the first buffer layer is grown on the silicon face of the first processed substrate. For more information about the target pressure and the target temperature, please refer to the foregoing related description.
[0042] The carbon source refers to a substance or material that provides carbon elements. For example, methane, ethylene, etc. In some embodiments, the carbon source flow required for growing the first buffer layer can be 0-500 sccm. The carbon source flow required for growing the first buffer layer can also be 100-400 sccm. The carbon source flow required for growing the first buffer layer can also be 200-300 sccm. The silicon source refers to a substance or material that provides silicon elements. For example, silane, etc. In some embodiments, the silicon source flow required for growing the first buffer layer can be 0-500 sccm. The silicon source flow required for growing the first buffer layer can also be 100-400 sccm. The silicon source flow required for growing the first buffer layer can also be 200-300 sccm. The doping source refers to a substance or material that provides other doping elements (such as phosphorus elements, boron elements, arsenic elements, etc.). For example, phosphine, boron trichloride, arsine, etc. The flow refers to the volume passing through a given cross section per unit time. In some embodiments, the doping source flow required for growing the first buffer layer can be 0-500 sccm. The doping source flow required for growing the first buffer layer can also be 100-400 sccm.
[0043] In some embodiments, the doping concentration of the first buffer layer can be 1x10 17 cm -3 -9x10 18 cm -3 . The doping concentration of the first buffer layer can also be 5x10 17 cm -3 -5x10 18 cm -3 . The doping concentration of the first buffer layer can also be 9x10 17 cm -3 -1x10 18 cm -3By setting a proper doping concentration, the grown buffer layer can have excellent electrical conductivity. In some embodiments, the doping concentration of the first buffer layer is lower than that of the silicon carbide substrate. It can be understood that by setting the doping concentration of the first buffer layer to be lower than that of the silicon carbide substrate, the stress caused by the large difference in doping concentration between the silicon carbide substrate and the epitaxial layer can be reduced, the generation of dislocations and defects can be reduced, and the derivation of defects from the silicon carbide substrate to the epitaxial layer can be controlled.
[0044] In step 130, the first buffer layer is subjected to a second in-situ etching using a second hydrogen gas flow to generate a first processed buffer layer.
[0045] The second hydrogen gas flow refers to the hydrogen gas flow used to etch the first buffer layer. For more information about etching by a hydrogen gas flow, please refer to the foregoing relevant description. In some embodiments, the second hydrogen gas flow can have a second flow rate. The second flow rate refers to the flow rate corresponding to the second hydrogen gas flow.
[0046] In some embodiments, the second flow rate can be lower than the first flow rate. It can be understood that, on the one hand, the second in-situ etching is to remove amorphous carbon or other impurities on the surface of the first buffer layer, ensure the cleanliness of the buffer layer surface, and provide good conditions for the growth of the subsequent epitaxial layer, so a large flow rate is not needed. On the other hand, compared with the silicon carbide substrate, the first buffer layer has fewer defects, and using a large flow rate (such as the flow rate agreed with the first in-situ etching) not only cannot reduce the defects, but also can easily cause over-etching, introduce defects, affect the subsequent process, and reduce the crystal quality of the epitaxial layer. Furthermore, the thickness of the silicon carbide substrate is usually 350 μm to 500 μm, and the thickness of the first buffer layer is 0.3 μm to 2 μm. If a large flow rate (such as the flow rate agreed with the first in-situ etching ) is used for the second in-situ etching, the first buffer layer can be etched through. By setting the second flow rate to be lower than the first flow rate, a more suitable etching gas flow rate can be provided for the first buffer layer, the amorphous carbon or other impurities on the surface of the first buffer layer can be removed, and defects caused by over-etching can be avoided.
[0047] In some embodiments, the second flow rate can be greater than or equal to 30 SLM and less than 80 SLM. The second flow rate can also be greater than or equal to 40 SLM and less than or equal to 70 SLM. The second flow rate can also be greater than or equal to 50 SLM and less than or equal to 60 SLM. It can be understood that if the second flow rate is too high (such as greater than 80 SLM), over-etching can easily cause defects; if the second flow rate is too low (such as less than 30 SLM), the etching can not be sufficient to completely remove the impurities on the surface of the first buffer layer. By setting the second flow rate to be greater than or equal to 30 SLM and less than 80 SLM, the amorphous carbon or other impurities on the surface of the first buffer layer can effectively be removed, over-etching can be avoided, and defects caused by etching itself can be reduced.
[0048] The first processed buffer layer refers to a buffer layer obtained after the first buffer layer is subjected to a second in-situ etching. The second in-situ etching refers to an in-situ etching performed on the first buffer layer. In some embodiments, the chamber pressure can be adjusted to a target pressure, and the chamber temperature can be adjusted to a target temperature; the second hydrogen gas flow can be adjusted to a second flow rate (i.e., 30 SLM-80 SLM, excluding 80 SLM) and introduced into the chamber; after the chamber pressure and the chamber temperature are respectively stabilized to the target pressure and the target temperature, the second in-situ etching is performed on the first buffer layer using the second hydrogen gas flow to generate the first processed buffer layer. For more information about the target pressure and the target temperature, please refer to the foregoing relevant description. The second in-situ etching can remove amorphous carbon or other impurities on the surface of the first buffer layer, ensuring the surface of the first buffer layer to be clean, and providing good conditions for the growth of the subsequent epitaxial layer.
[0049] In some embodiments, the etching duration of the second in-situ etching can be 5 min-20 min. It can be understood that if the etching duration of the second in-situ etching is too high (e.g., greater than 20 min), it is easy to cause over-etching and introduce defects; if the etching duration of the second in-situ etching is too low (e.g., less than 5 min), the etching is insufficient, and it is difficult to remove amorphous carbon or other impurities on the surface of the first buffer layer, etc., and it is impossible to ensure the surface of the first buffer layer to be clean.
[0050] Step 140, growing a first epitaxial layer on the first processed buffer layer at a first rate.
[0051] The first rate refers to the growth rate of the first epitaxial layer. In some embodiments, the first rate can be greater than or equal to 20 pm / h and less than or equal to 30 pm / h. The first rate can also be greater than or equal to 22 pm / h and less than or equal to 28 pm / h. The first rate can also be greater than or equal to 24 pm / h and less than or equal to 26 pm / h. It can be understood that if the first rate is too high (e.g., greater than 30 pm / h), it is easy to inherit native defects and cannot obtain a high-quality first epitaxial layer; if the first rate is too low (e.g., less than 20 pm / h), it reduces the production efficiency and slows down the crystal growth process. The first rate is a low growth rate, and growing the first epitaxial layer based on the low growth rate helps to alleviate defects during the growth process, thereby obtaining a high-quality crystal structure. The rate of crystal growth is related to temperature and gas flow. Generally speaking, the higher the temperature and the greater the gas flow, the higher the rate of crystal growth. The rate of crystal growth can be adjusted by controlling the temperature and the gas flow during the growth process.
[0052] The epitaxial layer refers to a single crystal thin film with the same structure as the substrate layer grown by epitaxial growth technology. The first epitaxial layer refers to an epitaxial layer grown on the buffer layer. In some embodiments, the crystal structure type of the first epitaxial layer is a 4H-SiC structure. In some embodiments, the thickness of the first epitaxial layer can be 5-15 μm. The thickness of the first epitaxial layer can also be 7-12 μm. The thickness of the first epitaxial layer can also be 8-10 μm. It can be understood that the purpose of the first epitaxial layer is to provide a good crystal quality basis. If the first epitaxial layer is too thick (e.g., greater than 15 μm), it is over-processing, which can easily cause unnecessary waste of production resources and slow down the crystal growth process. If the first epitaxial layer is too thin (e.g., less than 5 μm), it is not sufficient to provide a good crystal quality basis.
[0053] In some embodiments, the reaction chamber pressure can be adjusted to a target pressure, and the reaction chamber temperature can be adjusted to a target temperature. The carbon source, the silicon source, and the doping source can be adjusted to the flow required for growing the first epitaxial layer and then introduced into the reaction chamber. After the reaction chamber pressure and the reaction chamber temperature are respectively stabilized to the target pressure and the target temperature, the first epitaxial layer can be generated by performing the first epitaxial growth at a first rate on the first post-processing buffer layer. More details about the carbon source, the silicon source, the doping source, the target pressure, and the target temperature can be found in the foregoing related description.
[0054] In some embodiments, the carbon source flow, the silicon source flow, and the doping source flow required for growing the first epitaxial layer can be related to the first rate. The faster the first rate, the higher the carbon source flow, the silicon source flow, and the doping source flow required for growing the first epitaxial layer can be set. For example, the carbon source flow required for growing the first epitaxial layer can be set as a*first rate, the silicon source flow required for growing the first epitaxial layer can be set as b*first rate, and the doping source flow required for growing the first epitaxial layer can be set as c*first rate, where a, b, and c are constants that can be set based on experience or demand.
[0055] In some embodiments, the silicon-to-carbon ratio of the grown first epitaxial layer can be (0.75-1.1):1. The silicon-to-carbon ratio of the grown first epitaxial layer can also be (0.8-1.0):1. The silicon-to-carbon ratio of the grown first epitaxial layer can also be (0.85-0.95):1. It can be appreciated that if the silicon-to-carbon ratio is too high (i.e., under silicon-rich conditions), it can lead to the formation of Frank-type stacking faults, silicon droplet phenomenon, etc., and can be accompanied by carbon vacancies; if the silicon-to-carbon ratio is too low (i.e., under carbon-rich conditions), it can lead to the formation of primary-type stacking faults, triangular defects, 3C inclusion defects, etc., and can also lead to the exacerbation of epitaxial layer surface step bunching and surface roughening. The silicon-to-carbon ratio refers to the ratio of carbon elements and silicon elements in a silicon carbide crystal. The control of the silicon-to-carbon ratio can be achieved by adjusting the flow ratio of the carbon source and the silicon source. Specifically, to increase the silicon-to-carbon ratio, the carbon source flow can be reduced or the silicon source flow can be increased (i.e., the flow ratio of the carbon source and the silicon source is increased); to decrease the silicon-to-carbon ratio, the carbon source flow can be increased or the silicon source flow can be reduced (i.e., the flow ratio of the carbon source and the silicon source is decreased).
[0056] In some embodiments, the doping concentration of the first epitaxial layer can be 3x10 14 cm -3 ~5x10 16 cm -3 . The doping concentration of the first epitaxial layer can also be 9x10 14 cm -3 ~1x10 16 cm -3 . The doping concentration of the first epitaxial layer can also be 1x10 15 cm -3 ~9x10 15 cm -3 . It can be appreciated that if the doping concentration of the first epitaxial layer is too low, it can affect the electrical conductivity performance (too low electrical conductivity, too high resistance, etc.), device reliability, etc. of the silicon carbide epitaxial wafer formed into a device; if the doping concentration of the first epitaxial layer is too low, it can increase the stress in the epitaxial layer, leading to the generation of defects, affecting the electrical conductivity performance (too high electrical conductivity, too low resistance, etc.) of the silicon carbide epitaxial wafer formed into a device, and reducing the withstand voltage and conduction characteristics of the device, etc. By setting an appropriate doping concentration of the first epitaxial layer, the crystal quality of the epitaxial layer can be optimized, the generation of defects can be controlled, the stress can be managed, and the electrical performance can be balanced, so as to improve the overall performance of the silicon carbide epitaxial wafer and the reliability of the device formed therefrom.
[0057] Step 150, growing a second epitaxial layer on the first epitaxial layer at a second rate.
[0058] The second rate refers to a growth rate of the second epitaxial layer. In some embodiments, the second rate can be greater than the first rate. In some embodiments, the second rate can be greater than or equal to 60 pm / h and less than or equal to 100 pm / h. The second rate can also be greater than or equal to 75 pm / h and less than or equal to 90 pm / h. The second rate can also be greater than or equal to 80 pm / h and less than or equal to 85 pm / h. It can be understood that if the growth rate of the epitaxial layer is too fast, defects can be introduced or the transmission of defects can be caused, affecting the crystal quality of the epitaxial layer; if the growth rate of the epitaxial layer is too slow, the growth process of the epitaxial layer can be slowed down, reducing the production efficiency. By setting the second rate as a high growth rate greater than the first rate (low growth rate), the second epitaxial layer can be grown based on the high growth rate after the first epitaxial layer grown at the first rate has provided a good crystal quality basis, so as to balance the crystal quality and the production efficiency, and reduce the cost; in addition, the second rate as a high growth rate can also prevent the generation of defects such as screw dislocations and edge dislocations during the crystal growth.
[0059] The second epitaxial layer refers to an epitaxial layer grown on the first epitaxial layer. In some embodiments, the crystal structure type of the second epitaxial layer is a 4H-SiC structure. In some embodiments, the thickness of the second epitaxial layer can be 5 pm to 50 pm. The thickness of the second epitaxial layer can also be 15 pm to 40 pm. The thickness of the second epitaxial layer can also be 25 pm to 35 pm. The thickness of the second epitaxial layer can be set based on the requirements of the semiconductor device.
[0060] In some embodiments, the reaction chamber pressure can be adjusted to a target pressure, and the reaction chamber temperature can be adjusted to a target temperature; the carbon source, the silicon source, and the doping source can be adjusted to the flow required for growing the second epitaxial layer and then introduced into the reaction chamber; after the reaction chamber pressure and the reaction chamber temperature are respectively stabilized to the target pressure and the target temperature, the second epitaxial layer can be generated by performing a second epitaxial growth on the first epitaxial layer at the second rate. More details about the carbon source, the silicon source, the doping source, the target pressure, and the target temperature can be referred to the foregoing related description.
[0061] In some embodiments, the carbon source flow, the silicon source flow, and the doping source flow required for growing the second epitaxial layer can be related to the second rate, and the faster the second rate, the higher the carbon source flow, the silicon source flow, and the doping source flow required for growing the epitaxial layer can be set. For example, the carbon source flow required for growing the second epitaxial layer can be set as d*second rate, the silicon source flow required for growing the second epitaxial layer can be set as e*second rate, and the doping source flow required for growing the second epitaxial layer can be set as f*second rate, where d, e, and f are constants that can be set based on experience or requirements.
[0062] In some embodiments, the silicon-to-carbon ratio of the grown second epitaxial layer is the same as that of the first epitaxial layer. In some embodiments, the carbon source flow rate and the silicon source flow rate used for growing the second epitaxial layer can be increased proportionally while keeping the silicon-to-carbon ratio of the second epitaxial layer the same as that of the first epitaxial layer, to achieve growing the second epitaxial layer at a second rate that is greater than the first rate.
[0063] In some embodiments, the doping concentration of the second epitaxial layer is the same as that of the first epitaxial layer, being 3x1018cm-3. 14 cm-3. -3 ~5x1018cm-3. 16 cm-3. - 3 The doping concentration can affect the electrical conductivity of the epitaxial layers (the first epitaxial layer and the second epitaxial layer). By setting a reasonable doping concentration, the grown epitaxial layers can have excellent electrical conductivity.
[0064] In some embodiments, the method of growing the silicon carbide epitaxial layer can further include: growing a second buffer layer on the first post-processing buffer layer; performing a third in-situ etching on the second buffer layer using a third hydrogen gas flow to generate a second post-processing buffer layer, the third hydrogen gas flow having a third flow rate; and growing the first epitaxial layer on the second post-processing buffer layer at the first rate. Details can be found in FIG. 4 and its related description.
[0065] FIG. 2 is a schematic diagram of an exemplary silicon carbide crystal structure, according to some embodiments of the present specification. As shown in FIG. 2, a first in-situ etching is performed on a silicon face 211 of a silicon carbide substrate 210 using a first hydrogen gas flow 220 with a first flow rate to generate a first post-processing substrate 230. A first buffer layer 240 is grown on a silicon face 231 of the first post-processing substrate 230. A second in-situ etching is performed on the first buffer layer 240 using a second hydrogen gas flow 250 with a second flow rate to generate a first post-processing buffer layer 260. A first epitaxial layer 270 is grown on the first post-processing buffer layer 260 at a first rate. A second epitaxial layer 280 is grown on the first epitaxial layer 270 at a second rate. According to the scheme of the present application, the formation of stacking faults can be effectively reduced, so that the obtained silicon carbide epitaxial layer has less defects, high quality, and stable comprehensive performance. The scheme implemented in the present specification can alleviate the lattice mismatch and the difference in the coefficient of thermal expansion between the silicon carbide substrate 210 and the epitaxial layer (the first epitaxial layer 270 and the second epitaxial layer 280), and prevent the vertical growth of defects. By using hydrogen gas flows (the first hydrogen gas flow 220 and the second hydrogen gas flow 250) with different flow rates for the first in-situ etching and the second in-situ etching, the surface morphology and the surface flatness of the silicon carbide substrate 210 and the first buffer layer 240 can be effectively improved, which provides good conditions for the growth of the subsequent epitaxial layer (the first epitaxial layer 270 and the second epitaxial layer 280), reduces the original defects, and avoids damage defects caused by excessive etching. By using a gradient epitaxial growth rate (a lower first rate and a higher second rate) for the growth of the epitaxial layer, the layer faults can be effectively avoided from being derived to the epitaxial layer.
[0066] In the embodiments of the present specification, the method for growing the silicon carbide epitaxial layer can include the following steps:
[0067] In step S1, the pressure of the reaction chamber is adjusted to 50 mbar-150 mbar, and the temperature of the reaction chamber is adjusted to 1550°C-1700°C.
[0068] In step S2, after the pressure and the temperature of the reaction chamber are stabilized, high-purity hydrogen is introduced into the reaction chamber, the flow rate of the hydrogen is adjusted to 80 SLM-150 SLM, the silicon face of the silicon carbide substrate is etched in-situ using the hydrogen to obtain a first post-processing substrate, and the etching time is 5 min-20 min.
[0069] In step S3, the flow rate of the carbon source is adjusted to 5 sccm-20 sccm, the flow rate of the silicon source is adjusted to 20 sccm-70 sccm, the flow rate of the doping source is adjusted to 100 sccm-500 sccm, and the reaction chamber is introduced, so that a first buffer layer with a thickness of 0.3 μm-2 μm is grown on the silicon face of the first post-processing substrate, wherein the doping concentration of the first buffer layer is 1 x 1017 cm -3 ~9x10 18 cm -3 .
[0070] Step S4, the carbon source, silicon source and doping source are introduced into the exclusive pipeline, not into the reaction chamber, the hydrogen flow is adjusted to 30 SLM-80 SLM, the second in-situ etching is performed on the first buffer layer, and the first processed buffer layer is obtained, and the etching time is 5 min-20 min.
[0071] Step S5, the carbon source flow is adjusted to 75 sccm-100 sccm, the silicon source flow is adjusted to 150 sccm-267 sccm, the doping source flow is adjusted to 20 sccm-500 sccm, and the reaction chamber is introduced, the silicon-carbon ratio is kept at (0.75-1.1):1, the first epitaxial growth is performed on the first processed buffer layer at a first rate, and the first epitaxial layer with a thickness of 5 μm-15 μm is obtained, wherein the first rate is 20 μm / h-30 μm / h, and the doping concentration of the first epitaxial layer is 3x10 14 cm -3 ~5x10 16 cm -3 .
[0072] Step S6, the carbon source flow is adjusted to 125 sccm-275 sccm, the silicon source flow is adjusted to 300 sccm-500 sccm, the doping source flow is adjusted to 20 sccm-500 sccm, and the reaction chamber is introduced, the silicon-carbon ratio is kept at (0.75-1.1):1, the second epitaxial growth is performed on the first epitaxial layer at a second rate, and the second epitaxial layer with a thickness of 5 μm-50 μm is obtained, wherein the second rate is 60 μm / h-100 μm / h, and the doping concentration of the second epitaxial layer is 3x10 14 cm -3 ~5x10 16 cm -3 .
[0073] Figure 3A is a surface defect test pattern of a silicon carbide epitaxial layer grown by using the embodiment of the present specification. The dots in the figure are stacking faults (SF) and bar stacking faults (BSF) in the epitaxial layer. As shown in Figure 3A, it can be seen that the number of stacking faults in the epitaxial layer grown based on the embodiment of the present specification (i.e. the method of first etching + first buffer layer growth + second etching + double-layer different-rate epitaxial layer growth) is small and the distribution is sparse, and the crystal quality is good.
[0074] FIG. 3B is a surface defect test map of a silicon carbide epitaxial layer grown by a method of first etching + first buffer layer growth + second etching + single layer epitaxial layer growth. As shown in FIG. 3B, it can be seen that compared with FIG. 3A, the number of stacking faults in the silicon carbide epitaxial layer grown by the method of first etching + first buffer layer growth + second etching + single layer epitaxial layer growth is more and the distribution is dense, the defects are more, and the crystal quality is worse.
[0075] FIG. 3C is a surface defect test map of a silicon carbide epitaxial layer grown by a method of single etching + first buffer layer growth + single layer epitaxial layer growth. As shown in FIG. 3C, it can be seen that compared with FIGS. 3A and 3B, the number of stacking faults in the silicon carbide epitaxial layer grown by the method of single etching + buffer layer growth + single layer epitaxial layer growth is more and the distribution is dense, the defects are more, and the crystal quality is worse.
[0076] In summary, the silicon carbide epitaxial layer grown by the method of growing a silicon carbide epitaxial layer described in the embodiments of the present specification has a significant reduction in stacking faults and improved crystal quality.
[0077] FIG. 4 is a flowchart of an exemplary method of growing a silicon carbide epitaxial layer according to some embodiments of the present specification. As shown in FIG. 4, the flow 400 includes the following steps.
[0078] Step 410, performing first in-situ etching on the silicon face of the silicon carbide substrate using a first hydrogen gas flow to generate a first treated substrate.
[0079] Step 420, growing a first buffer layer on the silicon face of the first treated substrate.
[0080] Step 430, performing second in-situ etching on the first buffer layer using a second hydrogen gas flow to generate a first treated buffer layer.
[0081] For more information about steps 410-430, please refer to the relevant description of steps 110-130 in FIG. 1, which will not be repeated here.
[0082] Step 440, growing a second buffer layer on the first treated buffer layer.
[0083] The second buffer layer refers to a second layer transition layer close to the silicon carbide substrate between the silicon carbide substrate and the epitaxial layer. For example, the second buffer layer 510 in FIG. 5. In some embodiments, the crystal structure, thickness, growth process, etc. of the second buffer layer are the same as those of the first buffer layer, which can be referred to the foregoing description of the first buffer layer in step 120.
[0084] Step 450, performing third in-situ etching on the second buffer layer using a third hydrogen gas flow to generate a second treated buffer layer.
[0085] The third hydrogen gas flow refers to a hydrogen gas flow used for etching the second buffer layer. More details about etching by a hydrogen gas flow can be found in the relevant description in steps 110 and 130. In some embodiments, the third hydrogen gas flow can have a third flow rate. The third flow rate refers to the flow rate of the third hydrogen gas flow.
[0086] In some embodiments, the third flow rate can be lower than the second flow rate. It can be understood that the lower the flow rate of the hydrogen gas flow, the slower the etching process, and the more precise the process. By setting the third flow rate to be lower than the second flow rate, a more precise etching can be achieved on the surface of the second buffer layer, avoiding over-etching and reducing defects caused by etching itself.
[0087] The second processed buffer layer refers to a buffer layer obtained after the third in-situ etching process on the second buffer layer. The third in-situ etching refers to an in-situ etching process on the second buffer layer. In some embodiments, the third in-situ etching process is the same as the second in-situ etching process, and the description of the second in-situ etching in the foregoing step 130 can be referred to.
[0088] Step 460: growing a first epitaxial layer on the second processed buffer layer at a first rate.
[0089] Step 470: growing a second epitaxial layer on the first epitaxial layer at a second rate.
[0090] In some embodiments, the process of growing the first epitaxial layer and the second epitaxial layer on the second processed buffer layer is the same as the process of growing the first epitaxial layer and the second epitaxial layer on the first processed buffer layer, and the description of growing the first epitaxial layer and the second epitaxial layer in the foregoing steps 140-150 can be referred to.
[0091] In some embodiments, the method for growing a silicon carbide epitaxial layer can further include step 480: growing a third epitaxial layer on the second epitaxial layer at a third rate.
[0092] The third rate refers to the growth rate of the third epitaxial layer. In some embodiments, the third rate can be greater than the second rate. In some embodiments, the third rate can be 80 μm / h-130 μm / h. The third rate can also be 90 μm / h-120 μm / h. The third rate can also be 100 μm / h-110 μm / h. It can be understood that the first rate is the slowest, and the first epitaxial layer grown at the first rate effectively alleviates the native defects transferred from the substrate layer; the second rate is moderate, and the production efficiency is improved on the basis of the excellent crystal quality of the first epitaxial layer; the third rate is the fastest, and the production process is further accelerated on the basis of the second epitaxial layer. By setting the third rate to be a high growth rate greater than the second rate, the crystal production capacity can be further improved and the time cost can be reduced while ensuring the crystal quality, and other defects such as screw dislocations and edge dislocations generated in the epitaxial layer production process can be reduced.
[0093] The third epitaxial layer refers to an epitaxial layer grown on the second epitaxial layer. In some embodiments, the crystal structure type of the third epitaxial layer is a 4H-SiC structure. In some embodiments, the thickness of the third epitaxial layer can be 5 μm-200 μm. The thickness of the third epitaxial layer can also be 40 μm-160 μm. The thickness of the third epitaxial layer can also be 80 μm-120 μm.
[0094] In some embodiments, the reaction chamber pressure can be adjusted to a target pressure, and the reaction chamber temperature can be adjusted to a target temperature; the carbon source, the silicon source, and the doping source can be adjusted to the flow rates required for growing the third epitaxial layer and then introduced into the reaction chamber; after the reaction chamber pressure and the reaction chamber temperature are respectively stabilized to the target pressure and the target temperature, the third epitaxial layer can be grown on the second epitaxial layer at a third rate to generate the third epitaxial layer. For more information about the carbon source, the silicon source, the doping source, the target pressure, and the target temperature, please refer to the foregoing relevant description.
[0095] In some embodiments, the carbon source flow rate, the silicon source flow rate, and the doping source flow rate required for growing the third epitaxial layer can be related to the third rate, and the faster the third rate, the higher the carbon source flow rate, the silicon source flow rate, and the doping source flow rate required to grow the third epitaxial layer can be set. For example, the carbon source flow rate required to grow the third epitaxial layer can be set to g*third rate, the silicon source flow rate required to grow the third epitaxial layer can be set to h*third rate, and the doping source flow rate required to grow the third epitaxial layer can be i*third rate, where g, h, and i are constants that can be set based on experience or requirements.
[0096] In some embodiments, the silicon-carbon ratio of the third epitaxial layer is the same as the silicon-carbon ratio of the second epitaxial layer. In some embodiments, while keeping the silicon-carbon ratio of the third epitaxial layer the same as the silicon-carbon ratio of the second epitaxial layer, the carbon source flow rate and the silicon source flow rate used to grow the third epitaxial layer can be proportionally increased to achieve the growth of the third epitaxial layer at a third rate greater than the second rate.
[0097] In some embodiments, the doping concentration of the third epitaxial layer is the same as the doping concentration of the first epitaxial layer and the second epitaxial layer, which is 3×10 14 cm -3 -5×10 16 cm -3 . The doping concentration can affect the conductivity of the epitaxial layers (the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer). By setting a reasonable doping concentration, the grown epitaxial layer can have excellent conductivity.
[0098] In some embodiments of the present specification, by growing the third epitaxial layer on the second epitaxial layer at a third rate, the epitaxial layer growth rate can be improved, the production efficiency can be improved, and the time cost can be saved.
[0099] FIG. 5 is a schematic diagram of an exemplary silicon carbide crystal structure, according to some embodiments of the present specification. As shown in FIG. 5, a second buffer layer 510 is grown on the first post-treatment buffer layer 260 (grown on the first post-treatment substrate 230); the second buffer layer 510 is subjected to a third in-situ etching with a third hydrogen gas flow 520 having a third flow rate to generate a second post-treatment buffer layer 530; and a first epitaxial layer 270 is grown on the second post-treatment buffer layer 530 at a first rate; a second epitaxial layer 280 is grown on the first epitaxial layer 270 at a second rate; and a third epitaxial layer 540 is grown on the second epitaxial layer 280 at a third rate. By providing the second buffer layer 510, the matching between the substrate layer and the epitaxial layers (the first epitaxial layer 270, the second epitaxial layer 280, and the third epitaxial layer 540) can be further improved, the internal stress of the crystal can be reduced, and the defects in the epitaxial layers can be reduced. In addition, by using a third hydrogen gas flow with a lower flow rate for etching, a second post-treatment buffer layer with more delicate etching can be obtained, the surface morphology and flatness of the second buffer layer can be improved, and a more optimized environment can be provided for the growth of subsequent epitaxial layers.
[0100] FIG. 6 is a schematic diagram of an exemplary silicon carbide epitaxial layer growth system, according to some embodiments of the present specification. In some embodiments, the growth method of the silicon carbide epitaxial layer described in the embodiments of the present specification can be implemented by the growth system. As shown in FIG. 6, the growth system 600 can include a crystal growth device 610 and a processing device 620.
[0101] As shown in FIG. 6, the crystal growth device 610 can include a seed crystal holder 611, a seed crystal connecting rod 612, and a vacuum furnace 613.
[0102] The seed crystal holder 611 is used to fix the silicon carbide substrate. The material of the seed crystal holder 611 can be graphite. The side of the seed crystal holder 611 in contact with the melt can be provided with a bonding surface for bonding the silicon carbide substrate. The silicon carbide substrate can be bonded to the bonding surface of the seed crystal holder 611 under certain conditions (e.g., vacuumizing, heating, etc.). The seed crystal holder 611 can be provided in a columnar shape, a table shape, or other feasible shapes.
[0103] The seed crystal connecting rod 612 is used to connect the seed crystal holder 611. One end of the seed crystal connecting rod 612 can be connected with the seed crystal holder 611. The other end of the seed crystal connecting rod 612 can be connected with the top wall of the crystal growth device 610. The seed crystal connecting rod 612 can be connected with the seed crystal holder 611 in various ways. For example, the seed crystal connecting rod 612 can be threadedly connected with the seed crystal holder 611. For another example, the seed crystal connecting rod 612 can be snap-connected with the seed crystal holder 611. In some embodiments, the seed crystal connecting rod 612 can move axially along the seed crystal connecting rod 612, thereby driving the seed crystal holder 611 to move axially along the seed crystal connecting rod 612.
[0104] The seed holder 611, the seed connecting rod 612, etc. can be arranged in the vacuum furnace 613 (i.e., the reaction chamber).
[0105] The crystal growth apparatus 610 can further include auxiliary components (not shown in FIG. 6), such as pipes for introducing hydrogen, carbon source, silicon source, and dopant source into the reaction chamber, equipment for heating the vacuum furnace, equipment for pressurizing the vacuum furnace, etc.
[0106] The processing device 620 can be arranged outside the crystal growth apparatus 610 and signal-connected with each component of the crystal growth apparatus 610. The processing device 620 can control each component of the crystal growth apparatus 610. For example, the processing device 620 can control the components for heating in the crystal growth apparatus 610. The processing device 620 can also process data and / or information obtained from the components of the crystal growth apparatus 610 or other devices. The processing device 620 can control the components of the crystal growth apparatus 610 to execute program instructions based on the data, information, and / or processing results to perform one or more functions described in the present specification. Specifically, the processing device 620 can perform corresponding functions according to instructions triggered by a user.
[0107] For example, the user fixes the silicon carbide substrate on the seed holder 611 with the silicon surface of the silicon carbide substrate facing the crucible. The user can input parameters required for growing the epitaxial layer through the interface of the processing device 620 as needed, such as the pressure and temperature of the vacuum furnace, the first flow rate of the first hydrogen gas flow, the etching time of the first in-situ etching, the carbon source flow rate, the silicon source flow rate, and the dopant source flow rate for growing the first buffer layer, the thickness of the first buffer layer, the doping concentration of the first buffer layer, the second flow rate of the second hydrogen gas flow, the etching time of the second in-situ etching, the carbon source flow rate, the silicon source flow rate, the dopant source flow rate, and the silicon-carbon ratio for growing the first epitaxial layer, the thickness of the first epitaxial layer, the doping concentration of the first epitaxial layer, the first growth rate of the first epitaxial layer, the carbon source flow rate, the silicon source flow rate, the dopant source flow rate and the silicon-carbon ratio for growing the second epitaxial layer, the thickness of the second epitaxial layer, the doping concentration of the second epitaxial layer, the second growth rate of the second epitaxial layer, etc. Then, the user can issue a command to start growing the epitaxial layer through the processing device 620.
[0108] In response to the command, the processing device 620 can adjust the pressure and temperature of the vacuum furnace 613. After the pressure and temperature are stabilized (e.g., determined by detecting the pressure change and temperature change of the vacuum furnace 613), the processing device 620 instructs the high-purity hydrogen to be introduced into the vacuum furnace 613 through the hydrogen pipe at the first flow rate, and the silicon surface of the silicon carbide substrate is etched by hydrogen for the first in-situ etching. After the etching is completed, the processing device 620 stops the hydrogen introduction.
[0109] Afterwards, the processing device 620 adjusts the carbon source flow rate, the silicon source flow rate, the dopant source flow rate, and the dopant concentration and inputs them into the vacuum furnace 613 to grow a first buffer layer on the silicon surface of the first in-situ etched substrate.
[0110] When the first buffer layer reaches the target thickness, the carbon source, the silicon source, and the dopant source are switched to the exhaust pipeline, and high-purity hydrogen is input into the vacuum furnace 613 at a second flow rate through the hydrogen pipeline to perform a second in-situ etching of the silicon surface of the silicon carbide substrate using hydrogen. After the etching is completed, the processing device 620 stops the input of hydrogen.
[0111] Afterwards, the processing device 620 adjusts the carbon source flow rate, the silicon source flow rate, the dopant source flow rate, the silicon-to-carbon ratio, and the dopant concentration and inputs them into the vacuum furnace 613 to grow a first epitaxial layer on the second in-situ etched buffer layer at a first rate.
[0112] When the first epitaxial layer reaches the target thickness, the processing device 620 maintains the silicon-to-carbon ratio and the dopant concentration, increases the carbon source flow rate, the silicon source flow rate, and the dopant source flow rate, and grows a second epitaxial layer on the first epitaxial layer at a second rate. When the second epitaxial layer reaches the target thickness, the processing device 620 terminates the process, and the vacuum furnace 613 starts to cool down and reduce the pressure.
[0113] In some embodiments, the processing device 620 can include one or more sub-processing devices (e.g., single-core processing devices or multi-core multi-thread processing devices). By way of example only, the processing device 620 can include a central processing unit (CPU), a graphics processing unit (GPU), a reduced instruction set computer (RISC), a microprocessor, etc., or any combination thereof.
[0114] It should be noted that the foregoing description is only illustrative of the application and not intended to be limiting. Various modifications and changes can be made as would be obvious to a person ordinarily skilled in the art having the benefit of this disclosure. The features, structures, methods, and other characteristics described in the examples of the present description can be combined in various ways to obtain additional and / or alternative exemplary embodiments.
[0115] One or more embodiments of the present description provide a silicon carbide epitaxial layer. The silicon carbide epitaxial layer is grown by the method for growing a silicon carbide epitaxial layer described in the embodiments of the present description.
[0116] One or more embodiments of the present description provide a silicon carbide crystal. The silicon carbide crystal is grown on the silicon carbide epitaxial layer grown by the method described in the embodiments of the present description by a physical vapor transport (PVT) method.
[0117] It can be understood that the principle of the physical vapor transport method is to make the silicon carbide raw material (e.g., silicon carbide powder, etc.) decompose and sublimate into a gaseous component (e.g., Si gas, Si2C gas, SiC2 gas, etc.) at a high temperature, and the gaseous component can be transported to a lower temperature region (e.g., a seed crystal, etc.) under the action of a temperature gradient, and recrystallize to form a solid-phase silicon carbide single crystal.
[0118] The foregoing detailed description has set forth various embodiments of the application via the use of specific terminology. As such, it is to be understood that the term "one embodiment" or "an embodiment" or "some embodiments" or "one alternative" or "an alternative" or "some alternatives" is a description of certain embodiments which do not necessarily cover all embodiments of the application. It is to be understood that the use of such terms as "one embodiment" or "an embodiment" or "some embodiments" or "one alternative" or "an alternative" or "some alternatives" or "one implementation" or "an implementation" or "some implementations" or "one aspect" or "an aspect" or "some aspects" or "one feature" or "an feature" or "some features" or "one characteristic" or "an characteristic" or "some characteristics" or "one property" or "an property" or "some properties" or "one element" or "an element" or "some elements" or "one component" or "an component" or "some components" or "one step" or "an step" or "some steps" or "one element" or "an element" or "some elements" or "one feature" or "an feature" or "some features" or "one element" or "an element" or "some elements" or "one characteristic" or "an characteristic" or "some characteristics" or "one element" or "an element" or "some elements" or "one property" or "an property" or "some properties" or "one step" or "an step" or "some steps" or "one step" or "an step" or "some steps" or "one characteristic" or "an characteristic" or "some characteristics" or "one characteristic" or "an characteristic" or "some characteristics" or "one step" or "an step" or "some steps" or "one feature" or "an feature" or "some features" or "one step" or "an step" or "some steps" or "one property" or "an property" or "some properties" or "one characteristic" or "an characteristic" or "some characteristics" or "one feature" or "an feature" or "some features" or "one property" or "an property" or "some properties" or "one feature" or "an feature" or "some features" or "one feature" or "an feature" or "some features" or "one aspect" or "an aspect" or "some aspects" or "one element" or "an element" or "some elements" or "one element" or "an element" or "some elements" or "one step" or "an step" or "some steps" or "one aspect" or "an aspect" or "some aspects" or "one characteristic" or "an characteristic" or "some characteristics" or "one aspect" or "an aspect" or "some aspects" or "one aspect" or "an aspect" or "some aspects" or "one step" or "an step" or "some steps" or "one implementation" or "an implementation" or "some implementations" or "one element" or "an element" or "some elements" or "one aspect" or "an aspect" or "some aspects" or "one implementation" or "an implementation" or "some implementations" or "one characteristic" or "an characteristic" or "some characteristics" or "one implementation" or "an implementation" or "some implementations" or "one implementation" or "an implementation" or "some implementations" or "one feature" or "an feature" or "some features" or "one implementation" or "an implementation" or "some implementations" or "one property" or "an property" or "some properties" or "one implementation" or "an implementation" or "some implementations" or "one step" or "an step" or "some steps" or "one alternative" or "an alternative" or "some alternatives" or "one aspect" or "an aspect" or "some aspects" or "one
[0119] At the same time, the present specification uses specific terms to describe the embodiments of the present specification. As "one embodiment", "an embodiment", and / or "some embodiments" mean a certain feature, structure or characteristic related to at least one embodiment of the present specification. Therefore, it should be emphasized and noted that the "one embodiment" or "an embodiment" or "one alternative" or "an alternative" or "some alternatives" mentioned in different positions in the present specification do not necessarily refer to the same embodiment. In addition, some features, structures or characteristics in one or more embodiments of the present specification can be properly combined.
[0120] In addition, unless the claims specify, the order of the processing elements and sequences, the use of numerical letters, or the use of other names in the present specification are not intended to limit the order of the processes and methods of the present specification. Although some currently considered useful embodiments of the application are discussed in the above disclosure through various examples, it should be understood that such details are only for the purpose of illustration, and the additional claims are not limited to the disclosed embodiments, but rather, the claims are intended to cover all modifications and equivalent combinations within the spirit and scope of the embodiments of the present specification. For example, although the system components described above can be implemented by hardware devices, they can also be implemented only by software solutions, such as installing the described system on existing servers or mobile devices.
[0121] Similarly, it should be noted that in order to simplify the expression of the disclosure of the present specification and to help understand one or more embodiments of the present specification, the foregoing description of the embodiments of the present specification sometimes combines various features into one embodiment, figure or description thereof. However, this disclosure method does not mean that the features required by the object of the present specification are more than the features mentioned in the claims. In fact, the features of the embodiments are less than all the features of the single embodiment disclosed above.
[0122] In some embodiments, numbers describing the quantity of components and attributes are used. It should be understood that such numbers used in the description of embodiments are modified in some examples with the terms "approximately," "approximately," or "generally." Unless otherwise stated, "approximately," "approximately," or "generally" indicates that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, which may be changed depending on the characteristics required by individual embodiments. In some embodiments, numerical parameters should take into account specified significant digits and employ a general method of digit reservation. Although the numerical ranges and parameters used to confirm their breadth of range in some embodiments of this specification are approximate values, in specific embodiments, such values are set as precisely as feasible.
[0123] For each patent, patent application, patent application publication, and other material, such as articles, books, specifications, publications, and documents, referenced in this specification, the entire contents of which are incorporated herein by reference. This excludes historical application documents that are inconsistent with or conflict with the content of this specification, as well as documents that limit the broadest scope of the claims in this specification (currently or subsequently appended to this specification). It should be noted that in the event of any inconsistency or conflict between the descriptions, definitions, and / or terminology used in the supplementary materials to this specification and the content of this specification, the descriptions, definitions, and / or terminology used in this specification shall prevail.
[0124] Finally, it should be understood that the embodiments described in this specification are merely illustrative of the principles of the embodiments described herein. Other variations may also fall within the scope of this specification. Therefore, alternative configurations of the embodiments described herein are intended to be illustrative rather than limiting, and should be considered consistent with the teachings of this specification. Accordingly, the embodiments described herein are not limited to those explicitly introduced and described herein.
Claims
1. A method of growing a silicon carbide epitaxial layer, comprising: performing a first in-situ etch of a silicon face of a silicon carbide substrate with a first hydrogen gas flow to produce a first post-processed substrate, the first hydrogen gas flow having a first flow rate; growing a first buffer layer on the silicon face of the first post-processed substrate; performing a second in-situ etch of the first buffer layer with a second hydrogen gas flow to produce a first post-processed buffer layer, the second hydrogen gas flow having a second flow rate; growing a first epitaxial layer on the first post-processed buffer layer at a first rate; and growing a second epitaxial layer on the first epitaxial layer at a second rate.
2. The method of claim 1, wherein the second flow rate is lower than the first flow rate.
3. The method of claim 2, wherein the first flow rate is greater than or equal to 80 SLM and less than or equal to 150 SLM.
4. The method of claim 3, wherein the second flow rate is greater than or equal to 30 SLM and less than 80 SLM.
5. The method of any one of claims 1-4, wherein the first buffer layer has a thickness of 0.3 pm to 2 pm.
6. The method of claim 5, wherein the first buffer layer has the thickness of 0.8 pm to 1.5 pm.
7. The method of any one of claims 1-6, wherein the second rate is greater than the first rate.
8. The method of claim 7, wherein the first rate is greater than or equal to 20 pm / h and less than or equal to 30 pm / h.
9. The method of claim 8, wherein the second rate is greater than or equal to 60 pm / h and less than or equal to 100 pm / h.
10. The method of any one of claims 1-8, further comprising: growing a second buffer layer on the first post-processed buffer layer; performing a third in-situ etch of the second buffer layer with a third hydrogen gas flow to produce a second post-processed buffer layer, the third hydrogen gas flow having a third flow rate; and growing the first epitaxial layer on the second post-processed buffer layer at the first rate.
11. The method of claim 10, wherein the third flow rate is lower than the second flow rate.
12. The method of claim 10, further comprising: growing a third epitaxial layer on the second epitaxial layer at a third rate.
13. The method of claim 12, wherein the third rate is greater than the second rate.
14. A silicon carbide epitaxial layer grown using the method of any one of claims 1-13.
15. A silicon carbide crystal grown on the silicon carbide epitaxial layer grown using the method of any one of claims 1-13 by a physical vapor transport method.