Pixel circuit, display panel and display apparatus

Abstract

A pixel circuit (21), comprising: a main light emission path (210), wherein a first terminal (210a) of the main light emission path (210) is connected to a first voltage terminal (VDD), and a second terminal (210b) of the main light emission path (210) is connected to a light-emitting device (22); the main light emission path (210) comprises at least two first transistors (T1) connected between the first terminal (210a) and the second terminal (210b), and the at least two first transistors (T1) are connected in series; the at least two first transistors (T1) comprise a driving transistor (TD) and at least one light emission control transistor (TL); and at least one first transistor (T1) comprises two gate electrodes, and the two gate electrodes are connected to form a control terminal of the first transistor (T1).

Description

Pixel circuits, display panels and display devices Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a pixel circuit, a display panel, and a display device. Background Technology

[0002] With the development of display technology, display devices (such as mobile phones, laptops, or tablets) are increasingly used in people's lives. Among them, organic light-emitting diode (OLED) display devices have received widespread attention due to their advantages such as active light emission, wide viewing angle, high contrast, fast response speed, low power consumption, and ultra-thin design. Summary of the Invention

[0003] On one hand, a pixel circuit is provided. The pixel circuit includes a main light-emitting path, a first end of which is connected to a first voltage terminal, and a second end of which is connected to a light-emitting device; the main light-emitting path includes at least two control units connected in series between the first end and the second end, each control unit including a first transistor; the at least two first transistors include a driving transistor and at least one light-emitting control transistor; the at least one first transistor includes two gates connected together to form a control terminal of the first transistor; the at least one control unit further includes at least one second transistor, wherein the first transistor and the at least one second transistor of the same control unit are connected in parallel.

[0004] In some embodiments, the second transistor includes two gates connected together to form the control terminal of the second transistor.

[0005] In some embodiments, the driving transistor includes two gates connected together.

[0006] In some embodiments, at least one of the second transistors is connected in parallel with the driving transistor.

[0007] In some embodiments, the at least two first transistors include a first light-emitting control transistor and a second light-emitting control transistor, a first terminal of the first light-emitting control transistor is connected to the first voltage terminal, a second terminal of the first light-emitting control transistor is connected to the first terminal of the driving transistor, a second terminal of the driving transistor is connected to the first terminal of the second light-emitting control transistor, and a second terminal of the second light-emitting control transistor is connected to the light-emitting device; the first light-emitting control transistor includes two gates connected to each other; and / or, the second light-emitting control transistor includes two gates connected to each other.

[0008] In some embodiments, at least one third transistor is connected in parallel with the first light-emitting control transistor; and / or, at least one fourth transistor is connected in parallel with the second light-emitting control transistor.

[0009] On the other hand, a display panel is provided. The display panel includes a substrate; a plurality of pixel circuits disposed on the substrate, the pixel circuits being pixel circuits as described in any of the above embodiments; a plurality of light-emitting devices disposed on the side of the plurality of pixel circuits away from the substrate, wherein one pixel circuit is connected to at least one of the light-emitting devices.

[0010] In some embodiments, at least one first transistor in the pixel circuit includes: an active layer; and a first gate and a second gate located on both sides of the active layer along the thickness direction of the display panel, the first gate and the second gate being electrically connected.

[0011] In some embodiments, the display panel further includes: a first gate insulating layer located between the first gate and the active layer; a second gate insulating layer located between the active layer and the second gate; a first via is disposed in the first gate insulating layer, a second via is disposed in the second gate insulating layer, and the first gate and the second gate are interconnected through the second via and the first via.

[0012] In some embodiments, along the thickness direction of the display panel, both the second via and the first via are offset from the active layer.

[0013] In some embodiments, the display panel further includes: a source / drain conductive layer located on the side of the second gate away from the first gate, the source / drain conductive layer including a first bridging portion; the first gate and the second gate are electrically connected through the first bridging portion.

[0014] In some embodiments, the display panel further includes: a first gate insulating layer located between the first gate and the active layer; a second gate insulating layer located between the active layer and the second gate; and a third insulating layer located between the second gate and the source / drain conductive layer; a first via is disposed in the first gate insulating layer, a second via is disposed in the second gate insulating layer, and a third via is disposed in the third insulating layer; the first via, the second via, and the third via are interconnected; one end of the first bridging portion is electrically connected to the first gate through the first via, the second via, and the third via; the third insulating layer is further provided with a fourth via, and the other end of the first bridging portion is electrically connected to the second gate through the fourth via.

[0015] In some embodiments, the first gate is closer to the substrate than the second gate; the display panel further includes a light-shielding layer located between the substrate and the film layer containing the first gate; the orthographic projection of the active layer on the substrate is within the range of the orthographic projection of the light-shielding layer on the substrate, and the first gate and the light-shielding layer are made of the same material and are disposed in the same layer.

[0016] In some embodiments, the pixel circuit further includes the at least one second transistor disposed in parallel with the first transistor; the second transistor includes: an active layer; and a first gate and a second gate located on both sides of the active layer along the thickness direction of the display panel, the first gate and the second gate being electrically connected; the first gate of the first transistor and the first gate of the at least one second transistor are disposed on the same layer and interconnected with each other, and the second gate of the first transistor and the second gate of the at least one second transistor are disposed on the same layer and interconnected with each other.

[0017] In some embodiments, the first gate of the first transistor and the first gate of the at least one second transistor are interconnected to form a first gate pattern, and the second gate of the first transistor and the second gate of the at least one second transistor are interconnected to form a second gate pattern; the first gate pattern and the second gate pattern both extend in the same direction, and the orthographic projection of the first gate pattern on the substrate and the orthographic projection of the second gate pattern on the substrate overlap.

[0018] In some embodiments, the driving circuit further includes a first capacitor; the display panel further includes: a second electrode plate located on the side of the second gate pattern away from the first gate pattern, the second electrode plate being the upper electrode plate of the first capacitor; the second gate pattern being multiplexed as the first electrode plate, the first electrode plate being the lower electrode plate of the first capacitor; the orthographic projection of the second electrode plate on the substrate is located within the orthographic projection of the first electrode plate on the substrate; the second electrode plate is annular; when the display panel includes a third insulating layer and a fourth via is provided on the third insulating layer, the orthographic projection of the fourth via on the substrate is located within the inner boundary of the orthographic projection of the second electrode plate on the substrate.

[0019] In some embodiments, the driving circuit further includes a first capacitor; the display panel further includes: a second electrode plate located on the side of the second gate away from the first gate, the second electrode plate being the upper electrode plate of the first capacitor; the second gate pattern is multiplexed as the first electrode plate, the first electrode plate being the lower electrode plate of the first capacitor; the orthographic projection of the second electrode plate on the substrate is located within the orthographic projection of the first electrode plate on the substrate; the second electrode plate is block-shaped; when the display panel includes a third insulating layer and a fourth via is provided on the third insulating layer, the orthographic projection of the fourth via on the substrate is offset from the orthographic projection of the second electrode plate on the substrate.

[0020] In some embodiments, the active layer of the first transistor and the active layer of the at least one second transistor are disposed on the same layer; the active layer of the first transistor and the active layer of the at least one second transistor are both disposed intersecting with the first gate pattern and are spaced apart from each other along the extension direction of the first gate pattern.

[0021] In some embodiments, the display panel further includes: a first connecting portion and a second connecting portion, which are disposed on the same layer as the active layer of the first transistor; the active layer of the first transistor and the active layer of the at least one second transistor are located between the first connecting portion and the second connecting portion, and one end of the active layer of the first transistor and the active layer of the at least one second transistor are both connected to the first connecting portion, and the other end of the active layer of the first transistor and the active layer of the at least one second transistor are both connected to the second connecting portion.

[0022] In some embodiments, where the display panel further includes a source / drain conductive layer located on the side of the second gate away from the first gate, the source / drain conductive layer further includes: at least one connection pattern, the orthographic projection of the connection pattern on the substrate at least partially overlapping the orthographic projection of the first connection portion on the substrate, and the connection pattern and the first connection portion are electrically connected through a plurality of fifth vias; and / or,

[0023] The orthographic projection of the connection pattern on the substrate at least partially overlaps with the orthographic projection of the second connection portion on the substrate, and the connection pattern and the second connection portion are electrically connected through a plurality of sixth vias.

[0024] In another aspect, a display device is provided. The display device includes a display panel as described in any of the above embodiments; and a driving circuit board electrically connected to the display panel. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0026] Figure 1 is a structural diagram of a display device according to some embodiments;

[0027] Figure 2 is a structural diagram of another display device according to some embodiments;

[0028] Figure 3 is a structural diagram of a display panel including a substrate and pixel circuitry according to some embodiments;

[0029] Figure 4 is a structural diagram of a display panel according to some embodiments;

[0030] Figure 5 is a circuit diagram of a pixel circuit according to some embodiments;

[0031] Figure 6 is a schematic diagram showing the change in output current of a dual-gate transistor as the voltage received by the bottom gate varies.

[0032] Figure 7 shows the on-state current of a single-gate transistor and multiple dual-gate transistors (where the bottom gate of the multiple dual-gate transistors receives different voltages) as a function of the voltages they receive.

[0033] Figure 8 is a comparison of the on-state current values ​​of a single-gate transistor and multiple dual-gate transistors;

[0034] Figure 9 is a circuit diagram of another driving circuit according to some embodiments;

[0035] Figure 10 is a circuit diagram of another driving circuit according to some embodiments;

[0036] Figure 11 is a circuit diagram of another driving circuit according to some embodiments;

[0037] Figure 12 is a circuit diagram of another display panel according to some embodiments;

[0038] Figure 13 is a circuit diagram of yet another display panel according to some embodiments;

[0039] Figure 14 is a circuit diagram of another display panel according to some embodiments;

[0040] Figure 15 is a plan view of a partial area of ​​a pixel circuit 21 in a display panel according to some embodiments;

[0041] Figure 16 is a partial plan view of another pixel circuit 21 in a display panel according to some embodiments;

[0042] Figure 17 is a partial plan view of another pixel circuit 21 in a display panel according to some embodiments;

[0043] Figure 18 is a partial plan view of another pixel circuit 21 in a display panel according to some embodiments;

[0044] Figure 19 is a partial plan view of another pixel circuit 21 in a display panel according to some embodiments. Detailed Implementation

[0045] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0046] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0047] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0048] In describing some embodiments, the terms "electrical connection" and "connection" and their derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. The term "electrical connection," for example, indicates that two or more components have direct physical or electrical contact. The terms "electrical connection" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0049] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0050] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0051] As used herein, depending on the context, the term “if” may optionally be interpreted as meaning “when”, “in the event of”, “in response to determination”, or “in response to detection”. Similarly, depending on the context, the phrase “if it is determined that…” or “if [the stated condition or event] is detected” may optionally be interpreted as meaning “in the event of determination that…”, “in response to determination that…”, “when [the stated condition or event] is detected”, or “in response to the detection of [the stated condition or event]”.

[0052] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0053] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0054] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0055] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equal items less than or equal to 5% of either one.

[0056] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0057] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0058] As shown in FIG1, some embodiments of the present disclosure provide a display device 1000, which can be any device that displays images, whether moving (e.g., video) or fixed (e.g., still images) and whether it is text or images.

[0059] For example, the display device 1000 may be any one of the following: monitor, television, billboard, digital photo frame, laser printer with display function, telephone, mobile phone, personal digital assistant (PDA), digital camera, portable camcorder, viewfinder, navigator, large-area wall, home appliance, information query device (such as business query device for e-government, bank, hospital, power and other departments), monitor, electronic display screen, virtual reality (VR) display device, augmented reality (AR) display device and vehicle display, but is not limited thereto.

[0060] For example, the display device 1000 can be an electroluminescent display device or a photoluminescent display device. When the display device 1000 is an electroluminescent display device, it can be an organic light-emitting diode (OLED) display device or a quantum dot light-emitting diode (QLED) display device. When the display device 1000 is a photoluminescent display device, it can be a quantum dot photoluminescent display device.

[0061] The display device 1000 can also be a micro light-emitting diode (Micro LED) display device or a mini light-emitting diode (Mini LED) display device.

[0062] The following uses an organic light-emitting diode (OLED) display device as an example to illustrate some embodiments of the present disclosure. However, the implementation of the present disclosure includes, but is not limited to, these embodiments. Any other display device can also be considered as long as the same technical concept is applied.

[0063] For example, as shown in FIG2, the display device 1000 includes a display panel 100, a driving circuit board 200, a housing 300, and a cover plate 400.

[0064] The display panel 100 has a light-emitting side 100A and a non-light-emitting side 100B. The light-emitting side 100A refers to the side of the display panel 100 that can emit light (the upper side of the display panel 100 in Figure 2), and the non-light-emitting side 100B refers to the other side opposite to the light-emitting side 100A (the lower side of the display panel 100 in Figure 2).

[0065] The driving circuit board 200 is located on the non-light-emitting side of the display panel 100 and is connected to the display panel 100 to provide light-emitting signals to the display panel 100.

[0066] The housing 300 can be a box-shaped structure with an opening. The display panel 100 and the driving circuit board 200 can be disposed inside the housing 300. The cover plate 400 is disposed on the light-emitting side of the display panel 100 and is located at the opening of the housing 300.

[0067] As shown in Figure 2, the longitudinal section of the housing 300 can be U-shaped, for example. The display panel 100 and the driving circuit board 200 are disposed inside the housing 300, and the cover plate 400 is disposed at the opening of the housing 300.

[0068] In some embodiments, as shown in FIG3, FIG3 is a structural diagram of a display panel 100 according to some embodiments. The display panel 100 may be a rectangular structure.

[0069] It should be noted that the aforementioned "rectangular structure" refers to the fact that the overall shape of the boundary of the display panel 100 is rectangular, but it is not limited to a standard rectangle. That is, the "rectangle" here includes not only the shape of a standard rectangle, but also shapes similar to rectangles, taking into account manufacturing conditions. For example, as shown in Figure 3, the long and short sides of the rectangle are curved at each intersection point (i.e., at the corner G), meaning that the corner G is smooth, making the boundary of the display panel 100 a rounded rectangle in the plan view.

[0070] In other embodiments, the display panel 100 may be a circular structure or other shapes with corners. The embodiments disclosed herein are not limited to this.

[0071] The following uses a rectangular structure for the display panel 100 as an example to illustrate some embodiments of the present disclosure. However, the implementation of the present disclosure includes, but is not limited to, this, and the shape of the display panel 100 can also be any other shape.

[0072] In some embodiments, please continue to refer to FIG3, the display panel 100 has a display area AA for displaying images and a peripheral area AN located on at least one side of the display area AA.

[0073] For example, the peripheral area AN of the display panel 100 may be located on one side of the display area AA of the display panel 100.

[0074] Alternatively, the peripheral area AN of the display panel 100 may be located on opposite sides of the display area AA of the display panel 100.

[0075] Alternatively, please refer to Figure 3, where the peripheral area AN of the display panel 100 can surround the display area AA of the display panel 100.

[0076] It should be noted that the specific arrangement of the peripheral area AN of the display panel 100 is related to the specific design of the display panel 100 and can be designed according to actual needs. This is only an example and is not intended to limit this disclosure.

[0077] For example, the peripheral area AN of the display panel 100 may contain a gate driver circuit (e.g., Gate driver On Array, GOA), control signal lines (e.g., clock signal lines, power supply voltage signal lines, etc.), and a bonding driver chip (e.g., a source driver IC, SDC). However, the functions of the peripheral area AN of the display panel 100 include, but are not limited to, these.

[0078] In some embodiments, as shown in Figures 3 and 4, the display panel 100 includes a substrate 10 and a plurality of sub-pixels 20. The plurality of sub-pixels 20 are disposed in a display area AA, and the sub-pixel 20 is the smallest light-emitting unit within the display area AA.

[0079] The substrate 10 may be made of polymer resin or glass.

[0080] For example, the substrate 10 may be flexible, and the material used for the substrate 10 includes a polymer resin, such as one of polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenyl sulfide granula (PPS), polyimide (PI), polycarbonate (PC), and cellulose acetate propionate (CAP).

[0081] Alternatively, the substrate 10 may be rigid, including a glass material containing SiO2 as the main component.

[0082] As shown in Figure 3, multiple sub-pixels 20 are disposed on the substrate 10. These sub-pixels 20 can be arranged, for example, in multiple columns along a first direction X and multiple rows along a second direction Y. Each row of sub-pixels 20 includes multiple sub-pixels 20 arranged sequentially along the first direction X. Each column of sub-pixels 20 includes multiple sub-pixels 20 arranged sequentially along the second direction Y.

[0083] For example, the first direction X intersects the second direction Y. Here, the angle between the first direction X and the second direction Y can be selected and set according to actual needs. For example, the angle between the first direction X and the second direction Y can be 85°, 88°, or 90°, etc.

[0084] In some examples, multiple sub-pixels 20 within the display area AA of the display panel 100 can emit light of the same color. The display panel 100 may also include a color filter layer disposed on the light-emitting side of the multiple sub-pixels 20. For example, the multiple sub-pixels 20 may emit light of colors such as white, red, green, or blue. In this case, the colored light emitted by the sub-pixels 20 may remain the same color after passing through the color filter layer, or be converted into other colors before being emitted. Thus, when the multiple sub-pixels 20 emit light of the same color, the display panel 100 can achieve multi-color light emission.

[0085] In other examples, multiple sub-pixels 20 within the display area AA of the display panel 100 emit light of different colors. For example, the multiple sub-pixels 20 may include sub-pixels of at least three colors. Specifically, the multiple sub-pixels 20 include a first sub-pixel emitting light of a first color, a second sub-pixel emitting light of a second color, and a third sub-pixel emitting light of a third color, thereby achieving multi-color light emission from the display panel 100. The first, second, and third colors are three primary colors. For example, the first color may be red, the second color blue, and the third color green; however, this embodiment does not impose specific limitations.

[0086] For example, the display panel 100 also includes multiple signal lines electrically connected to multiple sub-pixels 20.

[0087] In some embodiments, as shown in Figures 3 and 4, each sub-pixel 20 includes a plurality of pixel circuits 21 and a plurality of light-emitting devices 22 disposed on the substrate 10. The plurality of light-emitting devices 22 are located on the side of the plurality of pixel circuits 21 away from the substrate 10. One pixel circuit 21 is connected to at least one light-emitting device 22.

[0088] The pixel circuit 21 may include multiple transistors 211 and a storage capacitor 212 (Ct).

[0089] The transistors used in the circuits provided in the embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. In the embodiments of this disclosure, thin-film transistors are used as an example for illustration.

[0090] For example, transistor 211 is an oxide thin-film transistor, which has a higher carrier mobility, thus improving the response speed of transistor 211.

[0091] The pixel circuit 21 described above has various structures, which can be selected and configured according to actual needs. For example, the structure of the pixel circuit 21 may include "2T1C", "3T1C", "6T1C", "7T1C", "6T2C" or "7T2C", etc. Here, "T" represents transistor 211, and the number before "T" indicates the number of transistors 211; "C" represents storage capacitor 212, and the number before "C" indicates the number of storage capacitors 212.

[0092] For example, pixel circuits 21 and light-emitting devices 22 can be electrically connected in a one-to-one correspondence. In other examples, one pixel circuit 21 can be electrically connected to multiple light-emitting devices 22, or multiple pixel circuits 21 can be electrically connected to one light-emitting device 22.

[0093] The present disclosure will now illustrate the structure of the display panel 100 by taking the example of an electrical connection between a pixel circuit 21 and a light-emitting device 22.

[0094] For example, in the display panel 100, the pixel circuit 21 can generate a driving signal. Each light-emitting device 22 can emit light under the driving action of the driving signal generated by the corresponding pixel circuit 21. The light emitted by multiple light-emitting devices 22 cooperates with each other, thereby enabling the display panel 1000 to realize the display function.

[0095] For example, when the display device 1000 is an organic light-emitting diode (OLED) display device, the display panel 100 in the display device 1000 is an organic light-emitting diode (OLED) display panel, and the light-emitting device 22 in the display panel 100 can be an OLED light-emitting device.

[0096] For example, as shown in FIG4, the light-emitting device 22 includes a first electrode 221, a light-emitting portion 222, and a second electrode 223 sequentially stacked along a direction away from the substrate 10.

[0097] For example, one of the first electrode 221 and the second electrode 223 can serve as the anode of the light-emitting device 22, and the other can serve as the cathode of the light-emitting device 22.

[0098] For example, the first electrode 221 can serve as the anode of the light-emitting device 22, and the second electrode 223 can serve as the cathode of the light-emitting device 22. Alternatively, the first electrode 221 can serve as the cathode of the light-emitting device 22, and the second electrode 223 can serve as the anode of the light-emitting device 22. In the embodiments of this disclosure, the example of the first electrode 221 serving as the anode of the light-emitting device 22 and the second electrode 223 serving as the cathode of the light-emitting device 22 will be described. The first electrode 221 of the light-emitting device 22 can be illustrated, for example, by being electrically connected to a transistor among the plurality of transistors 211 that serves as a driving transistor.

[0099] In some examples, where the second electrode 223 serves as the cathode of the light-emitting device 22, the second electrodes 223 of multiple light-emitting devices 22 can be interconnected to form a continuous film structure.

[0100] The first electrode 221 is configured to inject holes into the light-emitting part 222. The second electrode 223 is configured to inject electrons into the light-emitting part 222. When a voltage is applied to the first electrode 221 and the second electrode 223 respectively, an electric field can be generated between the first electrode 221 and the second electrode 223. This electric field can drive electrons and holes to move and recombine in the light-emitting part 222 to form excitons. The excitons emit light through radiative transitions, thus producing a light emission phenomenon, i.e., electroluminescence.

[0101] Specifically, the pixel circuit 21 transmits a driving signal to the first electrode 221 of the light-emitting device 22. This driving signal can cooperate with the second voltage signal VSS provided by the second voltage signal terminal VSS, which is electrically connected to the second electrode 223 of the light-emitting device 22, thereby driving the light-emitting device 22 to emit light normally.

[0102] For example, the material of the first electrode 221 may include metallic materials, such as any one or more of magnesium (Mg), silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo).

[0103] For example, the material used to form the first electrode 221 may also include an alloy of the aforementioned metallic materials, such as an aluminum-neodymium alloy (AlNd) or a molybdenum-niobium alloy (MoNb).

[0104] For example, the first electrode 221 may be a single-layer structure.

[0105] Alternatively, the first electrode 221 can also be a multilayer composite structure. For example, the first electrode 221 can be a Ti / Al / Ti structure, etc. Another example is that the first electrode 221 can be a stacked structure formed of metallic materials and transparent conductive materials, such as ITO / Ag / ITO, Mo / AlNd / ITO, etc.

[0106] For example, the material used to form the second electrode 223 may include any one or more of magnesium (Mg), silver (Ag), aluminum (Al), etc.

[0107] For example, the material used to form the second electrode 223 may also include alloys made of any one or more of magnesium (Mg), silver (Ag), aluminum (Al), etc.

[0108] For example, the material used to form the second electrode 223 may also include a transparent conductive material, such as indium tin oxide (ITO).

[0109] For example, the light-emitting portion 222 described above may include an electroluminescent (EL) layer. In other examples, the light-emitting portion 222 may include, in addition to the EL layer, one or more of an electron transport layer (ETL), an electron injection layer (EIL), a hole transport layer (HTL), and a hole injection layer (HIL). When the display panel 100 is an organic electroluminescent display panel, the EL layer is an organic EL layer. When the display panel 100 is a quantum dot electroluminescent display panel, the EL layer is a quantum dot EL layer.

[0110] In some embodiments, as shown in FIG4, the display panel 100 further includes an encapsulation layer 30. The encapsulation layer 30 is disposed on the side of the plurality of sub-pixels 20 away from the substrate 10, and the encapsulation layer 30 is used to encapsulate the light-emitting device 22 to improve the service life of the light-emitting device 22. The encapsulation layer 30 can be an encapsulation film or an encapsulation substrate, and the embodiments disclosed herein are not specifically limited thereto.

[0111] For example, the encapsulation layer 30 may include a single encapsulation film, or it may include two or more encapsulation films stacked together. For instance, as shown in FIG4, the encapsulation layer 30 includes a first inorganic encapsulation layer 31, a first organic encapsulation layer 32, and a second inorganic encapsulation layer 33 stacked along a direction perpendicular to and away from the substrate 10. The materials of the first inorganic encapsulation layer 31 and the second inorganic encapsulation layer 33 include any one or more of silicon nitride, silicon oxynitride, or silicon oxide. The material of the first organic encapsulation layer 32 includes a polymer resin, such as polyimide.

[0112] For example, the display device 1000 may include a high pixel density (pixels per inch, or PPI) display device and a low pixel density display device. The high PPI display device is suitable for close-range viewing, such as mobile phones, tablets, and laptops; the low PPI display device is suitable for long-distance viewing, for example, the low PPI display device 1000 is used in high-end business video conferencing, exhibition halls, classrooms, and other splicing display applications.

[0113] When the display device 1000 is used for viewing at a distance, a high contrast ratio and a high display brightness are required.

[0114] The brightness of the light-emitting device 22 is positively correlated with the driving current provided by the pixel circuit 21 connected to it. That is, the greater the driving current provided by the pixel circuit 21, the brighter the light-emitting device 22 connected to the pixel circuit 21, and the higher the contrast of the displayed image on the display panel 100.

[0115] In addition, to improve product reliability and reduce transportation and maintenance costs, larger display devices can be assembled by splicing together multiple smaller display devices.

[0116] For example, taking display device 1000 as a splicing display device, relevant tests and simulations show that when low-PPI display devices and high-PPI display devices achieve the same brightness, the driving current required by the low-PPI display device is in the microampere range of 10. -6 A is hundreds or thousands of times the drive current required by high PPI display devices.

[0117] In other words, when the display device 1000 is used for viewing at a distance, the light-emitting device 22 requires a higher driving current in order to achieve high brightness and high contrast of the displayed image on the display panel 100. When the driving current of the light-emitting device 22 is low, the display device 1000 is prone to uneven display at low gray levels, which affects the user's viewing experience.

[0118] Based on this, in the embodiments of this disclosure, a pixel circuit 21 is provided. As shown in FIG5, the pixel circuit 21 includes a main light-emitting path 210. The main light-emitting path 210 refers to the branch that is conducted in the pixel circuit 21 during the light-emitting stage. The main light-emitting path 210 is electrically connected to the light-emitting device 22, and the main light-emitting path 210 is configured to provide a driving current to the light-emitting device 22 to cause the light-emitting device 22 to emit light.

[0119] For example, as shown in FIG5, the first end 210a of the main light-emitting path 210 is connected to the first voltage terminal VDD, and the second end 210b of the main light-emitting path 210 is connected to the light-emitting device 22. The main light-emitting path 210 includes at least two first transistors T1 connected between the first end 210a and the second end 210b, and the at least two first transistors T1 are connected in series. The at least two first transistors T1 include a driving transistor TD and at least one light-emitting control transistor TL. The at least one first transistor T1 includes two gates, and the two gates are connected to form the control terminal of the first transistor T1.

[0120] For example, during the light-emitting phase, the driving current is transmitted to the light-emitting device 22 through the driving transistor TD and at least one light-emitting control transistor TL.

[0121] For example, the main light-emitting path 210 may include two or more first transistors T1. The embodiments of this disclosure are not limited in this respect. For instance, as shown in FIG5, the main light-emitting path 210 includes three first transistors T1.

[0122] In some examples, in at least two first transistors T1, a portion of the first transistors T1 includes two gates. When a portion of the first transistors T1 includes two gates, it can be that the driving transistor TD includes two gates, or that the light-emitting control transistor TL includes two gates; alternatively, both the driving transistor TD and at least one light-emitting control transistor TL may include two gates.

[0123] In other examples, in at least two first transistors T1, each first transistor T1 includes two gates, as shown in Figure 5. One gate can serve as the bottom gate of the first transistor T1, and the other gate can serve as the top gate of the first transistor T1.

[0124] It is understood that the above-mentioned at least one first transistor T1 includes two gates, and the two gates are connected to form the control terminal of the first transistor T1. That is, the at least one first transistor T1 is a dual-gate transistor, and the two gates of the dual-gate transistor are connected.

[0125] In some examples, the on-state current of a single-gate transistor and a dual-gate transistor is verified when the bottom gate voltages of the single-gate transistor and multiple dual-gate transistors are different.

[0126] The test results are shown in Figures 6 and 7. Figure 6 is a schematic diagram showing the on-state current of a single-gate transistor and multiple dual-gate transistors (where the bottom gate voltages of the multiple dual-gate transistors are different) as a function of the voltages they receive. In Figure 6, the horizontal axis represents voltage (Voltage (V)) and the vertical axis represents current Ion (Current (A)).

[0127] As shown in Figures 6 and 7, when the voltage received by the bottom gate of the dual-gate transistor is 4.6V, the on-state current Ion of the dual-gate transistor is slightly low; when the bottom gate voltage received by the dual-gate transistor decreases from 4.6V to -4.4V, the on-state current Ion of the dual-gate transistor increases from 5.74μA to 15.2μA, which is a 2.64-fold increase.

[0128] As can be seen from the above, the on-state current of a transistor and the output current value of the transistor during operation are positively correlated. When the bottom gate voltage received by the dual-gate transistor decreases from 4.6V to -4.4V, the output capability of the dual-gate transistor increases by 2.64 times.

[0129] Furthermore, in some examples, the on-state currents of the single-gate and dual-gate transistors are verified when the voltages received by the single-gate and dual-gate transistors are different. Here, the voltages received by the single-gate and dual-gate transistors refer to the voltages received at the first terminal (input terminal) of the single-gate and dual-gate transistors. Specifically, the voltage received by the bottom gate of the dual-gate transistor is set to -4.6V.

[0130] It is understandable that the on-state current of a transistor is positively correlated with its output current during operation. That is, the larger the on-state current of the transistor, the larger the output current during operation.

[0131] The test results are shown in Figure 8, which is a schematic diagram of the output current of the dual-gate transistor changing with the voltage received by the bottom gate. The horizontal axis represents the voltage received by the bottom gate (Gate Voltage (V)), and the vertical axis represents the current (Current (A)). In Figure 8, DTFT refers to the driving transistor; TFT refers to the switching transistor (e.g., the first light-emitting control transistor TL1 and the second light-emitting control transistor TL2 mentioned below).

[0132] Compared to a single-gate transistor, a dual-gate transistor has a larger on-state current. In other words, a dual-gate transistor outputs a larger current, and its output capability is higher than that of a single-gate transistor.

[0133] As shown in Figure 8, the on-state current of the dual-gate transistor increases as the voltage received by the bottom gate of the dual-gate transistor decreases.

[0134] In this embodiment, at least one of the driving transistor TD and at least one light-emitting control transistor TL in the main light-emitting path 210 includes two gates, and the two gates are connected to form the control terminal of the first transistor. That is, at least one of the driving transistor TD and at least one light-emitting control transistor TL in the main light-emitting path 210 is set as a dual-gate transistor. Compared with a single-gate transistor, a dual-gate transistor has two gates and two channels. When the driving current is transmitted in the main light-emitting path 210, it will pass through the channel region of the transistor. Using a dual-gate transistor is equivalent to increasing the output channel of the driving current, reducing the transmission time of the driving current, which is beneficial to improving the transmission efficiency of the driving current and reducing the power consumption of the pixel circuit 21. Moreover, by increasing the output channel of the driving current, it is also beneficial to increase the output current and improve the driving capability of the pixel circuit 21 for the light-emitting device, thereby improving the brightness of the light-emitting device 22. When the pixel circuit 21 is applied in a display device, it can improve the contrast and brightness of the display panel 100, and improve the user's viewing experience. Moreover, when the two gates of a dual-gate transistor are connected and the two gates maintain the same electrical signal, the transistor's output current can be further increased by about 200%.

[0135] In some embodiments, as shown in FIG5 and FIG9, the main light-emitting path 210 includes at least two control units Q connected in series between the first end 210a and the second end 210b. Each control unit Q includes a first transistor T1; at least one control unit Q also includes at least one second transistor T2, and the first transistor T1 and at least one second transistor T2 of the same control unit Q are connected in parallel.

[0136] For example, the number of control units Q included in the main light-emitting path 210 can be two, three, or more. The embodiments of this disclosure are not limited in this respect.

[0137] For example, as shown in Figures 5 and 9, the main light-emitting path 210 includes three control units Q; the three control units Q are the first control unit Q1, the second control unit Q2, and the third control unit Q3, which are connected in series.

[0138] In some examples, at least one of the at least two control units Q further includes at least one second transistor T2. In other examples, each of the at least two control units Q further includes at least one second transistor T2, as shown in Figure 9.

[0139] For example, in the same control unit Q, the number of second transistors T2 connected in parallel with the first transistor T1 is 'a'. For instance, the number of second transistors T2 connected in parallel with the first transistor T1 in the same control unit Q, 'a', can be 1, 2, 3, 4, 5, etc. The embodiments of this disclosure do not limit this.

[0140] For example, in the same control unit Q, the first terminal of the second transistor T2, which is connected in parallel with the first transistor T1, is connected to the same signal terminal as the first terminal of the first transistor T1; the second terminal of the second transistor T2, which is connected in parallel with the first transistor T1, is connected to the same signal terminal as the second terminal of the first transistor T1; and the control terminal of the second transistor T2, which is connected in parallel with the first transistor T1, is connected to the same signal terminal as the control terminal of the first transistor T1.

[0141] For example, as shown in Figure 9, the first control unit Q1 includes at least one second transistor T2 connected in parallel with a first transistor T1. In the first control unit Q1, the first terminals of the plurality of second transistors T2 and the first transistor T1 are both connected to a first voltage terminal VDD; the second terminals of the plurality of second transistors T2 and the second terminals of the first transistor T1 are both connected to a second node N2 and to the input terminal of the first control unit Q2; the control terminals of the plurality of second transistors T2 and the first transistor T1 are both connected to an enable signal terminal EM. In the first control unit Q1, the plurality of second transistors T2 and the first transistor T1 can simultaneously conduct under the control of the voltage signal received at the enable signal terminal EM.

[0142] For example, as shown in Figure 9, the second control unit Q2 includes at least one second transistor T2 connected in parallel with a first transistor T1. In the second control unit Q2, the first terminals of multiple second transistors T2 and the first terminal of the first transistor T1 are both connected to the second node N2; the second terminals of multiple second transistors T2 and the second terminal of the first transistor T1 are both connected to the third node N3 and to the input terminal of the third control unit Q3; the control terminals of multiple second transistors T2 and the first transistor T1 are both connected to the first node N1. In the second control unit Q2, multiple second transistors T2 and the first transistor T1 can simultaneously conduct under the control of the voltage signal at the first node N1.

[0143] For example, as shown in Figure 9, the third control unit Q3 includes at least one second transistor T2 connected in parallel with a first transistor T1. In the third control unit Q3, the first terminals of the plurality of second transistors T2 and the first terminal of the first transistor T1 are all connected to the third node N3; the second terminals of the plurality of second transistors T2 and the second terminal of the first transistor T1 are all connected to the light-emitting device 22; and the control terminals of the plurality of second transistors T2 and the first transistor T1 are all connected to the enable signal terminal EM. In the third control unit Q3, the plurality of second transistors T2 and the first transistor T1 can be simultaneously turned on under the control of the voltage signal received at the enable signal terminal EM.

[0144] It is understandable that the upper limit of the on-state current of the first transistor T1 may limit the maximum output current of the pixel circuit 21. In this embodiment, among the control units Q included in the main light-emitting path 210, at least one control unit Q is formed by at least one second transistor T2 connected in parallel with the first transistor T1. During the operation of the pixel circuit 21, the first transistor T1 and at least one second transistor T2 in this control unit Q can be turned on simultaneously. The first transistor T1 and at least one second transistor T2 can simultaneously provide driving current to the light-emitting device 22, so that the upper limit of the output current of the control unit Q is not limited by the upper limit of the on-state current of the first transistor T1. This allows the pixel circuit 21 to output a larger current, thereby improving the driving capability of the pixel circuit 21 to the light-emitting device, thereby improving the contrast and brightness of the display screen 100 and improving the user's viewing experience. For example, if the number of second transistors T2 connected in parallel with the first transistor T1 in the same control unit Q is a, the output current of the control unit Q can be increased to 2a times the original.

[0145] In some embodiments, as shown in FIG9, the second transistor T2 includes two gates, which are connected to form the control terminal of the second transistor T2.

[0146] As can be seen from the above, compared with a single-gate transistor, a dual-gate transistor has a larger on-state current and a larger output current when the transistor is working, under the condition of a certain received voltage.

[0147] In this embodiment, by configuring the second transistor T2, which is connected in parallel with the first transistor T1 in at least one control unit Q, as a dual-gate transistor, and connecting the two gates to form the control terminal of the second transistor T2, the dual-gate transistor, compared to a single-gate transistor, has two gates and two channels. When the driving current is transmitted in the main light-emitting path 210, it passes through the channel region of the transistor. Using a dual-gate transistor is equivalent to increasing the output channel of the driving current, thereby further improving the output capability of at least one control unit Q, improving the driving capability of the pixel circuit 21 for the light-emitting device, thereby improving the contrast and brightness of the display screen 100, and improving the user's viewing experience. Moreover, when the two gates of the dual-gate transistor are connected and the two gates maintain the same electrical signal, the output current of the transistor can be further increased by about 200%.

[0148] In some embodiments, as shown in FIG5, the driving transistor TD includes two gates connected to each other.

[0149] For example, the two gates of the driving transistor TD are a first gate and a second gate, and the first gate and the second gate of the driving transistor TD are located on both sides of the active layer of the driving transistor TD. The overlapping area of ​​the first gate of the driving transistor TD and the active layer of the driving transistor TD forms the first channel of the driving transistor TD; the overlapping area of ​​the second gate of the driving transistor TD and the active layer of the driving transistor TD forms the second channel of the driving transistor TD, thereby making the driving transistor TD have a dual channel.

[0150] For example, the two gates of the driving transistor TD are connected to form the control terminal of the driving transistor TD.

[0151] For example, the first terminal of the driving transistor TD is connected to the second node N2, the second terminal of the driving transistor TD is connected to the third node N3, and the control terminal of the driving transistor TD is connected to the first node N1, resulting in a simple structure. The driving transistor TD is configured to control the conduction and cutoff of the circuit between the second node N2 and the third node N3 under the control of the voltage of the first node N1; and to generate a grayscale current signal based on the voltage of the first node N1 and the voltage of the second node N2.

[0152] In this embodiment, the two gates of the driving transistor TD are connected to form the control terminal of the driving transistor TD. Thus, during the light-emitting stage, when the driving current is transmitted in the main light-emitting path 210, it will pass through the two channels of the driving transistor TD, thereby effectively increasing the transmission rate of the driving current. Furthermore, by increasing the output channel of the driving current, it is also beneficial to increase the output current and improve the driving capability of the pixel circuit 21 for the light-emitting device, thereby improving the brightness of the light-emitting device 22. When the pixel circuit 21 is applied in a display device, it can improve the contrast and brightness of the display screen 100, thereby improving the user's viewing experience.

[0153] In some embodiments, as shown in FIG9, at least one second transistor T2 is connected in parallel with the driving transistor TD.

[0154] For example, the first terminal of the second transistor T2, which is connected in parallel with the driving transistor TD, and the first terminal of the driving transistor TD are both connected to the second node N2; the second terminal of the second transistor T2, which is connected in parallel with the driving transistor TD, and the second terminal of the driving transistor TD are both connected to the third node N3; the control terminal of the second transistor T2, which is connected in parallel with the driving transistor TD, and the control terminal of the driving transistor TD are both connected to the first node N1. The second transistor T2 and the driving transistor TD, which are connected in parallel with the driving transistor TD, can be turned on simultaneously under the control of the voltage signal of the first node N1; and the second transistor T2 and the driving transistor TD, which are connected in parallel with the driving transistor TD, are configured to transmit the voltage of the second node N2 to the third node N3.

[0155] For example, the second transistor T2, which is connected in parallel with the driving transistor TD, can have approximately the same channel width-to-length ratio as the driving transistor TD.

[0156] For example, the channel width-to-length ratio of the driving transistor TD is A1, and the channel width-to-length ratio of the second transistor T2 connected in parallel with the driving transistor TD is A2. The fact that the channel width-to-length ratio of the second transistor T2 connected in parallel with the driving transistor TD is approximately the same as that of the driving transistor TD can be understood as |A1-A2| / A2 being less than or equal to 10%.

[0157] It should be noted that in the pixel circuit 21 shown in Figure 9, the two second transistors T2 are connected in parallel with the driving transistor TD. It should be understood that in other examples, the number of second transistors T2 connected in parallel with the driving transistor TD can also be 1, 3, 4, 5, etc.

[0158] During the operation of the pixel circuit 21, driving current can be supplied to the light-emitting device 22 simultaneously through the driving transistor TD and the second transistor T2 connected in parallel with it.

[0159] It is understandable that the upper limit of the on-state current of the driving transistor TD may limit the maximum output current of the pixel circuit 21. In this embodiment, by setting at least one second transistor T2 in parallel with the driving transistor TD, the driving current can be simultaneously provided to the light-emitting device 22 through at least one second transistor T2 and the driving transistor TD. This allows the upper limit of the output current of the pixel circuit 21 to be unrestricted by the upper limit of the on-state current of the driving transistor TD, enabling the pixel circuit 21 to output a larger current. This improves the driving capability of the pixel circuit 21 to the light-emitting device 22, thereby improving the contrast and brightness of the displayed image on the display panel 100 and enhancing the user's viewing experience.

[0160] In some embodiments, as shown in Figures 5 and 9, at least two first transistors T1 include a first light-emitting control transistor TL1 and a second light-emitting control transistor TL2. A first terminal of the first light-emitting control transistor TL1 is connected to a first voltage terminal VDD, a second terminal of the first light-emitting control transistor TL1 is connected to a second node N2 (the first terminal of the driving transistor TD), a third node N3 (the second terminal of the driving transistor TD) is connected to the first terminal of the second light-emitting control transistor TL2, and a second terminal of the second light-emitting control transistor TL2 is connected to the light-emitting device 22. The first light-emitting control transistor TL1 includes two gates connected to each other; and / or, the second light-emitting control transistor TL2 includes two gates connected to each other. The first and second light-emitting control transistors TL1 and TL2 are configured to cooperate with the driving transistor TD to transmit a drive current signal to the light-emitting device 22.

[0161] For example, the two gates of the first light-emitting control transistor TL1 are connected to form the control terminal of the first light-emitting control transistor TL1; the two gates of the second light-emitting control transistor TL2 are connected to form the control terminal of the second light-emitting control transistor TL2.

[0162] In some examples, the first light-emitting control transistor TL1 includes two gates connected together. In another example, the second light-emitting control transistor TL2 includes two gates connected together. In still other examples, both the first light-emitting control transistor TL1 and the second light-emitting control transistor TL2 include two gates connected together.

[0163] For example, as shown in Figures 5 and 9, in the main light-emitting path 210, the driving transistor TD, the first light-emitting control transistor TL1, and the second light-emitting control transistor TL2 are all dual-gate transistors, and each transistor has two channels.

[0164] With the above configuration, during the light-emitting stage, when the driving current is transmitted in the main light-emitting path 210, it passes through the two channels of each transistor, including the driving transistor TD, the first light-emitting control transistor TL1, and the second light-emitting control transistor TL2. This effectively increases the transmission rate of the driving current. Furthermore, by increasing the output channel of the driving current, it is also beneficial to increase the output current and improve the driving capability of the pixel circuit 21 for the light-emitting device. This, in turn, helps to improve the brightness of the light-emitting device 22. When the pixel circuit 21 is applied in a display device, it can improve the contrast and brightness of the display screen 100, thereby enhancing the user's viewing experience.

[0165] It is understandable that, for ease of distinction, the second transistor T2, which is connected in parallel with the first light-emitting control transistor TL1, is defined as the third transistor T3; and the second transistor T2, which is connected in parallel with the second light-emitting control transistor TL2, is defined as the fourth transistor T4.

[0166] In some embodiments, as shown in FIG9, at least one third transistor T3 is connected in parallel with the first light-emitting control transistor TL1; and / or, at least one fourth transistor T4 is connected in parallel with the second light-emitting control transistor TL2.

[0167] In some examples, at least one third transistor T3 is connected in parallel with the first light-emitting control transistor TL1.

[0168] For example, the first terminal of the third transistor T3, which is connected in parallel with the first light-emitting control transistor TL1, is connected to the first terminal of the first light-emitting control transistor TL1 and to the first voltage terminal VDD; the second terminal of the third transistor T3, which is connected in parallel with the first light-emitting control transistor TL1, is connected to the second terminal of the first light-emitting control transistor TL1 and to the second node N2 (the first terminal of the driving transistor TD); the control terminal of the third transistor T3, which is connected in parallel with the first light-emitting control transistor TL1, is connected to the control terminal of the first light-emitting control transistor TL1 and to the same enable signal terminal EM. The first light-emitting control transistor TL1 and the third transistor T3, which are connected in parallel with the first light-emitting control transistor TL1, can be turned on simultaneously under the control of the signal at the enable signal terminal EM; and the first light-emitting control transistor TL1 and the third transistor T3, which are connected in parallel with the first light-emitting control transistor TL1, are configured to control the on and off states between the first voltage terminal VDD and the first terminal of the driving transistor TD in response to the signal received at the enable signal terminal EM.

[0169] For example, the third transistor T3, which is connected in parallel with the first light-emitting control transistor TL1, may have approximately the same channel width-to-length ratio as the first light-emitting control transistor TL1.

[0170] It should be noted that in the pixel circuit 21 shown in Figure 9, the two third transistors T3 are connected in parallel with the first light-emitting control transistor TL1. It should be understood that in other examples, the number of third transistors T3 connected in parallel with the first light-emitting control transistor TL1 can also be 1, 3, 4, 5, etc.

[0171] In other examples, at least one fourth transistor T4 is connected in parallel with a second light-emitting control transistor TL2.

[0172] For example, the first terminal of the fourth transistor T4, which is connected in parallel with the second light-emitting control transistor TL2, is connected to the first terminal of the second light-emitting control transistor TL2 and to the second terminal of the driving transistor TD; the second terminal of the fourth transistor T4, which is connected in parallel with the second light-emitting control transistor TL2, is connected to the second terminal of the second light-emitting control transistor TL2 and to the light-emitting device 22; the control terminal of the fourth transistor T4, which is connected in parallel with the second light-emitting control transistor TL2, is connected to the control terminal of the second light-emitting control transistor TL2 and to the same enable signal terminal EM. The second light-emitting control transistor TL2 and the fourth transistor T4, which are connected in parallel with the second light-emitting control transistor TL2, can be turned on simultaneously under the control of the signal at the enable signal terminal EM; and the second light-emitting control transistor TL2 and the fourth transistor T4, which are connected in parallel with the second light-emitting control transistor TL2, are configured to control the conduction and cutoff between the second terminal of the driving transistor TD and the anode of the light-emitting device 22 in response to the signal received at the enable signal terminal EM.

[0173] For example, the fourth transistor T4, which is connected in parallel with the second light-emitting control transistor TL2, can have approximately the same channel width-to-length ratio as the second light-emitting control transistor TL2.

[0174] It should be noted that in the pixel circuit 21 shown in Figure 9, the two fourth transistors T4 are connected in parallel with the second light-emitting control transistor TL2. It should be understood that in other examples, the number of fourth transistors T4 connected in parallel with the second light-emitting control transistor TL2 can also be 1, 3, 4, 5, etc.

[0175] Furthermore, the enable signal terminal EM connected to the control terminal of the first light-emitting control transistor TL1 and the third transistor T3 connected in parallel with the first light-emitting control transistor TL1, and the enable signal terminal EM connected to the control terminal of the second light-emitting control transistor TL2 and the fourth transistor T4 connected in parallel with the second light-emitting control transistor TL2, can be the same enable signal terminal EM. That is, the first light-emitting control transistor TL1, the third transistor T3 connected in parallel with the first light-emitting control transistor TL1, the second light-emitting control transistor TL2, and the fourth transistor T4 connected in parallel with the second light-emitting control transistor TL2 can be turned on simultaneously.

[0176] It should be understood that, in other examples, the enable signal terminal EM connected to the control terminal of the first light-emitting control transistor TL1 and the third transistor T3 connected in parallel with the first light-emitting control transistor TL1, and the enable signal terminal EM connected to the control terminal of the second light-emitting control transistor TL2 and the fourth transistor T4 connected in parallel with the second light-emitting control transistor TL2, may also be different signal terminals.

[0177] In some other examples, as shown in Figure 9, at least one third transistor T3 is connected in parallel with the first light-emitting control transistor TL1, and at least one fourth transistor T4 is connected in parallel with the second light-emitting control transistor TL2.

[0178] For example, the number of third transistors T3 connected in parallel with the first light-emitting control transistor TL1 and the number of fourth transistors T4 connected in parallel with the second light-emitting control transistor TL2 may be equal or unequal. For instance, as shown in FIG9, the number of third transistors T3 connected in parallel with the first light-emitting control transistor TL1 and the number of fourth transistors T4 connected in parallel with the second light-emitting control transistor TL2 are equal.

[0179] For example, as shown in Figure 9, two third transistors T3 are connected in parallel with the first light-emitting control transistor TL1, and two fourth transistors T4 are connected in parallel with the second light-emitting control transistor TL2.

[0180] The inventors of this disclosure have discovered that the upper limit of the on-state current of the first light-emitting control transistor TL1 and the second light-emitting control transistor TL2 may limit the maximum output current of the pixel circuit 21.

[0181] In this embodiment, by setting at least one third transistor T3 in parallel with the first light-emitting control transistor TL1, and at least one fourth transistor T4 in parallel with the second light-emitting control transistor TL2, during the operation of the pixel circuit 21, at least one third transistor T3 and the first light-emitting control transistor TL1 are simultaneously turned on, providing driving current to the light-emitting device 22. This ensures that the driving current of the pixel circuit 21 is not limited by the upper limit of the conducting current of the first light-emitting control transistor TL1. Simultaneously, at least one fourth transistor T4 and the second light-emitting control transistor TL2 are simultaneously turned on, providing driving current to the light-emitting device 22. This ensures that the driving current of the pixel circuit 21 is not limited by the upper limit of the conducting current of the second light-emitting control transistor TL2, allowing the pixel circuit 21 to output a larger current. This improves the driving capability of the pixel circuit 21 to the light-emitting device 22, thereby enhancing the brightness of the light-emitting device 22. When the pixel circuit 21 is applied in the display device 1000, it can improve the contrast and brightness of the displayed image on the display panel 100, thus improving the user's viewing experience.

[0182] In some embodiments, as shown in FIG10, the pixel circuit 21 includes at least two light-emitting main paths 210, the first end 210a of the at least two light-emitting main paths 210 is connected to the first voltage terminal VDD, and the second end 210b of the at least two light-emitting main paths 210 is connected to the light-emitting device 22.

[0183] For example, the pixel circuit 21 may include multiple main light-emitting paths 210. The embodiments of this disclosure are not limited in this respect. For instance, Figure 10 illustrates two main light-emitting paths 210 connected in parallel. It should be understood that in other examples, the number of second transistors T2 connected in parallel with the driving transistor TD may also be 3, 4, 5, 6, etc.

[0184] During the operation of the pixel circuit 21, in the light-emitting stage, at least two main light-emitting paths 210 are simultaneously turned on, providing driving current to the light-emitting device 22. This further increases the driving current of the pixel circuit 21 and improves the driving capability of the pixel circuit 21 to the light-emitting device 22, thereby improving the brightness of the light-emitting device 22. When the pixel circuit 21 is applied to a display device, it can improve the contrast and brightness of the display panel 100, thus improving the user's viewing experience.

[0185] Furthermore, when the number of second transistors T2 connected in parallel with the first transistor T1 of the dual-gate structure is a, and the number of light-emitting main paths 210 connected in parallel is b, the output current of the pixel circuit 21 can be increased to 2*a*b times the original.

[0186] Furthermore, it should be noted that Figures 5, 9, and 10 only show the main light-emitting path 210 in the pixel circuit 21, and do not show other branches in the pixel circuit 21. However, this is not a limitation, and the pixel circuit 21 provided in the embodiments of this disclosure may also include other branches. For example, the pixel circuit 21 may also include a writing sub-circuit, a compensation sub-circuit, or a reset sub-circuit, etc.

[0187] In some examples, as shown in Figure 11, pixel circuit 21 further includes a compensator circuit 220.

[0188] As shown in Figure 11, the compensation sub-circuit 220 is electrically connected to the first node N1, the third node N3, and the first scan signal terminal Gate1. The compensation sub-circuit 220 is configured to, during the initialization phase, transmit the voltage of the first node N1 to the third node N3 under the control of the scan signal transmitted from the first scan signal terminal Gate1; and during the write phase, transmit the voltage of the third node N3 to the first node N1 under the control of the scan signal transmitted from the first scan signal terminal Gate1.

[0189] For example, as shown in Figure 11, the compensation sub-circuit 220 includes a plurality of fifth transistors T5 connected in series. The control electrode of each fifth transistor T5 is electrically connected to the first scan signal terminal Gate1; among the plurality of fifth transistors T5 connected in series, the first electrode of the first fifth transistor T5 is electrically connected to the first node N1, and the second electrode of the last fifth transistor T5 connected in series is electrically connected to the third node N3; at least two adjacent fifth transistors T5 are connected such that the second electrode of one fifth transistor T5 is connected to the first electrode of the other fifth transistor T5, which can reduce the risk of leakage current from the first node N1 to the compensation sub-circuit 220 and is more conducive to ensuring the voltage stability of the first node N1.

[0190] The number of fifth transistors T5 can be, for example, two, three or more, and the embodiments disclosed herein do not limit this.

[0191] For example, as shown in Figure 11, the compensation sub-circuit 220 includes two fifth transistors T5 connected in series. Of the two fifth transistors T5, the first terminal of one fifth transistor T5 is connected to the third node N3, and its second terminal is connected to the first terminal of the other fifth transistor T5. The second terminal of the other fifth transistor T5 is connected to the first node N1. In this case, by effectively reducing the leakage current between the first node N1 and the third node N3, the compensation sub-circuit 220 includes fewer third transistors T3, which can reduce the area occupied by the pixel circuit 21 and improve the pixel aperture ratio of the display panel 100.

[0192] Furthermore, the fifth transistor T5 can be an oxide thin-film transistor.

[0193] Since oxide thin-film transistors have low leakage current, by setting the fifth transistor T5 as an oxide thin-film transistor, the leakage current of the compensation sub-circuit 220 can be reduced during the data writing and compensation stages, and the leakage current of the first node N1 through the fifth transistor T5 can be avoided, thereby ensuring the compensation effect of the driving transistor TD, ensuring the stability of the voltage of the first node N1, and thus improving the display quality of the display panel 100.

[0194] In some examples, as shown in Figure 11, pixel circuit 21 further includes a write sub-circuit 230.

[0195] As shown in Figure 11, the write sub-circuit 230 is electrically connected to the second node N2, the first scan signal terminal Gate1, and the data signal terminal Data. The write sub-circuit 230 is configured to, during the data writing phase, transmit the data signal received at the data signal terminal Data to the second node N2 under the control of the gate scan signal received from the first scan signal terminal Gate1. Furthermore, the data signal at the second node N2 is compensated before being written to the first node N1 to facilitate the subsequent generation of grayscale current signals by the driving transistor TD21, as detailed below.

[0196] In other examples, the write sub-circuit 230 is also configured to, during the adjustment phase, transmit the data signal received at the data signal terminal Data to the second node N2 under the control of the gate scan signal received from the first scan signal terminal Gate1, so as to reset the second node N2.

[0197] As exemplarily shown in FIG11, the write sub-circuit 230 includes a sixth transistor T6.

[0198] As shown in Figure 11, the gate of the sixth transistor T6 is electrically connected to the first scan signal terminal Gate1; the first terminal of the sixth transistor T6 is electrically connected to the data signal terminal Data; and the second terminal of the sixth transistor T6 is electrically connected to the second node N2.

[0199] For example, when the level of the gate scan signal received at the first scan signal terminal Gate1 is an effective level, the sixth transistor T6 can be turned on under the control of the gate scan signal to transmit the data signal provided by the data signal terminal Data to the second node N2.

[0200] It should be noted that the "effective level" in this disclosure refers to the level that enables the transistor to conduct. When the transistor is an N-type transistor, the "effective level" is high; when the transistor is a P-type transistor, the "effective level" is low. The following embodiments are the same and will not be described again.

[0201] Using the above configuration, during the writing phase, the writing sub-circuit 230 can be turned on under the control of the gate scan signal received at the first scan signal terminal Gate1. In this way, the writing sub-circuit 230 will transmit the data signal received at the data signal terminal Data to the second node N2. The data signal is transformed into a compensation signal after passing through the driving transistor TD. The compensation signal is transmitted to the first node N1 through the compensation sub-circuit 220, that is, the compensation signal writing is completed, and the compensation of the threshold voltage Vth is also realized.

[0202] In some examples, as shown in Figure 11, pixel circuit 21 further includes energy storage sub-circuit 240.

[0203] As shown in Figure 11, the energy storage sub-circuit 240 is electrically connected to the first node N1 and the first voltage terminal VDD. The energy storage sub-circuit 240 is configured to store and maintain the voltage of the first node N1, thus playing a role in voltage stabilization.

[0204] As exemplarily shown in Figure 11, the energy storage sub-circuit 240 includes a first capacitor Cst.

[0205] The first plate of the first capacitor Cst is electrically connected to the first voltage terminal VDD, and the second plate of the first capacitor Cst is electrically connected to the first node N1.

[0206] Therefore, when at least two fifth transistors T5 in the compensation sub-circuit 220 and the sixth transistor T6 in the write sub-circuit 230 are turned on, the compensation sub-circuit 220 also charges the first capacitor Cst during the process of transmitting the data signal received at the data signal terminal Data to the first node N1. After at least two fifth transistors T5 in the compensation sub-circuit 220 are turned off, the first capacitor Cst can discharge to the first node N1, ensuring the potential stability of the first node N1, thereby improving the flicker phenomenon of the display panel 100.

[0207] In some examples, as shown in Figure 11, the pixel circuit 21 further includes a first reset circuit 250.

[0208] As shown in Figure 11, the first reset sub-circuit 250 is electrically connected to the first reset signal terminal RST1, the first initialization signal terminal Vinit1, and the first node N1. The first reset sub-circuit 250 is configured to, under the control of the first reset signal received from the first reset signal terminal RST1, transmit the initialization signal received from the first initialization signal terminal Vinit1 to the first node N1 to reset the voltage of the first node N1, clear the influence of the data signal of the previous frame F on the voltage of the first node N1, improve the afterimage performance, reduce the flicker value of the display panel 100, and improve the problem of flickering of the display screen that can be perceived by the human eye.

[0209] For example, as shown in Figure 11, the first reset sub-circuit 250 includes a plurality of seventh transistors T7 connected in series. The control electrode of each of the seventh transistors T7 is electrically connected to the first reset signal terminal RST1; among the plurality of seventh transistors T7 connected in series, the first electrode of the first seventh transistor T7 is electrically connected to the first initialization signal terminal Vinit1, and the second electrode of the last seventh transistor T7 among at least two seventh transistors T7 is electrically connected to the first node N1; among at least two seventh transistors T7, the second electrode of one seventh transistor T7 is connected to the first electrode of the other seventh transistor T7, which can reduce the risk of leakage current from the first node N1 from the at least two seventh transistors T7, and is more conducive to ensuring the voltage stability of the first node N1.

[0210] The number of seventh transistors T7 can be, for example, two, three or more, and the embodiments disclosed herein do not limit this.

[0211] For example, as shown in Figure 11, the first reset circuit 250 includes two seventh transistors T7 connected in series. One of the seventh transistors T7 has its first terminal electrically connected to the first initialization signal terminal Vinit1, and its second terminal connected to the first terminal of the other seventh transistor T7. The second terminal of the other seventh transistor T7 is also electrically connected to the first node N1. In this case, by effectively reducing the leakage current between the first node N1 and the first initialization signal terminal Vinit1, the first reset circuit 250 includes fewer seventh transistors T7, which can reduce the area occupied by the pixel circuit 21 and improve the pixel aperture ratio of the display panel 100.

[0212] Furthermore, the seventh transistor T7 can be an oxide thin-film transistor.

[0213] Since oxide thin-film transistors have low leakage current, setting the seventh transistor T7 to be an oxide thin-film transistor can reduce the leakage current of the first node N1 in the seventh transistor T7 when the first node N1 is reset and in the off state, thereby making the reset effect of the first node N1 better.

[0214] In some examples, as shown in Figure 11, the pixel circuit 21 further includes a second reset circuit 260.

[0215] The second reset sub-circuit 260 is electrically connected to the second reset signal terminal RST2, the second initialization signal terminal Vinit2, and the light-emitting device 22. The second reset sub-circuit 260 is configured to transmit the initialization signal received from the second initialization signal terminal Vinit2 to the light-emitting device 22 under the control of the second reset signal received from the second reset signal terminal RST2.

[0216] For example, as shown in FIG11, the second reset circuit 260 includes an eighth transistor T8.

[0217] As shown in Figure 11, the gate of the eighth transistor T8 is electrically connected to the second reset signal terminal RST2, the first terminal of the eighth transistor T8 is electrically connected to the second initialization signal terminal Vinit2, and the second terminal of the eighth transistor T8 is electrically connected to the anode of the light-emitting device 22.

[0218] For example, when the level of the second reset signal received at the second reset signal terminal RST2 is an effective level, the eighth transistor T8 can be turned on under the control of the second reset signal, receive and transmit the initialization signal received at the second initialization signal terminal Vinit2 to the light-emitting device 22, and reset the anode of the light-emitting device 22.

[0219] It should be noted that the display panel 100 is provided with a first reset signal line for transmitting a first reset signal, a second reset signal line for transmitting a second reset signal, a first initialization signal line for transmitting the initialization signal received by the first initialization signal terminal Vinit1, and a second initialization signal line for transmitting the initialization signal received by the second initialization signal terminal Vinit2. Based on this, the first reset signal terminal RST1 in the pixel circuit 21 is electrically connected to the first reset signal line to receive the first reset signal; the second reset signal terminal RST2 is electrically connected to the second reset signal line to receive the second reset signal; the first initialization signal terminal Vinit1 is electrically connected to the first initialization signal line to receive the initialization signal; and the second initialization signal terminal Vinit2 is electrically connected to the second initialization signal line to receive the initialization signal.

[0220] In some embodiments of this disclosure, the specific implementation of the compensation sub-circuit 210, writing sub-circuit 230, storage sub-circuit 240, first reset sub-circuit 250, and second reset sub-circuit 260 is not limited to the methods described above. They can be implemented in any manner, such as conventional connection methods well-known to those skilled in the art, as long as the corresponding functions are achieved. The above examples do not limit the scope of protection of this disclosure. In practical applications, those skilled in the art can choose to use or not use one or more of the above circuits depending on the circumstances. Various combinations and variations based on the aforementioned circuits do not depart from the principles of this invention, and will not be elaborated further.

[0221] The pixel circuit 21 provided in some embodiments of this disclosure will be described below with reference to the film layer of the display panel 100.

[0222] As shown in Figures 12 to 16, the display panel 100 includes an active layer 201.

[0223] It is understandable that an active pattern of at least one first transistor T1 in the pixel circuit 21 can be set within the active layer 201.

[0224] For example, the active layer 201 can be made of low-temperature polycrystalline silicon.

[0225] Alternatively, the active layer 201 can be made of either indium gallium zinc oxide or low-temperature polycrystalline oxide. For example, the active layer 201 can be made of indium gallium zinc oxide (IGZO). Another example is that the active layer 201 can be made of indium gallium zinc tin oxide (IGZTO).

[0226] It is understandable that when the active layer 201 is made of low-temperature polycrystalline silicon, the transistor with the active pattern located on the active layer 201 is a low-temperature polycrystalline silicon thin-film transistor; when the active layer 201 is made of either indium gallium zinc oxide or low-temperature polycrystalline oxide, the transistor with the active pattern located on the active layer 201 is an oxide thin-film transistor.

[0227] For example, the active layer 201 can be obtained using an excimer laser annealing process. Also for example, the active layer 201 can be obtained using a physical vapor deposition (PVD) process.

[0228] Referring to Figures 12-16, the display panel 100 further includes a first gate 202 and a second gate 203 located on both sides of the active layer 201 along the thickness direction of the display panel 100, and the first gate 202 and the second gate 203 are electrically connected. Figures 14-15 are planar structural diagrams of a partial area of ​​the pixel circuit 21 within the display panel 100 according to some embodiments. It should be noted that, in order to expose a portion of the film layer located on the side of the second gate 203 near the substrate 10 (e.g., the film layer containing the active layer 201 and the first gate 202), the various film layers in the pixel circuit 21 within the display panel 100 are made transparent in Figures 14-15.

[0229] In some examples, the first gate 202 is the top gate of a transistor (e.g., the first transistor T1), located on the side of the active layer 201 away from the substrate 10, and the second gate 203 is the bottom gate of a transistor (e.g., the first transistor T1), located on the side of the active layer 201 close to the substrate 10. In other examples, the first gate 202 is the bottom gate of a transistor (e.g., the first transistor T1), located on the side of the active layer 201 close to the substrate 10, and the second gate 203 is the top gate of a transistor (e.g., the first transistor T1), located on the side of the active layer 201 away from the substrate 10, as shown in Figures 12-14. In the embodiments of this disclosure, the example of the first gate 202 being the bottom gate of the transistor and the second gate 203 being the top gate of the transistor will be described.

[0230] For example, the orthographic projection of the active layer 201 onto the substrate 10 overlaps with the orthographic projection of the first gate 202 onto the substrate 10. The portion of the active layer 201 covered by the first gate 202 constitutes the channel portion of each transistor (e.g., the first transistor T1), while the portion of the active layer 201 not covered by the first gate 202 is a conductive portion, constituting part of the first or second electrode of each transistor (e.g., the first transistor T1). The channel portion has a channel length and a channel width. The orthographic projection of the active layer 201 onto the substrate 10 overlaps with the orthographic projection of the second gate 203 onto the substrate 10. The portion of the active layer 201 covered by the second gate 203 constitutes the channel portion of each transistor (e.g., the first transistor T1), while the portion of the active layer 201 not covered by the second gate 203 is a conductive portion, constituting part of the first or second electrode of each transistor (e.g., the first transistor T1).

[0231] That is, the region formed by the overlap of the first gate 202 and the active layer 201 constitutes the first channel of the transistor. The region formed by the overlap of the second gate 203 and the active layer 201 constitutes the second channel of the transistor. The first channel and the second channel overlap along the thickness direction of the display panel 100 to form a dual-channel structure.

[0232] Furthermore, the orthogonal projection of the first gate 202 onto the substrate 10 at least partially overlaps with the orthogonal projection of the second gate 203 onto the substrate 10. For example, the orthogonal projection of the second gate 203 onto the substrate 10 lies within the orthogonal projection of the first gate 202 onto the substrate 10. In this way, misalignment of the first gate 202 and the second gate 203 can be avoided, thus ensuring the dual-gate and dual-channel structure of the transistor.

[0233] Therefore, when the dual-gate transistor is turned on, the driving current is transmitted to the light-emitting device 22 through the first channel and the second channel respectively, which is equivalent to increasing the transmission channel of the driving current. The charge carriers can migrate upward or downward at the same time, thereby improving the output capability of the transistor, thereby improving the driving capability of the pixel circuit 21 to the light-emitting device, increasing the brightness of the light-emitting device 22, and thus improving the contrast and brightness of the display screen 100, and improving the user's viewing experience.

[0234] In some embodiments, as shown in FIG12, FIG13 and FIG14, the display panel 100 further includes: a first gate insulating layer 204 located between the first gate 202 and the active layer 201; and a second gate insulating layer 205 located between the active layer 201 and the second gate 203.

[0235] As shown in Figure 13, a first via 41 is provided in the first gate insulating layer 204, and a second via 51 is provided in the second gate insulating layer 205. The first gate 202 and the second gate 203 are interconnected through the second via 51 and the first via 41.

[0236] For example, a first gate insulating layer 204 is used to electrically insulate the active layer 201 and the first gate 202. A second gate insulating layer 205 is used to electrically insulate the active layer 201 and the second gate 203.

[0237] For example, the material of the first gate insulating layer 204 includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide. For instance, the material of the first gate insulating layer 204 may include silicon dioxide, but this disclosure is not limited thereto.

[0238] For example, the material of the second gate insulating layer 205 includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide. For instance, the material of the second gate insulating layer 205 may include silicon dioxide, but this disclosure is not limited thereto.

[0239] For example, as shown in FIG13, the orthographic projection of the first via 41 on the substrate 10 at least partially overlaps with the orthographic projection of the second via 51 on the substrate 10. For instance, the orthographic projection of the first via 41 on the substrate 10 partially overlaps with the orthographic projection of the second via 51 on the substrate 10. Or, for another example, the orthographic projection of the first via 41 on the substrate 10 completely overlaps with the orthographic projection of the second via 51 on the substrate 10. That is, the second via 51 and the first via 41 can form a through-hole.

[0240] In some examples, the first gate 202 and the second gate 203 are interconnected through a through-hole. In other examples, the first gate 202 and the second gate 203 are interconnected through two through-holes. The embodiments of this disclosure are not limited thereto.

[0241] With the above configuration, the first gate 201 and the second gate 203 are interconnected through a through-hole formed by the second via 51 and the first via 41, realizing a dual-gate and dual-channel structure of the transistor (e.g., the first transistor T1). During the light-emitting stage, the driving current can be transmitted to the light-emitting device 22 through the two channels of the transistor. This is equivalent to increasing the output channel of the driving current, thereby reducing the transmission time of the driving current, which is beneficial to improving the transmission efficiency of the driving current and reducing the power consumption of the pixel circuit 21. Moreover, by increasing the output channel of the driving current, it is also beneficial to increase the output current and improve the driving capability of the pixel circuit 21 to the light-emitting device 22, which is beneficial to improve the brightness of the light-emitting device 22, improve the contrast and brightness of the display screen 100, and improve the user's viewing experience.

[0242] In some embodiments, as shown in FIG13, the second via 51 and the first via 41 are both offset from the active layer 201 along the thickness direction of the display panel 100.

[0243] For example, as shown in FIG13, the orthographic projection of the second via 51 on the substrate 10 is offset from the orthographic projection of the active layer 201 on the substrate 10; the orthographic projection of the first via 41 on the substrate 10 is also offset from the orthographic projection of the active layer 201 on the substrate 10.

[0244] By adopting the above configuration, the dual-gate and dual-channel structure of the transistor can be ensured. During the light-emitting stage, the driving current can be transmitted to the light-emitting device 22 through the two channels of the transistor. This is equivalent to increasing the output channel of the driving current, thereby reducing the transmission time of the driving current, which is beneficial to improving the transmission efficiency of the driving current and reducing the power consumption of the pixel circuit 21. Moreover, by increasing the output channel of the driving current, it is also beneficial to increase the output current and improve the driving capability of the pixel circuit 21 to the light-emitting device 22, which is beneficial to improve the brightness of the light-emitting device 22, improve the contrast and brightness of the display screen 100, and improve the user's viewing experience. It also avoids the problem of unstable transistor performance caused by the through-hole formed by the second via 51 and the first via 41 having to pass through the active layer 201.

[0245] In some embodiments, as shown in FIG14, the display panel 100 further includes a source / drain conductive layer 206 located on the side of the second gate 203 away from the first gate 202.

[0246] For example, the source / drain conductive layer 206 can be multiple layers. For instance, the display panel 100 includes two or three source / drain conductive layers 206.

[0247] For example, the source / drain conductive layer 206 is made of a conductive material. For instance, the source / drain conductive layer 206 may be made of a metallic material, such as Al (aluminum), Ag (silver), Cu (copper), Cr (chromium), etc. The embodiments disclosed herein are not limited in this respect.

[0248] For example, the source-drain conductive layer 206 may include a first electrode (one of the source or drain) and a second electrode (the other of the source or drain) of a transistor (e.g., a first transistor T1) in the pixel circuit 21.

[0249] For example, as shown in FIG14, the source-drain metal layer 206 includes a first bridging portion 2061, and the first gate 201 and the second gate 203 are electrically connected through the first bridging portion 2061.

[0250] For example, the orthographic projection of the first bridging portion 2061 on the substrate 10 partially overlaps with the orthographic projection of the second gate 203 on the substrate 10; the orthographic projection of the first bridging portion 2061 on the substrate 10 also partially overlaps with the orthographic projection of the first gate 201 on the substrate 10. In the orthographic projection of the first gate 201 on the substrate 10, a portion overlaps with the orthographic projection of the second gate 203 on the substrate 10, while another portion is offset from the orthographic projection of the second gate 203 on the substrate 10. The offset portions of the first gate 201 and the second gate 203 are electrically connected to the first bridging portion 2061.

[0251] Thus, the first bridging section 2061 achieves the electrical connection between the first gate 201 and the second gate 203, ensuring the dual-gate and dual-channel structure of the transistor (e.g., the first transistor T1). During the light-emitting stage, the driving current can be transmitted to the light-emitting device 22 through the two channels of the transistor. This is equivalent to increasing the output channel of the driving current, thereby reducing the transmission time of the driving current, improving the transmission efficiency of the driving current, and reducing the power consumption of the pixel circuit 21. Moreover, by increasing the output channel of the driving current, it is also beneficial to increase the output current, improve the driving capability of the pixel circuit 21 to the light-emitting device, thereby improving the brightness of the light-emitting device 22, increasing the contrast and brightness of the display screen 100, and improving the user's viewing experience.

[0252] In some embodiments, as shown in FIG14, the display panel 100 further includes a third insulating layer 207 located between the second gate 203 and the source / drain metal layer 206. The third insulating layer 207 is used to electrically insulate the second gate 203 and the source / drain metal layer 206.

[0253] For example, the material of the third insulating layer 207 includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide. For instance, the material of the third insulating layer 207 may include silicon dioxide, but this disclosure is not limited thereto.

[0254] For example, as shown in FIG14, the third insulating layer 207 is provided with a third via 71. The third via 71, the second via 51 and the first via 41 are interconnected, and one end of the first bridging portion 2061 is electrically connected to the first gate 202 through the third via 71, the second via 51 and the first via 41.

[0255] As exemplarily shown in FIG14, the third insulating layer 207 is further provided with a fourth via 72. The other end of the first bridging portion 2061 is electrically connected to the second gate 203 through the fourth via 72.

[0256] By adopting the above configuration, the electrical connection between the first gate 201 and the second gate 203 can be achieved through the first bridging section 2061. This ensures the dual-gate and dual-channel structure of the transistor (e.g., the first transistor T1) in the pixel circuit 21. During the light-emitting stage, the driving current can be transmitted to the light-emitting device 22 through the two channels of the transistor. This is equivalent to increasing the output channel of the driving current, thereby reducing the transmission time of the driving current, improving the transmission efficiency of the driving current, and reducing the power consumption of the pixel circuit 21. Moreover, by increasing the output channel of the driving current, it is also beneficial to increase the output current and improve the driving capability of the pixel circuit 21 to the light-emitting device, thereby improving the brightness of the light-emitting device 22, increasing the contrast and brightness of the display screen 100, and improving the user's viewing experience.

[0257] In some embodiments, as shown in Figures 12, 13, and 14, the first gate 202 is closer to the substrate 10 than the second gate 203. That is, the first gate 202 serves as the bottom gate of the transistor, and the second gate 203 serves as the top gate of the transistor.

[0258] As shown in Figures 12, 13 and 14, the display panel 100 further includes: a light-shielding layer 6 (i.e., a bottom shielding metal (BSM) layer) located between the substrate 10 and the film layer where the first gate 202 is located; the orthogonal projection of the active layer 201 on the substrate 10 is within the range of the orthogonal projection of the light-shielding layer 6 on the substrate 10, and the first gate 202 is made of the same material as the light-shielding layer 6 and is disposed in the same layer.

[0259] For example, the material of the light-shielding layer 6 includes metal, and it has the functions of being conductive and light-shielding. The thickness of the light-shielding layer 6 should be sufficient to block light.

[0260] For example, the material of the light-shielding layer 6 can be a high-temperature and oxidation-resistant metal material such as molybdenum, molybdenum-niobium, or molybdenum-titanium.

[0261] For example, the light-shielding layer 6 is configured to block light and prevent light from passing through the light-shielding layer itself and entering from one side of the light-shielding layer to the opposite side.

[0262] The term "same layer" as used in this disclosure refers to a layer structure formed using the same film deposition process to create a specific pattern, and then using the same photomask through a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0263] In this embodiment, the first gate 202 and the light-shielding layer 6 are made of the same material and are disposed in the same layer. That is, the first gate 202 and the light-shielding layer 6 are formed through a single patterning process. Thus, a dual-gate transistor with a first gate 202 and a second gate 203 can be formed without adding a mask. During the light-emitting stage, the driving current can be transmitted to the light-emitting device 22 through the two channels of the dual-gate transistor. This is equivalent to adding an output channel for the driving current, thereby reducing the transmission time of the driving current, which is beneficial to improving the transmission efficiency of the driving current and reducing the power consumption of the pixel circuit 21. Moreover, by adding an output channel for the driving current, it is also beneficial to increase the output current and improve the driving capability of the pixel circuit 21 to the light-emitting device, which is beneficial to improve the brightness of the light-emitting device 22, improve the contrast and brightness of the display screen 100, and improve the user's viewing experience. Furthermore, in the fabrication process of the display panel 100, only one perforated mask is needed to realize the conduction of the first gate 202 and the second gate 203, thus realizing the dual-gate and dual-channel design of the transistor.

[0264] In some embodiments, as shown in FIG12 and FIG16, the pixel circuit 21 further includes at least one second transistor T2 disposed in parallel with the first transistor T1.

[0265] As shown in Figure 12, the second transistor T2 includes: an active layer 211; and a first gate 212 and a second gate 213 located on both sides of the active layer 211 along the thickness direction of the display panel 100, wherein the first gate 212 and the second gate 213 of the second transistor T2 are electrically connected.

[0266] As shown in Figures 12 and 16, the first gate 202 of the first transistor T1 and the first gate 212 of at least one second transistor T2 are disposed on the same layer and interconnected with each other, and the second gate 203 of the first transistor T1 and the second gate 213 of at least one second transistor T2 are disposed on the same layer and interconnected with each other.

[0267] For example, when the display panel 100 further includes a light-shielding layer 6 located between the substrate 10 and the film layer containing the first gate 202, the first gate 212 of at least one second transistor T2 can be made of the same material as the light-shielding layer 6 and disposed in the same layer. This simplifies the manufacturing process of the display panel 100 and reduces its manufacturing cost.

[0268] With the above configuration, at least one second transistor T2 is connected in parallel with the first transistor T1. During the operation of the pixel circuit 21, the first transistor T1 and at least one second transistor T2 connected in parallel can be turned on simultaneously. The first transistor T1 and at least one second transistor T2 connected in parallel can simultaneously provide driving current to the light-emitting device 22, so that the upper limit of the output current of the pixel circuit 21 is not limited by the upper limit of the conduction current of the first transistor T1. This allows the pixel circuit 21 to output a larger current, thereby improving the driving capability of the pixel circuit 21 to the light-emitting device, thus improving the contrast and brightness of the display screen 100 and enhancing the user's viewing experience.

[0269] In some embodiments, as shown in FIG16, the first gate 202 of the first transistor T1 and the first gate 212 of at least one second transistor T2 are interconnected to form a first gate pattern GL1, and the second gate 203 of the first transistor T1 and the second gate 213 of at least one second transistor T2 are interconnected to form a second gate pattern GL2.

[0270] The first gate pattern GL1 and the second gate pattern GL2 both extend in the same direction, and the orthographic projection of the first gate pattern GL1 on the substrate 10 and the orthographic projection of the second gate pattern GL2 on the substrate 10 overlap.

[0271] For example, when at least one second transistor T2 and a driving transistor TD are connected in parallel, the first gate 202 of the driving transistor TD and the first gate 212 of the at least one second transistor T2 are interconnected to form a first gate pattern GL1; the second gate 203 of the driving transistor TD and the second gate 213 of the at least one second transistor T2 are interconnected to form a second gate pattern GL2. The first gate pattern GL1 and the second gate pattern GL2 extend along the second direction Y, as shown in FIG16.

[0272] As another example, when at least one second transistor T2 and a first light-emitting control transistor TL1 are connected in parallel, the first gate 202 of the first light-emitting control transistor TL1 and the first gate 212 of the at least one second transistor T2 are interconnected to form a first gate pattern GL1; the second gate 203 of the first light-emitting control transistor TL1 and the second gate 213 of the at least one second transistor T2 are interconnected to form a second gate pattern GL2. The first gate pattern GL1 and the second gate pattern GL2 extend along a first direction X.

[0273] As another example, when at least one second transistor T2 and a second light-emitting control transistor TL2 are arranged in parallel, the first gate 202 of the second light-emitting control transistor TL2 and the first gate 212 of the at least one second transistor T2 are interconnected to form a first gate pattern GL1; the second gate 203 of the second light-emitting control transistor TL2 and the second gate 213 of the at least one second transistor T2 are interconnected to form a second gate pattern GL2. The first gate pattern GL1 and the second gate pattern GL2 extend along a first direction X.

[0274] Since the first gate 202 of the first transistor T1 and the first gate 212 of at least one second transistor T2 are interconnected, that is, the first gate 202 of the first transistor T1 and the first gate 212 of at least one second transistor T2 can be used to receive the same electrical signal; and the second gate 203 of the first transistor T1 and the second gate 213 of at least one second transistor T2 are interconnected, that is, the second gate 203 of the first transistor T1 and the second gate 213 of at least one second transistor T2 can be used to receive the same electrical signal, thus realizing the parallel configuration of the first transistor T1 and at least one second transistor T2, and now the first transistor T1 and the transistor connected in parallel with it... At least one second transistor T2 can be turned on or off simultaneously under the control of the same control signal, thereby enabling the first transistor T1 and at least one second transistor T2 connected in parallel to simultaneously provide driving current to the light-emitting device 22. This allows the driving current of the pixel circuit 21 to be unrestricted by the upper limit of the conducting current of the first transistor T1, enabling the pixel circuit 21 to output a larger current. This improves the driving capability of the pixel circuit 21 to the light-emitting device, which in turn helps to improve the brightness of the light-emitting device 22. When the pixel circuit 21 is applied in a display device, it can improve the contrast and brightness of the display screen 100, thus enhancing the user's viewing experience.

[0275] In some embodiments, as shown in FIG16, the display panel 100 further includes a second electrode plate C2 located on the side of the second gate pattern GL2 away from the first gate pattern GL1, the second electrode plate C2 serving as the upper electrode plate of the first capacitor Cst.

[0276] As shown in Figure 16, the second gate pattern GL2 is multiplexed as the first electrode C1, and the first electrode C1 serves as the lower electrode of the first capacitor Cst; the orthogonal projection of the second electrode C2 on the substrate 10 is located within the orthogonal projection of the first electrode C1 on the substrate 10.

[0277] For example, as shown in Figure 16, the second electrode C2 is annular.

[0278] As shown in Figures 14 and 17, when the display panel 100 includes a third insulating layer 207 and a fourth via 72 is provided on the third insulating layer 207, the orthogonal projection of the fourth via 72 on the substrate 10 is located within the inner boundary of the orthogonal projection of the second electrode C2 on the substrate 10.

[0279] For example, the number of fourth vias 72 can be one or more. When there are multiple fourth vias 72, the effectiveness of the electrical connection between the first gate 202 and the second gate 203 can be guaranteed, and the signal transmission effect can also be improved. When there are multiple fourth vias 72, the orthogonal projections i of the multiple fourth vias 72 on the substrate 10 can all be located within the inner boundary of the orthogonal projection of the second electrode C2 on the substrate 10.

[0280] By adopting the above configuration, the potential stability of the first node N1 in the pixel circuit 21 can be ensured by utilizing the first capacitor Cst, and the electrical connection between the first gate 202 and the second gate 203 can be realized. This achieves a dual-gate and dual-channel structure of the transistor (e.g., the first transistor T1). During the light-emitting stage, the driving current can be transmitted to the light-emitting device 22 through the two channels of the transistor. This is equivalent to increasing the output channel of the driving current, thereby reducing the transmission time of the driving current, which is beneficial to improving the transmission efficiency of the driving current and reducing the power consumption of the pixel circuit 21. Moreover, by increasing the output channel of the driving current, it is also beneficial to increase the output current and improve the driving capability of the pixel circuit 21 to the light-emitting device 22, which is beneficial to improve the brightness of the light-emitting device 22, improve the contrast and brightness of the display screen 100, and improve the user's viewing experience.

[0281] In some other embodiments, as shown in FIG18, the second electrode plate C2 is a block structure.

[0282] As shown in Figures 14 and 18, when the display panel 100 includes a third insulating layer 207 and a fourth via 72 is provided on the third insulating layer 207, the orthogonal projection of the fourth via 72 on the substrate 10 is offset from the orthogonal projection of the second electrode C2 on the substrate 10.

[0283] Therefore, it is possible to ensure that the first gate 202 and the second gate 203 are electrically connected through the first bridging portion 2061, thereby realizing the dual-gate and dual-channel structure of the transistor (e.g., the first transistor T1). During the light-emitting stage, the driving current can be transmitted to the light-emitting device 22 through the two channels of the transistor. This is equivalent to increasing the output channel of the driving current, thereby reducing the transmission time of the driving current, which is beneficial to improving the transmission efficiency of the driving current and reducing the power consumption of the pixel circuit 21. Moreover, by increasing the output channel of the driving current, it is also beneficial to increase the output current and improve the driving capability of the pixel circuit 21 to the light-emitting device 22, which is beneficial to improve the brightness of the light-emitting device 22, improve the contrast and brightness of the display screen 100, and improve the user's viewing experience. In addition, the second electrode C2 is a block structure, which can also increase the overlapping panel between the second electrode C2 and the first electrode C1 of the first capacitor Cst, increase the storage capacitance of the first capacitor Cst, improve the storage effect of the first capacitor Cst, and further maintain the voltage of the first node N1.

[0284] In some embodiments, as shown in Figures 12 and 15, the active layer 201 of the first transistor T1 and the active layer 211 of at least one second transistor T2 are disposed on the same layer. Therefore, the active layer 201 of the first transistor T1 and the active layer 211 of at least one second transistor T2 can be fabricated simultaneously, thereby simplifying the manufacturing process of the display panel 100.

[0285] The active layer 201 of the first transistor T1 and the active layer 211 of at least one second transistor T2 are both intersected with the first gate pattern GL1 and are spaced apart from each other along the extension direction of the first gate pattern GL1.

[0286] For example, as shown in Figures 12 and 15, the active layer 201 of the first transistor T1 and the active layer 211 of at least one second transistor T2 are spaced apart along the second direction Y. The orthographic projection of the first gate pattern GL1 onto the substrate 10 overlaps with the orthographic projections of the active layer 201 of the first transistor T1 and the active layer 211 of at least one second transistor T2 onto the substrate 10. The portion of the first gate pattern GL1 overlapping with the active layer 201 of the first transistor T1 constitutes the first gate 202 of the first transistor T1; the portion of the first gate pattern GL1 overlapping with the active layer 211 of the second transistor T2 constitutes the first gate 212 of the second transistor T2.

[0287] For example, the active layer 201 of the first transistor T1 and the active layer 211 of at least one second transistor T2 are both intersected with the second gate pattern GL2. The orthographic projection of the second gate pattern GL2 onto the substrate 10 overlaps with the orthographic projections of the active layer 201 of the first transistor T1 and the active layer 211 of at least one second transistor T2 onto the substrate 10. The portion of the second gate pattern GL2 that overlaps with the active layer 201 of the first transistor T1 constitutes the second gate 203 of the first transistor T1; the portion of the second gate pattern GL2 that overlaps with the active layer 211 of the second transistor T2 constitutes the second gate 213 of the second transistor T2.

[0288] By adopting the above configuration, the first transistor T1 and at least one second transistor T2 are connected in parallel, so that the driving current of the pixel circuit 21 is not limited by the upper limit of the conduction current of the first transistor T1, and the pixel circuit 21 can output a larger current, thereby improving the driving capability of the pixel circuit 21 for the light-emitting device, which is beneficial to improving the brightness of the light-emitting device 22. When the pixel circuit 21 is applied in a display device, it can improve the contrast and brightness of the display panel 100, and improve the user's viewing experience.

[0289] In some embodiments, as shown in Figures 16 to 18, the display panel 100 further includes a first connecting portion PL1 and a second connecting portion PL2, which are disposed on the same layer as the active layer 201 of the first transistor T1.

[0290] The active layer 201 of the first transistor T1 and the active layer 211 of at least one second transistor T2 are located between the first connection portion PL1 and the second connection portion PL2. One end of the active layer 201 of the first transistor T1 and the active layer 211 of at least one second transistor T2 are both connected to the first connection portion PL1, and the other end of the active layer 201 of the first transistor T1 and the active layer 211 of at least one second transistor T2 are both connected to the second connection portion PL2.

[0291] For example, the portion of the active layer 201 of the first transistor T1 and the active layer 211 of at least one second transistor T2 that overlaps with the first gate pattern GL1 constitutes the active pattern of the transistor, and the portion of the active layer 201 of the first transistor T1 and the active layer 211 of at least one second transistor T2 that is offset from the first gate pattern GL1 constitutes the first electrode and the second electrode of the transistor.

[0292] In this embodiment, one end of the active layer 201 of the first transistor T1 and one end of the active layer 211 of at least one second transistor T2 are both connected to the first connection portion PL1, and the other end of the active layer 201 of the first transistor T1 and one end of the active layer 211 of at least one second transistor T2 are both connected to the second connection portion PL2. That is, the first electrode of the first transistor T1 and the first electrode of at least one second transistor T2 are connected to each other through the first connection portion PL1, and the second electrode of the first transistor T1 and the second electrode of at least one second transistor T2 are connected to each other through the second connection portion PL2, thereby realizing the parallel connection of the first transistor T1 and at least one second transistor T2. This allows the driving current of the pixel circuit 21 to be unrestricted by the upper limit of the conduction current of the first transistor T1, enabling the pixel circuit 21 to output a larger current, thereby improving the driving capability of the pixel circuit 21 for the light-emitting device, which is beneficial to improving the brightness of the light-emitting device 22. When the pixel circuit 21 is applied in a display device, it can improve the contrast and brightness of the display screen 100, and improve the user's viewing experience.

[0293] In some embodiments, as shown in Figures 16 to 18, the main light-emitting path 210 of the pixel circuit 21 includes a driving transistor TD, a first light-emitting control transistor TL1, and a second light-emitting control transistor TL2. The driving transistor TD is connected in parallel with at least one second transistor T2. A first connection portion PL1 and a second connection portion PL2 are provided on both sides of the driving transistor TD and the at least one second transistor T2. One end of the active layer 201 of the driving transistor TD and one end of the active layer 211 of the at least one second transistor T2 are both connected to the first connection portion PL1, and the first connection portion PL1 is connected to the active layer of the first light-emitting control transistor TL1. The other end of the active layer 201 of the driving transistor TD and one end of the active layer 211 of the at least one second transistor T2 are both connected to the second connection portion PL2, and the second connection portion PL2 is connected to the active layer of the second light-emitting control transistor TL2.

[0294] The driving transistor TD and at least one second transistor T2 are provided with a first connection portion PL1 and a second connection portion PL2 on both sides. One end of the active layer 201 of the driving transistor TD and one end of the active layer 211 of the at least one second transistor T2 are both connected to the first connection portion PL1, and the other end of the active layer 201 of the driving transistor TD and the active layer 211 of the at least one second transistor T2 are both connected to the second connection portion PL2. That is, the first terminal of the driving transistor TD and the first terminal of the at least one second transistor T2 are interconnected through the first connection portion PL1; the second terminal of the driving transistor TD and the second terminal of the at least one second transistor T2 are interconnected through the second connection portion PL2, thereby realizing the parallel connection of the driving transistor TD and the at least one second transistor T2.

[0295] Furthermore, one end of the parallel-connected driving transistor TD and at least one second transistor T2 is connected to the first light-emitting control transistor TL1 through the first connection part PL1; the other end of the parallel-connected driving transistor TD and at least one second transistor T2 is connected to the second light-emitting control transistor TL2 through the second connection part PL2, thereby forming a branch formed by the first light-emitting control transistor TL1, the parallel-connected driving transistor TD and at least one second transistor T2, and the second light-emitting control transistor TL2 in series, that is, the light-emitting main path 210; during the light-emitting stage, the light-emitting device 22 can be provided with driving current through the light-emitting main path 210 to make the light-emitting device 22 emit light.

[0296] Furthermore, in the main light-emitting path 210, the driving transistor TD and at least one second transistor T2 are connected in parallel, which enables the upper limit of the output current of the pixel circuit 21 to be unrestricted by the upper limit of the conduction current of the driving transistor TD, allowing the pixel circuit 21 to output a larger current, thereby improving the driving capability of the pixel circuit 21 to the light-emitting device 22, thereby improving the contrast and brightness of the display screen 100 and enhancing the user's viewing experience.

[0297] In some embodiments, as shown in FIG18, the display panel 100 further includes: in the case that the source-drain conductive layer 206 is located on the side of the second gate 203 away from the first gate 202, the source-drain conductive layer 206 further includes: at least one connection pattern 2062.

[0298] The orthographic projection of the connection pattern 2062 on the substrate 10 at least partially overlaps with the orthographic projection of the first connection portion PL1 on the substrate 10, and the connection pattern 2062 and the first connection portion PL1 are electrically connected through a plurality of fifth vias 75.

[0299] The orthographic projection of the connection pattern 2062 on the substrate 10 at least partially overlaps with the orthographic projection of the second connection portion PL2 on the substrate 10, and the connection pattern 2062 and the second connection portion PL2 are electrically connected through a plurality of sixth vias 76.

[0300] For example, the number of connection patterns 2062 can be multiple.

[0301] For example, the connection pattern 2062 electrically connected to the first connection portion PL1 is used to realize the electrical connection between the driving transistor TD and one of the sixth transistor T6 included in the writing sub-circuit 230 and the fifth transistor T5 included in the compensation sub-circuit 220; the connection pattern 2062 electrically connected to the second connection portion PL2 is used to realize the electrical connection between the driving transistor TD and the other of the sixth transistor T6 included in the writing sub-circuit 230 and the fifth transistor T5 included in the compensation sub-circuit 220.

[0302] The first connecting part PL1 and the second connecting part PL2 are elongated strips, which increases resistance and can easily lead to signal delay.

[0303] In the embodiments of this disclosure, by making the connection pattern 2062 and the first connection portion PL1 electrically connected through a plurality of fifth vias 75, and / or making the connection pattern 2062 and the second connection portion PL2 electrically connected through a plurality of sixth vias 76, the voltage drop across the first connection portion PL1 and the second connection portion PL2 can be reduced, thereby improving the display effect of the display panel 100 and increasing the brightness uniformity of the display panel 100.

[0304] In some embodiments, as shown in FIG19, the pixel circuit 21 includes two main light-emitting paths 210, which are located on both sides of the light-emitting device 22 corresponding to the pixel circuit 21.

[0305] For example, the main light-emitting path 210 is electrically connected to the first electrode 221 of the corresponding light-emitting device 22.

[0306] Furthermore, as shown in Figure 19, in the pixel circuit 21, the two main light-emitting paths 210 can be symmetrically distributed about the bisector aa of the first electrode 221 of the corresponding connected light-emitting device 22.

[0307] It should be noted that the above "symmetrical distribution" is not symmetrical in the strict sense, and the shapes of the two main light-emitting channels 210 can fluctuate within the error range.

[0308] In this embodiment, the pixel circuit 21 includes two main light-emitting paths 210. During the operation of the pixel circuit 21, in the light-emitting stage, the two main light-emitting paths 210 are simultaneously turned on to provide driving current to the light-emitting device 22, thereby further increasing the driving current of the pixel circuit 21 and improving the driving capability of the pixel circuit 21 to the light-emitting device. This is beneficial to improving the brightness of the light-emitting device 22. When the pixel circuit 21 is applied in a display device, it can improve the contrast and brightness of the display panel 100 and improve the user's viewing experience.

[0309] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A pixel circuit, comprising: The light-emitting main path has a first end connected to a first voltage terminal and a second end connected to a light-emitting device. The light-emitting main path includes at least two control units connected in series between the first end and the second end, each control unit including a first transistor; the at least two first transistors include a driving transistor and at least one light-emitting control transistor. At least one of the first transistors includes two gates connected together to form the control terminal of the first transistor. At least one of the control units further includes at least one second transistor, wherein the first transistor of the same control unit is connected in parallel with the at least one second transistor.

2. The pixel circuit according to claim 1, wherein, The second transistor includes two gates, which are connected to form the control terminal of the second transistor.

3. The pixel circuit according to claim 1 or 2, wherein, The driving transistor includes two gates connected to each other.

4. The pixel circuit according to claim 3, wherein, At least one of the second transistors is connected in parallel with the driving transistor.

5. The pixel circuit according to any one of claims 2 to 4, wherein, The at least two first transistors include a first light-emitting control transistor and a second light-emitting control transistor. A first terminal of the first light-emitting control transistor is connected to the first voltage terminal. A second terminal of the first light-emitting control transistor is connected to the first terminal of the driving transistor. A second terminal of the driving transistor is connected to the first terminal of the second light-emitting control transistor. A second terminal of the second light-emitting control transistor is connected to the light-emitting device. The first light-emitting control transistor includes two gates connected in series; and / or, The second light-emitting control transistor includes two gates connected to each other.

6. The pixel circuit according to claim 5, wherein, At least one third transistor is connected in parallel with the first light-emitting control transistor; and / or, At least one fourth transistor is connected in parallel with the second light-emitting control transistor.

7. A display panel, comprising: Substrate; A plurality of pixel circuits disposed on the substrate, wherein the pixel circuits are pixel circuits as described in any one of claims 1 to 6; A plurality of light-emitting devices are disposed on the side of the plurality of pixel circuits away from the substrate, and one pixel circuit is connected to at least one of the light-emitting devices.

8. The display panel according to claim 7, wherein, At least one first transistor in the pixel circuit includes: Active layer; and, Along the thickness direction of the display panel, there are a first gate and a second gate located on both sides of the active layer, and the first gate and the second gate are electrically connected.

9. The display panel according to claim 8, further comprising: A first gate insulating layer located between the first gate and the active layer; The second gate insulating layer is located between the active layer and the second gate. A first via is provided in the first gate insulating layer, and a second via is provided in the second gate insulating layer. The first gate and the second gate are interconnected through the second via and the first via.

10. The display panel according to claim 9, wherein, Along the thickness direction of the display panel, both the second via and the first via are offset from the active layer.

11. The display panel according to claim 8, further comprising: A source / drain conductive layer is located on the side of the second gate away from the first gate, and the source / drain conductive layer includes a first bridging portion; the first gate and the second gate are electrically connected through the first bridging portion.

12. The display panel according to claim 11, further comprising: A first gate insulating layer located between the first gate and the active layer; The second gate insulating layer is located between the active layer and the second gate. A third insulating layer is located between the second gate and the source / drain conductive layer; A first via is provided in the first gate insulating layer, a second via is provided in the second gate insulating layer, and a third via is provided in the third insulating layer. The first via, the second via, and the third via are interconnected, and one end of the first bridging portion is electrically connected to the first gate through the first via, the second via, and the third via. The third insulating layer is also provided with a fourth via, and the other end of the first bridging portion is electrically connected to the second gate through the fourth via.

13. The display panel according to any one of claims 8 to 12, wherein, The first gate is closer to the substrate than the second gate; The display panel also includes: A light-shielding layer is located between the substrate and the film layer containing the first gate; the orthographic projection of the active layer on the substrate is within the range of the orthographic projection of the light-shielding layer on the substrate, and the first gate is made of the same material as the light-shielding layer and is disposed in the same layer.

14. The display panel according to any one of claims 8 to 13, wherein, The pixel circuit also includes the at least one second transistor connected in parallel with the first transistor; The second transistor includes: an active layer; and a first gate and a second gate located on both sides of the active layer along the thickness direction of the display panel, the first gate and the second gate being electrically connected; The first gate of the first transistor and the first gate of the at least one second transistor are disposed on the same layer and interconnected with each other, and the second gate of the first transistor and the second gate of the at least one second transistor are disposed on the same layer and interconnected with each other.

15. The display panel according to claim 14, wherein, The first gate of the first transistor and the first gate of the at least one second transistor are interconnected to form a first gate pattern, and the second gate of the first transistor and the second gate of the at least one second transistor are interconnected to form a second gate pattern; The first gate pattern and the second gate pattern both extend in the same direction, and the orthographic projection of the first gate pattern on the substrate and the orthographic projection of the second gate pattern on the substrate overlap.

16. The display panel according to claim 15, wherein, The driving circuit also includes a first capacitor; The display panel further includes: a second electrode plate located on the side of the second gate pattern away from the first gate pattern, the second electrode plate being the upper electrode plate of the first capacitor; The second gate pattern is multiplexed to form the first electrode plate, which is the lower electrode plate of the first capacitor; the orthographic projection of the second electrode plate on the substrate is located within the orthographic projection of the first electrode plate on the substrate. The second electrode plate is annular; when the display panel includes a third insulating layer and a fourth via is provided on the third insulating layer, the orthogonal projection of the fourth via on the substrate is located within the inner boundary of the orthogonal projection of the second electrode plate on the substrate.

17. The display panel according to claim 16, wherein, The driving circuit also includes a first capacitor; The display panel further includes: a second electrode plate located on the side of the second gate away from the first gate, the second electrode plate being the upper electrode plate of the first capacitor; The second gate pattern is multiplexed to form the first electrode plate, which is the lower electrode plate of the first capacitor; the orthographic projection of the second electrode plate on the substrate is located within the orthographic projection of the first electrode plate on the substrate. The second electrode plate is block-shaped; when the display panel includes a third insulating layer and a fourth via is provided on the third insulating layer, the orthographic projection of the fourth via on the substrate is offset from the orthographic projection of the second electrode plate on the substrate.

18. The display panel according to any one of claims 14 to 17, further comprising: The first connecting portion and the second connecting portion are disposed on the same layer as the active layer of the first transistor; The active layer of the first transistor and the active layer of the at least one second transistor are located between the first connection portion and the second connection portion, and one end of the active layer of the first transistor and the active layer of the at least one second transistor are both connected to the first connection portion, and the other end of the active layer of the first transistor and the active layer of the at least one second transistor are both connected to the second connection portion.

19. The display panel according to claim 18, wherein, In the case where the display panel further includes a source / drain conductive layer located on the side of the second gate away from the first gate, the source / drain conductive layer further includes: at least one connection pattern, wherein the orthographic projection of the connection pattern on the substrate at least partially overlaps with the orthographic projection of the first connection portion on the substrate, and the connection pattern and the first connection portion are electrically connected through a plurality of fifth vias; and / or, The orthographic projection of the connection pattern on the substrate at least partially overlaps with the orthographic projection of the second connection portion on the substrate, and the connection pattern and the second connection portion are electrically connected through a plurality of sixth vias.

20. A display device, comprising: The display panel as described in any one of claims 7 to 19; The driver circuit board is electrically connected to the display panel.

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