Array substrate and manufacturing method therefor, display panel, and projection device

Abstract

An array substrate, comprising: a first substrate, a semiconductor layer, a first conductive layer, a second conductive layer, a first light shielding layer, and a second light shielding pattern. The semiconductor layer comprises a plurality of semiconductor patterns, and the semiconductor patterns comprise a channel region and a conductor region. The first conductive layer is located on the side of the semiconductor layer away from the first substrate, and comprises a plurality of gate lines and gate electrodes electrically connected to the gate lines. The second conductive layer is located on the side of the first conductive layer away from the first substrate, and comprises a plurality of data lines, first electrodes electrically connected to the data lines, and second electrodes. The first light shielding layer is located on the side of the semiconductor layer close to the first substrate and comprises a plurality of first light shielding patterns, and the orthographic projections of the first light shielding patterns on the first substrate at least cover the orthographic projection of the channel region on the first substrate. The second light shielding pattern is located on the second conductive layer or on the side of the second conductive layer away from the first substrate. The orthographic projection of the second light shielding pattern on the first substrate at least covers the orthographic projection of the channel region on the first substrate.

Description

Array substrate and its fabrication method, display panel and projection device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an array substrate and its fabrication method, a display panel, and a projection device. Background Technology

[0002] Currently, projection technologies with market scale and relatively mature technology include DLP (Digital Light Processing) projection technology, LCD (Liquid Crystal Display) projection technology, and LCOS (Liquid Crystal on Silicon) projection technology. Among them, benefiting from the mature and stable technology, relatively low cost, and high image quality of LCD panels, their application in projection devices (such as projectors) is becoming increasingly widespread. At the same time, users are also placing higher demands on the performance of LCD projection devices (including but not limited to image quality, brightness, and lifespan). Summary of the Invention

[0003] On one hand, an array substrate is provided. The array substrate includes a first substrate, a semiconductor layer, a first conductive layer, a second conductive layer, a first light-shielding layer, and a second light-shielding pattern. The semiconductor layer is located on one side of the first substrate and includes a plurality of semiconductor patterns arranged in an array. Each semiconductor pattern includes a channel region and a conductor region. The first conductive layer is located on the side of the semiconductor layer away from the first substrate and includes a plurality of gate lines and a gate electrically connected to the gate lines. The second conductive layer is located on the side of the first conductive layer away from the first substrate and includes a plurality of data lines intersecting the gate lines, a first electrode electrically connected to the data lines, and a second electrode. The first light-shielding layer is located on the side of the semiconductor layer close to the first substrate and includes a plurality of first light-shielding patterns. The orthographic projection of the first light-shielding patterns on the first substrate at least covers the orthographic projection of the channel regions on the first substrate. The second light-shielding pattern is located on the side of the first conductive layer away from the first substrate. The orthographic projection of the second light-shielding pattern on the first substrate at least covers the orthographic projection of the channel regions on the first substrate.

[0004] In some embodiments, the array substrate further includes a first electrode layer and a second electrode layer. The first electrode layer is located on the side of the second electrode layer away from the first substrate and is electrically connected to the second electrode. The second electrode layer is located on the side of the first electrode layer away from the first substrate. A second light-shielding pattern is located between the first electrode layer and the second electrode layer, and the orthographic projection of the second light-shielding pattern on the first substrate at least partially coincides with the orthographic projection of the second electrode layer on the first substrate, wherein the second light-shielding pattern is electrically connected to the second electrode layer.

[0005] In some embodiments, the second electrode layer is in direct contact with the second light-shielding pattern.

[0006] In some embodiments, the array substrate further includes a first insulating layer and a first via. The first insulating layer is located between the first conductive layer and the second conductive layer. The first via penetrates at least the first insulating layer and exposes the conductive region. The first electrode and the second electrode are electrically connected to the conductive region through a first via, respectively. The orthographic projection of the second light-shielding pattern on the first substrate also covers the orthographic projection of the first via on the first substrate.

[0007] In some embodiments, the array substrate further includes a second insulating layer. The second insulating layer is located between the semiconductor layer and the first conductive layer, and the thickness of the second insulating layer is less than or equal to... Alternatively, the distance between the surface of the first light-shielding layer near the semiconductor layer and the surface of the semiconductor layer near the first light-shielding layer is less than or equal to...

[0008] In some embodiments, the orthographic projection of a second light-shielding pattern on the first substrate overlaps the orthographic projection of the channel region of the semiconductor pattern on the first substrate.

[0009] In some embodiments, the semiconductor pattern includes two channel regions spaced apart. The second light-shielding pattern includes two first sub-patterns, wherein the orthographic projection of one of the first sub-patterns on the first substrate overlaps the orthographic projection of one of the channel regions on the first substrate.

[0010] In some embodiments, the semiconductor layer includes multiple rows of the semiconductor patterns, and each row of the semiconductor patterns includes a plurality of the semiconductor patterns spaced apart along a first direction. The orthographic projection of a second light-shielding pattern on the first substrate covers the orthographic projection of the channel region of a row of the semiconductor patterns on the first substrate.

[0011] In some embodiments, the semiconductor pattern includes two channel regions spaced apart. The first electrode is integrally disposed with the second light-shielding pattern, and the orthogonal projection of the first electrode on the first substrate overlaps the orthogonal projection of one of the channel regions on the first substrate; and / or, the second electrode is integrally disposed with the second light-shielding pattern, and the orthogonal projection of the second electrode on the first substrate overlaps the orthogonal projection of one of the channel regions on the first substrate; the linewidth of the first electrode is greater than the linewidth of the data line.

[0012] In some embodiments, the semiconductor pattern includes two channel regions spaced apart. The orthographic projection of one of the first light-shielding patterns onto the first substrate covers the orthographic projection of one of the channel regions of the semiconductor pattern onto the first substrate.

[0013] In some embodiments, the semiconductor layer includes multiple rows of the semiconductor patterns, and each row of the semiconductor patterns includes a plurality of the semiconductor patterns spaced apart along a first direction. The orthographic projection of one of the first light-shielding patterns onto the first substrate covers the orthographic projection of the channel region of a row of the semiconductor patterns onto the first substrate.

[0014] In some embodiments, the first light-shielding pattern includes alternately connected first and second extensions, wherein the orthographic projection of the first extension on the first substrate at least covers the orthographic projection of the channel region on the first substrate, and the orthographic projection of the second extension on the first substrate does not coincide with the orthographic projection of the channel region on the first substrate. The dimension of the first extension along a second direction is equal to the dimension of the second extension along the second direction, and the second direction intersects the first direction.

[0015] In some embodiments, the semiconductor pattern includes two extensions and a connecting portion. The two extensions are disposed opposite to each other along a first direction and both extend along a second direction. The two ends of the connecting portion are respectively connected to the ends of the two extensions located on the same side. The second direction intersects the first direction. Along the first direction, the first light-shielding pattern includes alternately connected first and second extension segments. The orthographic projection of the first extension segment onto the first substrate at least covers the orthographic projection of the channel region onto the first substrate. The orthographic projection of the second extension segment onto the first substrate does not coincide with the orthographic projection of the channel region onto the first substrate. The dimension of the first extension segment in the second direction is larger than the dimension of the second extension segment in the second direction.

[0016] In some embodiments, along the second direction, the ends of the first extension and the second extension away from the connector are flush, the end of the first extension near the connector protrudes beyond the end of the second extension near the connector. The orthographic projection of the boundary of the first extension away from the connector onto the first substrate coincides with the orthographic projection of the boundary of the extension away from the connector onto the first substrate; the orthographic projection of the boundary of the second extension near the connector onto the first substrate coincides with the orthographic projection of the boundary of the gate line near the connector onto the first substrate.

[0017] In some embodiments, the array substrate includes a display area and a peripheral area; the array substrate further includes bonding pins located in the peripheral area. The bonding pins include a first sub-part located in the first conductive layer, a second sub-part located in the second conductive layer, and a third sub-part disposed in the same layer as the second light-shielding pattern; the second sub-part is electrically connected to the first sub-part and the third sub-part respectively; the orthographic projection of the third sub-part on the first substrate covers the orthographic projection of the second sub-part on the first substrate. Alternatively, the bonding pins include a first sub-part located in the first conductive layer, a second sub-part located in the second conductive layer, a third sub-part disposed in the same layer as the second light-shielding pattern, and a fourth sub-part located in the second electrode layer; the second sub-part is electrically connected to the first sub-part and the third sub-part respectively; the orthographic projection of the third sub-part on the first substrate covers the orthographic projection of the second sub-part on the first substrate; the fourth sub-part is electrically connected to the third sub-part, and the orthographic projection of the fourth sub-part on the first substrate covers the orthographic projection of the third sub-part on the first substrate.

[0018] In some embodiments, the array substrate further includes a first signal line located in the peripheral region and in the second conductive layer, the first signal line being spaced apart from the second sub-part. The first sub-part is also electrically connected to the first signal line.

[0019] In some embodiments, the semiconductor pattern includes two channel regions spaced apart, and the conductor region includes a first sub-region connecting the two channel regions and two second sub-regions located on the side of the two channel regions away from the first sub-region. The orthographic projection of the first light-shielding layer on the first substrate covers the orthographic projections of the two channel regions, the two second sub-regions, and at least a portion of the first sub-region near the channel regions on the first substrate; the orthographic projection of the second light-shielding pattern on the first substrate covers the orthographic projections of the two channel regions, the two second sub-regions, and at least a portion of the first sub-region near the channel regions on the first substrate.

[0020] In some embodiments, the portion of the conductor region whose orthographic projection on the first substrate coincides with the orthographic projection of the first light-shielding pattern on the first substrate has a dimension along the length of the channel region that is greater than or equal to 1.3 μm. And / or, the portion of the conductor region whose orthographic projection on the first substrate coincides with the orthographic projection of the second light-shielding pattern on the first substrate has a dimension along the length of the channel region that is greater than or equal to 1.3 μm.

[0021] In some embodiments, along a direction perpendicular to the extension direction of the channel region, the orthographic projection of the boundary of the first light-shielding layer onto the first substrate is spaced at a distance greater than or equal to 2 μm from the orthographic projection of the channel region onto the first substrate. And / or, along a direction perpendicular to the extension direction of the channel region, the orthographic projection of the boundary of the second light-shielding pattern onto the first substrate is spaced at a distance greater than or equal to 2 μm from the orthographic projection of the channel region onto the first substrate.

[0022] In some embodiments, the orthographic projection of the first light-shielding pattern on the first substrate completely coincides with the orthographic projection of the second light-shielding pattern on the first substrate; or, the orthographic projection of one of the first light-shielding pattern and the second light-shielding pattern on the light-incident side away from the array substrate on the first substrate is within the range of the orthographic projection of the other on the first substrate, and the minimum interval between the orthographic projection of the boundary of the first light-shielding pattern on the first substrate and the orthographic projection of the boundary of the second light-shielding pattern on the first substrate is less than or equal to 1.1 μm.

[0023] In some embodiments, the semiconductor pattern includes two extensions and a connecting portion. The two extensions are disposed opposite to each other along a first direction and both extend along a second direction. The two ends of the connecting portion are respectively connected to the ends of the two extensions located on the same side. The dimension of the extensions along the first direction is equal to the dimension of the connecting portion along the second direction. The second direction intersects the first direction.

[0024] In some embodiments, the dimension of the extension along the first direction is 1.4 μm to 2 μm.

[0025] In some embodiments, the thickness of the first light-shielding layer is And / or, the thickness of the second light-shielding pattern is

[0026] In some embodiments, the array substrate further includes an anti-reflection layer. The anti-reflection layer is located between the first light-shielding layer and the semiconductor layer, and the orthogonal projection of the anti-reflection layer on the first substrate covers the orthogonal projection of the channel region on the first substrate. The reflectivity of the anti-reflection layer is less than that of the first light-shielding layer.

[0027] On the other hand, a display panel is provided. The display panel includes the array substrate, color filter substrate, and liquid crystal layer described in any of the above embodiments. The color filter substrate is disposed opposite to the array substrate. The liquid crystal layer is located between the array substrate and the color filter substrate.

[0028] In some embodiments, the array substrate includes a plurality of sub-pixels, which are arranged in rows along a first direction and in columns along a second direction. Each sub-pixel includes a semiconductor pattern. The first direction intersects the second direction. The color filter substrate includes a second substrate and a color filter layer located on the second substrate. The color filter layer includes a plurality of first filter portions and a plurality of second filter portions. The first filter portions extend along the second direction, and the orthographic projection of one first filter portion onto the array substrate covers one column of sub-pixels and the semiconductor pattern of that column of sub-pixels. The second filter portions include filter sub-portions and separator portions, which are alternately arranged along the second direction. The orthographic projection of the filter sub-portion onto the array substrate covers the sub-pixels but does not coincide with the channel region of the semiconductor pattern. The orthographic projection of the separator portion onto the array substrate at least covers the channel region. The wavelength of light transmitted through the separator portion is greater than the wavelength of light transmitted through the filter sub-portion; or, the brightness of light transmitted through the separator portion is less than the brightness of light transmitted through the filter sub-portion.

[0029] In some embodiments, the plurality of first filters include a red filter, and the plurality of second filters include a blue filter and a green filter.

[0030] In some embodiments, the plurality of first filters include a red filter and a green filter, and the plurality of second filters include a blue filter.

[0031] In some embodiments, the separator and the red filter are made of the same material, and the wavelength of light passing through the separator is greater than the wavelength of light passing through the filter.

[0032] In some embodiments, the dividing portion includes a black matrix, and the brightness of light passing through the dividing portion is less than the brightness of light passing through the filter portion.

[0033] In another aspect, a projection device is provided, comprising the display panel and light source described in any of the above embodiments. The light source is located on the side of the display panel's array substrate away from the color filter substrate. Alternatively, the light source is located on the side of the display panel's color filter substrate away from the array substrate.

[0034] In another aspect, a method for fabricating an array substrate is provided. The method includes forming a first substrate; the first substrate includes a first substrate, and a first light-shielding layer, a semiconductor layer, a first conductive layer, a second conductive layer, and a first electrode layer disposed along a direction away from the first substrate. The semiconductor layer includes a channel region and a conductor region. The first substrate includes a display region and a peripheral region. The peripheral region includes an initial pin. The initial pin includes a first sub-part located in the first conductive layer and a second sub-part located in the second conductive layer. The second sub-part is electrically connected to the first sub-part, and the first substrate exposes a surface of the second sub-part away from the first substrate. A light-shielding film is formed on the side of the first electrode layer away from the first substrate. The light-shielding film is patterned to form a second light-shielding layer. The second light-shielding layer includes a second light-shielding pattern and a third sub-part. The orthographic projection of the second light-shielding pattern onto the first substrate at least covers the orthographic projection of the channel region onto the first substrate, and the third sub-part covers the second sub-part.

[0035] In some embodiments, the step of patterning the light-shielding film to form the second light-shielding layer includes: coating the light-shielding film to form a photoresist film; performing photolithography on the photoresist film to form a mask layer; the orthographic projection of the mask layer on the first substrate at least covers the orthographic projection of the channel region on the first substrate, and covers the orthographic projection of the second sub-part on the first substrate; using an etching process to remove the portion of the light-shielding film exposed by the mask layer, the remaining portion of the light-shielding film forming the second light-shielding layer; and removing the mask layer.

[0036] In some embodiments, after the light-shielding film is patterned, the fabrication method further includes forming a second electrode layer on the second light-shielding layer. The second electrode layer is in direct contact with the second light-shielding layer, and the second light-shielding layer includes a fourth sub-part located in the peripheral region, wherein the orthographic projection of the fourth sub-part on the first substrate at least partially overlaps with the orthographic projection of the third sub-part on the first substrate. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0038] Figure 1 is a structural diagram of a projection device according to some embodiments;

[0039] Figure 2A is a structural diagram of a display panel according to some embodiments;

[0040] Figure 2B is a plan view of a display panel according to some embodiments;

[0041] Figure 3A is a planar structural diagram of an array substrate according to some embodiments;

[0042] Figure 3B is a magnified view of region C in Figure 3A;

[0043] Figure 3C is a planar structural diagram of a semiconductor pattern according to some embodiments;

[0044] Figure 4 is a cross-sectional view based on section line DD in Figure 3B;

[0045] Figure 5 is another planar structure diagram of the array substrate according to some embodiments;

[0046] Figure 6 is a planar structural diagram of the array substrate when the second light-shielding pattern according to some embodiments includes two first sub-patterns;

[0047] Figure 7 is a planar structural diagram of the array substrate when the second light-shielding pattern is a plate-like structure according to some embodiments;

[0048] Figure 8 is a planar structural diagram of the array substrate when the semiconductor pattern is a U-shaped structure according to some embodiments;

[0049] Figure 9A is a planar structural diagram of the array substrate when the semiconductor pattern is an L-shaped structure according to some embodiments;

[0050] Figure 9B is a planar structural diagram of the array substrate when the semiconductor pattern is a line-shaped structure according to some embodiments;

[0051] Figure 10 is a planar structural diagram of an array substrate when a second light-shielding pattern is set in a row of semiconductor patterns according to some embodiments;

[0052] Figure 11 is another planar structure diagram of the array substrate when a second light-shielding pattern is set in a row of semiconductor patterns according to some embodiments;

[0053] Figure 12A is a magnified view of region E in Figure 3A;

[0054] Figure 12B is a cross-sectional view of a bonding pin according to section line FF in Figure 12A;

[0055] Figure 12C is a cross-sectional view of another bonding pin according to section line FF in Figure 12A;

[0056] Figure 13 is a planar structural diagram of the array substrate when the second conductive layer forms a second light-shielding pattern according to some embodiments;

[0057] Figure 14 is a planar structural diagram of the array substrate when the first light-shielding pattern according to some embodiments includes two second sub-patterns;

[0058] Figure 15 is a planar structural diagram of an array substrate when a first light-shielding pattern is set in a row of semiconductor patterns according to some embodiments;

[0059] Figure 16 is another planar structure diagram of the array substrate when a first light-shielding pattern is set in a row of semiconductor patterns according to some embodiments;

[0060] Figure 17 is a structural diagram of the array substrate when the first and second light-shielding patterns are projected to overlap according to some embodiments.

[0061] Figure 18 is a planar structural diagram of an array substrate when the projections of the first and second light-shielding patterns do not overlap according to some embodiments.

[0062] Figure 19 is a structural diagram of a first or second light-shielding pattern according to some embodiments;

[0063] Figure 20 is a structural diagram of a semiconductor pattern according to some embodiments;

[0064] Figure 21 is a graph showing the relationship between the spacing between the semiconductor pattern and the first light-shielding pattern and the light leakage current according to some embodiments;

[0065] Figure 22 is a structural diagram of an array substrate including a de-reflection layer according to some embodiments;

[0066] Figure 23 is a structural diagram of a color filter substrate according to some embodiments;

[0067] Figure 24 is another structural diagram of a color filter substrate according to some embodiments;

[0068] Figure 25 is another structural diagram of a color filter substrate according to some embodiments;

[0069] Figure 26 is a graph showing the relationship between illumination wavelength and illumination leakage current according to some embodiments;

[0070] Figures 27 to 30 are process steps of fabrication of array substrates according to some embodiments. Detailed Implementation

[0071] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0072] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0073] In this disclosure, terms such as “down,” “below,” “above,” and “up” are used to explain the relationships between components shown in the accompanying drawings. The terms may be relative concepts and described based on the directions shown in the drawings, or based on the sequence of process steps, but are not limited thereto.

[0074] The term "relative" means that the first element can be directly or indirectly relative to the second element. In the case where the third element is between the first and second elements, although they are still relative to each other, the first and second elements can be understood as being indirectly relative to each other.

[0075] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0076] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium.

[0077] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0078] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0079] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0080] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0081] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0082] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0083] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0084] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0085] Some embodiments of this disclosure provide a projection device, such as a liquid crystal display projection device including a liquid crystal display panel. Referring to FIG1, the direction of the arrow in FIG1 can be considered as the propagation direction of light from the projection device. In the propagation direction of light from the projection device, the projection device 1000 may include a light source 1100, a display panel 1200, and a projection lens 1300. The display panel 1200 may be, for example, a liquid crystal display panel, used to form an image and project it from the projection lens 1300. Of course, the structure of the projection device 1000 is not limited to this, as long as the same technical concept is adopted.

[0086] In one example, as shown in Figure 1, the projection device 1000 may further include a first lens assembly 1400, a second lens assembly 1500, and a reflector 1600. Exemplarily, the first lens assembly 1400 is located between the light source 1100 and the display panel 1200, and can be used to collimate the light emitted from the light source 1100, making the light as perpendicular as possible to the display panel 1200; for example, the first lens assembly 1400 may include a Fresnel lens. The second lens assembly 1500 and the reflector 1600 may be sequentially located between the display panel 1200 and the projection lens 1300 along the direction of light propagation. The second lens assembly 1500 can focus the light emitted from the display panel 1200, ensuring that the light emitted from the display panel 1200 completely enters the reflector 1600, which reflects the light to the projection lens 1300, where the light is projected. Of course, the structure of the projection device 1000 is not limited to this. The projection device 1000 may also include any other suitable structure (such as a housing, circuit board, etc.), which will not be listed one by one in the embodiments disclosed herein.

[0087] In some embodiments, referring to FIG2A, the display panel 1200 may include an array substrate 100, a color filter substrate 200, and a liquid crystal layer 300. The array substrate 100 and the color filter substrate 200 are disposed opposite to each other, and the liquid crystal layer 300 is located between the array substrate 100 and the color filter substrate 200. The array substrate 100 may include multiple switching elements, such as thin-film transistors. The color filter substrate 200 may also be referred to as an opposing substrate or a packaged substrate. The color filter substrate 200 may include a black matrix and multiple light filters. The black matrix is ​​used to distinguish multiple sub-pixels and can also be used to block some structures on the array substrate 100 (such as the channels of thin-film transistors). The light filters are used to filter the light incident on the color filter substrate 200 so that the light passing through each light filter presents a color (such as red, green, or blue). The light passing through different light filters can be the same or different colors, thereby enabling the display panel 1200 to achieve color display. Of course, the structure of the display panel is not limited to this. For example, the display panel 1200 may also include alignment films located on the side of the array substrate 100 and the color filter substrate 200 near the liquid crystal layer 300, which will not be listed here.

[0088] In some embodiments, referring to FIG2B, the display panel 1200 may include a display area AA and a peripheral area BB surrounding the display area AA. The display area AA refers to the area in the display panel 1200 used for displaying images, and includes multiple sub-pixels P, where each sub-pixel P is the smallest light-emitting unit in the display panel 1200. The peripheral area BB can be used to set signal traces (such as power signal lines, clock signal lines, etc.), driving circuits (such as gate driving circuits), and bonding pins, etc. Of course, the structure and function of the peripheral area BB are not limited to these, and will not be listed here. The bonding pins can be used for bonding and connecting to the source driver chip and / or the driver circuit board (PCB board).

[0089] In related technologies, the color filter substrate of the display panel is typically positioned facing the light source. That is, the color filter substrate is closer to the light source than the array substrate, and the light emitted from the light source passes through the color filter substrate before reaching the array substrate. In projection devices, the brightness of the light emitted from the light source is generally high; for example, in some high-brightness projection devices, the brightness of the light emitted from the light source may reach 800 lm or higher. The black matrix material in the color filter substrate is usually resin, which has a high light absorption rate. After light enters the color filter substrate, the temperature on the substrate rises significantly (e.g., more than 5°C). This increases the risk of failure of the internal structures of the display panel (including but not limited to alignment films, liquid crystal molecules, and encapsulating adhesives), negatively impacting the lifespan of the projection device. Furthermore, the black matrix material has extremely low reflectivity; light illuminating the black matrix is ​​essentially not reflected back for reuse. Under the same light source conditions, the transmittance of the display panel is low, which is detrimental to improving the projection brightness of the projection device. Moreover, in existing display panels, a black matrix is ​​needed to block light leakage from the metal on the array substrate and the channel structure of the thin-film transistor. There is a large gap between the color filter substrate and the array substrate, and there is a misalignment between the two. In order to ensure that the black matrix can effectively block the corresponding structures on the array substrate, the size of the black matrix usually needs to be set to be large. This will limit the improvement of the aperture ratio and pixel density of the display panel. The pixel density of the display panel directly affects the image quality of its imaging, and thus affects the image quality of the projection device.

[0090] To address at least one of the aforementioned technical problems, referring to Figures 3A, 3B, 3C, and 4, embodiments of this disclosure provide an array substrate 100. The array substrate 100 may include a display area AA and a peripheral area BB surrounding the display area AA. The display area AA and peripheral area BB of the array substrate 100 may correspond to the display area AA and peripheral area BB of a display panel, respectively. For example, multiple sub-pixels may be located in the display area AA of the array substrate 100, and the aforementioned signal traces, driving circuits, and bonding pins may be disposed in the peripheral area BB of the array substrate.

[0091] The array substrate 100 includes a first substrate 10, a first light-shielding layer 20, a semiconductor layer 30, a first conductive layer 14, a second conductive layer 15, and a second light-shielding pattern 13. The semiconductor layer 30 is located on one side of the first substrate 10, the first conductive layer 14 is located on the side of the semiconductor layer 30 away from the first substrate 10, the second conductive layer 15 is located on the side of the first conductive layer 14 away from the first substrate 10, and the first light-shielding layer 20 is located on the side of the semiconductor layer 30 close to the first substrate 10. In other words, the array substrate 100 includes a first substrate 10 and the first light-shielding layer 20, semiconductor layer 30, first conductive layer 14, and second conductive layer 15 sequentially disposed along a direction away from the first substrate 10 (from bottom to top in FIG. 4). The second light-shielding pattern 13 is located on the side of the first conductive layer 14 away from the first substrate 10. Exemplarily, the second light-shielding pattern 13 may be located on the second conductive layer 15, or the second light-shielding pattern 13 may be located on the side of the second conductive layer 15 away from the first substrate 10.

[0092] For example, the first substrate 10 can be a transparent substrate, which can increase the transmittance of the first substrate 10. The material of the transparent substrate can be a rigid material such as glass; or, the material of the first substrate 10 can also be a flexible material such as TAC (tri-cellulose acetate), PI (polyimide), PET (polyethylene terephthalate).

[0093] Semiconductor layer 30 includes a plurality of semiconductor patterns 12 arranged in an array. Each semiconductor pattern 12 includes a channel region 121 and a conductor region 122. Exemplarily, the concentration of doped ions in the conductor region 122 is greater than the concentration of doped ions in the channel region 121, so that the channel region 121 remains semiconductor and the conductor region 122 forms a conductor. In this case, the conductivity of the conductor region 122 is greater than the conductivity of the channel region 121. Exemplarily, the channel region 121 and the conductor region 122 may include the same semiconductor material. The difference between the conductor region 121 and the channel region 122 is that the conductor region 122 undergoes a process (such as a doping process) to make it more conductive. That is, the conductor region 122 refers to the region in the semiconductor pattern 12 that has been treated by the doping process; correspondingly, the channel region 121 refers to the region in the semiconductor pattern 12 that has not been treated to become conductive but still retains its semiconductor properties. In the above doping process, the semiconductor pattern 12 can be doped using the first conductive layer 14 as a mask. At this time, the portion of the semiconductor pattern 12 that is shielded by the first conductive layer 14 is not doped with doped ions, forming a channel region 121; the doped ions mainly dop into the portion of the semiconductor pattern 12 that is not shielded by the first conductive layer 14, and make this portion a conductor region. Based on this, the concentration of doped ions in the conductor region 122 is greater than the concentration of doped ions in the channel region 121. Of course, the semiconductor pattern 12 can also be a structure using a lightly doped drain (LDD) process. The embodiments of this disclosure do not specifically limit the doping process of the semiconductor pattern 12. In some of the accompanying drawings (Figures 3C and 4) provided in the embodiments of this disclosure, the channel region 121 and the conductor region 122 use different filling patterns, but in actual structure, there may be no obvious dividing line between them. Therefore, the positions and shapes of the channel region 121 and the conductor region 122 in the drawings are schematic and are not used to limit the specific structure of the semiconductor pattern 12.

[0094] The first conductive layer 14 includes multiple gate lines 142 and gates 141 electrically connected to the gate lines 142. The orthographic projection of one gate line 142 onto the first substrate 10 may coincide with the orthographic projection of a row of semiconductor patterns 12 onto the first substrate 10. The second conductive layer 15 may include multiple data lines DL, a first electrode 151 electrically connected to the data lines DL, and a second electrode 152. Exemplarily, the portion of the gate line 142 whose orthographic projection onto the first substrate 10 coincides with the orthographic projection of the semiconductor pattern 12 onto the first substrate 10 forms the gate 141. The data lines DL may be used, for example, to transmit data signals, and the portion of the data lines DL used for electrical connection to the semiconductor pattern 12 forms the first electrode 151, for example, the first electrode 151 is integrally formed with the data lines DL. In embodiments of this disclosure, the extension direction of the gate lines 142 is defined as the first direction X, and the extension direction of the data lines DL is defined as the second direction Y. The first direction X and the second direction Y intersect; for example, the first direction X is perpendicular to the second direction Y.

[0095] The array substrate 100 also includes a thin film transistor (TFT) T1, which includes the aforementioned semiconductor pattern 12, a gate 141 located within the first conductive layer 14, and a first electrode 151 and a second electrode 152 located within the second conductive layer 15. The gate 141 is located on the side of the semiconductor pattern 12 away from the first substrate 10; that is, the TFT T1 can be a top-gate transistor. A TFT T1 can be configured to control the charging of the pixel electrode of a sub-pixel.

[0096] The orthographic projection of the first conductive layer 14 on the first substrate 10 mainly covers the orthographic projection of the channel region 121 of the semiconductor pattern 12 on the first substrate 10. That is, the first conductive layer 14 can only be used to block the channel region 121 of the semiconductor pattern 12. In the embodiments of this disclosure, the second light-shielding pattern 13 is disposed on the second conductive layer 15 or on the side of the second conductive layer 15 away from the first substrate. That is, the second light-shielding pattern 13 is disposed on the side of the first conductive layer 14 away from the first substrate 10, which is beneficial to adjust the area of ​​the semiconductor pattern 12 blocked by the second light-shielding pattern 13. For example, the second light-shielding pattern 13 can also be disposed to block part of the conductor region 122 of the semiconductor pattern 12.

[0097] The first light-shielding layer 20 includes a plurality of first light-shielding patterns 11. The orthographic projection of the first light-shielding pattern 11 on the first substrate 10 at least covers the orthographic projection of the channel region 121 of the semiconductor pattern 12 on the first substrate 10. The orthographic projection of the second light-shielding pattern 13 on the first substrate 10 at least covers the orthographic projection of the channel region 121 of the semiconductor pattern 12 on the first substrate 10. That is, on the array substrate 100 and on opposite sides of the semiconductor pattern 12 perpendicular to the first substrate 10, first light-shielding patterns 11 and second light-shielding patterns 13 capable of blocking the channel region 121 of the semiconductor pattern 12 are respectively provided. Thus, light rays incident from the side (lower side) of the semiconductor pattern 12 closer to the first substrate 10 toward the channel region 121 can be blocked by the first light-shielding pattern 11, and light rays incident from the side (upper side) of the semiconductor pattern 12 away from the first substrate 10 toward the channel region 121 can be blocked by the second light-shielding pattern 13. Based on this, during the assembly of the display panel including the above-mentioned array substrate 100 to form a projector, the array substrate 100 can be oriented toward the light source. At this time, the light rays incident from the light source side toward the channel region 121 can be blocked by the first light-blocking pattern 11. The light rays reflected from the side of the array substrate 100 away from the light source toward the array substrate and incident toward the channel region 121 (such as the light rays reflected back to the display panel by the second lens assembly 1500, hereinafter referred to as reflected light) can be blocked by the second light-blocking pattern 13. The first light-blocking pattern 11 and the second light-blocking pattern 13 can effectively block the light in the channel region 121, reducing the risk of light leakage current generated by the thin film transistor T1. Furthermore, when the array substrate 100 has a second light-shielding pattern 13, the size of the black matrix in the channel region of the color filter substrate used to block the semiconductor pattern can be reduced or eliminated. Moreover, the alignment accuracy between the second light-shielding pattern 13 and the semiconductor pattern 12 is better than the alignment accuracy between the black matrix and the semiconductor pattern 12 on the color filter substrate. This facilitates reducing the size of the second light-shielding pattern 13 (compared to the size of the black matrix), thereby improving the aperture ratio and pixel density of the display panel, and enhancing the image quality of the display panel and the projection image quality of the projection device. Furthermore, compared to the color filter substrate, the array substrate includes multiple reflective film structures (such as, but not limited to, the first conductive layer, the first electrode layer, and the second electrode layer), providing better reflectivity. When light emitted from the light source strikes the array substrate, the array substrate can reflect at least a portion of the light. Based on this, a reflective structure can be provided on the display panel near the light source. The light reflected by the array substrate can be reflected back to the display panel by the reflective structure, which helps improve the utilization rate of the light emitted by the light source and enhances the projection brightness of the projection device.

[0098] In some embodiments, continuing to refer to FIG4, the array substrate 100 may further include a first electrode layer 16 and a second electrode layer 17. One of the first electrode layer 16 and the second electrode layer 17 is configured to form a pixel electrode, and the other is configured to form a common electrode. Exemplarily, the first electrode layer 16 is configured to form a pixel electrode, and the second electrode layer 17 is configured to form a common electrode. At this time, the second electrode 152 is also electrically connected to the first electrode layer 16. The thin-film transistor T1 is also configured to be turned on or off under the control of the gate 141, and when the thin-film transistor T1 is turned on, the signal (data signal) transmitted on the data line DL is transmitted to the first electrode layer 16. The second electrode layer 17 is configured to transmit a common voltage signal. An electric field can be generated between the first electrode layer 16 and the second electrode layer 17. The electric field can drive the liquid crystal molecules in the liquid crystal layer to rotate, thereby adjusting the brightness transmitted through the display panel and realizing grayscale display.

[0099] In some embodiments, as shown in FIG4, the array substrate 100 includes a first electrode layer 16 and a second electrode layer 17. The first electrode layer 16 is located on the side of the second conductive layer 15 away from the first substrate 10, and the first electrode layer 16 is electrically connected to the semiconductor pattern 12. For example, the first electrode layer 16 is electrically connected to a second electrode 152, and the second electrode 152 is electrically connected to the conductor region 122 of the semiconductor pattern 12. The first electrode layer 16 is indirectly electrically connected to the semiconductor pattern 12 through the second electrode 152. The second electrode layer 17 is located on the side of the first electrode layer 16 away from the first substrate 10, and is electrically connected to the second light-shielding pattern 13. The second light-shielding pattern 13 is located between the first electrode layer 16 and the second electrode layer 17, and is electrically connected to the second electrode layer 17. This prevents the second light-shielding pattern 13 from forming a floating conductor (not electrically connected to any signal lines or conductive layers). When the second light-shielding pattern 13 forms parasitic capacitances with other conductive structures (such as the first conductive layer, the second conductive layer, or the first electrode layer), it prevents voltage fluctuations in the second light-shielding pattern 13 due to voltage fluctuations on other conductive structures under the influence of these parasitic capacitances. Thus, not only can voltage fluctuations on the second light-shielding pattern 13 be prevented from affecting the characteristics (switching state) of the thin-film transistor T1, reducing the leakage current of the thin-film transistor T1, but the risk of the second light-shielding pattern 13 generating an electric field and affecting the deflection of liquid crystal molecules in the liquid crystal layer can also be reduced.

[0100] In some embodiments, the array substrate can be an Advanced Super Dimension Switch (ADS) type or a High-Advanced Dimension Switch (HADS) type with a high aperture ratio. ADS technology places both the common electrode and pixel electrode on the array substrate. A multidimensional electric field is formed by the electric field generated at the edge of the slit electrode in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer. This allows all oriented liquid crystal molecules within the liquid crystal layer, between the slit electrodes and directly above the electrodes, to rotate, thereby improving the liquid crystal's working efficiency and increasing light transmittance. It also offers advantages such as high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, and no push ripples. HADS technology is an important implementation of ADS technology, featuring an even higher aperture ratio.

[0101] In some embodiments, the orthographic projections of the second electrode layer 17 and the second light-shielding pattern 13 onto the first substrate 10 at least partially overlap. Exemplarily, the second electrode layer 17 can be configured as a slit electrode layer, and the first electrode layer 16 as a plate-like electrode layer; in this case, the second electrode layer 17 may include a plurality of slit openings, and the second electrode layer 17 may cover a portion of the second light-shielding pattern 13 while exposing a portion of the second light-shielding pattern 13. Alternatively, exemplarily, the first electrode layer 16 can be configured as a slit electrode layer, and the second electrode layer 17 as a plate-like electrode layer; in this case, the second electrode layer 17 may cover the entire second light-shielding pattern 13.

[0102] In some embodiments, continuing to refer to FIG4, the second electrode layer 17 is in direct contact with the second light-shielding pattern 13, that is, there is no other film layer between the second electrode layer 17 and the second light-shielding pattern 13. In this way, during the fabrication process of the array substrate 100, the second electrode layer 17 can be fabricated directly after the second light-shielding pattern 13 is formed, without the need to set any conductive layer or insulating layer in between. This not only greatly increases the contact area between the second electrode layer 17 and the second light-shielding pattern 13, but also simplifies the fabrication process of the array substrate 100 and reduces the fabrication cost of the array substrate 100.

[0103] The array substrate 100 may further include an insulating layer located between adjacent conductive layers to prevent short circuits between adjacent conductive layers. As shown in FIG4, the array substrate 100 may further include a fourth insulating layer GI, a first insulating layer ILD1, a planarization layer PLN, a third insulating layer PVX, and a second insulating layer ILD2. The fourth insulating layer GI is located between the semiconductor layer 30 and the first electrode layer 16. Specifically, the fourth insulating layer GI may be located between the semiconductor layer 30 and the first conductive layer 14. The first insulating layer ILD1 is located between the first conductive layer 14 and the first electrode layer 16. Specifically, the first insulating layer ILD1 may be located between the first conductive layer 14 and the second conductive layer 15. The planarization layer PLN may be located between the second conductive layer 15 and the first electrode layer 16. The third insulating layer PVX is located between the first electrode layer 16 and the second electrode layer 17. The second insulating layer ILD2 may be located between the first light-shielding layer 20 and the semiconductor layer 30. Among them, any one of the above-mentioned fourth insulating layer GI, first insulating layer ILD1, planarization layer PLN, third insulating layer PVX and second insulating layer ILD2 can be a single-layer structure formed of a single material, or a multi-layer structure formed of multiple (two or two) materials.

[0104] In some embodiments, referring to Figures 3B and 4, the array substrate further includes a first via V1, which penetrates at least the first insulating layer ILD1 and exposes a portion of the conductor region 122 of the semiconductor pattern 12. Exemplarily, the fourth insulating layer GI may extend substantially across the entire surface of the array substrate, i.e., the fourth insulating layer GI is not patterned to remove areas not covered by the first conductive layer 14 (as shown in Figure 4). In this case, the first via V1 penetrates both the second insulating layer ILD and the fourth insulating layer GI. Alternatively, exemplarily, the fourth insulating layer GI may be patterned within the array substrate, for example, the pattern of the fourth insulating layer GI may be similar to the pattern of the first conductive layer 14. In this case, the fourth insulating layer GI may not cover the conductor region 122 of the semiconductor pattern 12, and the first via V1 only penetrates the second insulating layer ILD.

[0105] Each semiconductor pattern 12 can be provided with two first vias V1. The two first vias V1 expose the portions of the conductor region 122 located on both sides of the channel region 121, that is, the two regions of the conductor region 122 exposed by the two first vias V1 are separated by the channel region 121. The first electrode 151 and the second electrode 152 are electrically connected to the semiconductor pattern 12 through a first via V1, respectively.

[0106] In some embodiments, referring to FIG5, the orthographic projection of the second light-shielding pattern 13 on the first substrate 10 also covers the orthographic projection of the first via V1 on the first substrate 10. As shown in FIG4, the first electrode 151 and the second electrode 152 form a large undulating morphology at the first via V1. For example, the portion of the first electrode 151 and the second electrode 152 covering the sidewall of the first via V1 is the first portion, and the first portion has an angle with the first substrate 10. Moreover, since the first portion has a ring structure along the sidewall of the first via V1, the light reflected by the first portion can scatter in all directions and may hit the semiconductor pattern 12, or the light reflected by the first portion may hit the semiconductor pattern 12 after being reflected again by other film layers. The embodiments of this disclosure provide a second light-shielding pattern 13 to shield the first via V1. In this way, the second light-shielding pattern 13 can also shield at least part of the reflected light hitting the first portion, reducing the risk that the reflected light will be reflected again on the surface of the first portion and hit the semiconductor pattern 12, and reducing the risk of light leakage current generated by the thin film transistor T1.

[0107] For example, as shown in FIG5, the boundary of the orthographic projection of the second light-shielding pattern 13 on the first substrate 10 and the boundary of the orthographic projection of the first via V1 on the first substrate 10 are spaced apart. This can improve the shielding effect on the first via V1. The range of the above-mentioned interval can be 0.2μm to 1.5μm. For example, the above-mentioned interval can be 0.2μm, 0.25μm, 0.5μm, 0.7μm, 0.85μm, 1.2μm or 1.5μm, etc. The embodiments of this disclosure will not be listed one by one.

[0108] In some embodiments, referring to FIG5, along a direction perpendicular to the extension direction of the channel region 121, the orthographic projection of the boundary of the second light-shielding pattern 13 on the first substrate 10 and the orthographic projection of the boundary of the semiconductor pattern 12 on the first substrate 10 are at least 2 μm apart, with a distance D2 greater than or equal to 2 μm; that is, the second light-shielding pattern 13 extends beyond the boundary of the channel region 121 along the width direction of the channel region 121 by a distance greater than 2 μm. This reduces the risk of light entering the channel region 121 from the side and helps to reduce the alignment accuracy requirements between the second light-shielding pattern 13 and the channel region 121. Exemplarily, the distance D2 between the orthographic projection of the boundary of the second light-shielding pattern 13 on the first substrate 10 and the orthographic projection of the boundary of the channel region 121 on the first substrate 10 can be 2 μm, 2.2 μm, 2.5 μm, 2.8 μm, or 3 μm, etc., and these embodiments of the present disclosure will not be listed individually. The extension direction of the channel region 121 refers to the length direction of the channel structure of the thin-film transistor T1, that is, the arrangement direction of the channel region 121 and at least some of the conductor regions 122 located on both sides of the channel region 121 (the second direction Y in Figure 5).

[0109] For example, as shown in FIG5, the extension direction of the channel region 121 of the semiconductor pattern 12 is the second direction Y. Based on this, the direction perpendicular to the extension direction of the channel region 121 is the first direction X. That is, in the first direction X, the two side boundaries of the second light-shielding pattern 13 have the aforementioned interval D2 with the two side boundaries of the semiconductor pattern 12.

[0110] In some embodiments, as shown in FIG6, the semiconductor layer 30 includes a plurality of semiconductor patterns 12 arranged in an array, the plurality of semiconductor patterns 12 being spaced apart; wherein, FIG6 only shows two semiconductor patterns 12 by way of example. By way of example, the plurality of semiconductor patterns 12 are arranged in rows along a first direction X, and the array substrate may include multiple rows of semiconductor patterns (not shown in the figure), the multiple rows of semiconductor patterns being spaced apart along a second direction Y.

[0111] Referring to Figures 6 and 7, the orthographic projection of a second light-shielding pattern 13 on the first substrate covers the orthographic projection of the channel region 121 of a semiconductor pattern 12 on the first substrate. In other words, each semiconductor pattern 12 corresponds to one second light-shielding pattern 13, and multiple second light-shielding patterns 13 are distributed at intervals. This is beneficial for reducing the area of ​​the second light-shielding pattern 13, improving the aperture ratio of the array substrate, and reducing the materials and costs required to fabricate the second light-shielding pattern 13.

[0112] In some embodiments, referring to FIG3B, FIG5 and FIG6, each semiconductor pattern 12 includes two channel regions 121 spaced apart, that is, the thin film transistor T1 including the semiconductor pattern 12 is a dual-gate transistor. And when the orthographic projection of a second light-shielding pattern 13 on the first substrate 10 covers the orthographic projection of the channel region 121 of a semiconductor pattern 12 on the first substrate 10 (each semiconductor pattern 12 is provided with a corresponding second light-shielding pattern 13), each second light-shielding pattern 13 may include two first sub-patterns 131, and the orthographic projection of one first sub-pattern 131 on the first substrate 10 covers the orthographic projection of one channel region 121 on the first substrate 10, that is, the orthographic projections of the two first sub-patterns 131 on the first substrate 10 at least partially overlap with the orthographic projections of the two channel regions 121 on the first substrate 10. As shown in Figures 5 and 6, when the orthographic projection of the second light-shielding pattern 13 on the first substrate 10 also covers the orthographic projection of the first via V1 on the first substrate 10, the first sub-pattern 131 also covers a first via V1 near the channel region 121 it covers.

[0113] In other embodiments, referring to FIG7, when the semiconductor pattern 12 includes two spaced-apart channel regions 121, and the orthographic projection of a second light-shielding pattern 13 on the first substrate 10 covers the orthographic projection of the channel region 121 of a semiconductor pattern 12 on the first substrate 10 (each semiconductor pattern 12 corresponds to one second light-shielding pattern 13), the second light-shielding pattern 13 can also be a single unit. Unlike the structure of the second light-shielding pattern 13 shown in FIGS. 5 and 6, in this embodiment, the two first sub-patterns 131 shown in FIGS. 5 and 6 are interconnected. This simplifies the structure of the second light-shielding pattern 13 and reduces the fabrication difficulty and cost of the array substrate 100.

[0114] In some embodiments, as shown in Figures 3C and 5, when the semiconductor pattern 12 includes two spaced-apart channel regions 121, the conductor region 122 of the semiconductor pattern 12 may include a first sub-region 123 connecting the two channel regions 121 and two second sub-regions 124 located on the side of the two channel regions 121 away from the first sub-region 123. The two first vias V1 may expose portions of the two second sub-regions 124 respectively. The orthographic projection of the second light-shielding pattern 13 on the first substrate 10 covers the orthographic projections of the two channel regions 121 and the two second sub-regions 124 on the first substrate 10. In this way, the portion of the second light-shielding pattern 13 that blocks the channel region 121 and the portion that blocks the first via V1 can be connected as a whole, which helps to simplify the structure of the second light-shielding pattern 13. Furthermore, the second light-shielding pattern 13 covering the second sub-regions 124 can largely block the light incident on the first via V1.

[0115] For example, as shown in FIG5, along the arrangement direction of the channel region 121 and the second sub-region 124 (the second direction Y in FIG5), the orthographic projection of the side boundary (upper boundary) of the second light-shielding pattern 13 away from the first sub-region 123 on the first substrate 10 coincides with the orthographic projection of the side boundary (upper boundary) of the second sub-region 124 away from the first sub-region 123 on the first substrate 10. In this way, not only can the second light-shielding pattern 13 completely block the second sub-region 124, but the size of the second light-shielding pattern 13 in the second direction Y can also be greatly reduced, reducing or even avoiding the risk of a decrease in the aperture ratio of the array substrate 100 caused by setting the second light-shielding pattern 13, which is beneficial to improving the pixel density of the display panel.

[0116] Referring again to Figure 5, the orthographic projection of the second light-shielding pattern 13 onto the first substrate 10 also covers at least a portion of the first sub-region 123 near the channel region 121. This helps to reduce the risk of tilted (at an angle with the direction perpendicular to the first substrate) light rays hitting the channel region 121, and also reduces the risk that the second light-shielding pattern 13 may not completely cover the channel region 121 due to alignment errors between the second light-shielding pattern 13 and the semiconductor pattern 12.

[0117] In some embodiments, as shown in FIG5, the portion of the second light-shielding pattern 13 whose orthogonal projection on the first substrate 10 coincides with the orthogonal projection of the conductor region 122 (first sub-region 123) on the first substrate 10 has a dimension D1 greater than or equal to 1.3 μm along the length direction of the channel region 121 (the second direction in FIG5). In this way, on the one hand, the shielding effect of the second light-shielding pattern 13 on the channel region 121 can be greatly improved. On the other hand, even if the second light-shielding pattern 13 and / or the semiconductor pattern 12 have certain manufacturing errors (critical dimension CD deviation), or if there are certain alignment errors between the second light-shielding pattern 13 and the semiconductor pattern 12, it can still be ensured that the orthogonal projection of the second light-shielding pattern 13 on the first substrate 10 completely covers the orthogonal projection of the channel region 121 on the first substrate 10. For example, the portion where the orthographic projection of the conductor region 122 (first sub-region 123) on the first substrate 10 coincides with the orthographic projection of the second light-shielding pattern 13 on the first substrate 10, has a dimension D1 along the length direction of the channel region 121 that can be 1.3 μm, 1.5 μm, 1.6 μm, 1.9 μm, or 2 μm, etc., and these will not be listed individually in the embodiments of this disclosure. The length direction of the channel region 121 refers to the length direction of the channel structure of the thin-film transistor T1, that is, the arrangement direction of the channel region 121 and at least a portion of the conductor regions 122 located on both sides of the channel region 121 (the second direction Y in FIG. 5).

[0118] The dimension D1 of the second light-shielding pattern 13 covering the conductor region 122 (first sub-region 123) can be related to the manufacturing process precision of the display panel. When the manufacturing process precision of the display panel changes, the dimension D1 of the second light-shielding pattern 13 covering the first sub-region 123 can also be adaptively adjusted. For example, when the array substrate is manufactured using high-precision manufacturing equipment, the dimension D1 of the second light-shielding pattern 13 covering the first sub-region 123 can be appropriately reduced. For example, the dimension D1 of the second light-shielding pattern 13 covering the first sub-region 123 can be greater than 0.6μm, 0.8μm, 1μm, or 1.1μm, etc.

[0119] In some embodiments, the semiconductor pattern 12 may include only one channel region 121, that is, the thin film transistor formed by the semiconductor pattern 12 is not a dual-gate transistor. In this case, the conductor region 122 of the semiconductor pattern 12 includes only two second sub-regions 124 located on both sides of the channel region 121. The orthogonal projection of the second light-shielding pattern 13 on the first substrate 10 can cover the orthogonal projection of the semiconductor pattern 12 on the first substrate 10.

[0120] In some embodiments, referring to FIG8, the semiconductor pattern 12 can be a U-shaped structure. In this case, the semiconductor pattern 12 includes two extensions 125 disposed opposite to each other and a connecting portion 126. The two extensions 125 can be spaced apart along a first direction X and both extend along a second direction Y. The two ends of the connecting portion 126 are respectively connected to the two ends of the two extensions 125 located on the same side (e.g., the lower side). The orthographic projection of the gate line 142 on the first substrate 10 can coincide with the orthographic projection portion of the two extensions 125 on the first substrate 10, and is spaced apart from the orthographic projection of the connecting portion 126 on the first substrate 10.

[0121] Alternatively, in some embodiments, referring to FIG9A, the semiconductor pattern 12 can also be an L-shaped structure. In this case, the semiconductor pattern 12 can include two extensions 125, the extension directions of the two extensions 125 having an included angle, for example, the extension directions of the two extensions 125 can be perpendicular to each other. The ends of the two extensions 125 that are close to each other are connected to each other. In this case, the gate line 142 can include a first main body 143 extending along the first direction X, and a first protrusion 144 integrally disposed with the first main body 143 and protruding from one side of the main body 143 along the second direction Y. The orthographic projection of the first main body 143 on the first substrate coincides with the orthographic projection of one extension 125 on the first substrate, and the orthographic projection of the first protrusion 144 on the first substrate coincides with the orthographic projection of the other extension 125 on the first substrate. Figure 9A only shows the structure of semiconductor pattern 12, first conductive layer 14 and second conductive layer 15 by way of example. The array substrate 100 may also include other film layers (such as first light-shielding layer, first electrode layer, second electrode layer and second light-shielding pattern, etc.), which will not be shown here.

[0122] Alternatively, in some embodiments, referring to FIG9B, the semiconductor pattern 12 can also be a linear structure. In this case, at least a portion of the semiconductor pattern 12 extends along a straight line. For example, the two channel regions of the semiconductor pattern 12 and the first sub-region connecting the two channel regions are spaced apart along a straight line. The gate line 142 may include a second main body portion 145 extending along a first direction X, and two second protrusions 146 integrally disposed with the first main body portion 143 and protruding from one side of the second main body portion 145 along a second direction Y. The two second protrusions 146 are spaced apart along the first direction X. The orthographic projection of the second main body portion 145 on the first substrate does not coincide with the orthographic projection of the semiconductor pattern 12 on the first substrate, while the orthographic projections of the two second protrusions 146 on the first substrate both partially coincide with the orthographic projection of the semiconductor pattern 12 on the first substrate. FIG7 only exemplarily shows the structure of the semiconductor pattern 12, the first conductive layer 14, and the second conductive layer 15. The array substrate may also include other film layers, which will not be shown in detail here.

[0123] Of course, the shape and structure of the semiconductor pattern 12 in this application include, but are not limited to, the three specific embodiments shown in Figures 8, 9A, and 9B above. The shape and structure of the semiconductor pattern 12 can be flexibly designed according to actual needs. The embodiments disclosed herein will not be listed one by one, as long as the same technical concept as this application is adopted. That is, when the shape of the semiconductor pattern 12 changes, the position and shape of the first light-shielding pattern 11 and the second light-shielding pattern 13 are also adaptively adjusted so that the orthogonal projection of the first light-shielding pattern 11 and the second light-shielding pattern 13 on the substrate can at least cover the channel region 121 of the semiconductor pattern 12. In all the embodiments and figures of this disclosure below, the shape and structure of the semiconductor pattern 12 shown in Figure 8 are only described by way of example and should be understood as an explanatory description and example of this application, rather than a limitation on the structure of the array substrate of this application.

[0124] Referring to Figure 5, when the semiconductor pattern 12 is a U-shaped structure and the second light-shielding pattern 13 includes two first sub-patterns 131, the two first sub-patterns 131 can be distributed at intervals along the first direction X, the first sub-patterns 131 extend along the second direction Y, and one first sub-pattern 131 covers a channel region 121 and a first via V1 near the channel region 121.

[0125] In some embodiments, referring to FIG10, the semiconductor layer 30 includes multiple rows of semiconductor patterns 12, and each row of semiconductor patterns 12 includes a plurality of semiconductor patterns 12 spaced apart along a first direction X, that is, the plurality of semiconductor patterns 12 are arranged in a row along the first direction X. The first conductive layer 14 includes a plurality of gate lines 142, the orthographic projection of one gate line 142 on the first substrate 10 partially overlaps with the orthographic projection of a row of semiconductor patterns 12 on the first substrate 10, and (one gate line 142) is configured as the gate 141 of a row of thin-film transistors. A second light-shielding pattern 13 is correspondingly provided for each row of semiconductor patterns 12. At this time, the orthographic projection of the second light-shielding pattern 13 on the first substrate 10 covers the orthographic projection of the channel region 121 of the row of semiconductor patterns 12 on the first substrate 10, that is, it at least partially overlaps with each semiconductor pattern 12 included in the row of semiconductor patterns 12. In this way, the structure of the second light-shielding pattern 13 can be further simplified, and the second light-shielding pattern 13 can also serve to separate adjacent sub-pixels along the second direction Y.

[0126] When a second light-shielding pattern 13 is provided corresponding to a row of semiconductor patterns 12, as shown in FIG10, the second light-shielding pattern 13 extends along the first direction X, and the second light-shielding pattern 13 includes a third extension segment 132 and a fourth extension segment 133 alternately connected along the first direction X. The orthographic projection of the third extension segment 132 on the first substrate 10 at least partially coincides with the orthographic projection of the extension portion 125 on the first substrate 10, and the orthographic projection of the fourth extension segment 133 on the first substrate 10 does not coincide with the orthographic projection of the extension portion 125 on the first substrate 10. That is, the third extension segment 132 is the part used to shield the semiconductor pattern 12, and the fourth extension segment 133 is the part used to connect the third extension segment 132. The dimension of the third extension segment 132 along the second direction Y is equal to the dimension of the fourth extension segment 133 along the second direction Y. That is, the dimension of the second light-shielding pattern 13 along the second direction Y is equal at any position in the first direction X, that is, the line width of the second light-shielding pattern 13 is equal everywhere in its extension direction. This helps to simplify the structure of the second light-shielding pattern 13, and the uniformity of the second light-shielding pattern 13 is better.

[0127] Alternatively, when a second light-shielding pattern 13 is provided corresponding to a row of semiconductor patterns 12, as shown in FIG11, the second light-shielding pattern 13 extends along the first direction X, and the second light-shielding pattern 13 includes a third extension segment 132 and a fourth extension segment 133 alternately connected along the first direction X. The orthographic projection of the third extension segment 132 on the first substrate 10 at least partially coincides with the orthographic projection of the extension portion 125 on the first substrate 10, and the orthographic projection of the fourth extension segment 133 on the first substrate 10 does not coincide with the orthographic projection of the extension portion 125 on the first substrate 10. That is, the third extension segment 132 is the portion used to shield the semiconductor pattern 12, and the fourth extension segment 133 is the portion used to connect the third extension segment 132. The dimension of the third extension segment 132 in the second direction Y can be larger than the dimension of the fourth extension segment 133 in the second direction Y.

[0128] For example, as shown in FIG11, along the second direction Y, the third extension segment 132 and the fourth extension segment 133 are flush with the end (upper end) away from the connecting portion 126 along the second direction Y, the third extension segment 132 is close to the end (lower end) of the connecting portion 126, and the fourth extension segment 133 protrudes from the end (lower end) of the connecting portion 126. That is, the second light-shielding pattern 13 protrudes downward at the position where the third extension segment 132 is located to form a protrusion.

[0129] For example, as shown in FIG11, the orthographic projection of the side boundary of the third extension 132 away from the connector 126 on the first substrate 10 coincides with the orthographic projection of the side boundary of the extension 125 away from the connector 126 on the first substrate 10 (without considering critical dimension CD deviation and alignment error). The orthographic projection of the side boundary of the fourth extension 133 near the connector 126 on the first substrate 10 coincides with the orthographic projection of the side boundary of the gate line 142 near the connector 126 on the first substrate 10. In this way, the second light-shielding pattern 13 can also be used to block reflected light incident on the gate line 142. When the second light-shielding pattern 13 includes the third extension 132 and the fourth extension 133, the dimensional relationship of the fourth extension 133 and the relative positional relationship between the fourth extension 133 and other film layers (such as semiconductor patterns and second conductive layers) include, but are not limited to, the scheme shown in FIG11. The shape, size and relative positional relationship of the fourth extension can also be adjusted according to actual needs.

[0130] In some embodiments, referring to Figures 12A, 12B and 12C, the array substrate 100 may further include bonding pins 50 located in the peripheral area BB of the array substrate. The bonding pins 50 can be used to bond and connect with components including but not limited to chips and circuit boards. For example, the chips or circuit boards can be electrically connected to the bonding pins through processes including but not limited to pressing and soldering processes.

[0131] In some embodiments, referring to FIG12B, the bonding pin 50 includes a first sub-part 51 located on the first conductive layer 14, a second sub-part 52 located on the second conductive layer 15, and a third sub-part 53 disposed on the same layer as the second light-shielding pattern 13. The second sub-part 52 is electrically connected to both the first sub-part 51 and the third sub-part 53; that is, the bonding pin 50 may include the first sub-part 51, the second sub-part 52, and the third sub-part 53 stacked together. The orthographic projection of the third sub-part 53 on the first substrate 10 covers the orthographic projection of the second sub-part 52 on the first substrate 10. For example, the third sub-part 53 is in direct contact with the second sub-part 52, and the third sub-part 53 covers the surface of the second sub-part 52 away from the first substrate 10.

[0132] In other embodiments, as shown in FIG12C, the bonding pin 50 includes a first sub-part 51 located on the first conductive layer 14, a second sub-part 52 located on the second conductive layer 15, a third sub-part 53 disposed on the same layer as the second light-shielding pattern 13, and a fourth sub-part 54 located on the second electrode layer 17. The second sub-part 52 is electrically connected to both the first sub-part 51 and the third sub-part 53, and the fourth sub-part 54 is electrically connected to the third sub-part 53. That is, the bonding pin 50 may include the first sub-part 51, the second sub-part 52, the third sub-part 53, and the fourth sub-part 54 stacked together. The orthographic projection of the third sub-part 53 on the first substrate 10 overlaps the orthographic projection of the second sub-part 52 on the first substrate 10. For example, the third sub-part 53 is in direct contact with the second sub-part 52, and the third sub-part 53 covers the surface of the second sub-part 52 away from the first substrate 10. The orthographic projection of the fourth sub-part 54 on the first substrate 10 overlaps the orthographic projection of the third sub-part 53 on the first substrate 10. For example, the fourth sub-part 54 is in direct contact with the third sub-part 53, and the fourth sub-part 54 covers the surface of the third sub-part 53 away from the first substrate 10.

[0133] In the embodiments of this disclosure, the bonding pin 50 includes a third sub-part 53 disposed on the same layer as the second light-shielding pattern 13. On the one hand, this can avoid damage to the second sub-part 52 during the fabrication process of the second light-shielding pattern 13 (in the etching process), reducing the risk of defects in the bonding pin 50. On the other hand, the third sub-part 53 and the second light-shielding pattern 13 are made of the same material and disposed on the same layer. For example, the third sub-part 53 and the second light-shielding pattern 13 can be made of the same material and fabricated in the same step using the same mask, without the need for an additional process to form the third sub-part 53, thus not increasing the fabrication cost of the array substrate.

[0134] In some embodiments, as shown in Figures 12A, 12B, and 12C, the array substrate 100 further includes a first signal line 19 located in the peripheral region BB and in the second conductive layer 15. The first signal line 19 is spaced from the second sub-part 52. The first sub-part 51 is also electrically connected to the first signal line 19.

[0135] For example, the array substrate 100 may include multiple rows of bonding pins 50, with adjacent rows of bonding pins 50 staggered. In each bonding pin 50, the width (dimension along the first direction X) of the second sub-part 52 is greater than the width (dimension along the first direction X) of the first sub-part 51. Based on this, compared to the first signal line 19 being electrically connected to the bonding pin 50 via the second sub-part 52, as shown in FIG12A, in the peripheral area BB, the first signal line 19 located in the second conductive layer 15 is connected to the bonding pin 50 via the first sub-part 51 located in the first conductive layer 14. This allows for more (e.g., two) first sub-parts 51 to be provided between adjacent bonding pins 50, reducing the spacing between the first sub-part 51 and other rows of bonding pins 50. This is beneficial for increasing the density of the bonding pins and improving the space utilization of the peripheral area BB.

[0136] In some embodiments, referring to FIG13, the second light-shielding pattern 13 is located in the second conductive layer 15. A first electrode 151 is integrally disposed with the second light-shielding pattern 13, and the orthogonal projection of the first electrode 151 on the first substrate 10 overlaps the orthogonal projection of a channel region 121 on the first substrate 10; and / or, a second electrode 152 is integrally disposed with the second light-shielding pattern 13, and the orthogonal projection of the second electrode 152 on the first substrate 10 overlaps the orthogonal projection of a channel region 121 on the first substrate 10. By disposing the second light-shielding pattern 13 within the second conductive layer 15, an additional process step is not required to fabricate the second light-shielding pattern 13, which facilitates a simplified fabrication process for the array substrate and reduces fabrication costs. Exemplarily, the second light-shielding pattern 13 includes two spaced-apart sub-patterns 131, with the two first sub-patterns 131 integrally disposed with the first electrode 151 and the second electrode 152, respectively; or, the two first sub-patterns 131 respectively form the first electrode 151 and the second electrode 152.

[0137] In the case where the second light-shielding pattern 13 is disposed within the second conductive layer 15, the structure of the two first sub-patterns 131 can be referred to Figures 3B, 5, and 6 above. The area and size of the semiconductor pattern 12 covered by the first sub-pattern 131 are also referred to above and will not be repeated here. Furthermore, unlike the embodiment described above where the second light-shielding pattern 13 is disposed between the first electrode layer 16 and the second electrode layer 17, in the case where the second light-shielding pattern 13 is disposed within the second conductive layer 15, the second light-shielding pattern 13 can only include two spaced-apart first sub-patterns 131, and each semiconductor pattern 12 corresponds to two first sub-patterns 131. The two first sub-patterns cannot be connected as a whole; that is, the second light-shielding pattern 13 cannot be configured as shown in Figure 7 or Figure 10. This is to avoid short-circuiting between the first electrode 151 and the second electrode 152 of the thin-film transistor T1, which includes the semiconductor pattern 12.

[0138] In some embodiments, as shown in FIG13, the array substrate 100 further includes a data line DL, the data line DL being integrally disposed with one of the first sub-patterns 131, and the line width of the first sub-pattern 131 being greater than the line width of the data line DL.

[0139] In some embodiments, referring to FIG14, the semiconductor layer 30 includes a plurality of semiconductor patterns 12 arranged in an array. Each thin-film transistor T1 may include one semiconductor pattern 12, and the plurality of semiconductor patterns 12 may be arranged in a row along a first direction X. Each semiconductor pattern 12 includes two channel regions 121 spaced apart. The orthographic projection of each first light-shielding pattern 11 on the first substrate 10 covers the orthographic projection of the channel region 121 of a semiconductor pattern 12 on the first substrate 10, that is, each semiconductor pattern 12 is respectively provided with a first light-shielding pattern 11.

[0140] In some embodiments, the first light-shielding pattern 11 includes two second sub-patterns 111, the orthographic projections of the two second sub-patterns 111 onto the first substrate 10 at least partially overlapping with the orthographic projections of the two channel regions 121 onto the first substrate 10. In this case, the structure, shape, and size of the first light-shielding pattern 11 can be the same as the structure, shape, and size of the second light-shielding pattern 13 shown in FIG. 3B or FIG. 5, and will not be described again here. Of course, at least one of the structure, shape, and size of the first light-shielding pattern 11 can also be different from the second light-shielding pattern 13 shown in FIG. 3B or FIG. 5. For example, the size of the first light-shielding pattern 11 can be slightly larger or slightly smaller than the size of the second light-shielding pattern 13, and will not be described again in detail in the embodiments of this disclosure.

[0141] In some embodiments, referring to FIG15, the semiconductor layer 30 includes a plurality of semiconductor patterns 12 arranged in an array. Each thin-film transistor T1 may include a semiconductor pattern 12, and the plurality of semiconductor patterns 12 may be arranged in a row along a first direction X. The first conductive layer 14 includes a plurality of gate lines 142, the orthographic projection of one gate line 142 on the first substrate 10 partially overlapping the orthographic projection of a row of semiconductor patterns 12 on the first substrate 10. The orthographic projection of a first light-shielding pattern 11 on the first substrate 10 covers the orthographic projection of the channel region 121 of a row of semiconductor patterns 12 on the first substrate 10. That is, a row of semiconductor patterns 12 corresponds to a first light-shielding pattern 11, and the orthographic projection of the first light-shielding pattern 11 on the first substrate 10 at least partially overlaps with the orthographic projection of a row of semiconductor patterns 12 on the first substrate 10. In other words, the orthographic projection of the first light-shielding pattern 11 on the first substrate 10 at least partially overlaps with each semiconductor pattern 12 included in a row of semiconductor patterns 12. This further simplifies the structure of the first light-shielding pattern 11. At this time, the structure, shape, and size of the first light-shielding pattern 11 can be the same as those of the second light-shielding pattern 13 shown in FIG10, and will not be described again here. Of course, at least one of the structure, shape, and size of the first light-shielding pattern 11 can also be different from that of the second light-shielding pattern 13 shown in FIG10. For example, the size of the first light-shielding pattern 11 can be slightly larger or slightly smaller than the size of the second light-shielding pattern 13. The embodiments of this disclosure will not be described in detail here.

[0142] In some embodiments, as shown in FIG15, the first light-shielding pattern 11 extends along a first direction X, and the first light-shielding pattern 11 includes alternating first extension segments 112 and second extension segments 113. The orthographic projection of the first extension segment 112 on the first substrate 10 at least covers the orthographic projection of the channel region 121 on the first substrate 10, and the orthographic projection of the second extension segment 113 on the first substrate 10 does not coincide with the orthographic projection of the channel region 121 on the first substrate 10. That is, the first extension segment 112 refers to the portion used to shield the semiconductor pattern 12, and the second extension segment 113 refers to the portion used to connect adjacent first extension segments 112. The dimension of the first extension segment 112 along the second direction Y is equal to the dimension of the second extension segment 113 along the second direction Y, or in other words, the dimension of the first light-shielding pattern 11 is equal at all points along the first direction X in the direction perpendicular to the first direction X, that is, the linewidth of the first light-shielding pattern 11 is equal everywhere in its extension direction. This is beneficial to simplifying the structure of the first light-shielding pattern 11 and improving the uniformity of the first light-shielding pattern 11.

[0143] In some embodiments, referring to Figures 8 and 16, the semiconductor pattern 12 has a U-shaped structure, including two extensions 125 and a connecting portion 126. The two extensions 125 may be spaced apart along a first direction X and both extend along a second direction Y. The two ends of the connecting portion 126 are respectively connected to the two ends of the two extensions 125 on the same side (e.g., the lower side). The orthographic projection of the gate line GL on the first substrate 10 may coincide with the orthographic projection portion of the two extensions 125 on the first substrate 10, and is spaced apart from the orthographic projection of the connecting portion 126 on the first substrate 10.

[0144] Along the first direction X, the first light-shielding pattern 11 includes alternating first extensions 112 and second extensions 113. The orthographic projection of the first extension 112 onto the first substrate 10 at least covers the orthographic projection of the channel region 121 onto the first substrate 10, and the orthographic projection of the second extension 113 onto the first substrate 10 does not coincide with the orthographic projection of the channel region 121 onto the first substrate 10. The dimension of the first extension 112 in the second direction Y is larger than the dimension of the second extension 113 in the second direction Y.

[0145] In some embodiments, as shown in FIG16, along the second direction Y, the ends (upper ends) of the first extension segment 112 and the second extension segment 113 away from the connecting portion 126 are flush, the end of the first extension segment 112 near the connecting portion 126 protrudes from the end (lower end) of the second extension segment 113 near the connecting portion 126. That is, the first light-shielding pattern 11 protrudes downward at the location of the first extension segment 112 to form a protrusion.

[0146] For example, the orthographic projection of the side boundary of the first extension 112 away from the connector 126 on the first substrate 10 coincides with the orthographic projection of the side boundary of the extension 125 away from the connector 126 on the first substrate 10. The orthographic projection of the side boundary of the second extension 113 near the connector 126 on the first substrate 10 coincides with the orthographic projection of the side boundary of the gate line 142 near the connector 126 on the first substrate 10. Thus, the second light-shielding pattern 13 can also be used to block reflected light incident on the gate line GL. When the first light-shielding pattern 11 includes the first extension 112 and the second extension 113, the dimensional relationship of the second extension 113 and its relative positional relationship with other film layers (such as semiconductor layers and second conductive layers) include, but are not limited to, the scheme shown in FIG11. The shape, size, and relative positional relationship of the fourth extension can also be adjusted according to actual needs.

[0147] Referring to Figures 14, 15, and 16, the structure, shape, and size of the first light-shielding pattern 11 can be the same as those of the second light-shielding pattern 13 shown in Figures 5, 10, and 11, respectively, and will not be described again here. Of course, at least one of the structure, shape, and size of the first light-shielding pattern 11 can also be different from that of the second light-shielding pattern 13. For example, the size of the first light-shielding pattern 11 can be slightly larger or slightly smaller than the size of the second light-shielding pattern 13, and the embodiments of this disclosure will not be described in detail here.

[0148] For example, referring to FIG14, the orthographic projection of the first light-shielding pattern 11 on the first substrate 10 covers at least a portion of the orthographic projection of the two channel regions 121, the two second sub-regions 124, and the first sub-region 123 near the channel region 121 on the first substrate 10.

[0149] For example, referring to FIG14, the portion where the orthographic projection of the conductor region 122 on the first substrate 10 overlaps with the orthographic projection of the first light-shielding pattern 11 on the first substrate 10 has a dimension D6 greater than or equal to 1.3 μm along the length direction of the channel region 121. For example, the portion where the orthographic projection of the first light-shielding pattern 11 on the first substrate 10 overlaps with the orthographic projection of the first sub-region 123 on the first substrate 10 has a dimension D6 greater than or equal to 1.3 μm along the length direction of the channel region 121. In this way, on the one hand, the shielding effect of the first light-shielding pattern 11 on the channel region 121 can be greatly improved; on the other hand, even if there are certain manufacturing errors (critical dimension CD deviation) in the first light-shielding pattern 11 and / or the semiconductor pattern 12, or if there are certain alignment errors between the first light-shielding pattern 11 and the semiconductor pattern 12, it can still be ensured that the orthographic projection of the first light-shielding pattern 11 on the first substrate 10 completely covers the orthographic projection of the channel region 121 on the first substrate 10. For example, the portion where the first sub-region 123 and the first light-shielding pattern 11 overlap on the first substrate 10, the size D6 along the direction from the channel region 121 to the first sub-region 123 can be 1.3μm, 1.4μm, 1.6μm, 1.8μm or 2μm, etc., and the embodiments of this disclosure will not be listed one by one.

[0150] Referring to FIG14, the distance D7 between the orthographic projection of the boundary of the first light-shielding pattern 11 on the first substrate 10 and the orthographic projection of the channel region 121 on the first substrate 10 along a direction perpendicular to the extension direction of the channel region 121 is greater than or equal to 2 μm. In other words, in the orthographic projections of the first light-shielding pattern 11 and the semiconductor pattern 12 on the first substrate 10, the distance D7 between the boundary of the first light-shielding pattern 11 and the boundary of the semiconductor pattern 12 along a direction perpendicular to the extension direction of the channel region 121 is greater than or equal to 2 μm. This reduces the risk of light entering the channel region 121 from the side and helps to reduce the alignment accuracy requirements between the first light-shielding pattern 11 and the channel region 121. Exemplarily, the distance D7 between the orthographic projection of the boundary of the first light-shielding pattern 11 on the first substrate 10 and the orthographic projection of the boundary of the channel region 121 on the first substrate 10 can be 2 μm, 2.3 μm, 2.5 μm, 2.7 μm, or 3 μm, etc., and will not be listed individually in the embodiments of this disclosure.

[0151] In some embodiments, as shown in FIG17, the orthographic projections of the first light-shielding pattern 11 and the second light-shielding pattern 13 on the first substrate 10 completely overlap, that is, the first light-shielding pattern 11 and the second light-shielding pattern 13 have the same shape and the same size. In this way, the areas and sizes of the first light-shielding pattern 11 and the second light-shielding pattern 13 that block the semiconductor pattern 12 are the same. While ensuring the light-shielding effect of the first light-shielding pattern 11 and the second light-shielding pattern 13, the area of ​​the orthographic projection of the first light-shielding pattern 11 and the second light-shielding pattern 13 on the first substrate 10 can be reduced, thereby reducing the impact of the first light-shielding pattern 11 and the second light-shielding pattern 13 on the pixel density of the array substrate, which is beneficial to improving the pixel density of the array substrate.

[0152] In some embodiments, the orthographic projections of the first light-shielding pattern 11 and the second light-shielding pattern 13 on the first substrate 10 may at least partially not overlap. For example, the shape of the first light-shielding pattern 11 may be any of the shapes shown in Figures 14 to 16, and the shape of the second light-shielding pattern 13 may be any of the shapes shown in Figures 3B, 5, 7, 9B, and 10. Moreover, the pattern shapes of the first light-shielding pattern 11 and the second light-shielding pattern 13 are different.

[0153] In some embodiments, the orthographic projections of the first light-shielding pattern 11 and the second light-shielding pattern 13 onto the first substrate 10 may at least partially not overlap. For example, the first light-shielding pattern 11 and the second light-shielding pattern 13 may have the same shape, but the dimensions of the first light-shielding pattern 11 and the second light-shielding pattern 13 may have a certain difference.

[0154] In some embodiments, the array substrate 100 of the present disclosure includes a first light-shielding pattern 11 and a second light-shielding pattern 13. When a display panel formed from the array substrate 100 is assembled to form a projection device, the array substrate 100 can be positioned facing the light source, or the color filter substrate can be positioned facing the light source. When the projection device is working, the light entering the array substrate from the light source side is more than the reflected light entering the array substrate from the side away from the light source. Based on this, the orthographic projection of one of the light-incident sides of the first light-shielding pattern 11 and the second light-shielding pattern 13 (the one away from the light source) on the first substrate 10 is located within the range of the orthographic projection of the other (the one closer to the light source) on the first substrate 10, and the minimum interval between the orthographic projection of the boundary of the first light-shielding pattern 11 on the first substrate 10 and the orthographic projection of the boundary of the second light-shielding pattern 13 on the first substrate 10 is less than or equal to 1.1 μm. This increases the size of the light-incident side of the first light-shielding pattern 11 and the second light-shielding pattern 13 that is closer to the array substrate 100 (hereinafter referred to as the target light-shielding pattern), which is beneficial to improving the blocking effect of the target light-shielding pattern on the light incident on the semiconductor pattern 12.

[0155] When the array substrate 100 is oriented toward the light source, as shown in FIG18, the array substrate 100 is configured such that light is incident from the side of the first substrate 10 away from the semiconductor pattern 12. In this case, the amount of light incident on the semiconductor pattern 12 from the side of the first light-shielding pattern 11 is much greater than the amount of light incident on the semiconductor pattern 12 from the side of the second light-shielding pattern 13. Based on this, the orthographic projection of the second light-shielding pattern 13 on the first substrate 10 can be positioned within the range of the orthographic projection of the first light-shielding pattern 11 on the first substrate 10, and the minimum distance D5 between the orthographic projection of the boundary of the second light-shielding pattern 13 and the orthographic projection of the boundary of the first light-shielding pattern 11 on the first substrate 10 is less than or equal to 1.1 μm. Thus, the first light-shielding pattern 11, as the main light-shielding pattern, can have its size appropriately increased, which is beneficial for improving the blocking effect of the first light-shielding pattern 11 on the light incident on the semiconductor pattern 12. For example, the minimum interval D5 between the orthographic projection of the boundary of the second light-shielding pattern 13 on the first substrate 10 and the orthographic projection of the boundary of the first light-shielding pattern 11 on the first substrate 10 can be 0.3μm, 0.5μm, 0.8μm, 1.0μm or 1.1μm, etc.

[0156] When the color filter substrate is oriented towards the light source, the array substrate 100 is configured such that light is incident from the side of the second light-shielding pattern 13 away from the first substrate 10. At this time, the amount of light incident on the semiconductor pattern 12 from the side of the second light-shielding pattern 13 is much greater than the amount of light incident on the semiconductor pattern 12 from the side of the first light-shielding pattern 11. Based on this, the orthographic projection of the first light-shielding pattern 11 on the first substrate 10 can be positioned within the range of the orthographic projection of the second light-shielding pattern 13 on the first substrate 10, and the minimum distance between the orthographic projection of the boundary of the first light-shielding pattern 11 and the orthographic projection of the boundary of the second light-shielding pattern 13 on the first substrate 10 is less than or equal to 1.1 μm. Thus, with the first light-shielding pattern 11 as the primary light-shielding pattern, the size of the second light-shielding pattern 13 can be appropriately increased, which is beneficial for improving the blocking effect of the second light-shielding pattern 13 on the light incident on the semiconductor pattern 12. For example, the minimum interval between the orthographic projection of the boundary of the second light-shielding pattern 13 on the first substrate 10 and the orthographic projection of the boundary of the first light-shielding pattern 11 on the first substrate 10 can be 0.3μm, 0.5μm, 0.8μm, 1.0μm or 1.1μm, etc.

[0157] In some embodiments, the array substrate 100 is configured to receive light from the side of the first substrate 10 away from the semiconductor layer 30, i.e., the array substrate 100 is positioned toward the light source. Referring to FIG. 19, the arrows in FIG. 19 represent the direction of light propagation. The slope angle α of the sidewall 114 of the first light-shielding layer 20 is greater than 90°, and / or, the slope angle α of the sidewall 135 of the second light-shielding pattern 13 is greater than 90°. The slope angle α refers to the angle between the sidewall 114 of the first light-shielding layer 20 (or the sidewall 135 of the second light-shielding pattern 13) and the surface of the first light-shielding layer 20 near the first substrate 10. In this way, stray light rays (light rays with an angle to the direction perpendicular to the first substrate 10) that enter the sidewall 114 (or sidewall 115) from the light source side can be reflected on the sidewall 114 as far as possible towards the light source side, or towards the side away from the first light-shielding layer 20, that is, towards the direction away from the semiconductor pattern 12. This can reduce the risk of the stray light rays entering the semiconductor pattern 12 after being reflected on the sidewall 114, thereby improving the light-shielding effect of the first light-shielding layer 20 and the second light-shielding pattern 13.

[0158] In other embodiments, the array substrate 100 is configured such that light is incident from the side of the first substrate 10 near the semiconductor layer 30, i.e., the color filter substrate is positioned towards the light source. In this case, the slope angle of the sidewall 114 of the first light-shielding layer 20 can be less than 90°, and / or, the slope angle of the sidewall 135 of the second light-shielding pattern 13 can be less than 90°. In this way, stray light rays (light rays with an angle to the direction perpendicular to the first substrate 10) incident from the light source side into the sidewall 114 (or sidewall 115) can be reflected at the sidewall 114 as much as possible towards the light source side, thereby reducing the risk of the stray light rays being reflected from the sidewall 114 onto the semiconductor pattern 12, and thus improving the light-shielding effect of the first light-shielding layer 20 and the second light-shielding pattern 13.

[0159] In some embodiments, referring to Figures 3B and 5, the dimension (width) of the semiconductor pattern 12 at the location for connection with the first electrode 151 and the second electrode 152 is larger than the dimensions of other portions of the semiconductor pattern 12. This helps to reduce the alignment difficulty between the first via V1 and the semiconductor pattern 12, and also helps to increase the size of the first via V1.

[0160] In other embodiments, referring to FIG20, the semiconductor pattern 12 has equal dimensions in the direction perpendicular to the extension direction of the semiconductor pattern 12, that is, the linewidth is equal at all positions of the semiconductor pattern 12. For example, when the semiconductor pattern 12 has a U-shaped structure, the semiconductor pattern 12 includes two extensions 125 and a connecting portion 126. The two extensions 125 are arranged opposite each other along a first direction X and both extend along a second direction Y. The two ends of the connecting portion 126 are respectively connected to the ends of the two extensions 125 located on the same side. The dimension D3 of the extension 125 along the first direction X is equal to the dimension D3 of the connecting portion along the second direction Y. For example, the end of the extension 125 away from the connecting portion 126 is used for electrical connection with the first electrode 151 and the second electrode 152. The dimensions of the extension 125 in the first direction X are the same at all positions along the second direction Y. In this way, the photosensitive area of ​​the semiconductor pattern 12 can be reduced, the risk of light shining on the semiconductor pattern 12 can be reduced, and the risk of characteristic drift of the semiconductor pattern 12 due to light exposure can be reduced. The semiconductor pattern 12 shown in FIG20 provided in the embodiments of this disclosure can be applied to any of the above embodiments (e.g., FIG3B, FIG5 and FIG9B).

[0161] In some embodiments, continuing to refer to FIG20, the dimension D3 of the extension 125 along the first direction X is 1.4μm to 1.8μm. In this case, the dimension D3 of the connecting portion 126 along the second direction Y is also 1.4μm to 2μm. In other words, the dimension D3 of the semiconductor pattern 12 in the direction perpendicular to the extension direction of the semiconductor pattern 12 is 1.4μm to 2μm. This allows for a significant reduction in the size of the semiconductor pattern 12 and its photosensitive area while ensuring that the characteristics (e.g., aspect ratio) of the thin-film transistor T1 meet the usage requirements. Exemplarily, the dimension D3 of the extension 125 along the first direction X (and the dimension D3 of the connecting portion 126 along the second direction Y) is 1.4μm, 1.5μm, 1.6μm, 1.7μm, or 2μm, etc., and these will not be listed individually in the embodiments of this disclosure.

[0162] In some embodiments, as shown in FIG17, the second insulating layer ILD2 is located between the first light-shielding layer 20 and the semiconductor layer 30, and the thickness of the second insulating layer is less than or equal to Alternatively, the distance D4 between the surface (upper surface) of the first light-shielding layer 2020 near the semiconductor layer 30 and the surface (lower surface) of the semiconductor layer 30 near the first light-shielding layer 20 is less than or equal to That is, the spacing between the first light-shielding layer 20 and the semiconductor layer 30 Referring to Figure 21, the inventors discovered that as the spacing D4 between the first light-shielding layer 20 and the semiconductor layer 30 increases, the stray light incident into the channel region 121 increases accordingly. This increases the light-induced interference within the channel region 121, leading to a gradual increase in the light leakage current generated on the thin-film transistor T1, including the semiconductor pattern 12. Furthermore, as the spacing D4 between the first light-shielding pattern 11 and the semiconductor pattern 12 increases... Under these conditions, a higher level can be achieved. In embodiments of this disclosure, a setting is provided. This helps reduce stray light incident into the channel region 121, thereby reducing the impact of illumination on the channel region 121, reducing the photo-leakage current generated on the thin-film transistor T1 formed by the semiconductor pattern 12, and improving the stability of the characteristics of the thin-film transistor formed by the semiconductor layer 30. For example, or, or, For example, the spacing D4 between the first light-shielding layer 20 and the semiconductor layer 30 can be... or Examples of these will not be listed individually in the embodiments disclosed herein.

[0163] In some embodiments, referring to FIG22, the array substrate 100 may further include an anti-reflection layer 18. The anti-reflection layer 18 is located between the first light-shielding pattern 11 and the semiconductor layer 30, and its orthogonal projection on the first substrate 10 covers the orthogonal projection of the channel region 121 on the first substrate 10. The reflectivity of the anti-reflection layer 18 is less than that of the first light-shielding pattern 11. In this way, light rays G1 that are incident on the first light-shielding pattern 11 at an angle (at a certain angle to the direction perpendicular to the first substrate) from the side of the semiconductor layer 30 away from the first substrate 10 can be blocked by the anti-reflection layer 18. This reduces the reflection of the light rays G1 toward the channel region 121 on the surface of the first light-shielding pattern 11 near the semiconductor layer 30, further reducing the illumination received on the semiconductor pattern 12, especially on the channel region 121, and reducing the light leakage current on the thin film transistor including the semiconductor pattern 12.

[0164] In some embodiments, the first light-shielding pattern 11 and the second light-shielding pattern 13 may include the same material, and both include one or both of molybdenum and molybdenum oxide. The material of the anti-reflection layer 18 may include silicon (such as amorphous silicon or low-temperature polycrystalline silicon). Exemplarily, the material of the anti-reflection layer 18 may be adjusted according to the fabrication process of the array substrate. For example, if the array substrate includes thin-film transistors formed of low-temperature polycrystalline silicon, the material of the anti-reflection layer 18 may be low-temperature polycrystalline silicon. Of course, the materials of the first light-shielding pattern 11, the second light-shielding pattern 13, and the anti-reflection layer 18 are not limited to these, and any other suitable materials may be used, as long as the same technical concept is adopted.

[0165] In some embodiments, the first light-shielding pattern 11 has a dimension perpendicular to the first substrate 10. And / or, the second light-shielding pattern 13 has a dimension perpendicular to the first substrate 10. The thickness of the first light-shielding pattern 11 and the thickness of the second light-shielding pattern 13 can be the same. Alternatively, the thickness of the first light-shielding pattern 11 and the thickness of the second light-shielding pattern 13 can also be different.

[0166] For example, the thickness of the first light-shielding pattern 11 is the same as the thickness of the second light-shielding pattern 13, and both are... or Examples of these will not be listed individually in the embodiments disclosed herein.

[0167] In some embodiments, based on the structure of the array substrate 100 in any of the above embodiments, embodiments of this disclosure also provide a color filter substrate 200. Referring to FIG23, the color filter substrate 200 includes a second substrate and a color filter layer 22 located on the second substrate. The color filter layer 22 may include a plurality of filter portions 40. The plurality of filter portions 40 may be arranged alternately along a first direction X, and at least one filter portion 40 extends along a second direction Y. The at least one filter portion 40 may cover a plurality of sub-pixels arranged along the second direction Y. That is, the at least one filter portion 40 does not need to be separated by a black matrix between two adjacent sub-pixels along the second direction Y, i.e., at least part of the black matrix is ​​removed.

[0168] For example, as shown in FIG23, multiple light-filtering sections 40 extend along the second direction Y, and each light-filtering section 40 covers multiple (e.g., a column) sub-pixels along the second direction Y. In this case, a black matrix may not be provided on the color filter layer 22. After the color filter substrate 200 and the array substrate form a display panel, light is blocked by the first light-blocking layer and the second light-blocking pattern on the array substrate, and adjacent sub-pixels along the first direction X can be separated by the data lines in the array substrate.

[0169] The filter section 40 filters the light passing through it so that the light passing through it is a single color. The filter section 40 may include filters of multiple colors, so that multiple filters 40 can filter light of multiple colors to enable the display panel to achieve color display. For example, the multiple filters 40 may include a red filter 401, a green filter 402, and a blue filter 403; for instance, red light can pass through the red filter 401, green light can pass through the green filter 402, and blue light can pass through the blue filter 403.

[0170] In some embodiments, referring to Figures 24 and 25, the color filter layer 22 includes a plurality of first filter portions 41 and a plurality of second filter portions 42 and partition portions 422. The first filter portions 41 extend along a second direction Y, and the orthographic projection of one first filter portion 41 on the array substrate 100 covers a column of sub-pixels and the semiconductor pattern 12 of the column of sub-pixels. The second filter portions 42 include filter sub-portions 421 and partition portions 422, which are alternately arranged along the second direction Y. The orthographic projection of the filter sub-portions 421 on the array substrate 100 covers the sub-pixels and does not coincide with the channel region 121 of the semiconductor pattern 12; the orthographic projection of the partition portions 422 on the array substrate 100 at least covers the channel region 121. In other words, in the orthographic projection of the filter portion 421 and the separator portion 422 on the array substrate 100, one filter portion 421 covers one sub-pixel and does not coincide with the channel region 121 of the semiconductor pattern 12, and one separator portion 422 covers at least one channel region 121 of the semiconductor pattern 12.

[0171] In the embodiments of this disclosure, the first filter portion 41 refers to a filter portion 40 that extends continuously in the second direction Y and is capable of covering multiple sub-pixels (e.g., a column of sub-pixels), and may include one or both of a red filter portion 401, a green filter portion 402, and a blue filter portion 403; similarly, the filter sub-portion 421 refers to a filter portion 40 that is spaced apart in the second direction Y and covers only one sub-pixel, and may include one or both of a red filter portion 401, a green filter portion 402, and a blue filter portion 403. The separating portion 422 refers to other portions located between adjacent filter sub-portions 421.

[0172] For example, as shown in FIG24, the orthogonal projection of the separator 422 on the array substrate can completely cover the semiconductor pattern 12. Alternatively, as shown in FIG25, the orthogonal projection of the separator 422 on the array substrate covers a portion of the semiconductor pattern 12, and the orthogonal projection of the filter portion 421 on the array substrate partially coincides with the semiconductor pattern 12; for example, the separator 422 covers the channel region of the semiconductor pattern 12 and the second sub-region for connection with the first electrode and the second electrode, and the filter portion 421 partially coincides with the first sub-region of the semiconductor pattern 12.

[0173] The inventors discovered that, according to the photoelectric effect, when the light energy absorbed by a semiconductor material exceeds its bandgap, a photoelectric leakage current can be generated. That is: h×v≥Eg (1)

[0174] When equation (1) is satisfied, a light leakage current will be generated, where "h" is Planck's constant, "v" is the frequency of light, and "Eg" is the bandgap of the semiconductor material. Substituting v = c / λ, we can obtain equation (2), where "c" is the speed of light and "λ" is the wavelength of light. Λ≤h×c / Eg=1240 / Eg (2)

[0175] Taking the material of semiconductor pattern 12, which includes low-temperature polycrystalline silicon, as an example, we can obtain Figure 26. In Figure 26, the horizontal axis represents the wavelength of light, and the vertical axis represents the photo-leakage current of the low-temperature polycrystalline silicon material. As can be seen from Figure 26, the shorter the wavelength of the light irradiating the semiconductor pattern, the greater the photo-leakage current generated by the semiconductor pattern.

[0176] Based on the above research, in the embodiments of this disclosure, the wavelength of light passing through the separator 422 is greater than the wavelength of light passing through the second filter 42; or, the brightness of light passing through the separator 422 is less than the brightness of light passing through the second filter 42. This reduces the photoleakage current generated by the semiconductor pattern 12 when light shines on it.

[0177] In some embodiments, referring to FIG24, a plurality of first filter portions 41 include a red filter portion 401, and a plurality of second filter portions 42 (filter sub-portions 421) include a blue filter portion 403 and a green filter portion 402. The wavelengths of blue light and green light are both shorter than the wavelength of red light, thereby reducing the amount of blue and green light incident on the semiconductor pattern 12 and reducing the light leakage current of the thin film transistor T1 formed by the semiconductor pattern 12.

[0178] In some embodiments, referring to FIG25, a plurality of first filter portions 41 include a red filter portion 401 and a green filter portion 402, and a plurality of second filter portions 42 (filter sub-portions 421) include a blue filter portion 403. The wavelength of blue light is smaller than that of red light and blue light, and the blue filter portion 403 is separated at least by the separator portion 422 to reduce the amount of blue light incident on the semiconductor pattern.

[0179] In some embodiments, the partition 422 and the red filter 401 are made of the same material. That is, the partition 422 is formed by the material of the red filter 401. In this case, the wavelength of the light (red light) passing through the partition 422 is greater than the wavelength of the light (blue light or green light) passing through the filter 421.

[0180] In some embodiments, the partition 422 includes a black matrix. In this case, the brightness of the light passing through the partition 422 is less than the brightness of the light passing through the photosensitive filter 421, which can reduce the light incident on the semiconductor pattern 12 and thereby reduce the light leakage current of the thin film transistor T1 including the semiconductor pattern 12.

[0181] The display panel 1200 provided in the embodiments of this disclosure includes the array substrate 100 described in any of the above embodiments, but does not include the color filter substrate 200 described in the above embodiments. In this case, the color filter substrate can be, for example, a color filter substrate in conventional technology. When the display panel 1200 is used to form a projection device, the array substrate 100 of the display panel can be arranged facing the light source.

[0182] When the display panel includes the array substrate 100 described in any of the above embodiments and the color filter substrate 200 described in any of the above embodiments, the display panel 1200 may be configured such that the array substrate 100 of the display panel faces the light source, or the color filter substrate 200 of the display panel faces the light source when forming a projection device.

[0183] In some embodiments, the present disclosure also provides a method for fabricating an array substrate, which can be used to fabricate the array substrate described in any of the above embodiments. Exemplarily, the fabrication method may include steps S100 to S300.

[0184] S100, referring to Figure 27, forms the first substrate 101.

[0185] The first substrate 101 includes a first substrate 10, and a first light-shielding layer 20, a semiconductor layer 30, a first conductive layer 14, a second conductive layer 15, and a first electrode layer 16 disposed along a direction away from the first substrate 10 (from bottom to top in FIG. 27). The semiconductor layer 30 includes a plurality of semiconductor patterns 12 arranged in an array, a semiconductor pattern channel region 121, and a conductor region 122. The first substrate 101 includes a display area AA and a peripheral area BB. The peripheral area BB includes an initial pin 50'. The initial pin 50' includes a first sub-part 51 located on the first conductive layer 14 and a second sub-part 52 located on the second conductive layer 15. The second sub-part 52 is electrically connected to the first sub-part 51, and the first substrate 101 exposes the surface of the second sub-part 52 away from the first substrate 10. The first light-shielding layer 20, the semiconductor layer 30, the first conductive layer 14, the second conductive layer 15, and the first electrode layer 16 are described above and will not be repeated here.

[0186] As shown in Figure 27, the first substrate 101 also includes a third insulating layer PVX located within the display area AA.

[0187] S200, referring to FIG28, a light-shielding film 130 is formed on the first substrate 101.

[0188] The light-shielding film 130 is located on the side of the first electrode layer 16 away from the first substrate 10 and covers the first substrate 101. For example, the light-shielding film 130 covers the third insulating layer PVX located in the display area AA and covers the second sub-section 52 located in the peripheral area. Exemplarily, the upper light-shielding film 130 can be formed by a thin film deposition process (such as evaporation or sputtering).

[0189] S300, referring to Figure 29, the light-shielding film 130 is patterned to form a second light-shielding layer 13'.

[0190] The second light-shielding layer 13' includes a second light-shielding pattern 13 and a third sub-section 53. The orthographic projection of the second light-shielding pattern 13 onto the first substrate 10 at least covers the orthographic projection of the channel region 121 onto the first substrate 10, and the third sub-section 53 covers the second sub-section 52. For example, the light-shielding film 130 can be patterned by an etching process.

[0191] In the above-described preparation method provided by the embodiments of this disclosure, during the process of patterning the light-shielding film 130 to form the second light-shielding layer 13' in step S300, since the third sub-part 53 is to be formed, the second sub-part 52 of the bonding pin 50 will not be etched, which can reduce the risk of defects in the bonding pin 50.

[0192] In some embodiments, the above step S300, which involves patterning the light-shielding film 130 to form the second light-shielding layer 13', may include steps S310 to S340.

[0193] S310, a photoresist film is formed by coating the light-shielding film 130.

[0194] For example, a photoresist film covers a light-shielding film 130.

[0195] S320 is used to perform photolithography on a photoresist film to form a mask layer.

[0196] The orthographic projection of the mask layer on the first substrate 10 at least covers the orthographic projection of the channel region 121 on the first substrate 10, and also covers the orthographic projection of the second sub-region 52 on the first substrate 10. Exemplarily, the above photolithography process may include exposure and development.

[0197] S330 uses an etching process to remove the portion of the light-shielding film 130 that is exposed by the mask layer.

[0198] The portion retained in the light-shielding film 130 (the portion not removed by the etching process described above) forms the second light-shielding layer 13'. Exemplarily, the etching process described above may include one of a dry etching process and a wet etching process, without specific limitations herein.

[0199] S340, remove the mask layer.

[0200] For example, the mask layer can be removed by etching or other suitable processes.

[0201] In some embodiments, the method for fabricating the array substrate further includes step S400 after step S300 described above.

[0202] S400, referring to Figure 30, a second electrode layer 17 is formed on the second light-shielding layer 13'.

[0203] The second electrode layer 17 is in direct contact with the second light-shielding layer 13', and the second light-shielding layer 13' includes a fourth sub-part 54 located in the peripheral region BB. The orthographic projection of the fourth sub-part 54 on the first substrate 10 at least partially overlaps with the orthographic projection of the third sub-part 53 on the first substrate 10. For example, the fourth sub-part 54 can completely cover the third sub-part 53.

[0204] Of course, in other examples, where the fourth sub-part 54 is not included in the bonding pin, the second electrode layer 17 formed in step S400 above may also not include the fourth sub-part.

[0205] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An array substrate, comprising: First substrate; A semiconductor layer is located on one side of the first substrate. The semiconductor layer includes a plurality of semiconductor patterns arranged in an array. The semiconductor patterns include channel regions and conductor regions. A first conductive layer is located on the side of the semiconductor layer away from the first substrate. The first conductive layer includes a plurality of gate lines and a gate electrically connected to the gate lines. The second conductive layer is located on the side of the first conductive layer away from the first substrate. The second conductive layer includes multiple data lines intersecting with the gate line, a first electrode electrically connected to the data lines, and a second electrode. A first light-shielding layer is located on the side of the semiconductor layer close to the first substrate. The first light-shielding layer includes a plurality of first light-shielding patterns. The orthographic projection of the first light-shielding patterns on the first substrate at least covers the orthographic projection of the channel region on the first substrate. The second light-shielding pattern is located on the side of the first conductive layer away from the first substrate; wherein the orthographic projection of the second light-shielding pattern on the first substrate at least covers the orthographic projection of the channel region on the first substrate.

2. The array substrate according to claim 1, further comprising: The first electrode layer is located on the side of the second conductive layer away from the first substrate and is electrically connected to the second electrode. The second electrode layer is located on the side of the first electrode layer away from the first substrate; The second light-shielding pattern is located between the first electrode layer and the second electrode layer, and the orthographic projection of the second light-shielding pattern on the first substrate at least partially overlaps with the orthographic projection of the second electrode layer on the first substrate, wherein the second light-shielding pattern is electrically connected to the second electrode layer.

3. The array substrate according to claim 2, wherein, The second electrode layer is in direct contact with the second light-shielding pattern.

4. The array substrate according to any one of claims 2 to 3, further comprising: A first insulating layer is located between the first conductive layer and the second conductive layer; The first via penetrates at least the first insulating layer and exposes the conductor region; The first electrode and the second electrode are respectively electrically connected to the conductor region through a first via; The orthographic projection of the second light-shielding pattern on the first substrate also covers the orthographic projection of the first via on the first substrate.

5. The array substrate according to claim 1, further comprising: A second insulating layer is located between the semiconductor layer and the first light-shielding layer, and the thickness of the second insulating layer is less than or equal to... or, The distance between the surface of the first light-shielding layer near the semiconductor layer and the surface of the semiconductor layer near the first light-shielding layer is less than or equal to the distance between the two surfaces.

6. The array substrate according to any one of claims 2 to 4, wherein, The orthographic projection of a second light-shielding pattern on the first substrate overlaps the orthographic projection of the channel region of the semiconductor pattern on the first substrate.

7. The array substrate according to claim 6, wherein, The semiconductor pattern includes two channel regions spaced apart. The second light-shielding pattern includes two first sub-patterns, one of which has an orthographic projection on the first substrate that overlaps the orthographic projection of the channel region on the first substrate.

8. The array substrate according to any one of claims 2 to 4, wherein, The semiconductor layer includes multiple rows of semiconductor patterns, and each row of semiconductor patterns includes multiple semiconductor patterns spaced apart along a first direction; An orthographic projection of a second light-shielding pattern onto the first substrate covers the orthographic projection of the channel region of a row of the semiconductor pattern onto the first substrate.

9. The array substrate according to claim 1, wherein, The semiconductor pattern includes two channel regions spaced apart. The first electrode and the second light-shielding pattern are integrally formed, and the orthographic projection of the first electrode on the first substrate covers the orthographic projection of the channel region on the first substrate; And / or, the second electrode is integrally disposed with the second light-shielding pattern, and the orthographic projection of the second electrode on the first substrate covers the orthographic projection of one of the channel regions on the first substrate; The line width of the first pole is greater than the line width of the data line.

10. The array substrate according to any one of claims 1 to 9, wherein, The semiconductor pattern includes two channel regions spaced apart. An orthographic projection of the first light-shielding pattern onto the first substrate covers an orthographic projection of the channel region of the semiconductor pattern onto the first substrate.

11. The array substrate according to any one of claims 1 to 9, wherein, The semiconductor layer includes multiple rows of the semiconductor pattern, and each row of the semiconductor pattern includes multiple semiconductor patterns spaced apart along a first direction; An orthographic projection of the first light-shielding pattern onto the first substrate covers the orthographic projection of the channel region of a row of the semiconductor pattern onto the first substrate.

12. The array substrate according to claim 11, wherein, The first light-shielding pattern includes alternating first extension segments and second extension segments. The orthographic projection of the first extension segment onto the first substrate at least covers the orthographic projection of the channel region onto the first substrate. The orthographic projection of the second extension segment onto the first substrate does not coincide with the orthographic projection of the channel region onto the first substrate. The dimension of the first extension segment along the second direction is equal to the dimension of the second extension segment along the second direction, and the second direction intersects the first direction.

13. The array substrate according to claim 11, wherein, The semiconductor pattern includes two extensions and a connecting portion. The two extensions are arranged opposite to each other along the first direction and both extend along the second direction. The two ends of the connecting portion are respectively connected to the ends of the two extensions located on the same side. The second direction intersects the first direction. Along the first direction, the first light-shielding pattern includes alternating first extension segments and second extension segments; the orthographic projection of the first extension segment on the first substrate at least covers the orthographic projection of the channel region on the first substrate, and the orthographic projection of the second extension segment on the first substrate does not coincide with the orthographic projection of the channel region on the first substrate; The dimension of the first extension segment in the second direction is greater than the dimension of the second extension segment in the second direction.

14. The array substrate according to claim 13, wherein, Along the second direction, the ends of the first extension and the second extension away from the connecting portion are flush, the end of the first extension near the connecting portion protrudes from the end of the second extension near the connecting portion; The orthographic projection of the side boundary of the first extension segment away from the connector on the first substrate coincides with the orthographic projection of the side boundary of the extension segment away from the connector on the first substrate; the orthographic projection of the side boundary of the second extension segment near the connector on the first substrate coincides with the orthographic projection of the side boundary of the gate line near the connector on the first substrate.

15. The array substrate according to any one of claims 2 to 8, wherein, The array substrate includes a display area and a peripheral area; the array substrate also includes bonding pins located in the peripheral area. The bonding pin includes a first sub-part located in the first conductive layer, a second sub-part located in the second conductive layer, and a third sub-part disposed in the same layer as the second light-shielding pattern; the second sub-part is electrically connected to both the first sub-part and the third sub-part; the orthographic projection of the third sub-part on the first substrate covers the orthographic projection of the second sub-part on the first substrate; or... The bonding pin includes a first sub-part located in the first conductive layer, a second sub-part located in the second conductive layer, a third sub-part disposed in the same layer as the second light-shielding pattern, and a fourth sub-part located in the second electrode layer; the second sub-part is electrically connected to the first sub-part and the third sub-part respectively; the orthographic projection of the third sub-part on the first substrate covers the orthographic projection of the second sub-part on the first substrate, the fourth sub-part is electrically connected to the third sub-part, and the orthographic projection of the fourth sub-part on the first substrate covers the orthographic projection of the third sub-part on the first substrate.

16. The array substrate according to claim 15, further comprising: A first signal line is located in the peripheral area and in the second conductive layer, and the first signal line is spaced apart from the second sub-part; The first sub-part is also electrically connected to the first signal line.

17. The array substrate according to any one of claims 1 to 16, wherein, The semiconductor pattern includes two channel regions spaced apart, and the conductor region includes a first sub-region connecting the two channel regions and two second sub-regions located on the side of the two channel regions away from the first sub-region, respectively. The orthographic projection of the first light-shielding layer on the first substrate covers the orthographic projection of the two channel regions, the two second sub-regions, and at least a portion of the first sub-region near the channel regions on the first substrate. The orthographic projection of the second light-shielding pattern on the first substrate covers the orthographic projection of the two channel regions, the two second sub-regions, and at least a portion of the first sub-region near the channel regions on the first substrate.

18. The array substrate according to any one of claims 1 to 17, wherein, The portion of the conductor region whose orthographic projection on the first substrate coincides with the orthographic projection of the first light-shielding pattern on the first substrate has a dimension along the length of the channel region that is greater than or equal to 1.3 μm. And / or, The portion of the conductor region whose orthographic projection on the first substrate coincides with the second light-shielding pattern's orthographic projection on the first substrate has a dimension along the length of the channel region that is greater than or equal to 1.3 μm.

19. The array substrate according to claim 17 or 18, wherein, Along a direction perpendicular to the extension direction of the channel region, the orthographic projection of the boundary of the first light-shielding pattern on the first substrate and the orthographic projection of the channel region on the first substrate are at a distance greater than or equal to 2 μm. And / or, Along a direction perpendicular to the extension direction of the channel region, the orthographic projection of the boundary of the second light-shielding pattern onto the first substrate and the orthographic projection of the channel region onto the first substrate are spaced at a distance greater than or equal to 2 μm.

20. The array substrate according to any one of claims 1 to 19, wherein, The orthographic projection of the first light-shielding pattern on the first substrate completely coincides with the orthographic projection of the second light-shielding pattern on the first substrate; or, the orthographic projection of one of the first light-shielding patterns and the second light-shielding pattern on the light-incident side away from the array substrate on the first substrate is within the range of the orthographic projection of the other on the first substrate, and the minimum interval between the orthographic projection of the boundary of the first light-shielding pattern on the first substrate and the orthographic projection of the boundary of the second light-shielding pattern on the first substrate is less than or equal to 1.1 μm.

21. The array substrate according to any one of claims 1 to 20, wherein, The semiconductor pattern includes two extensions and a connecting portion. The two extensions are arranged opposite to each other along the first direction and both extend along the second direction. The two ends of the connecting portion are respectively connected to the ends of the two extensions located on the same side. The second direction intersects the first direction. The dimension of the extension along the first direction is equal to the dimension of the connecting portion along the second direction.

22. The array substrate according to claim 21, wherein, The extension has a dimension of 1.4 μm to 2 μm along the first direction.

23. The array substrate according to any one of claims 1 to 22, wherein, The thickness of the first light-shielding layer is And / or, The thickness of the second light-shielding pattern is 24. The array substrate according to any one of claims 1 to 23, further comprising: An anti-reflection layer is located between the first light-shielding layer and the semiconductor layer. The orthogonal projection of the anti-reflection layer on the first substrate covers the orthogonal projection of the channel region on the first substrate. The reflectivity of the anti-reflection layer is less than that of the first light-shielding layer.

25. A display panel, comprising: The array substrate as described in any one of claims 1 to 24; A color filter substrate is disposed opposite to the array substrate; A liquid crystal layer is located between the array substrate and the color filter substrate.

26. The display panel according to claim 25, wherein, The array substrate includes a plurality of sub-pixels, which are arranged in rows along a first direction and in columns along a second direction. Each sub-pixel includes a semiconductor pattern located in a semiconductor layer. The first direction and the second direction intersect. The color filter substrate includes a second substrate and a color filter layer located on the second substrate, the color filter layer including a plurality of first filter portions and a plurality of second filter portions; The first filter extends along the second direction, and the orthographic projection of one of the first filter on the array substrate covers a column of the sub-pixels and covers the semiconductor pattern of the column of the sub-pixels; The second filter portion includes a filter sub-portion and a separator portion, which are alternately arranged along a second direction. The orthographic projection of the filter sub-portion on the array substrate covers the sub-pixel and does not coincide with the channel region of the semiconductor pattern. The orthographic projection of the separator portion on the array substrate at least covers the channel region. The wavelength of the light passing through the dividing section is greater than the wavelength of the light passing through the photofilter; or, the brightness of the light passing through the dividing section is less than the brightness of the light passing through the photofilter.

27. The display panel according to claim 26, wherein, The plurality of first filter sections include a red filter section, and the plurality of second filter sections include a blue filter section and a green filter section.

28. The display panel according to claim 26, wherein, The plurality of first filter sections include a red filter section and a green filter section, and the plurality of second filter sections include a blue filter section.

29. The display panel according to claim 27 or 28, wherein, The separating portion and the red filter portion are made of the same material, and the wavelength of light passing through the separating portion is greater than the wavelength of light passing through the filter portion.

30. The display panel according to claim 27 or 28, wherein, The dividing section includes a black matrix, and the brightness of the light passing through the dividing section is less than the brightness of the light passing through the filter section.

31. A projection device, comprising: The display panel as described in claims 25-30; The light source is located on the side of the array substrate of the display panel away from the color filter substrate; or, it is located on the side of the color filter substrate of the display panel away from the array substrate.

32. A method for fabricating an array substrate, comprising: Forming the first substrate; The first substrate includes a first substrate, and a first light-shielding layer, a semiconductor layer, a first conductive layer, a second conductive layer, and a first electrode layer disposed in a direction away from the first substrate. The semiconductor layer includes a plurality of semiconductor patterns arranged in an array. The semiconductor patterns include a channel region and a conductor region. The first substrate includes a display region and a peripheral region. The peripheral region includes an initial pin. The initial pin includes a first sub-part located in the first conductive layer and a second sub-part located in the second conductive layer. The second sub-part is electrically connected to the first sub-part, and the first substrate exposes the surface of the second sub-part away from the first substrate. A light-shielding film is formed on the first substrate; the light-shielding film is located on the side of the first electrode layer away from the first substrate and covers the first substrate; The light-shielding film is patterned to form a second light-shielding layer; the second light-shielding layer includes a second light-shielding pattern and a third sub-part, the orthographic projection of the second light-shielding pattern on the first substrate at least covers the orthographic projection of the channel region on the first substrate, and the third sub-part covers the second sub-part.

33. The preparation method according to claim 32, wherein, The step of patterning the light-shielding film to form the second light-shielding layer includes: A photoresist film is formed by coating the light-shielding film; A photoresist film is photolithographically processed to form a mask layer; the orthographic projection of the mask layer on the first substrate at least covers the orthographic projection of the channel region on the first substrate, and also covers the orthographic projection of the second sub-part on the first substrate; An etching process is used to remove the portion of the light-shielding film exposed by the mask layer, and the remaining portion of the light-shielding film forms the second light-shielding layer; Remove the mask layer.

34. The preparation method according to claim 32 or 33, wherein, After the light-shielding film is patterned, the preparation method further includes: A second electrode layer is formed on the second light-shielding layer; the second electrode layer is in direct contact with the second light-shielding layer, and the second light-shielding layer includes a fourth sub-part located in the peripheral region, the orthographic projection of the fourth sub-part on the first substrate at least partially overlapping the orthographic projection of the third sub-part on the first substrate.

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