Display substrate and manufacturing method therefor

Abstract

A display substrate and a manufacturing method therefor. The display substrate comprises a base substrate (110) and a transistor (120) disposed on the base substrate (110). The transistor (120) comprises an active layer (121), a gate electrode (122), and a source / drain electrode (123 / 124). The active layer (121) comprises a channel region (1211), and a source region (1212) and a drain region (1213) located on two sides of the channel region (1211). The source / drain electrode (123 / 124) comprises a source electrode (123) electrically connected to the source region (1212) and a drain electrode (124) electrically connected to the drain region (1213). The gate electrode (122) is disposed on the side of the source / drain electrode (123 / 124) distant from the base substrate (110). The display substrate has a better display effect and a simpler manufacturing process.

Description

Display substrate and its preparation method Technical Field

[0001] Embodiments of this disclosure relate to a display substrate and a method for preparing the same. Background Technology

[0002] In flat panel display technology, such as liquid crystal displays (LCDs) or organic light-emitting diode (OLEDs), transistors are used as switching control elements or integrated components in peripheral driving circuits, and are considered core components of flat panel display technology. The performance of transistors directly affects the performance of display devices, and the transistor fabrication process directly impacts the fabrication process of display devices, including factors such as fabrication difficulty and cost.

[0003] Therefore, continuously optimizing the structure and fabrication process of transistors is a subject of ongoing research for those skilled in the art. Summary of the Invention

[0004] At least one embodiment of this disclosure provides a display substrate, which includes a substrate and a transistor disposed on the substrate. The transistor includes an active layer, a gate, and source / drain electrodes. The active layer includes a channel region and a source region and a drain region located on both sides of the channel region. The source / drain electrodes include a source electrode electrically connected to the source region and a drain electrode electrically connected to the drain region. The gate is disposed on the side of the source / drain electrodes away from the substrate.

[0005] For example, in a display substrate provided in at least one embodiment of this disclosure, the source electrode is directly in contact with the source region for electrical connection, and the drain electrode is directly in contact with the drain region for electrical connection.

[0006] For example, at least one embodiment of the present disclosure provides a display substrate that further includes a first insulating layer, wherein the source / drain electrode and the gate are disposed on the side of the active layer away from the substrate, and the first insulating layer is disposed on the side of the source / drain electrode and the gate away from the substrate and directly contacts the source / drain electrode and the gate.

[0007] For example, at least one embodiment of the present disclosure provides a display substrate that further includes a first insulating layer, wherein the source and drain electrodes are disposed on the side of the active layer near the substrate, the gate electrode is disposed on the side of the active layer away from the substrate, and the first insulating layer is disposed on the side of the gate electrode away from the substrate and directly contacts the gate electrode, at least a portion of the source region, and at least a portion of the drain region.

[0008] For example, at least one embodiment of the present disclosure provides a display substrate that further includes: a light-shielding layer disposed on the side of the active layer near the substrate, wherein, in a direction perpendicular to the substrate, the light-shielding layer at least partially overlaps with the channel region, and the source / drain electrodes are disposed in the same layer as the light-shielding layer.

[0009] For example, at least one embodiment of the present disclosure provides a display substrate that further includes: a second insulating layer disposed between the source / drain electrodes and the active layer, including a first via exposing at least a portion of the source electrode and a second via exposing at least a portion of the drain electrode, wherein the source region is electrically connected to the source electrode through the first via, and the drain region is electrically connected to the drain electrode through the second via.

[0010] For example, in a display substrate provided in at least one embodiment of this disclosure, the active layer is a semiconductor layer, the source / drain electrode is a source / drain electrode layer, and the orthographic projection of the source / drain electrode layer on the substrate is located inside the orthographic projection of the semiconductor layer on the substrate.

[0011] For example, in a display substrate provided in at least one embodiment of this disclosure, the source / drain electrode layer further includes a first signal line, which is integrally connected to the source electrode. The semiconductor layer further includes a semiconductor extension, which is integrally connected to the source region. The semiconductor extension has a substantially the same planar shape and size as the first signal line.

[0012] For example, at least one embodiment of the present disclosure provides a display substrate that further includes a gate insulating pattern, wherein the gate is disposed on the side of the active layer away from the substrate, the gate insulating pattern is disposed between the gate and the active layer, and the gate and the gate insulating pattern have substantially the same planar shape and size.

[0013] For example, at least one embodiment of the present disclosure provides a display substrate that further includes: a planarization layer, a first electrode pattern, a third insulating layer, and a second electrode pattern; the planarization layer is disposed on the side of the transistor away from the substrate, the first electrode pattern is disposed on the side of the planarization layer away from the substrate, the third insulating layer is disposed on the side of the planarization layer away from the substrate, the second electrode pattern is disposed on the side of the third insulating layer away from the substrate, and is electrically connected to the drain electrode through vias in the planarization layer and the third insulating layer.

[0014] For example, in at least one embodiment of the present disclosure, the display substrate has a display area and a peripheral area at least partially surrounding the display area. The transistor is at least disposed in the display area. The peripheral area includes a second signal line disposed on the same layer as the gate and a third signal line disposed on the same layer as the source and drain electrodes. The second signal line and the third signal line are electrically connected by a connecting trace, which is disposed on the same layer as the first electrode pattern or the second electrode pattern.

[0015] For example, in at least one embodiment of the display substrate provided in this disclosure, the transistor is a single-gate transistor having one gate.

[0016] At least one embodiment of this disclosure also provides a method for fabricating a display substrate, the method comprising: providing a substrate, and forming a transistor on the substrate, wherein the transistor includes an active layer, a gate, and source / drain electrodes, the active layer includes a channel region and a source region and a drain region located on both sides of the channel region, the source / drain electrodes include a source electrode electrically connected to the source region and a drain electrode electrically connected to the drain region, wherein the gate is formed after the source / drain electrodes are formed.

[0017] For example, in the fabrication method provided in at least one embodiment of this disclosure, the source and drain electrodes are directly formed on the side of the active layer away from the substrate, so that the source electrode is in direct contact with the source region for electrical connection, and the drain electrode is in direct contact with the drain region for electrical connection; or, the active layer is directly formed on the side of the source and drain electrodes away from the substrate, so that the source electrode is in direct contact with the source region for electrical connection, and the drain electrode is in direct contact with the drain region for electrical connection.

[0018] For example, at least one embodiment of the present disclosure provides a fabrication method that further includes: forming a gate insulating pattern, wherein forming the gate insulating pattern includes: forming a gate insulating material layer on the side of the active layer away from the substrate, forming a gate on the side of the gate insulating material layer away from the substrate, and patterning the gate insulating material layer with the gate as a mask to form the gate insulating pattern.

[0019] For example, in at least one embodiment of the present disclosure, the source / drain electrode and the gate are formed on the side of the active layer away from the substrate. The fabrication method further includes forming a first insulating layer on the side of the source / drain electrode and the gate away from the substrate, wherein the first insulating layer directly contacts the source / drain electrode and the gate.

[0020] For example, in a fabrication method provided in at least one embodiment of this disclosure, the source and drain electrodes are formed on the side of the active layer near the substrate, and the gate electrode is formed on the side of the active layer away from the substrate. The fabrication method further includes forming a first insulating layer on the side of the gate electrode away from the substrate, wherein the first insulating layer directly contacts the gate electrode, at least a portion of the source region, and at least a portion of the drain region.

[0021] For example, at least one embodiment of the present disclosure provides a fabrication method that further includes: forming a light-shielding layer on the side of the active layer near the substrate, wherein the light-shielding layer at least partially overlaps the channel region in a direction perpendicular to the substrate, and the source / drain electrodes are formed in the same layer as the light-shielding layer.

[0022] For example, at least one embodiment of the present disclosure provides a fabrication method that further includes: forming the active layer and the source / drain electrodes using the same halftone mask template.

[0023] For example, in at least one embodiment of the fabrication method provided in this disclosure, the source / drain electrodes are formed on the side of the active layer away from the substrate. The active layer has a first portion and a second portion. The first portion overlaps with the source / drain electrodes in a direction perpendicular to the substrate. The halftone mask includes a first mask portion, a second mask portion, and a third mask portion with sequentially increasing transmittance. The first mask portion corresponds to the first portion, and the second mask portion corresponds to the second portion. Forming the active layer and the source / drain electrodes includes: forming an active material layer and a source / drain material layer on the substrate, forming a photoresist material layer on the source / drain material layer, and so on. The photoresist material layer is exposed through the halftone mask, and the photoresist material layer is first developed to remove the portion of the photoresist material layer corresponding to the third mask portion to form a first mask pattern. Using the first mask pattern as a mask, the active material layer and the source / drain material layer are etched to form the active layer. The first mask pattern is second developed to remove the portion of the first mask pattern corresponding to the second mask portion to form a second mask pattern. Using the second mask pattern as a mask, the source / drain material layer is etched to remove the portion of the source / drain material layer corresponding to the second mask portion to form the source / drain electrode. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0025] Figure 1 is a cross-sectional schematic diagram of a display substrate;

[0026] Figure 2 is a plan view of a display substrate provided in at least one embodiment of the present disclosure;

[0027] Figure 3 is a cross-sectional view of the display substrate along line AA in Figure 2;

[0028] Figure 4 is a plan view of another display substrate provided in at least one embodiment of the present disclosure;

[0029] Figure 5 is a cross-sectional schematic diagram of the display substrate along line BB in Figure 4;

[0030] Figure 6 is a plan view of another display substrate provided in at least one embodiment of the present disclosure;

[0031] Figure 7 is a cross-sectional view of the display substrate in Figure 6 along the CC line;

[0032] Figure 8 is a plan view of another display substrate provided in at least one embodiment of the present disclosure;

[0033] Figure 9 is a cross-sectional schematic diagram of the display substrate along the DD line in Figure 8;

[0034] Figure 10 is another cross-sectional schematic diagram of a display substrate provided in at least one embodiment of the present disclosure;

[0035] Figure 11 is a plan view of a display substrate provided in at least one embodiment of the present disclosure;

[0036] Figure 12 is a cross-sectional schematic diagram of the peripheral region of a display substrate provided in at least one embodiment of the present disclosure;

[0037] Figures 13A-21B are planar schematic diagrams and corresponding cross-sectional schematic diagrams of a display substrate provided in at least one embodiment of the present disclosure during the fabrication process;

[0038] Figures 22-24 are cross-sectional schematic diagrams of another display substrate provided in at least one embodiment of the present disclosure during the fabrication process; and

[0039] Figure 25 is a scanning electron microscope image of a display substrate provided in at least one embodiment of the present disclosure. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0041] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0042] As mentioned earlier, transistors, such as thin-film transistors (TFTs), are core components of display devices, serving as switching control elements or integrated elements in peripheral driving circuits. Currently, the TFTs used in display devices include amorphous silicon (a-Si) TFTs and polycrystalline silicon (polycrystalline silicon) TFTs. Amorphous silicon (a-Si) TFTs can be used in pixel driving circuits or as switching control devices. However, the mobility of amorphous silicon is typically low, for example, below 1 cm⁻¹. 2 Polycrystalline silicon has poor uniformity, complex and costly manufacturing processes, and is sensitive to visible light, making it unsuitable for large-size and high-resolution displays.

[0043] Research has revealed that oxide semiconductor thin-film transistors exhibit superior performance; for example, indium gallium zinc oxide (IGZO) semiconductor materials demonstrate higher mobility, reaching, for instance, 20 cm⁻¹. 2 With a range of / V·S or higher, good uniformity, low processing temperature, high transmittance in the visible light region, and suitability for flexible displays, display devices utilizing oxide semiconductor thin-film transistors may have better display performance.

[0044] Thin-film transistors typically exhibit either a bottom-gate or top-gate structure. Top-gate thin-film transistors offer certain performance and process advantages over bottom-gate structures. However, the fabrication process for top-gate structures is more complex, generally involving a 9-mask process, and the dry etching process used in the fabrication may cause significant damage to the active layer.

[0045] For example, Figure 1 shows a cross-sectional schematic diagram of a display substrate. As shown in Figure 1, the display substrate includes a transistor disposed on a substrate 110. The transistor includes an active layer AT, a gate G, and source / drain electrodes SD. An interlayer insulating layer ILD is disposed between the gate G and the source / drain electrodes SD. The interlayer insulating layer ILD has a via V0 so that the source / drain electrodes SD are connected to the active layer AT through the via V0.

[0046] In the fabrication process of the aforementioned display substrate, the active layer AT, gate G, interlayer insulating layer ILD, and source / drain electrodes SD need to be formed sequentially. When forming the interlayer insulating layer ILD, a dry etching process is required to form the pattern of the interlayer insulating layer ILD, such as via V0. At this time, the dry etching process will damage the active layer AT below the via V0, such as thinning or etching through the active layer AT, thereby affecting the performance of the transistor and the display effect of the display device.

[0047] In this regard, at least one embodiment of the present disclosure provides a display substrate and a method for fabricating the same. The display substrate includes a substrate and a transistor disposed on the substrate. The transistor includes an active layer, a gate, and source / drain electrodes. The active layer includes a channel region and a source region and a drain region located on both sides of the channel region. The source / drain electrodes include a source electrode electrically connected to the source region and a drain electrode electrically connected to the drain region. The gate is disposed on the side of the source / drain electrodes away from the substrate.

[0048] The method for fabricating the display substrate includes: providing a substrate and forming a transistor on the substrate, wherein the transistor includes an active layer, a gate, and source / drain electrodes, the active layer includes a channel region and a source region and a drain region located on both sides of the channel region, and the source / drain electrodes include a source electrode electrically connected to the source region and a drain electrode electrically connected to the drain region, wherein the gate is formed after the source / drain electrodes are formed.

[0049] Therefore, in the above-mentioned display substrate and its preparation method provided in the embodiments of this disclosure, by adjusting the process sequence and adjusting the gate preparation process to be after the source and drain electrodes, the setting of the interlayer insulating layer in the display substrate can be eliminated, simplifying the structure of the display substrate, and saving the preparation process of the interlayer insulating layer in the preparation process, reducing one mask, making the preparation process simpler, reducing the preparation difficulty and preparation cost.

[0050] The following describes in detail the display substrate and its preparation method provided in this disclosure through several specific embodiments.

[0051] This disclosure provides at least one embodiment of a display substrate. FIG2 shows a partial planar schematic diagram of the display substrate, such as a planar schematic diagram of a transistor. FIG3 shows a cross-sectional schematic diagram of the display substrate in FIG2 along line AA. As shown in FIG2 and FIG3, the display substrate includes a substrate 110 and a transistor 120 disposed on the substrate 110. The transistor 120 includes an active layer 121, a gate 122, and source / drain electrodes 123 / 124. The active layer 121 includes a channel region 1211 and a source region 1212 and a drain region 1213 located on both sides of the channel region 1211. The source / drain electrodes 123 / 124 include a source electrode 123 electrically connected to the source region 1212 and a drain electrode 124 electrically connected to the drain region 1213. The gate 122 is disposed on the side of the source / drain electrodes 123 / 124 away from the substrate 110.

[0052] That is, in the layered structure of the display substrate, the gate 122 is disposed on the side of the source / drain electrodes 123 / 124 away from the substrate 110. In other words, during the fabrication process, the gate 122 is formed later than the source / drain electrodes 123 / 124, or the conductive layer where the gate 122 is located is formed later than the conductive layer where the source / drain electrodes 123 / 124 are located.

[0053] Therefore, the above-mentioned display substrate reduces the setting of the interlayer insulating layer (ILD) compared to the display substrate in FIG1. ​​Thus, in the fabrication process of the above-mentioned display substrate, the dry etching process for forming the pattern of the interlayer insulating layer (ILD) can be omitted, reducing one mask. Consequently, the dry etching process will not cause damage to the active layer 121, ensuring the integrity of the active layer 121, thereby ensuring the integrity of the transistor and improving the performance of the transistor.

[0054] For example, in some embodiments, as shown in FIG3, the source electrode 123 is directly in contact with the source region 1212 for electrical connection. That is, there is no other structure between the source electrode 123 and the source region 1212, such as an insulating layer, via, or connecting electrode. The source electrode 123 is directly disposed on the source region 1212 for direct contact and electrical connection. The drain electrode 124 is directly in contact with the drain region 1213 for electrical connection. That is, there is no other structure between the drain electrode 124 and the drain region 1213, such as an insulating layer or connecting electrode. The drain electrode 124 is directly disposed on the drain region 1213 for direct contact and electrical connection.

[0055] This simplifies the structure of the display substrate and thus the fabrication process. In addition, during subsequent fabrication, when vias are formed above the source / drain electrodes 123 / 124, for example, when vias are formed to expose the source / drain electrodes 123 / 124, the source / drain electrodes 123 / 124 can serve as a protective layer for the active layer 121, preventing damage to the active layer 121, thereby ensuring the integrity of the transistor and improving the performance of the transistor.

[0056] For example, in some embodiments, as shown in FIG3, the display substrate may further include a first insulating layer 130. The source / drain electrodes 123 / 124 and the gate electrode 122 are disposed on the side of the active layer 121 away from the substrate 110, and the first insulating layer 130 is disposed on the side of the source / drain electrodes 123 / 124 and the gate electrode 122 away from the substrate 110, and directly contacts the source / drain electrodes 123 / 124 and the gate electrode 122; that is, the first insulating layer 130 simultaneously and directly covers the source / drain electrodes 123 / 124 and the gate electrode 122. Thus, the source / drain electrodes 123 / 124 and the gate electrode 122 are covered, insulated, and protected by the same insulating layer, which can further simplify the structure of the display substrate and simplify the manufacturing process of the display substrate.

[0057] For example, in some examples, the first insulating layer 130 may be a passivation layer, such as an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0058] For example, in some embodiments, as shown in Figures 2 and 3, the display substrate may further include a light-shielding layer LS. The light-shielding layer LS is disposed on the side of the active layer 121 near the substrate 110. In a direction perpendicular to the substrate 110, the light-shielding layer LS at least partially overlaps with the channel region 1211, so that the light-shielding layer LS can achieve the light-shielding effect on the channel region 1211, preventing light incident from the substrate 110 from shining on the channel region 1211 and affecting the normal operation of the transistor 120.

[0059] For example, in some examples, the orthographic projection of the channel region 1211 onto the substrate 110 is located inside the orthographic projection of the light-shielding layer LS onto the substrate 110, so that the light-shielding layer LS can fully achieve the light-shielding effect on the channel region 1211. For example, the light-shielding layer LS can be made of metal or alloy materials, such as copper, aluminum, nickel, titanium, etc.

[0060] For example, in some embodiments, as shown in FIG3, the display substrate may further include a second insulating layer 140, which is disposed on the side of the light-shielding layer LS away from the substrate 110 to protect and insulate the light-shielding layer LS. The active layer 121 is disposed on the side of the second insulating layer 140 away from the substrate 110. For example, the second insulating layer 140 may be a buffer layer, such as an insulating material made of silicon oxide, silicon nitride, or silicon oxynitride.

[0061] For example, in some embodiments, as shown in FIG3, the display substrate may further include a gate insulating pattern 125, a gate 122 disposed on the side of the active layer 121 away from the substrate 110, and the gate insulating pattern 125 disposed between the gate 122 and the active layer 121, thereby separating the gate 122 and the active layer 121. The gate 122 and the gate insulating pattern 125 have substantially the same planar shape and size, so that the gate insulating pattern 125 sufficiently separates the gate 122 and the active layer 121.

[0062] For example, in the fabrication process of the display substrate, the gate 122 can be formed first, and then the gate 122 can be used as a mask to form the gate insulating pattern 125. This makes the planar shape and size of the gate 122 and the gate insulating pattern 125 substantially the same, and simplifies the fabrication process. For example, the gate insulating pattern 125 can be made of insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0063] For example, in some embodiments, as shown in FIG2, the planar pattern of the active layer 121 is Z-shaped, and the overlapping portions of the source region 1212 and the source electrode 123 and the overlapping portions of the drain region 1213 and the drain electrode 124 of the active layer 121 are respectively block-shaped to have a large area to achieve sufficient connectivity. The light-shielding layer LS is block-shaped to fully shield the channel region 1211 of the active layer 121.

[0064] For example, in addition to the transistor 120 mentioned above, the display substrate may also include other structures, which will be described later.

[0065] For example, Figure 4 is a plan view of another display substrate provided in at least one embodiment of the present disclosure, and Figure 5 is a cross-sectional view of the display substrate in Figure 4 along line BB; in the embodiments of Figures 4 and 5, the structure of transistor 120 is slightly different from that of the embodiments of Figures 2 and 3.

[0066] For example, as shown in Figures 4 and 5, the display substrate includes a substrate 110 and a transistor 120 disposed on the substrate 110. The transistor 120 includes an active layer 121, a gate 122, and source / drain electrodes 123 / 124. The active layer 121 includes a channel region 1211 and a source region 1212 and a drain region 1213 located on both sides of the channel region 1211. The source / drain electrodes 123 / 124 include a source electrode 123 electrically connected to the source region 1212 and a drain electrode 124 electrically connected to the drain region 1213. The gate 122 is disposed on the side of the source / drain electrodes 123 / 124 away from the substrate 110.

[0067] For example, as shown in Figures 4 and 5, the source / drain electrodes 123 / 124 are disposed on the side of the active layer 121 near the substrate 110. In this case, during the fabrication process, the source / drain electrodes 123 / 124 are formed first, and then the active layer 121 is formed. The source electrode 123 is in direct contact with the source region 1212 for electrical connection. That is, there are no other structures between the source electrode 123 and the source region 1212, such as insulating layers, vias, or connecting electrodes. The source electrode 123 is directly disposed on the source region 1212 for direct contact and electrical connection. The drain electrode 124 is in direct contact with the drain region 1213 for electrical connection. That is, there are no other structures between the drain electrode 124 and the drain region 1213, such as insulating layers or connecting electrodes. The drain electrode 124 is directly disposed on the drain region 1213 for direct contact and electrical connection.

[0068] For example, as shown in Figures 4 and 5, the gate 122 is disposed on the side of the active layer 121 away from the substrate 110. The display substrate also includes a first insulating layer 130, which is disposed on the side of the gate 122 away from the substrate 110 and directly contacts the gate 122, at least a portion (e.g., most or all) of the source region 1212, and at least a portion (e.g., most or all) of the drain region 1213. That is, the first insulating layer 130 simultaneously and directly covers the gate 122, at least a portion of the source region 1212, and at least a portion of the drain region 1213.

[0069] Therefore, at least a portion of the gate 122, the source region 1212, and at least a portion of the drain region 1213 are covered, protected, and insulated by the same insulating layer, which can further simplify the structure of the display substrate and simplify the manufacturing process of the display substrate.

[0070] For example, as shown in FIG5, the display substrate may further include a gate insulating pattern 125, a gate 122 disposed on the side of the active layer 121 away from the substrate 110, and the gate insulating pattern 125 disposed between the gate 122 and the active layer 121, thereby separating the gate 122 and the active layer 121. The gate 122 and the gate insulating pattern 125 have substantially the same planar shape and size, so that the gate insulating pattern 125 sufficiently separates the gate 122 and the active layer 121.

[0071] For example, regarding the embodiments of Figures 4 and 5, for structures and materials not mentioned, as well as technical effects not mentioned, please refer to the embodiments of Figures 2 and 3, which will not be repeated here.

[0072] For example, FIG6 is a plan view of another display substrate provided in at least one embodiment of the present disclosure, and FIG7 is a cross-sectional view of the display substrate in FIG6 along the CC line; in the embodiments of FIG6 and FIG7, the structure of transistor 120 is slightly different from the above embodiments.

[0073] For example, as shown in Figures 6 and 7, the display substrate includes a substrate 110 and a transistor 120 disposed on the substrate 110. The transistor 120 includes an active layer 121, a gate 122, and source / drain electrodes 123 / 124. The active layer 121 includes a channel region 1211 and a source region 1212 and a drain region 1213 located on both sides of the channel region 1211. The source / drain electrodes 123 / 124 include a source electrode 123 electrically connected to the source region 1212 and a drain electrode 124 electrically connected to the drain region 1213. The gate 122 is disposed on the side of the source / drain electrodes 123 / 124 away from the substrate 110.

[0074] For example, as shown in Figures 6 and 7, the display substrate also includes a light-shielding layer LS. The light-shielding layer LS is disposed on the side of the active layer 121 near the substrate 110. In the direction perpendicular to the substrate 110, the light-shielding layer LS overlaps at least partially with the channel region 1211. Thus, the light-shielding layer LS can achieve the light-shielding effect on the channel region 1211, preventing light incident from the substrate 110 from shining on the channel region 1211 and affecting the normal operation of the transistor 120.

[0075] For example, the source / drain electrodes 123 / 124 are disposed in the same layer as the light-shielding layer LS, thereby simplifying the structure and fabrication process of the display substrate.

[0076] It should be noted that in the embodiments of this disclosure, "same-layer setting" means that two functional layers or structural layers are formed on the same layer and with the same material in the layer structure of the display substrate. That is, in the manufacturing process, the two functional layers or structural layers can be formed from the same material layer and can be formed with the same patterning process to form the required pattern and structure.

[0077] For example, as shown in Figures 6 and 7, the display substrate may further include a second insulating layer 140. The second insulating layer 140 is disposed between the source / drain electrodes 123 / 124 and the active layer 121, and includes a first via V1 exposing at least a portion of the source electrode 123 and a second via V2 exposing at least a portion of the drain electrode 124. The source region 1212 is electrically connected to the source electrode 123 through the first via V1, and the drain region 1213 is electrically connected to the drain electrode 124 through the second via V2. Thus, the source region 1212 and the drain region 1213 of the active layer 121 are electrically connected to the source electrode 123 and the drain electrode 124 through the vias in the second insulating layer 140 disposed on the light-shielding layer LS. This solution does not add a new functional layer compared to the above embodiments, and the source / drain electrodes 123 / 124 and the light-shielding layer LS can be formed using the same patterning process, making the fabrication process simpler.

[0078] For example, the second insulating layer 140 can be a buffer layer, such as an insulating material made of silicon oxide, silicon nitride, or silicon oxynitride.

[0079] For example, as shown in Figures 6 and 7, the display substrate also includes a gate insulating pattern 125. The gate 122 is disposed on the side of the active layer 121 away from the substrate 110. The gate insulating pattern 125 is disposed between the gate 122 and the active layer 121. The gate 122 and the gate insulating pattern 125 have substantially the same planar shape and size, so that the gate insulating pattern 125 sufficiently separates the gate 122 and the active layer 121.

[0080] For example, regarding the embodiments of Figures 6 and 7, for structures and materials not mentioned, as well as technical effects not mentioned, please refer to the embodiments of Figures 2 and 3, which will not be repeated here.

[0081] For example, Figure 8 is a plan view of another display substrate provided in at least one embodiment of the present disclosure, and Figure 9 is a cross-sectional view of the display substrate in Figure 8 along the DD line; in the embodiments of Figures 8 and 9, the structure of some functional layers is slightly different from that of the embodiments of Figures 2 and 3.

[0082] For example, as shown in Figures 8 and 9, the display substrate includes a substrate 110 and a transistor 120 disposed on the substrate 110. The transistor 120 includes an active layer 121, a gate 122, and source / drain electrodes 123 / 124. The active layer 121 includes a channel region 1211 and a source region 1212 and a drain region 1213 located on both sides of the channel region 1211. The source / drain electrodes 123 / 124 include a source electrode 123 electrically connected to the source region 1212 and a drain electrode 124 electrically connected to the drain region 1213. The gate 122 is disposed on the side of the source / drain electrodes 123 / 124 away from the substrate 110. The cross-sectional structure shown in Figure 9 is basically the same as the cross-sectional structure shown in Figure 3.

[0083] For example, as shown in Figures 8 and 9, the active layer 121 is located in the semiconductor layer SM, and the source / drain electrodes 123 / 124 are located in the source / drain electrode layer SD1. The orthographic projection of the source / drain electrode layer SD1 onto the substrate 110 is located inside the orthographic projection of the semiconductor layer SM onto the substrate 110. For example, during the fabrication process, the semiconductor layer SM and the source / drain electrode layer SD1 can be formed using the same half-tone mask. In this case, some structures in the semiconductor layer SM and the source / drain electrode layer SD1 can have substantially the same shape and size.

[0084] For example, as shown in Figure 8, the source / drain electrode layer SD1 also includes a first signal line L1, which is integrally connected to the source electrode 123. For example, it can be a data line or other signal line used to provide data signals. The semiconductor layer SM also includes a semiconductor extension SM1, which is integrally connected to the source region 1212. The semiconductor extension SM1 and the first signal line L1 have essentially the same planar shape and size. In this case, during fabrication, the semiconductor extension SM1 and the first signal line L1 can be formed using the same mask pattern portion of the halftone mask described above. For example, the semiconductor extension SM1 can have good conductivity (e.g., be conductor-modified), thereby reducing the resistance of the source electrode 123. It should be noted that integral connection means fabricated in the same layer and directly connected to each other without separation.

[0085] For example, as shown in FIG9, the display substrate further includes a gate insulating pattern 125. The gate 122 is disposed on the side of the active layer 121 away from the substrate 110. The gate insulating pattern 125 is disposed between the gate 122 and the active layer 121. The gate 122 and the gate insulating pattern 125 have substantially the same planar shape and size, so that the gate insulating pattern 125 sufficiently separates the gate 122 and the active layer 121.

[0086] For example, regarding the embodiments of Figures 8 and 9, for structures and materials not mentioned, as well as technical effects not mentioned, please refer to the embodiments of Figures 2 and 3, which will not be repeated here.

[0087] For example, FIG10 is another cross-sectional schematic diagram of a display substrate provided in at least one embodiment of the present disclosure. Compared with the above embodiments, FIG10 also shows other structures included in the display substrate besides transistor 120, such as some structures disposed on transistor 20.

[0088] For example, as shown in FIG10, the display substrate may further include a planarization layer 150, a first electrode pattern 160, a third insulating layer 170, and a second electrode pattern 180; the planarization layer 150 is disposed on the side of the transistor 120 away from the substrate 110, for example, on the side of the first insulating layer 130 away from the substrate 110, to provide a flat surface for subsequent electrode pattern placement; the first electrode pattern 160 is disposed on the side of the planarization layer 150 away from the substrate 110, the third insulating layer 170 is disposed on the side of the planarization layer 150 away from the substrate 110, the second electrode pattern 180 is disposed on the side of the third insulating layer 170 away from the substrate 110, and is electrically connected to the drain 124 through vias V3 and V4 in the planarization layer 150 and the third insulating layer 170, and through via V5 in the first insulating layer 130.

[0089] For example, in some embodiments, the orthographic projection of via V3 of planarization layer 150 onto substrate 110 may extend beyond, be substantially equal to, or be less than the edge of the orthographic projection of drain 124 onto substrate 110. In this case, the orthographic projections of via V5 and via V4 onto substrate 110 may be located inside the orthographic projection of via V3 onto substrate 110, that is, the planar coverage of via V3 is greater than the planar coverage of V5 and V4. For example, via V5 and via V4 may be formed using a single etching process, thereby, the planar dimensions of via V5 and via V4 may be substantially the same.

[0090] For example, in some other embodiments, vias V3, V4, and V5 may also be in the form of vias. In this case, via V5 exposes part or all of the drain 124, and the planar dimension of via V5 is larger than the planar dimension of via V3, and the planar dimension of via V3 is larger than the planar dimension of via V4. The embodiments of this disclosure do not limit the specific form of vias V3, V4, and V5.

[0091] For example, the first electrode pattern 160 can be configured to provide a common voltage, such as a ground voltage or a low-level voltage, and the second electrode pattern 180 can be configured to provide a high-level voltage, so that a voltage difference can be generated between the first electrode pattern 160 and the second electrode pattern 180 to drive the liquid crystal molecules to rotate, thereby achieving a display effect.

[0092] For example, the planarization layer 150 can be made of organic insulating materials such as polyimide or resin; the third insulating layer 170 can be made of insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride; and the first electrode pattern 160 and the second electrode pattern 180 can be made of transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), or zinc gallium oxide (GZO). The materials of the first electrode pattern 160 and the second electrode pattern 180 can be the same or different.

[0093] For example, FIG11 is a planar schematic diagram of a display substrate provided in at least one embodiment of the present disclosure. As shown in FIG11, the display substrate has a display area AA and a peripheral area NA that at least partially surrounds the display area AA. A transistor 120 is at least disposed in the display area AA, for example for a pixel driving circuit. For example, in some examples, the transistor 120 may also be used in the peripheral area NA, for example as a component of a gate driving circuit (GOA, Gate On Array).

[0094] For example, Figure 12 is a cross-sectional schematic diagram of the peripheral region of a display substrate provided in at least one embodiment of this disclosure. For simplicity, Figure 12 only shows the structure of the semiconductor layer SM and above. As shown in Figure 12, the peripheral region NA includes a second signal line L2 disposed on the same layer as the gate 122 and a third signal line L3 disposed on the same layer as the source / drain electrodes 123 / 124. The second signal line L2 and the third signal line L3 are electrically connected by a connecting trace L4. The connecting trace L4 is disposed on the same layer as the first electrode pattern 160 or the second electrode pattern 180. Figure 12 shows the case where the connecting trace L4 is disposed on the same layer as the second electrode pattern 180. Therefore, the connecting trace L4 can be formed using the same patterning process as the first electrode pattern 160 or the second electrode pattern 180, which simplifies the fabrication process of the display substrate.

[0095] For example, as shown in Figure 12, an insulating pattern 1251, which is disposed on the same layer as the gate insulating pattern 125, is provided between the second signal line L2 and the semiconductor layer SM to space and insulate the second signal line L2 from the semiconductor layer SM. During the fabrication process, the insulating pattern 1251 and the gate insulating pattern 125 can be formed using the same patterning process, thereby simplifying the fabrication process of the display substrate.

[0096] For example, as shown in Figure 12, the first insulating layer 130 and the third insulating layer 170 may include a sleeve V6 that exposes the second signal line L2 and a sleeve V7 that exposes the third signal line L3, and the connecting trace L4 electrically connects the second signal line L2 and the third signal line L3 through the sleeve V6 and the sleeve V7, respectively.

[0097] For example, in some examples, the gate drive circuit also includes a transistor, and the second signal line L2 can provide a gate signal for the transistor, and the third signal line L3 can provide a source-drain electrode signal for the transistor; or, in other embodiments, the second signal line L2 and the third signal line L3 can also be used as other signal lines for the peripheral region NA, and the embodiments of this disclosure do not specifically limit this.

[0098] For example, in various embodiments of this disclosure, transistor 120 is a single-gate transistor with a gate 122. By applying a scan signal to the gate 122, the transistor 120 can be controlled to turn on and off, making the control process simpler.

[0099] For example, the active layer 121 of transistor 120 can be made of oxide semiconductor materials, such as amorphous oxide semiconductor (AOS), indium tin oxide (ITO), aluminum zinc oxide (AZO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), etc. Oxide semiconductors have high mobility, good uniformity, low processing temperature, high transmittance in the visible light region, and are suitable for flexible displays. Therefore, transistors using oxide semiconductors may have better performance.

[0100] For example, in embodiments of this disclosure, the substrate 110 can be a rigid substrate such as glass or quartz, or a flexible substrate such as polyimide or resin. The gate 122 can be made of metals or alloys such as copper (Cu), aluminum (Al), or titanium (Ti), and can be formed as a single-layer or multi-layer metal structure, such as a titanium / aluminum / titanium multi-layer metal structure. The source / drain electrodes 123 / 124 can be made of metals or alloys such as copper (Cu), aluminum (Al), or titanium (Ti), and can be formed as a single-layer or multi-layer metal structure, such as a titanium / aluminum / titanium multi-layer metal structure.

[0101] The embodiments disclosed herein do not specifically limit the materials of various structures of the display substrate, nor do they limit other structures of the display substrate. For details, please refer to the related technologies.

[0102] By performing performance tests on the transistor provided in the embodiments of this disclosure and obtaining the IV curve of source-drain electrode current I versus gate voltage V, the turn-on current I of the transistor can be determined. on By comparing key performance indicators, it can be found that the transistor provided in this embodiment has basically the same performance as the transistor with the structure of FIG1, or the transistor provided in this embodiment has better performance than the transistor with the structure of FIG1. ​​Therefore, through the structure of the transistor and its preparation method in this embodiment, the structure of the transistor is simpler, the preparation method is simpler, and it has better performance.

[0103] By testing the active layer of the transistor shown in FIG1 and the active layer of the transistor in the display substrate provided in the present disclosure embodiment, it can be concluded that, corresponding to the transistor in FIG1, the thickness of the active layer 121 is reduced by about 10nm during the dry etching process of the interlayer insulating layer (ILD). Based on the same test conditions and test methods, for the transistors 120 in FIG2 and FIG3, since there is no interlayer insulating layer (ILD) and the corresponding dry etching process, the thickness of the active layer 121 can be avoided during the dry etching process of the interlayer insulating layer (ILD), thereby the structure of the active layer 121 is thicker, and the transistor performance is better. For example, the impedance of the active layer 121 is lower, and the stability of the transistor is better. Moreover, when fabricating the active layer 121 of the same thickness, the present disclosure embodiment can use a lower thickness when the active layer is initially deposited, thereby reducing costs.

[0104] For example, the display substrate provided in the embodiments of this disclosure can be a liquid crystal display substrate, an organic light-emitting display substrate, or a quantum dot display substrate, etc. The embodiment in FIG10 is described using a liquid crystal display substrate as an example, but the embodiments of this disclosure are not limited thereto.

[0105] At least one embodiment of this disclosure also provides a method for fabricating a display substrate, the method comprising: providing a substrate 110 and forming a transistor 120 on the substrate 110, the transistor 120 including an active layer 121, a gate 122 and source / drain electrodes 123 / 124, the active layer 121 including a channel region 1211 and a source region 1212 and a drain region 1213 located on both sides of the channel region 1211, the source / drain electrodes 123 / 124 including a source electrode 123 electrically connected to the source region 1212 and a drain electrode 124 electrically connected to the drain region 1213, wherein, after the source / drain electrodes 123 / 124 are formed, the gate 122 is formed.

[0106] Therefore, by adjusting the process sequence and placing the gate fabrication process after the source and drain electrodes, the interlayer insulating layer in the display substrate can be eliminated, simplifying the structure of the display substrate. Furthermore, the fabrication process saves on the interlayer insulating layer fabrication process, reducing one mask, making the fabrication process simpler, and reducing the fabrication difficulty and cost.

[0107] For example, in some embodiments, referring to FIG2 and FIG3, the source and drain electrodes 123 / 124 can be directly formed on the side of the active layer 121 away from the substrate 110, so that the source electrode 123 is in direct contact with the source region 1212 for electrical connection, and the drain electrode 124 is in direct contact with the drain region 1213 for electrical connection; in this case, the active layer 121 is formed first, and then the source and drain electrodes 123 / 124 are formed.

[0108] Alternatively, in some other embodiments, referring to Figures 4 and 5, the active layer 121 can be directly formed on the side of the source / drain electrodes 123 / 124 away from the substrate 110, so that the source electrode 123 is in direct contact with the source region 1212 for electrical connection, and the drain electrode 124 is in direct contact with the drain region 1213 for electrical connection; in this case, the source / drain electrodes 123 / 124 are formed first, and then the active layer 121 is formed.

[0109] Therefore, there are no other structures between the source / drain electrodes 123 / 124 and the active layer 121, such as insulating layers, vias, connecting electrodes, etc., which simplifies the structure and the fabrication process.

[0110] For example, in some embodiments, referring to Figures 2 and 3, the source / drain electrodes 123 / 124 and the gate electrode 122 are formed on the side of the active layer 121 away from the substrate 110. The fabrication method may further include forming a first insulating layer 130 on the side of the source / drain electrodes 123 / 124 and the gate electrode 122 away from the substrate 110, with the first insulating layer 130 directly contacting the source / drain electrodes 123 / 124 and the gate electrode 122. Thus, after the source / drain electrodes 123 / 124 and the gate electrode 122 are formed, the first insulating layer 130 can be directly formed on the side of the source / drain electrodes 123 / 124 and the gate electrode 122 away from the substrate 110, thereby simultaneously insulating and protecting the source / drain electrodes 123 / 124 and the gate electrode 122, simplifying the structure and fabrication process of the display substrate.

[0111] For example, in some embodiments, referring to FIG4 and FIG5, source / drain electrodes 123 / 124 are formed on the side of active layer 121 close to substrate 110, and gate 122 is formed on the side of active layer 121 away from substrate 110. The fabrication method may further include: forming a first insulating layer 130 on the side of gate 122 away from substrate 110, the first insulating layer 130 directly contacting gate 122, at least a portion (e.g., most or all) of source region 1212 and at least a portion (e.g., most or all) of drain region 1213.

[0112] Therefore, after the gate 122 is formed, the first insulating layer 130 can be formed directly so that the first insulating layer 130 directly contacts and covers at least a portion of the gate 122, the source region 1212 and the drain region 1213, so as to insulate and protect at least a portion of the gate 122, the source region 1212 and the drain region 1213.

[0113] For example, in some embodiments, referring to Figures 2-9, and Figures 16B and 16C below, the fabrication method may further include forming a gate insulating pattern 125. Forming the gate insulating pattern 125 includes: forming a gate insulating material layer 1250 on the side of the active layer 121 away from the substrate 210; forming a gate 122 on the side of the gate insulating material layer 1250 away from the substrate 210; and patterning the gate insulating material layer 1250 using the gate 122 as a mask to form the gate insulating pattern 125. Therefore, no additional mask is needed to form the gate insulating pattern 125 during the fabrication process, simplifying the fabrication process. Furthermore, the gate insulating pattern 125 and the gate 122 formed therefrom have substantially the same shape and size, and the gate insulating pattern 125 can effectively achieve the function of insulating and protecting the gate 122.

[0114] For example, in some embodiments, referring to FIG6 and FIG7, the fabrication method may further include: forming a light-shielding layer LS on the side of the active layer 121 near the substrate 110, wherein the light-shielding layer LS overlaps at least partially with the channel region 1211 in a direction perpendicular to the substrate 110, and the source / drain electrodes 123 / 124 are formed in the same layer as the light-shielding layer LS, that is, the source / drain electrodes 123 / 124 and the light-shielding layer LS are formed using the same material layer and through the same patterning process, so as to simplify the fabrication process of the display substrate.

[0115] The preparation method provided in the embodiments of this disclosure will be described in detail below, taking the formation of the display substrate shown in Figures 2 and 3 as an example.

[0116] First, a substrate 110 is provided. The substrate 110 can be a rigid substrate such as glass or quartz, or a flexible substrate such as polyimide or resin. As shown in Figures 13A and 13B, a light-shielding layer LS is formed on the substrate 110. For example, a light-shielding material layer is formed on the substrate 110 by sputtering or deposition, and then a patterning process is performed on the light-shielding material layer to form the light-shielding layer LS.

[0117] For example, the light-shielding layer LS can be made of metal materials such as copper (Cu) and titanium (Ti) or alloy materials such as molybdenum-niobium alloy (MoNb) and nickel-titanium-molybdenum alloy (MTD). For example, the thickness of the light-shielding layer LS can be 100nm-300nm, such as 100nm, 150nm, 200nm, 250nm or 300nm.

[0118] In the embodiments of this disclosure, a patterning process may include steps such as photoresist formation, exposure, development, and etching of the material layer, and the embodiments of this disclosure do not specifically limit this process.

[0119] For example, after the light-shielding layer LS is formed, as shown in Figures 14A and 14B, a second insulating layer 140 is formed on the light-shielding layer LS. For example, the second insulating layer 140 can be formed by deposition or other methods. For example, the second insulating layer 140 can be a buffer layer, and can be one or more of silicon oxide, silicon nitride, and silicon oxynitride. The thickness of the second insulating layer 140 can be 300nm-500nm, such as 300nm, 350nm, 400nm, 450nm, or 500nm.

[0120] Subsequently, as shown in Figures 14A and 14B, a semiconductor material layer can be formed and patterned using methods such as deposition to form a semiconductor layer SM. The semiconductor layer SM includes an active layer 121, which can be made of oxide semiconductor materials, such as amorphous oxide semiconductor (AOS), indium tin oxide (ITO), aluminum zinc oxide (AZO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), etc. The thickness of the semiconductor layer SM can be 20nm-80nm, such as 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, or 80nm.

[0121] For example, after the semiconductor layer SM is formed, as shown in Figures 15A and 15B, source / drain electrode material layers can be formed using methods such as sputtering and deposition. These source / drain electrode material layers can then be patterned to form the source / drain electrode layer SD1, which includes source / drain electrodes 123 / 124. For instance, in some examples, referring to Figure 12, the source / drain electrode layer SD1 may also include a third signal line L3, etc. Thus, multiple structures can be formed through a single patterning process, simplifying the fabrication process.

[0122] For example, the source / drain electrode layer SD1 can be made of metal materials such as copper (Cu) or titanium (Ti) or alloy materials such as molybdenum-niobium alloy (MoNb) or nickel-titanium-molybdenum alloy (MTD), and can be a single-layer structure or a multi-layer structure. For example, the thickness of the source / drain electrode layer SD1 can be 300nm-500nm, such as 300nm, 350nm, 400nm, 450nm, or 500nm.

[0123] For example, after the source / drain electrode layer SD1 is formed, as shown in Figures 16A-16B, a gate insulating material layer 1250 can be formed by deposition or other methods. The gate insulating material layer 1250 can be one or more of silicon oxide, silicon nitride, or silicon oxynitride. Then, a gate 122 is formed on the gate insulating material layer 1250. For example, a gate material layer is first formed on the gate insulating material layer 1250 by sputtering or deposition or other methods, and the gate material layer is patterned to form the gate 122. For example, a second signal line L2 is also formed at the same time. Thus, multiple structures are formed by a single patterning process.

[0124] For example, the gate 122 can be made of metal materials such as copper (Cu) or titanium (Ti) or alloy materials such as molybdenum-niobium alloy (MoNb) or nickel-titanium-molybdenum alloy (MTD), and can be a single-layer structure or a multi-layer structure.

[0125] Then, as shown in FIG16C, the gate insulating material layer 1250 is etched using the gate 122 as a mask to form the gate insulating pattern 125.

[0126] For example, the thickness of the gate 122 can be 300nm-600nm, such as 300nm, 350nm, 400nm, 450nm, 500nm, 550nm, or 600nm. The thickness of the gate insulating pattern 125 can be 120nm-200nm, such as 120nm, 150nm, 170nm, 180nm, or 200nm.

[0127] Therefore, no additional mask is needed to form the gate insulating pattern 125 during the fabrication process, which simplifies the fabrication process; and the gate insulating pattern 125 formed therefrom has the same shape and size as the gate 122, so the gate insulating pattern 125 can fully realize the insulation and protection function of the gate 122.

[0128] For example, after the gate insulating pattern 125 is formed, as shown in FIG17, the active layer 121 can be subjected to a conductive process, such as plasma processing, to form the active layer 121 into a channel region 1211 and a source region 1212 and a drain region 1213 located on both sides of the channel region 1211. The source region 1212 and the drain region 1213 have good conductivity for electrical connection with the source electrode 123 and the drain electrode 124, while the channel region 1211 maintains semiconductor characteristics. For example, the gas used in the plasma processing can be He or a combination of He and Ar.

[0129] For example, after the active layer 121 is conductive, as shown in Figures 18A and 18B, a first insulating layer 130 can be formed by deposition or other methods. The first insulating layer 130 can be one or more of silicon oxide, silicon nitride, and silicon oxynitride. The thickness of the first insulating layer 130 can be 200nm-400nm, such as 200nm, 250nm, 300nm, 350nm, or 400nm.

[0130] Subsequently, as shown in Figures 18A and 18B, a planarization material layer is formed on the first insulating layer 130 by means of coating or other methods, and a patterning process is performed on the planarization material layer to form a planarization layer 150. The planarization layer 150 includes vias V3 corresponding to the drain electrode 124. For example, the planarization layer 150 can be made of insulating materials such as polyimide or resin, and the thickness can be 2000nm-3000nm, such as 2000nm, 2500nm, or 3000nm.

[0131] For example, after the planarization layer 150 is formed, as shown in Figures 19A and 19B, a first electrode material layer can be formed by sputtering, deposition, or other methods, and a patterning process can be performed on the first electrode material layer to form a first electrode pattern 160.

[0132] The first electrode pattern 160 can be, for example, a common electrode pattern configured to provide a common voltage. For example, the first electrode pattern 160 can be made of ITO, and the thickness can be 50nm-100nm, such as 50nm, 60nm, 70nm, 80nm, 90nm or 100nm.

[0133] For example, as shown in FIG19A, corresponding to each sub-pixel, the first electrode pattern 160 is a continuous structure covering the entire surface within that sub-pixel. For example, the first electrode pattern 160 also includes a connecting portion between adjacent sub-pixels, and the continuous structure of the first electrode pattern 160 within adjacent sub-pixels is electrically connected through the connecting portion. The first electrode pattern 160 is removed at the position corresponding to the via V3. Therefore, the distribution range of the first electrode pattern 160 is larger, which can reduce the voltage drop of the first electrode pattern 160, improve the uniformity of the common voltage provided by the first electrode pattern 160, and thus improve the display uniformity of the display substrate.

[0134] For example, after the first electrode pattern 160 is formed, as shown in Figures 20A and 20B, a third insulating material layer can be formed by deposition or other methods, and a patterning process can be performed on the third insulating material layer to form a third insulating layer 170, which includes a via V4. For example, while performing the patterning process on the third insulating material layer, the portion of the first insulating layer 130 corresponding to the drain 124 is also etched, for example, by dry etching, thereby forming a via V5 in the first insulating layer 130 that exposes the drain 124.

[0135] During the etching process to form vias, the active layer 121 will not be etched due to the protective effect of the drain 124, thus ensuring the integrity of the active layer 121, thereby ensuring the integrity of the transistor and improving the performance of the transistor.

[0136] For example, the third insulating layer 170 can be made of silicon oxide, silicon nitride, or silicon oxynitride, and its thickness can be 200nm-300nm, such as 200nm, 250nm, or 300nm. For example, the dimensions of vias V4 and V5 can be 3μm*3μm-5μm*5μm, such as 3μm*3μm, 3μm*4μm, 4μm*4μm, 4μm*6μm, or 5μm*5μm.

[0137] For example, after the third insulating layer 170 is formed, as shown in Figures 21A and 21B, a second electrode material layer can be formed by sputtering or deposition, and a patterning process can be performed on the second electrode material layer to form a second electrode pattern 180. The second electrode pattern 180 can also be called a pixel electrode, configured to provide a high-level voltage.

[0138] For example, the material of the second electrode pattern 180 can be ITO, and the thickness can be 50nm-100nm, such as 50nm, 60nm, 70nm, 80nm, 90nm or 100nm.

[0139] For example, Figure 25 is a partial scanning electron microscope image of the display substrate prepared by the above preparation method. As shown in Figure 25, each structure formed by the above method is in the design state, and the structure of the active layer 121 is more complete.

[0140] For example, the above preparation method is described with reference to the embodiments corresponding to Figures 2 and 3. For the embodiments of Figures 4 and 5, as well as the embodiments of Figures 6 and 7, the preparation method of the display substrate can be referred to the above embodiments, and will not be repeated here.

[0141] For example, in some other embodiments, for the display substrates of Figures 8 and 9, unlike the methods described above, the active layer 121 and the source / drain electrodes 123 / 124 can be formed using the same halftone mask (HTM mask). Thus, the active layer 121 and the source / drain electrodes 123 / 124 can be formed using a single mask, further saving one mask compared to the embodiments described above; and saving two masks compared to the embodiment of Figure 1.

[0142] The following is a detailed description of the formation of the active layer 121 and source / drain electrodes 123 / 124 using the same halftone mask, through a specific embodiment.

[0143] For example, referring to FIG22, source / drain electrodes 123 / 124 are formed on the side of active layer 121 away from substrate 110. Active layer 121 has a first portion 121A and a second portion 121B. The first portion 121A overlaps with source / drain electrodes 123 / 124 in a direction perpendicular to substrate 110, and the second portion 121B does not overlap with source / drain electrodes 123 / 124 in a direction perpendicular to substrate 110. Region 121C in FIG22 corresponds to the region where material of active layer 121 is removed.

[0144] For example, the halftone mask M includes a first mask portion M1, a second mask portion M2, and a third mask portion M3 with sequentially increasing transmittance. Therefore, when the photoresist material is exposed through the halftone mask M, the intensity of light passing through the first mask portion M1, the second mask portion M2, and the third mask portion M3 increases sequentially, thus increasing the exposure degree of the photoresist material. After development, the thickness of the photoresist material removed corresponding to the first mask portion M1, the second mask portion M2, and the third mask portion M3 increases sequentially. For example, the first mask portion M1 corresponds to the first portion 121A, the second mask portion M2 corresponds to the second portion 121B, and the third mask portion M3 corresponds to region 121C.

[0145] For example, as shown in FIG23, forming the active layer 121 and the source / drain electrodes 123 / 124 may include: forming an active material layer 1210 and a source / drain material layer 1230 on a substrate 110; forming a photoresist material layer on the source / drain material layer 1230; exposing the photoresist material layer through a halftone mask M; and performing a first development on the photoresist material layer to remove the portion of the photoresist material layer corresponding to the third mask portion M3, thereby forming a first mask pattern P1, the first mask pattern P1 corresponding to the first mask portion. The portion P11 of M1 is thicker, and the portion P12 of the first mask pattern corresponding to the second mask portion M2 is thinner. Then, using the first mask pattern P1 as a mask, the active material layer 1210 and the source / drain material layer 1230 are etched to form the active layer 121. For example, a semiconductor layer SM including the active layer 121 is formed. The semiconductor layer SM may also include a semiconductor extension SM1, etc. Referring to FIG8, at this time, the pattern of the source / drain material layer 1230 after one etching is the same as the pattern of the semiconductor layer SM.

[0146] For example, the semiconductor extension SM1 can have good conductivity (e.g., be conductor-based), thereby reducing the resistance of the source 123.

[0147] For example, as shown in Figure 24, the first mask pattern P1 is developed a second time to remove the portion of the first mask pattern P1 corresponding to the second mask portion M2, retaining only the portion of the first mask pattern P1 corresponding to the first mask portion M1, forming the second mask pattern P2. Then, using the second mask pattern P2 as a mask, the source / drain material layer 1230 is etched to remove the portion of the source / drain material layer 1230 corresponding to the second mask portion M2, forming source / drain electrodes 123 / 124. For example, a source / drain electrode layer SD1 including source / drain electrodes 123 / 124 is formed. The source / drain electrode layer SD1 may also include a first signal line L1, a third signal line L3, etc. The first signal line L1 is integrally connected to the source electrode 123, and may be a data line or other signal line used to provide data line numbers, as shown in Figures 22 and 8. The third signal line L3 can serve as a signal line for the peripheral region NA, providing electrical signals to the circuitry of the peripheral region NA, as shown in Figure 12.

[0148] Therefore, the active layer 121 and source / drain electrodes 123 / 124 can be formed using a single halftone mask, simplifying the fabrication process of the display substrate.

[0149] In summary, in the display substrate and its fabrication method provided in the embodiments of this disclosure, by adjusting the process sequence and placing the gate fabrication process after the source and drain electrodes, the interlayer insulating layer in the display substrate can be eliminated, simplifying the structure of the display substrate. Furthermore, the fabrication process saves the fabrication process of the interlayer insulating layer, reducing one mask, making the fabrication process simpler, and reducing the fabrication difficulty and cost. In addition, forming the gate insulating pattern using the gate as a mask can further simplify the fabrication process. In some embodiments, a halftone mask can also be used to form the active layer and source and drain electrodes, thereby further reducing one mask and making the fabrication process simpler.

[0150] The following points also need to be explained:

[0151] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure, and other structures can be referred to the general design.

[0152] (2) For clarity, the thickness of layers or regions is enlarged or reduced in the drawings used to describe embodiments of the present disclosure, i.e., these drawings are not drawn to actual scale. It is understood that when an element such as a layer, film, region, or substrate is referred to as being disposed “on” or “below” another element, the element may be disposed “directly” on or “below” the other element or there may be intermediate elements.

[0153] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0154] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure shall be determined by the scope of the claims.

Claims

1. A display substrate, comprising a substrate and transistors disposed on the substrate, wherein, The transistor includes an active layer, a gate, and source / drain electrodes. The active layer includes a channel region and source and drain regions located on both sides of the channel region. The source and drain electrodes include a source electrode electrically connected to the source region and a drain electrode electrically connected to the drain region. The gate is disposed on the side of the source / drain electrode away from the substrate.

2. The display substrate according to claim 1, wherein, The source electrode is in direct contact with the source region for electrical connection, and the drain electrode is in direct contact with the drain region for electrical connection.

3. The display substrate according to claim 1 or 2 further includes a first insulating layer. in, The source / drain electrode and the gate are disposed on the side of the active layer away from the substrate, and the first insulating layer is disposed on the side of the source / drain electrode and the gate away from the substrate, and directly contacts the source / drain electrode and the gate.

4. The display substrate according to claim 1 or 2, further comprising a first insulating layer, in, The source and drain electrodes are disposed on the side of the active layer near the substrate. The gate is disposed on the side of the active layer away from the substrate. The first insulating layer is disposed on the side of the gate away from the substrate and directly contacts the gate, at least a portion of the source region and at least a portion of the drain region.

5. The display substrate according to claim 1 or 2, further comprising: A light-shielding layer is disposed on the side of the active layer near the substrate. In a direction perpendicular to the substrate, the light-shielding layer at least partially overlaps with the channel region. The source and drain electrodes are disposed in the same layer as the light-shielding layer.

6. The display substrate according to claim 5, further comprising: A second insulating layer, disposed between the source / drain electrodes and the active layer, includes a first via exposing at least a portion of the source electrode and a second via exposing at least a portion of the drain electrode. The source region is electrically connected to the source electrode through the first via, and the drain region is electrically connected to the drain electrode through the second via.

7. The display substrate according to claim 1 or 2, wherein, The active layer is a semiconductor layer, and the source / drain electrodes are located in the source / drain electrode layer. The orthographic projection of the source / drain electrode layer on the substrate is located inside the orthographic projection of the semiconductor layer on the substrate.

8. The display substrate according to claim 7, wherein, The source / drain electrode layer further includes a first signal line, which is integrally connected to the source electrode. The semiconductor layer further includes a semiconductor extension portion, which is integrally connected to the source region. The semiconductor extension has a substantially the same planar shape and size as the first signal line.

9. The display substrate according to any one of claims 1-8, further comprising a gate insulating pattern, in, The gate is disposed on the side of the active layer away from the substrate, and the gate insulating pattern is disposed between the gate and the active layer. The gate and the gate insulation pattern have substantially the same planar shape and size.

10. The display substrate according to any one of claims 1-9, further comprising: A planarization layer is disposed on the side of the transistor away from the substrate. The first electrode pattern is disposed on the side of the planarization layer away from the substrate. A third insulating layer is disposed on the side of the planarization layer away from the substrate. The second electrode pattern is disposed on the side of the third insulating layer away from the substrate and is electrically connected to the drain electrode through the planarization layer and the vias in the third insulating layer.

11. The display substrate according to claim 10, wherein, The display substrate has a display area and a peripheral area at least partially surrounding the display area, and the transistors are at least disposed in the display area. The surrounding area includes a second signal line disposed on the same layer as the gate electrode and a third signal line disposed on the same layer as the source and drain electrodes. The second signal line and the third signal line are electrically connected by a connecting trace. The connection traces are disposed on the same layer as either the first electrode pattern or the second electrode pattern.

12. The display substrate according to any one of claims 1-11, wherein the transistor is a single-gate transistor having one of the gates.

13. A method for preparing a display substrate, comprising: Provide substrate, and A transistor is formed on the substrate, wherein the transistor includes an active layer, a gate, and source / drain electrodes. The active layer includes a channel region and source and drain regions located on both sides of the channel region. The source and drain electrodes include a source electrode electrically connected to the source region and a drain electrode electrically connected to the drain region. The gate electrode is formed after the source and drain electrodes are formed.

14. The preparation method according to claim 13, wherein, The source and drain electrodes are formed directly on the side of the active layer away from the substrate, so that the source electrode is in direct contact with the source region for electrical connection, and the drain electrode is in direct contact with the drain region for electrical connection; or... The active layer is formed directly on the side of the source and drain electrodes away from the substrate, so that the source electrode is in direct contact with the source region for electrical connection, and the drain electrode is in direct contact with the drain region for electrical connection.

15. The preparation method according to claim 13 or 14, further comprising: Forming a gate insulation pattern, wherein forming the gate insulation pattern includes: A gate insulating material layer is formed on the side of the active layer away from the substrate. A gate is formed on the side of the gate insulating material layer away from the substrate. The gate insulating material layer is patterned using the gate as a mask to form the gate insulating pattern.

16. The preparation method according to any one of claims 13-15, wherein, The source / drain electrodes and the gate electrode are formed on the side of the active layer away from the substrate. The preparation method further includes: A first insulating layer is formed on the side of the source / drain electrode and the gate electrode away from the substrate, wherein the first insulating layer directly contacts the source / drain electrode and the gate electrode.

17. The preparation method according to any one of claims 13-15, wherein, The source and drain electrodes are formed on the side of the active layer near the substrate. The gate is formed on the side of the active layer away from the substrate. The preparation method further includes: A first insulating layer is formed on the side of the gate away from the substrate, wherein the first insulating layer directly contacts the gate, at least a portion of the source region, and at least a portion of the drain region.

18. The preparation method according to claim 13, further comprising: A light-shielding layer is formed on the side of the active layer near the substrate. In a direction perpendicular to the substrate, the light-shielding layer at least partially overlaps with the channel region. The source and drain electrodes are formed in the same layer as the light-shielding layer.

19. The preparation method according to claim 18, further comprising: The active layer and the source / drain electrodes are formed using the same halftone mask.

20. The preparation method according to claim 19, wherein, The source / drain electrodes are formed on the side of the active layer away from the substrate. The active layer has a first portion and a second portion, the first portion overlapping the source / drain electrodes in a direction perpendicular to the substrate. The halftone mask includes a first mask portion, a second mask portion, and a third mask portion with sequentially increasing transmittance. The first mask portion corresponds to the first portion, and the second mask portion corresponds to the second portion. Forming the active layer and the source / drain electrodes includes: An active material layer and a source / drain material layer are formed on the substrate. A photoresist layer is formed on the source / drain material layer. The photoresist material layer is exposed through the halftone mask, and then the photoresist material layer is first developed to remove the portion of the photoresist material layer corresponding to the third mask portion, thereby forming a first mask pattern. Using the first mask pattern as a mask, the active material layer and the source / drain material layer are etched to form the active layer. The first mask pattern is then developed a second time to remove the portion of the first mask pattern corresponding to the second mask portion, forming the second mask pattern. Using the second mask pattern as a mask, the source / drain material layer is etched to remove the portion of the source / drain material layer corresponding to the second mask portion, thereby forming the source / drain electrode.

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